1/* OpenRISC simulator support code 2 Copyright (C) 2017-2023 Free Software Foundation, Inc. 3 4 This file is part of GDB, the GNU debugger. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 18 19/* This must come before any other includes. */ 20#include "defs.h" 21 22#define WANT_CPU_OR1K32BF 23#define WANT_CPU 24 25#include "sim-main.h" 26#include "symcat.h" 27#include "cgen-ops.h" 28#include "cgen-mem.h" 29#include "cpuall.h" 30 31#include <string.h> 32 33int 34or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, void *buf, int len) 35{ 36 if (rn < 32) 37 SETTWI (buf, GET_H_GPR (rn)); 38 else 39 switch (rn) 40 { 41 case PPC_REGNUM: 42 SETTWI (buf, GET_H_SYS_PPC ()); 43 break; 44 case PC_REGNUM: 45 SETTWI (buf, GET_H_PC ()); 46 break; 47 case SR_REGNUM: 48 SETTWI (buf, GET_H_SYS_SR ()); 49 break; 50 default: 51 return 0; 52 } 53 return sizeof (WI); /* WI from arch.h */ 54} 55 56int 57or1k32bf_store_register (sim_cpu *current_cpu, int rn, const void *buf, int len) 58{ 59 if (rn < 32) 60 SET_H_GPR (rn, GETTWI (buf)); 61 else 62 switch (rn) 63 { 64 case PPC_REGNUM: 65 SET_H_SYS_PPC (GETTWI (buf)); 66 break; 67 case PC_REGNUM: 68 SET_H_PC (GETTWI (buf)); 69 break; 70 case SR_REGNUM: 71 SET_H_SYS_SR (GETTWI (buf)); 72 break; 73 default: 74 return 0; 75 } 76 return sizeof (WI); /* WI from arch.h */ 77} 78 79int 80or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc, 81 int unit_num, int referenced) 82{ 83 return -1; 84} 85 86int 87or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc, 88 int unit_num, int referenced) 89{ 90 return -1; 91} 92 93void 94or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p) 95{ 96} 97 98void 99or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles) 100{ 101} 102 103USI 104or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr) 105{ 106 SIM_DESC sd = CPU_STATE (current_cpu); 107 SIM_ASSERT (addr < NUM_SPR); 108 return current_cpu->spr[addr]; 109} 110 111void 112or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val) 113{ 114 SIM_DESC sd = CPU_STATE (current_cpu); 115 SIM_ASSERT (addr < NUM_SPR); 116 current_cpu->spr[addr] = val; 117} 118 119USI 120or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb) 121{ 122 SIM_DESC sd = CPU_STATE (current_cpu); 123 SIM_ASSERT (addr < NUM_SPR); 124 return LSEXTRACTED (current_cpu->spr[addr], msb, lsb); 125} 126 127void 128or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb, 129 USI val) 130{ 131 current_cpu->spr[addr] &= ~LSMASK32 (msb, lsb); 132 current_cpu->spr[addr] |= LSINSERTED (val, msb, lsb); 133} 134 135/* Initialize a sim cpu object. */ 136void 137or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr, 138 const USI or1k_upr, const USI or1k_cpucfgr) 139{ 140 /* Set the configuration registers passed from the user. */ 141 SET_H_SYS_VR (or1k_vr); 142 SET_H_SYS_UPR (or1k_upr); 143 SET_H_SYS_CPUCFGR (or1k_cpucfgr); 144 145#define CHECK_SPR_FIELD(GROUP, INDEX, FIELD, test) \ 146 do \ 147 { \ 148 USI field = GET_H_##SYS##_##INDEX##_##FIELD (); \ 149 if (!(test)) \ 150 sim_io_eprintf \ 151 (sd, "WARNING: unsupported %s field in %s register: 0x%x\n", \ 152 #FIELD, #INDEX, field); \ 153 } while (0) 154 155 /* Set flags indicating if we are in a delay slot or not. */ 156 current_cpu->next_delay_slot = 0; 157 current_cpu->delay_slot = 0; 158 159 /* Verify any user passed fields and warn on configurations we don't 160 support. */ 161 CHECK_SPR_FIELD (SYS, UPR, UP, field == 1); 162 CHECK_SPR_FIELD (SYS, UPR, DCP, field == 0); 163 CHECK_SPR_FIELD (SYS, UPR, ICP, field == 0); 164 CHECK_SPR_FIELD (SYS, UPR, DMP, field == 0); 165 CHECK_SPR_FIELD (SYS, UPR, MP, field == 0); 166 CHECK_SPR_FIELD (SYS, UPR, IMP, field == 0); 167 CHECK_SPR_FIELD (SYS, UPR, DUP, field == 0); 168 CHECK_SPR_FIELD (SYS, UPR, PCUP, field == 0); 169 CHECK_SPR_FIELD (SYS, UPR, PICP, field == 0); 170 CHECK_SPR_FIELD (SYS, UPR, PMP, field == 0); 171 CHECK_SPR_FIELD (SYS, UPR, TTP, field == 0); 172 CHECK_SPR_FIELD (SYS, UPR, CUP, field == 0); 173 174 CHECK_SPR_FIELD (SYS, CPUCFGR, NSGR, field == 0); 175 CHECK_SPR_FIELD (SYS, CPUCFGR, CGF, field == 0); 176 CHECK_SPR_FIELD (SYS, CPUCFGR, OB32S, field == 1); 177 CHECK_SPR_FIELD (SYS, CPUCFGR, OF32S, field == 1); 178 CHECK_SPR_FIELD (SYS, CPUCFGR, OB64S, field == 0); 179 CHECK_SPR_FIELD (SYS, CPUCFGR, OF64S, field == 0); 180 CHECK_SPR_FIELD (SYS, CPUCFGR, OV64S, field == 0); 181 182#undef CHECK_SPR_FIELD 183 184 /* Configure the fpu operations and mark fpu available. */ 185 cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu), 186 or1k32bf_fpu_error); 187 SET_H_SYS_CPUCFGR_OF32S (1); 188 189 /* Set the UPR[UP] flag, even if the user tried to unset it, as we always 190 support the Unit Present Register. */ 191 SET_H_SYS_UPR_UP (1); 192 193 /* Set the supervisor register to indicate we are in supervisor mode and 194 set the Fixed-One bit which must always be set. */ 195 SET_H_SYS_SR (SPR_FIELD_MASK_SYS_SR_SM | SPR_FIELD_MASK_SYS_SR_FO); 196 197 /* Clear the floating point control status register. */ 198 SET_H_SYS_FPCSR (0); 199} 200 201void 202or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc) 203{ 204 SIM_DESC sd = CPU_STATE (current_cpu); 205 206 current_cpu->delay_slot = current_cpu->next_delay_slot; 207 current_cpu->next_delay_slot = 0; 208 209 if (current_cpu->delay_slot && 210 CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) & 211 CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT)) 212 { 213 USI pc; 214#ifdef WITH_SCACHE 215 pc = vpc->argbuf.addr; 216#else 217 pc = vpc; 218#endif 219 sim_io_error (sd, "invalid instruction in a delay slot at PC 0x%08x", 220 pc); 221 } 222 223} 224 225void 226or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc) 227{ 228 SIM_DESC sd = CPU_STATE (current_cpu); 229 USI ppc; 230 231#ifdef WITH_SCACHE 232 ppc = vpc->argbuf.addr; 233#else 234 ppc = vpc; 235#endif 236 237 SET_H_SYS_PPC (ppc); 238 239 if (!GET_H_SYS_CPUCFGR_ND () && 240 CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) & 241 CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI)) 242 { 243 SIM_ASSERT (!current_cpu->delay_slot); 244 current_cpu->next_delay_slot = 1; 245 } 246} 247 248void 249or1k32bf_nop (sim_cpu *current_cpu, USI uimm16) 250{ 251 SIM_DESC sd = CPU_STATE (current_cpu); 252 253 switch (uimm16) 254 { 255 256 case NOP_NOP: 257 break; 258 259 case NOP_EXIT: 260 sim_io_printf (CPU_STATE (current_cpu), "exit(%d)\n", GET_H_GPR (3)); 261 /* fall through */ 262 case NOP_EXIT_SILENT: 263 sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu), 264 sim_exited, GET_H_GPR (3)); 265 break; 266 267 case NOP_REPORT: 268 sim_io_printf (CPU_STATE (current_cpu), "report(0x%08x);\n", 269 GET_H_GPR (3)); 270 break; 271 272 case NOP_PUTC: 273 sim_io_printf (CPU_STATE (current_cpu), "%c", 274 (char) (GET_H_GPR (3) & 0xff)); 275 break; 276 277 default: 278 sim_io_eprintf (sd, "WARNING: l.nop with unsupported code 0x%08x\n", 279 uimm16); 280 break; 281 } 282 283} 284 285/* Build an address value used for load and store instructions. For example, 286 the instruction 'l.lws rD, I(rA)' will require to load data from the 4 byte 287 address represented by rA + I. Here the argument base is rA, offset is I 288 and the size is the read size in bytes. Note, OpenRISC requires that word 289 and half-word access be word and half-word aligned respectively, the check 290 for alignment is not needed here. */ 291 292USI 293or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset, 294 int size) 295{ 296 SIM_DESC sd = CPU_STATE (current_cpu); 297 298 USI addr = base + offset; 299 300 /* If little endian load/store is enabled we adjust the byte and half-word 301 addresses to the little endian equivalent. */ 302 if (GET_H_SYS_SR_LEE ()) 303 { 304 switch (size) 305 { 306 307 case 4: /* We are retrieving the entire word no adjustment. */ 308 break; 309 310 case 2: /* Perform half-word adjustment 0 -> 2, 2 -> 0. */ 311 addr ^= 0x2; 312 break; 313 314 case 1: /* Perform byte adjustment, 0 -> 3, 2 -> 3, etc. */ 315 addr ^= 0x3; 316 break; 317 318 default: 319 SIM_ASSERT (0); 320 return 0; 321 } 322 } 323 324 return addr; 325} 326 327/* The find first 1 instruction returns the location of the first set bit 328 in the argument register. */ 329 330USI 331or1k32bf_ff1 (sim_cpu *current_cpu, USI val) 332{ 333 USI bit; 334 USI ret; 335 for (bit = 1, ret = 1; bit; bit <<= 1, ret++) 336 { 337 if (val & bit) 338 return ret; 339 } 340 return 0; 341} 342 343/* The find last 1 instruction returns the location of the last set bit in 344 the argument register. */ 345 346USI 347or1k32bf_fl1 (sim_cpu *current_cpu, USI val) 348{ 349 USI bit; 350 USI ret; 351 for (bit = 1 << 31, ret = 32; bit; bit >>= 1, ret--) 352 { 353 if (val & bit) 354 return ret; 355 } 356 return 0; 357} 358