cpuv32.h revision 1.1.1.1
1/* CPU family header for crisv32f. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2010 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23*/ 24 25#ifndef CPU_CRISV32F_H 26#define CPU_CRISV32F_H 27 28/* Maximum number of instructions that are fetched at a time. 29 This is for LIW type instructions sets (e.g. m32r). */ 30#define MAX_LIW_INSNS 1 31 32/* Maximum number of instructions that can be executed in parallel. */ 33#define MAX_PARALLEL_INSNS 1 34 35/* The size of an "int" needed to hold an instruction word. 36 This is usually 32 bits, but some architectures needs 64 bits. */ 37typedef CGEN_INSN_INT CGEN_INSN_WORD; 38 39#include "cgen-engine.h" 40 41/* CPU state information. */ 42typedef struct { 43 /* Hardware elements. */ 44 struct { 45 /* program counter */ 46 USI h_pc; 47#define GET_H_PC() CPU (h_pc) 48#define SET_H_PC(x) \ 49do { \ 50CPU (h_pc) = ANDSI ((x), (~ (1)));\ 51;} while (0) 52 /* General purpose registers */ 53 SI h_gr_acr[16]; 54#define GET_H_GR_ACR(a1) CPU (h_gr_acr)[a1] 55#define SET_H_GR_ACR(a1, x) (CPU (h_gr_acr)[a1] = (x)) 56 /* Special registers for v32 */ 57 SI h_sr_v32[16]; 58#define GET_H_SR_V32(index) (ORIF (ORIF (((index) == (((UINT) 0))), ((index) == (((UINT) 4)))), ((index) == (((UINT) 8))))) ? (0) : (((index) == (((UINT) 1)))) ? (32) : (((index) == (((UINT) 13)))) ? (ORSI (ANDSI (CPU (h_sr_v32[((UINT) 13)]), 1073740800), ORSI (ZEXTBISI (CPU (h_cbit)), ORSI (SLLSI (ZEXTBISI (CPU (h_vbit)), 1), ORSI (SLLSI (ZEXTBISI (CPU (h_zbit)), 2), ORSI (SLLSI (ZEXTBISI (CPU (h_nbit)), 3), ORSI (SLLSI (ZEXTBISI (CPU (h_xbit)), 4), ORSI (SLLSI (ZEXTBISI (GET_H_IBIT ()), 5), ORSI (SLLSI (ZEXTBISI (GET_H_UBIT ()), 6), ORSI (SLLSI (ZEXTBISI (CPU (h_pbit)), 7), ORSI (SLLSI (ZEXTBISI (CPU (h_rbit)), 8), ORSI (SLLSI (ZEXTBISI (CPU (h_sbit)), 9), ORSI (SLLSI (ZEXTBISI (CPU (h_mbit)), 30), ORSI (SLLSI (ZEXTBISI (CPU (h_qbit)), 31), 0)))))))))))))) : (((index) == (((UINT) 14)))) ? (((GET_H_UBIT ()) ? (CPU (h_gr_acr[((UINT) 14)])) : (CPU (h_sr_v32[((UINT) 14)])))) : (CPU (h_sr_v32[index])) 59#define SET_H_SR_V32(index, x) \ 60do { \ 61if (ORIF (ORIF ((((index)) == (((UINT) 0))), (((index)) == (((UINT) 4)))), ORIF ((((index)) == (((UINT) 8))), (((index)) == (((UINT) 1)))))) {\ 62((void) 0); /*nop*/\ 63}\ 64 else if ((((index)) == (((UINT) 13)))) {\ 65{\ 66CPU (h_cbit) = ((NESI (ANDSI ((x), ((1) << (0))), 0)) ? (1) : (0));\ 67CPU (h_vbit) = ((NESI (ANDSI ((x), ((1) << (1))), 0)) ? (1) : (0));\ 68CPU (h_zbit) = ((NESI (ANDSI ((x), ((1) << (2))), 0)) ? (1) : (0));\ 69CPU (h_nbit) = ((NESI (ANDSI ((x), ((1) << (3))), 0)) ? (1) : (0));\ 70CPU (h_xbit) = ((NESI (ANDSI ((x), ((1) << (4))), 0)) ? (1) : (0));\ 71SET_H_IBIT (((NESI (ANDSI ((x), ((1) << (5))), 0)) ? (1) : (0)));\ 72SET_H_SBIT (((NESI (ANDSI ((x), ((1) << (9))), 0)) ? (1) : (0)));\ 73SET_H_MBIT (((NESI (ANDSI ((x), ((1) << (30))), 0)) ? (1) : (0)));\ 74CPU (h_pbit) = ((NESI (ANDSI ((x), ((1) << (7))), 0)) ? (1) : (0));\ 75CPU (h_rbit) = ((NESI (ANDSI ((x), ((1) << (8))), 0)) ? (1) : (0));\ 76SET_H_QBIT (((NESI (ANDSI ((x), ((1) << (31))), 0)) ? (1) : (0)));\ 77SET_H_UBIT (((NESI (ANDSI ((x), ((1) << (6))), 0)) ? (1) : (0)));\ 78CPU (h_sr_v32[(index)]) = (x);\ 79}\ 80}\ 81 else if ((((index)) == (((UINT) 14)))) {\ 82{\ 83if (GET_H_UBIT ()) {\ 84CPU (h_gr_acr[((UINT) 14)]) = (x);\ 85}\ 86CPU (h_sr_v32[((UINT) 14)]) = (x);\ 87}\ 88}\ 89 else if ((((index)) == (((UINT) 3)))) {\ 90if (NOTBI (GET_H_UBIT ())) {\ 91CPU (h_sr_v32[((UINT) 3)]) = (x);\ 92}\ 93}\ 94 else if ((((index)) == (((UINT) 9)))) {\ 95if (NOTBI (GET_H_UBIT ())) {\ 96CPU (h_sr_v32[((UINT) 9)]) = (x);\ 97}\ 98}\ 99 else if ((((index)) == (((UINT) 2)))) {\ 100if (NOTBI (GET_H_UBIT ())) {\ 101{\ 102crisv32f_write_pid_handler (current_cpu, (x));\ 103CPU (h_sr_v32[((UINT) 2)]) = (x);\ 104}\ 105}\ 106}\ 107 else if ((((index)) == (((UINT) 15)))) {\ 108if (NOTBI (GET_H_UBIT ())) {\ 109CPU (h_sr_v32[((UINT) 15)]) = (x);\ 110}\ 111}\ 112 else {\ 113CPU (h_sr_v32[(index)]) = (x);\ 114}\ 115;} while (0) 116 /* carry bit */ 117 BI h_cbit; 118#define GET_H_CBIT() CPU (h_cbit) 119#define SET_H_CBIT(x) (CPU (h_cbit) = (x)) 120 /* overflow bit */ 121 BI h_vbit; 122#define GET_H_VBIT() CPU (h_vbit) 123#define SET_H_VBIT(x) (CPU (h_vbit) = (x)) 124 /* zero bit */ 125 BI h_zbit; 126#define GET_H_ZBIT() CPU (h_zbit) 127#define SET_H_ZBIT(x) (CPU (h_zbit) = (x)) 128 /* sign bit */ 129 BI h_nbit; 130#define GET_H_NBIT() CPU (h_nbit) 131#define SET_H_NBIT(x) (CPU (h_nbit) = (x)) 132 /* extended-arithmetic bit */ 133 BI h_xbit; 134#define GET_H_XBIT() CPU (h_xbit) 135#define SET_H_XBIT(x) (CPU (h_xbit) = (x)) 136 /* sequence-broken bit */ 137 BI h_pbit; 138#define GET_H_PBIT() CPU (h_pbit) 139#define SET_H_PBIT(x) (CPU (h_pbit) = (x)) 140 /* carry bit for MCP+restore-p bit */ 141 BI h_rbit; 142#define GET_H_RBIT() CPU (h_rbit) 143#define SET_H_RBIT(x) (CPU (h_rbit) = (x)) 144 /* guru mode bit */ 145 BI h_gbit; 146#define GET_H_GBIT() CPU (h_gbit) 147#define SET_H_GBIT(x) (CPU (h_gbit) = (x)) 148 /* Kernel stack pointer during user mode */ 149 SI h_kernel_sp; 150#define GET_H_KERNEL_SP() CPU (h_kernel_sp) 151#define SET_H_KERNEL_SP(x) (CPU (h_kernel_sp) = (x)) 152 /* User mode bit */ 153 BI h_ubit_v32; 154#define GET_H_UBIT_V32() CPU (h_ubit_v32) 155#define SET_H_UBIT_V32(x) \ 156do { \ 157{\ 158if (ANDIF ((x), NOTBI (CPU (h_ubit_v32)))) {\ 159{\ 160CPU (h_kernel_sp) = CPU (h_gr_acr[((UINT) 14)]);\ 161CPU (h_gr_acr[((UINT) 14)]) = CPU (h_sr_v32[((UINT) 14)]);\ 162CPU (h_ubit_v32) = (x);\ 163crisv32f_usermode_enabled (current_cpu);\ 164}\ 165}\ 166}\ 167;} while (0) 168 /* Interrupt-enable bit */ 169 BI h_ibit_v32; 170#define GET_H_IBIT_V32() CPU (h_ibit_v32) 171#define SET_H_IBIT_V32(x) \ 172do { \ 173{\ 174if (NOTBI (GET_H_UBIT ())) {\ 175{\ 176 BI tmp_enabled;\ 177 tmp_enabled = ANDIF ((x), NOTBI (CPU (h_ibit_v32)));\ 178CPU (h_ibit_v32) = (x);\ 179if (tmp_enabled) {\ 180crisv32f_interrupts_enabled (current_cpu);\ 181}\ 182}\ 183}\ 184}\ 185;} while (0) 186 /* NMI enable bit */ 187 BI h_mbit; 188#define GET_H_MBIT() CPU (h_mbit) 189#define SET_H_MBIT(x) \ 190do { \ 191{\ 192if (ANDIF ((x), ANDIF (NOTBI (CPU (h_mbit)), NOTBI (GET_H_UBIT ())))) {\ 193{\ 194CPU (h_mbit) = 1;\ 195crisv32f_nmi_enabled (current_cpu);\ 196}\ 197}\ 198}\ 199;} while (0) 200 /* Pending single-step bit */ 201 BI h_qbit; 202#define GET_H_QBIT() CPU (h_qbit) 203#define SET_H_QBIT(x) \ 204do { \ 205{\ 206if (NOTBI (GET_H_UBIT ())) {\ 207CPU (h_qbit) = (x);\ 208}\ 209}\ 210;} while (0) 211 /* Cause single step exception on ... [see CRISv32 ref] bit */ 212 BI h_sbit; 213#define GET_H_SBIT() CPU (h_sbit) 214#define SET_H_SBIT(x) \ 215do { \ 216{\ 217if (NOTBI (GET_H_UBIT ())) {\ 218{\ 219 BI tmp_enabled;\ 220 tmp_enabled = ANDIF ((x), NOTBI (CPU (h_sbit)));\ 221CPU (h_sbit) = (x);\ 222if (tmp_enabled) {\ 223crisv32f_single_step_enabled (current_cpu);\ 224}\ 225}\ 226}\ 227}\ 228;} while (0) 229 } hardware; 230#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) 231} CRISV32F_CPU_DATA; 232 233/* Virtual regs. */ 234 235#define GET_H_V32_V32() 1 236#define SET_H_V32_V32(x) \ 237do { \ 238cgen_rtx_error (current_cpu, "Can't set h-v32");\ 239;} while (0) 240#define GET_H_GR(index) CPU (h_gr_acr[index]) 241#define SET_H_GR(index, x) \ 242do { \ 243CPU (h_gr_acr[(index)]) = (x);\ 244;} while (0) 245#define GET_H_RAW_GR_ACR(index) CPU (h_gr_acr[index]) 246#define SET_H_RAW_GR_ACR(index, x) \ 247do { \ 248CPU (h_gr_acr[(index)]) = (x);\ 249;} while (0) 250#define GET_H_SR(index) GET_H_SR_V32 (index) 251#define SET_H_SR(index, x) \ 252do { \ 253SET_H_SR_V32 ((index), (x));\ 254;} while (0) 255#define GET_H_SUPR(index) crisv32f_read_supr (current_cpu, index) 256#define SET_H_SUPR(index, x) \ 257do { \ 258crisv32f_write_supr (current_cpu, (index), (x));\ 259;} while (0) 260#define GET_H_CBIT_MOVE() GET_H_CBIT_MOVE_V32 () 261#define SET_H_CBIT_MOVE(x) \ 262do { \ 263SET_H_CBIT_MOVE_V32 ((x));\ 264;} while (0) 265#define GET_H_CBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-cbit-move on CRISv32"), 0) 266#define SET_H_CBIT_MOVE_V32(x) \ 267do { \ 268((void) 0); /*nop*/\ 269;} while (0) 270#define GET_H_VBIT_MOVE() GET_H_VBIT_MOVE_V32 () 271#define SET_H_VBIT_MOVE(x) \ 272do { \ 273SET_H_VBIT_MOVE_V32 ((x));\ 274;} while (0) 275#define GET_H_VBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-vbit-move on CRISv32"), 0) 276#define SET_H_VBIT_MOVE_V32(x) \ 277do { \ 278((void) 0); /*nop*/\ 279;} while (0) 280#define GET_H_ZBIT_MOVE() GET_H_ZBIT_MOVE_V32 () 281#define SET_H_ZBIT_MOVE(x) \ 282do { \ 283SET_H_ZBIT_MOVE_V32 ((x));\ 284;} while (0) 285#define GET_H_ZBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-zbit-move on CRISv32"), 0) 286#define SET_H_ZBIT_MOVE_V32(x) \ 287do { \ 288((void) 0); /*nop*/\ 289;} while (0) 290#define GET_H_NBIT_MOVE() GET_H_NBIT_MOVE_V32 () 291#define SET_H_NBIT_MOVE(x) \ 292do { \ 293SET_H_NBIT_MOVE_V32 ((x));\ 294;} while (0) 295#define GET_H_NBIT_MOVE_V32() (cgen_rtx_error (current_cpu, "Can't get h-nbit-move on CRISv32"), 0) 296#define SET_H_NBIT_MOVE_V32(x) \ 297do { \ 298((void) 0); /*nop*/\ 299;} while (0) 300#define GET_H_IBIT() CPU (h_ibit_v32) 301#define SET_H_IBIT(x) \ 302do { \ 303SET_H_IBIT_V32 ((x));\ 304;} while (0) 305#define GET_H_UBIT() CPU (h_ubit_v32) 306#define SET_H_UBIT(x) \ 307do { \ 308SET_H_UBIT_V32 ((x));\ 309;} while (0) 310#define GET_H_INSN_PREFIXED_P() GET_H_INSN_PREFIXED_P_V32 () 311#define SET_H_INSN_PREFIXED_P(x) \ 312do { \ 313SET_H_INSN_PREFIXED_P_V32 ((x));\ 314;} while (0) 315#define GET_H_INSN_PREFIXED_P_V32() 0 316#define SET_H_INSN_PREFIXED_P_V32(x) \ 317do { \ 318((void) 0); /*nop*/\ 319;} while (0) 320#define GET_H_PREFIXREG_V32() GET_H_GR (((UINT) 15)) 321#define SET_H_PREFIXREG_V32(x) \ 322do { \ 323SET_H_GR (((UINT) 15), (x));\ 324;} while (0) 325 326/* Cover fns for register access. */ 327BI crisv32f_h_v32_v32_get (SIM_CPU *); 328void crisv32f_h_v32_v32_set (SIM_CPU *, BI); 329USI crisv32f_h_pc_get (SIM_CPU *); 330void crisv32f_h_pc_set (SIM_CPU *, USI); 331SI crisv32f_h_gr_get (SIM_CPU *, UINT); 332void crisv32f_h_gr_set (SIM_CPU *, UINT, SI); 333SI crisv32f_h_gr_acr_get (SIM_CPU *, UINT); 334void crisv32f_h_gr_acr_set (SIM_CPU *, UINT, SI); 335SI crisv32f_h_raw_gr_acr_get (SIM_CPU *, UINT); 336void crisv32f_h_raw_gr_acr_set (SIM_CPU *, UINT, SI); 337SI crisv32f_h_sr_get (SIM_CPU *, UINT); 338void crisv32f_h_sr_set (SIM_CPU *, UINT, SI); 339SI crisv32f_h_sr_v32_get (SIM_CPU *, UINT); 340void crisv32f_h_sr_v32_set (SIM_CPU *, UINT, SI); 341SI crisv32f_h_supr_get (SIM_CPU *, UINT); 342void crisv32f_h_supr_set (SIM_CPU *, UINT, SI); 343BI crisv32f_h_cbit_get (SIM_CPU *); 344void crisv32f_h_cbit_set (SIM_CPU *, BI); 345BI crisv32f_h_cbit_move_get (SIM_CPU *); 346void crisv32f_h_cbit_move_set (SIM_CPU *, BI); 347BI crisv32f_h_cbit_move_v32_get (SIM_CPU *); 348void crisv32f_h_cbit_move_v32_set (SIM_CPU *, BI); 349BI crisv32f_h_vbit_get (SIM_CPU *); 350void crisv32f_h_vbit_set (SIM_CPU *, BI); 351BI crisv32f_h_vbit_move_get (SIM_CPU *); 352void crisv32f_h_vbit_move_set (SIM_CPU *, BI); 353BI crisv32f_h_vbit_move_v32_get (SIM_CPU *); 354void crisv32f_h_vbit_move_v32_set (SIM_CPU *, BI); 355BI crisv32f_h_zbit_get (SIM_CPU *); 356void crisv32f_h_zbit_set (SIM_CPU *, BI); 357BI crisv32f_h_zbit_move_get (SIM_CPU *); 358void crisv32f_h_zbit_move_set (SIM_CPU *, BI); 359BI crisv32f_h_zbit_move_v32_get (SIM_CPU *); 360void crisv32f_h_zbit_move_v32_set (SIM_CPU *, BI); 361BI crisv32f_h_nbit_get (SIM_CPU *); 362void crisv32f_h_nbit_set (SIM_CPU *, BI); 363BI crisv32f_h_nbit_move_get (SIM_CPU *); 364void crisv32f_h_nbit_move_set (SIM_CPU *, BI); 365BI crisv32f_h_nbit_move_v32_get (SIM_CPU *); 366void crisv32f_h_nbit_move_v32_set (SIM_CPU *, BI); 367BI crisv32f_h_xbit_get (SIM_CPU *); 368void crisv32f_h_xbit_set (SIM_CPU *, BI); 369BI crisv32f_h_ibit_get (SIM_CPU *); 370void crisv32f_h_ibit_set (SIM_CPU *, BI); 371BI crisv32f_h_pbit_get (SIM_CPU *); 372void crisv32f_h_pbit_set (SIM_CPU *, BI); 373BI crisv32f_h_rbit_get (SIM_CPU *); 374void crisv32f_h_rbit_set (SIM_CPU *, BI); 375BI crisv32f_h_ubit_get (SIM_CPU *); 376void crisv32f_h_ubit_set (SIM_CPU *, BI); 377BI crisv32f_h_gbit_get (SIM_CPU *); 378void crisv32f_h_gbit_set (SIM_CPU *, BI); 379SI crisv32f_h_kernel_sp_get (SIM_CPU *); 380void crisv32f_h_kernel_sp_set (SIM_CPU *, SI); 381BI crisv32f_h_ubit_v32_get (SIM_CPU *); 382void crisv32f_h_ubit_v32_set (SIM_CPU *, BI); 383BI crisv32f_h_ibit_v32_get (SIM_CPU *); 384void crisv32f_h_ibit_v32_set (SIM_CPU *, BI); 385BI crisv32f_h_mbit_get (SIM_CPU *); 386void crisv32f_h_mbit_set (SIM_CPU *, BI); 387BI crisv32f_h_qbit_get (SIM_CPU *); 388void crisv32f_h_qbit_set (SIM_CPU *, BI); 389BI crisv32f_h_sbit_get (SIM_CPU *); 390void crisv32f_h_sbit_set (SIM_CPU *, BI); 391BI crisv32f_h_insn_prefixed_p_get (SIM_CPU *); 392void crisv32f_h_insn_prefixed_p_set (SIM_CPU *, BI); 393BI crisv32f_h_insn_prefixed_p_v32_get (SIM_CPU *); 394void crisv32f_h_insn_prefixed_p_v32_set (SIM_CPU *, BI); 395SI crisv32f_h_prefixreg_v32_get (SIM_CPU *); 396void crisv32f_h_prefixreg_v32_set (SIM_CPU *, SI); 397 398/* These must be hand-written. */ 399extern CPUREG_FETCH_FN crisv32f_fetch_register; 400extern CPUREG_STORE_FN crisv32f_store_register; 401 402typedef struct { 403 UINT prev_prev_prev_modf_regs; 404 UINT prev_prev_modf_regs; 405 UINT prev_modf_regs; 406 UINT modf_regs; 407 UINT prev_prev_prev_movem_dest_regs; 408 UINT prev_prev_movem_dest_regs; 409 UINT prev_movem_dest_regs; 410 UINT movem_dest_regs; 411} MODEL_CRISV32_DATA; 412 413/* Instruction argument buffer. */ 414 415union sem_fields { 416 struct { /* no operands */ 417 int empty; 418 } sfmt_empty; 419 struct { /* */ 420 UINT f_u4; 421 } sfmt_break; 422 struct { /* */ 423 UINT f_dstsrc; 424 } sfmt_setf; 425 struct { /* */ 426 IADDR i_o_word_pcrel; 427 UINT f_operand2; 428 } sfmt_bcc_w; 429 struct { /* */ 430 IADDR i_o_pcrel; 431 UINT f_operand2; 432 } sfmt_bcc_b; 433 struct { /* */ 434 unsigned char in_h_sr_SI_13; 435 unsigned char out_h_sr_SI_13; 436 } sfmt_rfe; 437 struct { /* */ 438 INT f_s8; 439 UINT f_operand2; 440 unsigned char in_Rd; 441 } sfmt_addoq; 442 struct { /* */ 443 ADDR i_const32_pcrel; 444 UINT f_operand2; 445 unsigned char out_Pd; 446 } sfmt_bas_c; 447 struct { /* */ 448 ADDR i_qo; 449 UINT f_operand2; 450 unsigned char out_Rd; 451 } sfmt_lapcq; 452 struct { /* */ 453 ADDR i_const32_pcrel; 454 UINT f_operand2; 455 unsigned char out_Rd; 456 } sfmt_lapc_d; 457 struct { /* */ 458 INT f_indir_pc__dword; 459 UINT f_operand2; 460 unsigned char out_Pd; 461 } sfmt_move_c_sprv32_p2; 462 struct { /* */ 463 INT f_s6; 464 UINT f_operand2; 465 unsigned char out_Rd; 466 } sfmt_moveq; 467 struct { /* */ 468 INT f_indir_pc__dword; 469 UINT f_operand2; 470 unsigned char in_Rd; 471 unsigned char out_Rd; 472 } sfmt_bound_cd; 473 struct { /* */ 474 INT f_indir_pc__word; 475 UINT f_operand2; 476 unsigned char in_Rd; 477 unsigned char out_Rd; 478 } sfmt_bound_cw; 479 struct { /* */ 480 INT f_indir_pc__byte; 481 UINT f_operand2; 482 unsigned char in_Rd; 483 unsigned char out_Rd; 484 } sfmt_bound_cb; 485 struct { /* */ 486 UINT f_operand2; 487 UINT f_u5; 488 unsigned char in_Rd; 489 unsigned char out_Rd; 490 } sfmt_asrq; 491 struct { /* */ 492 INT f_s6; 493 UINT f_operand2; 494 unsigned char in_Rd; 495 unsigned char out_h_gr_SI_index_of__INT_Rd; 496 } sfmt_andq; 497 struct { /* */ 498 INT f_indir_pc__dword; 499 UINT f_operand2; 500 unsigned char in_Rd; 501 unsigned char out_h_gr_SI_index_of__INT_Rd; 502 } sfmt_addcdr; 503 struct { /* */ 504 INT f_indir_pc__word; 505 UINT f_operand2; 506 unsigned char in_Rd; 507 unsigned char out_h_gr_SI_index_of__INT_Rd; 508 } sfmt_addcwr; 509 struct { /* */ 510 INT f_indir_pc__byte; 511 UINT f_operand2; 512 unsigned char in_Rd; 513 unsigned char out_h_gr_SI_index_of__INT_Rd; 514 } sfmt_addcbr; 515 struct { /* */ 516 UINT f_operand2; 517 UINT f_u6; 518 unsigned char in_Rd; 519 unsigned char out_h_gr_SI_index_of__INT_Rd; 520 } sfmt_addq; 521 struct { /* */ 522 UINT f_operand1; 523 UINT f_operand2; 524 unsigned char in_Ps; 525 unsigned char in_Rs; 526 unsigned char out_h_gr_SI_index_of__INT_Rs; 527 } sfmt_mcp; 528 struct { /* */ 529 UINT f_operand1; 530 UINT f_operand2; 531 unsigned char in_Rd; 532 unsigned char in_Rs; 533 unsigned char out_Rd; 534 unsigned char out_h_sr_SI_7; 535 } sfmt_muls_b; 536 struct { /* */ 537 UINT f_memmode; 538 UINT f_operand1; 539 UINT f_operand2; 540 unsigned char in_Ps; 541 unsigned char in_Rs; 542 unsigned char out_Rs; 543 } sfmt_move_spr_mv32; 544 struct { /* */ 545 UINT f_memmode; 546 UINT f_operand1; 547 UINT f_operand2; 548 unsigned char in_Rs; 549 unsigned char out_Pd; 550 unsigned char out_Rs; 551 } sfmt_move_m_sprv32; 552 struct { /* */ 553 UINT f_memmode; 554 UINT f_operand1; 555 UINT f_operand2; 556 unsigned char in_Rs; 557 unsigned char out_Rd; 558 unsigned char out_Rs; 559 } sfmt_movs_m_b_m; 560 struct { /* */ 561 UINT f_memmode; 562 UINT f_operand1; 563 UINT f_operand2; 564 unsigned char in_Rd; 565 unsigned char in_Rs; 566 unsigned char out_Rs; 567 unsigned char out_h_gr_SI_index_of__INT_Rd; 568 } sfmt_addc_m; 569 struct { /* */ 570 UINT f_memmode; 571 UINT f_operand1; 572 UINT f_operand2; 573 unsigned char in_Rd; 574 unsigned char in_Rs; 575 unsigned char out_Rs; 576 unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__UINT_inc_index_of__INT_Rs_index_of__INT_Rd; 577 } sfmt_add_m_b_m; 578 struct { /* */ 579 UINT f_memmode; 580 UINT f_operand1; 581 UINT f_operand2; 582 unsigned char in_Rd; 583 unsigned char in_Rs; 584 unsigned char out_Rs; 585 unsigned char out_h_gr_SI_0; 586 unsigned char out_h_gr_SI_1; 587 unsigned char out_h_gr_SI_10; 588 unsigned char out_h_gr_SI_11; 589 unsigned char out_h_gr_SI_12; 590 unsigned char out_h_gr_SI_13; 591 unsigned char out_h_gr_SI_14; 592 unsigned char out_h_gr_SI_15; 593 unsigned char out_h_gr_SI_2; 594 unsigned char out_h_gr_SI_3; 595 unsigned char out_h_gr_SI_4; 596 unsigned char out_h_gr_SI_5; 597 unsigned char out_h_gr_SI_6; 598 unsigned char out_h_gr_SI_7; 599 unsigned char out_h_gr_SI_8; 600 unsigned char out_h_gr_SI_9; 601 } sfmt_movem_m_r_v32; 602 struct { /* */ 603 UINT f_memmode; 604 UINT f_operand1; 605 UINT f_operand2; 606 unsigned char in_Rd; 607 unsigned char in_Rs; 608 unsigned char in_h_gr_SI_0; 609 unsigned char in_h_gr_SI_1; 610 unsigned char in_h_gr_SI_10; 611 unsigned char in_h_gr_SI_11; 612 unsigned char in_h_gr_SI_12; 613 unsigned char in_h_gr_SI_13; 614 unsigned char in_h_gr_SI_14; 615 unsigned char in_h_gr_SI_15; 616 unsigned char in_h_gr_SI_2; 617 unsigned char in_h_gr_SI_3; 618 unsigned char in_h_gr_SI_4; 619 unsigned char in_h_gr_SI_5; 620 unsigned char in_h_gr_SI_6; 621 unsigned char in_h_gr_SI_7; 622 unsigned char in_h_gr_SI_8; 623 unsigned char in_h_gr_SI_9; 624 unsigned char out_Rs; 625 } sfmt_movem_r_m_v32; 626#if WITH_SCACHE_PBB 627 /* Writeback handler. */ 628 struct { 629 /* Pointer to argbuf entry for insn whose results need writing back. */ 630 const struct argbuf *abuf; 631 } write; 632 /* x-before handler */ 633 struct { 634 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/ 635 int first_p; 636 } before; 637 /* x-after handler */ 638 struct { 639 int empty; 640 } after; 641 /* This entry is used to terminate each pbb. */ 642 struct { 643 /* Number of insns in pbb. */ 644 int insn_count; 645 /* Next pbb to execute. */ 646 SCACHE *next; 647 SCACHE *branch_target; 648 } chain; 649#endif 650}; 651 652/* The ARGBUF struct. */ 653struct argbuf { 654 /* These are the baseclass definitions. */ 655 IADDR addr; 656 const IDESC *idesc; 657 char trace_p; 658 char profile_p; 659 /* ??? Temporary hack for skip insns. */ 660 char skip_count; 661 char unused; 662 /* cpu specific data follows */ 663 union sem semantic; 664 int written; 665 union sem_fields fields; 666}; 667 668/* A cached insn. 669 670 ??? SCACHE used to contain more than just argbuf. We could delete the 671 type entirely and always just use ARGBUF, but for future concerns and as 672 a level of abstraction it is left in. */ 673 674struct scache { 675 struct argbuf argbuf; 676}; 677 678/* Macros to simplify extraction, reading and semantic code. 679 These define and assign the local vars that contain the insn's fields. */ 680 681#define EXTRACT_IFMT_EMPTY_VARS \ 682 unsigned int length; 683#define EXTRACT_IFMT_EMPTY_CODE \ 684 length = 0; \ 685 686#define EXTRACT_IFMT_MOVE_B_R_VARS \ 687 UINT f_operand2; \ 688 UINT f_mode; \ 689 UINT f_opcode; \ 690 UINT f_size; \ 691 UINT f_operand1; \ 692 unsigned int length; 693#define EXTRACT_IFMT_MOVE_B_R_CODE \ 694 length = 2; \ 695 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 696 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 697 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 698 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 699 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 700 701#define EXTRACT_IFMT_MOVEQ_VARS \ 702 UINT f_operand2; \ 703 UINT f_mode; \ 704 UINT f_opcode; \ 705 INT f_s6; \ 706 unsigned int length; 707#define EXTRACT_IFMT_MOVEQ_CODE \ 708 length = 2; \ 709 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 710 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 711 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 712 f_s6 = EXTRACT_LSB0_SINT (insn, 16, 5, 6); \ 713 714#define EXTRACT_IFMT_MOVECBR_VARS \ 715 UINT f_operand2; \ 716 INT f_indir_pc__byte; \ 717 UINT f_mode; \ 718 UINT f_opcode; \ 719 UINT f_size; \ 720 UINT f_operand1; \ 721 /* Contents of trailing part of insn. */ \ 722 UINT word_1; \ 723 unsigned int length; 724#define EXTRACT_IFMT_MOVECBR_CODE \ 725 length = 4; \ 726 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 727 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 728 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ 729 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 730 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 731 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 732 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 733 734#define EXTRACT_IFMT_MOVECWR_VARS \ 735 UINT f_operand2; \ 736 INT f_indir_pc__word; \ 737 UINT f_mode; \ 738 UINT f_opcode; \ 739 UINT f_size; \ 740 UINT f_operand1; \ 741 /* Contents of trailing part of insn. */ \ 742 UINT word_1; \ 743 unsigned int length; 744#define EXTRACT_IFMT_MOVECWR_CODE \ 745 length = 4; \ 746 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 747 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 748 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ 749 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 750 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 751 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 752 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 753 754#define EXTRACT_IFMT_MOVECDR_VARS \ 755 INT f_indir_pc__dword; \ 756 UINT f_operand2; \ 757 UINT f_mode; \ 758 UINT f_opcode; \ 759 UINT f_size; \ 760 UINT f_operand1; \ 761 /* Contents of trailing part of insn. */ \ 762 UINT word_1; \ 763 unsigned int length; 764#define EXTRACT_IFMT_MOVECDR_CODE \ 765 length = 6; \ 766 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 767 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ 768 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 769 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 770 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 771 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 772 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 773 774#define EXTRACT_IFMT_MOVUCBR_VARS \ 775 UINT f_operand2; \ 776 INT f_indir_pc__byte; \ 777 UINT f_mode; \ 778 UINT f_opcode; \ 779 UINT f_size; \ 780 UINT f_operand1; \ 781 /* Contents of trailing part of insn. */ \ 782 UINT word_1; \ 783 unsigned int length; 784#define EXTRACT_IFMT_MOVUCBR_CODE \ 785 length = 4; \ 786 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 787 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 788 f_indir_pc__byte = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ 789 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 790 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 791 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 792 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 793 794#define EXTRACT_IFMT_MOVUCWR_VARS \ 795 UINT f_operand2; \ 796 INT f_indir_pc__word; \ 797 UINT f_mode; \ 798 UINT f_opcode; \ 799 UINT f_size; \ 800 UINT f_operand1; \ 801 /* Contents of trailing part of insn. */ \ 802 UINT word_1; \ 803 unsigned int length; 804#define EXTRACT_IFMT_MOVUCWR_CODE \ 805 length = 4; \ 806 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 807 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 808 f_indir_pc__word = (0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)); \ 809 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 810 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 811 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 812 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 813 814#define EXTRACT_IFMT_ADDQ_VARS \ 815 UINT f_operand2; \ 816 UINT f_mode; \ 817 UINT f_opcode; \ 818 UINT f_u6; \ 819 unsigned int length; 820#define EXTRACT_IFMT_ADDQ_CODE \ 821 length = 2; \ 822 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 823 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 824 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 825 f_u6 = EXTRACT_LSB0_UINT (insn, 16, 5, 6); \ 826 827#define EXTRACT_IFMT_CMP_M_B_M_VARS \ 828 UINT f_operand2; \ 829 UINT f_membit; \ 830 UINT f_memmode; \ 831 UINT f_opcode; \ 832 UINT f_size; \ 833 UINT f_operand1; \ 834 unsigned int length; 835#define EXTRACT_IFMT_CMP_M_B_M_CODE \ 836 length = 2; \ 837 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 838 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ 839 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ 840 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 841 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 842 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 843 844#define EXTRACT_IFMT_MOVE_R_SPRV32_VARS \ 845 UINT f_operand2; \ 846 UINT f_mode; \ 847 UINT f_opcode; \ 848 UINT f_size; \ 849 UINT f_operand1; \ 850 unsigned int length; 851#define EXTRACT_IFMT_MOVE_R_SPRV32_CODE \ 852 length = 2; \ 853 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 854 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 855 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 856 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 857 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 858 859#define EXTRACT_IFMT_MOVE_SPR_RV32_VARS \ 860 UINT f_operand2; \ 861 UINT f_mode; \ 862 UINT f_opcode; \ 863 UINT f_size; \ 864 UINT f_operand1; \ 865 unsigned int length; 866#define EXTRACT_IFMT_MOVE_SPR_RV32_CODE \ 867 length = 2; \ 868 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 869 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 870 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 871 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 872 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 873 874#define EXTRACT_IFMT_MOVE_M_SPRV32_VARS \ 875 UINT f_operand2; \ 876 UINT f_membit; \ 877 UINT f_memmode; \ 878 UINT f_opcode; \ 879 UINT f_size; \ 880 UINT f_operand1; \ 881 unsigned int length; 882#define EXTRACT_IFMT_MOVE_M_SPRV32_CODE \ 883 length = 2; \ 884 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 885 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ 886 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ 887 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 888 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 889 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 890 891#define EXTRACT_IFMT_MOVE_C_SPRV32_P2_VARS \ 892 INT f_indir_pc__dword; \ 893 UINT f_operand2; \ 894 UINT f_mode; \ 895 UINT f_opcode; \ 896 UINT f_size; \ 897 UINT f_operand1; \ 898 /* Contents of trailing part of insn. */ \ 899 UINT word_1; \ 900 unsigned int length; 901#define EXTRACT_IFMT_MOVE_C_SPRV32_P2_CODE \ 902 length = 6; \ 903 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 904 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ 905 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 906 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 907 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 908 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 909 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 910 911#define EXTRACT_IFMT_MOVE_SPR_MV32_VARS \ 912 UINT f_operand2; \ 913 UINT f_membit; \ 914 UINT f_memmode; \ 915 UINT f_opcode; \ 916 UINT f_size; \ 917 UINT f_operand1; \ 918 unsigned int length; 919#define EXTRACT_IFMT_MOVE_SPR_MV32_CODE \ 920 length = 2; \ 921 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 922 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ 923 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ 924 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 925 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 926 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 927 928#define EXTRACT_IFMT_MOVE_SS_R_VARS \ 929 UINT f_operand2; \ 930 UINT f_mode; \ 931 UINT f_opcode; \ 932 UINT f_size; \ 933 UINT f_operand1; \ 934 unsigned int length; 935#define EXTRACT_IFMT_MOVE_SS_R_CODE \ 936 length = 2; \ 937 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 938 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 939 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 940 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 941 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 942 943#define EXTRACT_IFMT_MOVE_R_SS_VARS \ 944 UINT f_operand2; \ 945 UINT f_mode; \ 946 UINT f_opcode; \ 947 UINT f_size; \ 948 UINT f_operand1; \ 949 unsigned int length; 950#define EXTRACT_IFMT_MOVE_R_SS_CODE \ 951 length = 2; \ 952 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 953 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 954 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 955 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 956 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 957 958#define EXTRACT_IFMT_LAPC_D_VARS \ 959 SI f_indir_pc__dword_pcrel; \ 960 UINT f_operand2; \ 961 UINT f_mode; \ 962 UINT f_opcode; \ 963 UINT f_size; \ 964 UINT f_operand1; \ 965 /* Contents of trailing part of insn. */ \ 966 UINT word_1; \ 967 unsigned int length; 968#define EXTRACT_IFMT_LAPC_D_CODE \ 969 length = 6; \ 970 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 971 f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \ 972 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 973 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 974 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 975 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 976 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 977 978#define EXTRACT_IFMT_LAPCQ_VARS \ 979 UINT f_operand2; \ 980 UINT f_mode; \ 981 UINT f_opcode; \ 982 UINT f_size; \ 983 SI f_qo; \ 984 unsigned int length; 985#define EXTRACT_IFMT_LAPCQ_CODE \ 986 length = 2; \ 987 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 988 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 989 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 990 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 991 f_qo = ((pc) + (((EXTRACT_LSB0_UINT (insn, 16, 3, 4)) << (1)))); \ 992 993#define EXTRACT_IFMT_TEST_M_B_M_VARS \ 994 UINT f_operand2; \ 995 UINT f_membit; \ 996 UINT f_memmode; \ 997 UINT f_opcode; \ 998 UINT f_size; \ 999 UINT f_operand1; \ 1000 unsigned int length; 1001#define EXTRACT_IFMT_TEST_M_B_M_CODE \ 1002 length = 2; \ 1003 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1004 f_membit = EXTRACT_LSB0_UINT (insn, 16, 11, 1); \ 1005 f_memmode = EXTRACT_LSB0_UINT (insn, 16, 10, 1); \ 1006 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1007 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1008 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1009 1010#define EXTRACT_IFMT_SWAP_VARS \ 1011 UINT f_operand2; \ 1012 UINT f_mode; \ 1013 UINT f_opcode; \ 1014 UINT f_size; \ 1015 UINT f_operand1; \ 1016 unsigned int length; 1017#define EXTRACT_IFMT_SWAP_CODE \ 1018 length = 2; \ 1019 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1020 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1021 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1022 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1023 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1024 1025#define EXTRACT_IFMT_ASRQ_VARS \ 1026 UINT f_operand2; \ 1027 UINT f_mode; \ 1028 UINT f_opcode; \ 1029 UINT f_b5; \ 1030 UINT f_u5; \ 1031 unsigned int length; 1032#define EXTRACT_IFMT_ASRQ_CODE \ 1033 length = 2; \ 1034 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1035 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1036 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1037 f_b5 = EXTRACT_LSB0_UINT (insn, 16, 5, 1); \ 1038 f_u5 = EXTRACT_LSB0_UINT (insn, 16, 4, 5); \ 1039 1040#define EXTRACT_IFMT_SETF_VARS \ 1041 UINT f_mode; \ 1042 UINT f_opcode; \ 1043 UINT f_size; \ 1044 UINT f_operand2; \ 1045 UINT f_operand1; \ 1046 UINT f_dstsrc; \ 1047 unsigned int length; 1048#define EXTRACT_IFMT_SETF_CODE \ 1049 length = 2; \ 1050 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1051 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1052 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1053 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1054 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1055 f_dstsrc = ((((f_operand1) | (((f_operand2) << (4))))) & (255));\ 1056 1057#define EXTRACT_IFMT_RFE_VARS \ 1058 UINT f_operand2; \ 1059 UINT f_mode; \ 1060 UINT f_opcode; \ 1061 UINT f_size; \ 1062 UINT f_operand1; \ 1063 unsigned int length; 1064#define EXTRACT_IFMT_RFE_CODE \ 1065 length = 2; \ 1066 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1067 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1068 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1069 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1070 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1071 1072#define EXTRACT_IFMT_BCC_B_VARS \ 1073 UINT f_operand2; \ 1074 UINT f_mode; \ 1075 UINT f_opcode_hi; \ 1076 INT f_disp9_hi; \ 1077 UINT f_disp9_lo; \ 1078 INT f_disp9; \ 1079 unsigned int length; 1080#define EXTRACT_IFMT_BCC_B_CODE \ 1081 length = 2; \ 1082 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1083 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1084 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ 1085 f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \ 1086 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \ 1087{\ 1088 SI tmp_abslo;\ 1089 SI tmp_absval;\ 1090 tmp_abslo = ((f_disp9_lo) << (1));\ 1091 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\ 1092 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\ 1093}\ 1094 1095#define EXTRACT_IFMT_BA_B_VARS \ 1096 UINT f_operand2; \ 1097 UINT f_mode; \ 1098 UINT f_opcode_hi; \ 1099 INT f_disp9_hi; \ 1100 UINT f_disp9_lo; \ 1101 INT f_disp9; \ 1102 unsigned int length; 1103#define EXTRACT_IFMT_BA_B_CODE \ 1104 length = 2; \ 1105 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1106 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1107 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ 1108 f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \ 1109 f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \ 1110{\ 1111 SI tmp_abslo;\ 1112 SI tmp_absval;\ 1113 tmp_abslo = ((f_disp9_lo) << (1));\ 1114 tmp_absval = ((((((f_disp9_hi) != (0))) ? ((~ (255))) : (0))) | (tmp_abslo));\ 1115 f_disp9 = ((((pc) + (tmp_absval))) + (((GET_H_V32_V32 ()) ? (0) : (2))));\ 1116}\ 1117 1118#define EXTRACT_IFMT_BCC_W_VARS \ 1119 UINT f_operand2; \ 1120 SI f_indir_pc__word_pcrel; \ 1121 UINT f_mode; \ 1122 UINT f_opcode; \ 1123 UINT f_size; \ 1124 UINT f_operand1; \ 1125 /* Contents of trailing part of insn. */ \ 1126 UINT word_1; \ 1127 unsigned int length; 1128#define EXTRACT_IFMT_BCC_W_CODE \ 1129 length = 4; \ 1130 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 1131 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1132 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \ 1133 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1134 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1135 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1136 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1137 1138#define EXTRACT_IFMT_BA_W_VARS \ 1139 UINT f_operand2; \ 1140 SI f_indir_pc__word_pcrel; \ 1141 UINT f_mode; \ 1142 UINT f_opcode; \ 1143 UINT f_size; \ 1144 UINT f_operand1; \ 1145 /* Contents of trailing part of insn. */ \ 1146 UINT word_1; \ 1147 unsigned int length; 1148#define EXTRACT_IFMT_BA_W_CODE \ 1149 length = 4; \ 1150 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 1151 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1152 f_indir_pc__word_pcrel = ((EXTHISI (((HI) (UINT) ((0|(EXTRACT_LSB0_UINT (word_1, 32, 15, 16) << 0)))))) + (((pc) + (((GET_H_V32_V32 ()) ? (0) : (4)))))); \ 1153 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1154 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1155 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1156 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1157 1158#define EXTRACT_IFMT_JAS_C_VARS \ 1159 INT f_indir_pc__dword; \ 1160 UINT f_operand2; \ 1161 UINT f_mode; \ 1162 UINT f_opcode; \ 1163 UINT f_size; \ 1164 UINT f_operand1; \ 1165 /* Contents of trailing part of insn. */ \ 1166 UINT word_1; \ 1167 unsigned int length; 1168#define EXTRACT_IFMT_JAS_C_CODE \ 1169 length = 6; \ 1170 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 1171 f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \ 1172 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1173 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1174 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1175 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1176 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1177 1178#define EXTRACT_IFMT_JUMP_P_VARS \ 1179 UINT f_operand2; \ 1180 UINT f_mode; \ 1181 UINT f_opcode; \ 1182 UINT f_size; \ 1183 UINT f_operand1; \ 1184 unsigned int length; 1185#define EXTRACT_IFMT_JUMP_P_CODE \ 1186 length = 2; \ 1187 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1188 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1189 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1190 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1191 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1192 1193#define EXTRACT_IFMT_BAS_C_VARS \ 1194 SI f_indir_pc__dword_pcrel; \ 1195 UINT f_operand2; \ 1196 UINT f_mode; \ 1197 UINT f_opcode; \ 1198 UINT f_size; \ 1199 UINT f_operand1; \ 1200 /* Contents of trailing part of insn. */ \ 1201 UINT word_1; \ 1202 unsigned int length; 1203#define EXTRACT_IFMT_BAS_C_CODE \ 1204 length = 6; \ 1205 word_1 = GETIMEMUSI (current_cpu, pc + 2); \ 1206 f_indir_pc__dword_pcrel = ((pc) + ((0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)))); \ 1207 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1208 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1209 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1210 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1211 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1212 1213#define EXTRACT_IFMT_BREAK_VARS \ 1214 UINT f_operand2; \ 1215 UINT f_mode; \ 1216 UINT f_opcode; \ 1217 UINT f_size; \ 1218 UINT f_u4; \ 1219 unsigned int length; 1220#define EXTRACT_IFMT_BREAK_CODE \ 1221 length = 2; \ 1222 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1223 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1224 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1225 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1226 f_u4 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1227 1228#define EXTRACT_IFMT_SCC_VARS \ 1229 UINT f_operand2; \ 1230 UINT f_mode; \ 1231 UINT f_opcode; \ 1232 UINT f_size; \ 1233 UINT f_operand1; \ 1234 unsigned int length; 1235#define EXTRACT_IFMT_SCC_CODE \ 1236 length = 2; \ 1237 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1238 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1239 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1240 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1241 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1242 1243#define EXTRACT_IFMT_ADDOQ_VARS \ 1244 UINT f_operand2; \ 1245 UINT f_mode; \ 1246 UINT f_opcode_hi; \ 1247 INT f_s8; \ 1248 unsigned int length; 1249#define EXTRACT_IFMT_ADDOQ_CODE \ 1250 length = 2; \ 1251 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1252 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1253 f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \ 1254 f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \ 1255 1256#define EXTRACT_IFMT_FIDXI_VARS \ 1257 UINT f_operand2; \ 1258 UINT f_mode; \ 1259 UINT f_opcode; \ 1260 UINT f_size; \ 1261 UINT f_operand1; \ 1262 unsigned int length; 1263#define EXTRACT_IFMT_FIDXI_CODE \ 1264 length = 2; \ 1265 f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \ 1266 f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \ 1267 f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \ 1268 f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \ 1269 f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \ 1270 1271/* Collection of various things for the trace handler to use. */ 1272 1273typedef struct trace_record { 1274 IADDR pc; 1275 /* FIXME:wip */ 1276} TRACE_RECORD; 1277 1278#endif /* CPU_CRISV32F_H */ 1279