dv-bfin_wp.c revision 1.1.1.3
1/* Blackfin Watchpoint (WP) model. 2 3 Copyright (C) 2010-2014 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21#include "config.h" 22 23#include "sim-main.h" 24#include "devices.h" 25#include "dv-bfin_wp.h" 26 27/* XXX: This is mostly a stub. */ 28 29#define WPI_NUM 6 /* 6 instruction watchpoints. */ 30#define WPD_NUM 2 /* 2 data watchpoints. */ 31 32struct bfin_wp 33{ 34 bu32 base; 35 36 /* Order after here is important -- matches hardware MMR layout. */ 37 bu32 iactl; 38 bu32 _pad0[15]; 39 bu32 ia[WPI_NUM]; 40 bu32 _pad1[16 - WPI_NUM]; 41 bu32 iacnt[WPI_NUM]; 42 bu32 _pad2[32 - WPI_NUM]; 43 44 bu32 dactl; 45 bu32 _pad3[15]; 46 bu32 da[WPD_NUM]; 47 bu32 _pad4[16 - WPD_NUM]; 48 bu32 dacnt[WPD_NUM]; 49 bu32 _pad5[32 - WPD_NUM]; 50 51 bu32 stat; 52}; 53#define mmr_base() offsetof(struct bfin_wp, iactl) 54#define mmr_offset(mmr) (offsetof(struct bfin_wp, mmr) - mmr_base()) 55#define mmr_idx(mmr) (mmr_offset (mmr) / 4) 56 57static const char * const mmr_names[] = 58{ 59 [mmr_idx (iactl)] = "WPIACTL", 60 [mmr_idx (ia)] = "WPIA0", "WPIA1", "WPIA2", "WPIA3", "WPIA4", "WPIA5", 61 [mmr_idx (iacnt)] = "WPIACNT0", "WPIACNT1", "WPIACNT2", 62 "WPIACNT3", "WPIACNT4", "WPIACNT5", 63 [mmr_idx (dactl)] = "WPDACTL", 64 [mmr_idx (da)] = "WPDA0", "WPDA1", "WPDA2", "WPDA3", "WPDA4", "WPDA5", 65 [mmr_idx (dacnt)] = "WPDACNT0", "WPDACNT1", "WPDACNT2", 66 "WPDACNT3", "WPDACNT4", "WPDACNT5", 67 [mmr_idx (stat)] = "WPSTAT", 68}; 69#define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") 70 71static unsigned 72bfin_wp_io_write_buffer (struct hw *me, const void *source, int space, 73 address_word addr, unsigned nr_bytes) 74{ 75 struct bfin_wp *wp = hw_data (me); 76 bu32 mmr_off; 77 bu32 value; 78 bu32 *valuep; 79 80 value = dv_load_4 (source); 81 mmr_off = addr - wp->base; 82 valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off); 83 84 HW_TRACE_WRITE (); 85 86 switch (mmr_off) 87 { 88 case mmr_offset(iactl): 89 case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): 90 case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): 91 case mmr_offset(dactl): 92 case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): 93 case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): 94 *valuep = value; 95 break; 96 case mmr_offset(stat): 97 /* Yes, the hardware is this dumb -- clear all bits on any write. */ 98 *valuep = 0; 99 break; 100 default: 101 dv_bfin_mmr_invalid (me, addr, nr_bytes, true); 102 break; 103 } 104 105 return nr_bytes; 106} 107 108static unsigned 109bfin_wp_io_read_buffer (struct hw *me, void *dest, int space, 110 address_word addr, unsigned nr_bytes) 111{ 112 struct bfin_wp *wp = hw_data (me); 113 bu32 mmr_off; 114 bu32 value; 115 bu32 *valuep; 116 117 mmr_off = addr - wp->base; 118 valuep = (void *)((unsigned long)wp + mmr_base() + mmr_off); 119 120 HW_TRACE_READ (); 121 122 switch (mmr_off) 123 { 124 case mmr_offset(iactl): 125 case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): 126 case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): 127 case mmr_offset(dactl): 128 case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): 129 case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): 130 case mmr_offset(stat): 131 value = *valuep; 132 break; 133 default: 134 while (1) /* Core MMRs -> exception -> doesn't return. */ 135 dv_bfin_mmr_invalid (me, addr, nr_bytes, false); 136 break; 137 } 138 139 dv_store_4 (dest, value); 140 141 return nr_bytes; 142} 143 144static void 145attach_bfin_wp_regs (struct hw *me, struct bfin_wp *wp) 146{ 147 address_word attach_address; 148 int attach_space; 149 unsigned attach_size; 150 reg_property_spec reg; 151 152 if (hw_find_property (me, "reg") == NULL) 153 hw_abort (me, "Missing \"reg\" property"); 154 155 if (!hw_find_reg_array_property (me, "reg", 0, ®)) 156 hw_abort (me, "\"reg\" property must contain three addr/size entries"); 157 158 hw_unit_address_to_attach_address (hw_parent (me), 159 ®.address, 160 &attach_space, &attach_address, me); 161 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); 162 163 if (attach_size != BFIN_COREMMR_WP_SIZE) 164 hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_WP_SIZE); 165 166 hw_attach_address (hw_parent (me), 167 0, attach_space, attach_address, attach_size, me); 168 169 wp->base = attach_address; 170} 171 172static void 173bfin_wp_finish (struct hw *me) 174{ 175 struct bfin_wp *wp; 176 177 wp = HW_ZALLOC (me, struct bfin_wp); 178 179 set_hw_data (me, wp); 180 set_hw_io_read_buffer (me, bfin_wp_io_read_buffer); 181 set_hw_io_write_buffer (me, bfin_wp_io_write_buffer); 182 183 attach_bfin_wp_regs (me, wp); 184} 185 186const struct hw_descriptor dv_bfin_wp_descriptor[] = 187{ 188 {"bfin_wp", bfin_wp_finish,}, 189 {NULL, NULL}, 190}; 191