armemu.h revision 1.1.1.2
1/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator. 2 Copyright (C) 1994 Advanced RISC Machines Ltd. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 3 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, see <http://www.gnu.org/licenses/>. */ 16 17extern ARMword isize; 18 19/* Condition code values. */ 20#define EQ 0 21#define NE 1 22#define CS 2 23#define CC 3 24#define MI 4 25#define PL 5 26#define VS 6 27#define VC 7 28#define HI 8 29#define LS 9 30#define GE 10 31#define LT 11 32#define GT 12 33#define LE 13 34#define AL 14 35#define NV 15 36 37/* Shift Opcodes. */ 38#define LSL 0 39#define LSR 1 40#define ASR 2 41#define ROR 3 42 43/* Macros to twiddle the status flags and mode. */ 44#define NBIT ((unsigned)1L << 31) 45#define ZBIT (1L << 30) 46#define CBIT (1L << 29) 47#define VBIT (1L << 28) 48#define SBIT (1L << 27) 49#define IBIT (1L << 7) 50#define FBIT (1L << 6) 51#define IFBITS (3L << 6) 52#define R15IBIT (1L << 27) 53#define R15FBIT (1L << 26) 54#define R15IFBITS (3L << 26) 55 56#define POS(i) ( (~(i)) >> 31 ) 57#define NEG(i) ( (i) >> 31 ) 58 59#ifdef MODET /* Thumb support. */ 60/* ??? This bit is actually in the low order bit of the PC in the hardware. 61 It isn't clear if the simulator needs to model that or not. */ 62#define TBIT (1L << 5) 63#define TFLAG state->TFlag 64#define SETT state->TFlag = 1 65#define CLEART state->TFlag = 0 66#define ASSIGNT(res) state->TFlag = res 67#define INSN_SIZE (TFLAG ? 2 : 4) 68#else 69#define INSN_SIZE 4 70#endif 71 72#define NFLAG state->NFlag 73#define SETN state->NFlag = 1 74#define CLEARN state->NFlag = 0 75#define ASSIGNN(res) state->NFlag = res 76 77#define ZFLAG state->ZFlag 78#define SETZ state->ZFlag = 1 79#define CLEARZ state->ZFlag = 0 80#define ASSIGNZ(res) state->ZFlag = res 81 82#define CFLAG state->CFlag 83#define SETC state->CFlag = 1 84#define CLEARC state->CFlag = 0 85#define ASSIGNC(res) state->CFlag = res 86 87#define VFLAG state->VFlag 88#define SETV state->VFlag = 1 89#define CLEARV state->VFlag = 0 90#define ASSIGNV(res) state->VFlag = res 91 92#define SFLAG state->SFlag 93#define SETS state->SFlag = 1 94#define CLEARS state->SFlag = 0 95#define ASSIGNS(res) state->SFlag = res 96 97#define IFLAG (state->IFFlags >> 1) 98#define FFLAG (state->IFFlags & 1) 99#define IFFLAGS state->IFFlags 100#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3) 101#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ; 102 103#define PSR_FBITS (0xff000000L) 104#define PSR_SBITS (0x00ff0000L) 105#define PSR_XBITS (0x0000ff00L) 106#define PSR_CBITS (0x000000ffL) 107 108#if defined MODE32 || defined MODET 109#define CCBITS (0xf8000000L) 110#else 111#define CCBITS (0xf0000000L) 112#endif 113 114#define INTBITS (0xc0L) 115 116#if defined MODET && defined MODE32 117#define PCBITS (0xffffffffL) 118#else 119#define PCBITS (0xfffffffcL) 120#endif 121 122#define MODEBITS (0x1fL) 123#define R15INTBITS (3L << 26) 124 125#if defined MODET && defined MODE32 126#define R15PCBITS (0x03ffffffL) 127#else 128#define R15PCBITS (0x03fffffcL) 129#endif 130 131#define R15PCMODEBITS (0x03ffffffL) 132#define R15MODEBITS (0x3L) 133 134#ifdef MODE32 135#define PCMASK PCBITS 136#define PCWRAP(pc) (pc) 137#else 138#define PCMASK R15PCBITS 139#define PCWRAP(pc) ((pc) & R15PCBITS) 140#endif 141 142#define PC (state->Reg[15] & PCMASK) 143#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS)) 144#define R15INT (state->Reg[15] & R15INTBITS) 145#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS)) 146#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS)) 147#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS)) 148#define R15PC (state->Reg[15] & R15PCBITS) 149#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS)) 150#define R15MODE (state->Reg[15] & R15MODEBITS) 151 152#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28) | (SFLAG << 27)) 153#define EINT (IFFLAGS << 6) 154#define ER15INT (IFFLAGS << 26) 155#define EMODE (state->Mode) 156 157#ifdef MODET 158#define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) 159#else 160#define CPSR (ECC | EINT | EMODE) 161#endif 162 163#ifdef MODE32 164#define PATCHR15 165#else 166#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC 167#endif 168 169#define GETSPSR(bank) (ARMul_GetSPSR (state, EMODE)) 170#define SETPSR_F(d,s) d = ((d) & ~PSR_FBITS) | ((s) & PSR_FBITS) 171#define SETPSR_S(d,s) d = ((d) & ~PSR_SBITS) | ((s) & PSR_SBITS) 172#define SETPSR_X(d,s) d = ((d) & ~PSR_XBITS) | ((s) & PSR_XBITS) 173#define SETPSR_C(d,s) d = ((d) & ~PSR_CBITS) | ((s) & PSR_CBITS) 174 175#define SETR15PSR(s) \ 176 do \ 177 { \ 178 if (state->Mode == USER26MODE) \ 179 { \ 180 state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE; \ 181 ASSIGNN ((state->Reg[15] & NBIT) != 0); \ 182 ASSIGNZ ((state->Reg[15] & ZBIT) != 0); \ 183 ASSIGNC ((state->Reg[15] & CBIT) != 0); \ 184 ASSIGNV ((state->Reg[15] & VBIT) != 0); \ 185 } \ 186 else \ 187 { \ 188 state->Reg[15] = R15PC | ((s) & (CCBITS | R15INTBITS | R15MODEBITS)); \ 189 ARMul_R15Altered (state); \ 190 } \ 191 } \ 192 while (0) 193 194#define SETABORT(i, m, d) \ 195 do \ 196 { \ 197 int SETABORT_mode = (m); \ 198 \ 199 ARMul_SetSPSR (state, SETABORT_mode, ARMul_GetCPSR (state)); \ 200 ARMul_SetCPSR (state, ((ARMul_GetCPSR (state) & ~(EMODE | TBIT)) \ 201 | (i) | SETABORT_mode)); \ 202 state->Reg[14] = temp - (d); \ 203 } \ 204 while (0) 205 206#ifndef MODE32 207#define VECTORS 0x20 208#define LEGALADDR 0x03ffffff 209#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig) 210#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig) 211#endif 212 213#define INTERNALABORT(address) \ 214 do \ 215 { \ 216 if (address < VECTORS) \ 217 state->Aborted = ARMul_DataAbortV; \ 218 else \ 219 state->Aborted = ARMul_AddrExceptnV; \ 220 } \ 221 while (0) 222 223#ifdef MODE32 224#define TAKEABORT ARMul_Abort (state, ARMul_DataAbortV) 225#else 226#define TAKEABORT \ 227 do \ 228 { \ 229 if (state->Aborted == ARMul_AddrExceptnV) \ 230 ARMul_Abort (state, ARMul_AddrExceptnV); \ 231 else \ 232 ARMul_Abort (state, ARMul_DataAbortV); \ 233 } \ 234 while (0) 235#endif 236 237#define CPTAKEABORT \ 238 do \ 239 { \ 240 if (!state->Aborted) \ 241 ARMul_Abort (state, ARMul_UndefinedInstrV); \ 242 else if (state->Aborted == ARMul_AddrExceptnV) \ 243 ARMul_Abort (state, ARMul_AddrExceptnV); \ 244 else \ 245 ARMul_Abort (state, ARMul_DataAbortV); \ 246 } \ 247 while (0); 248 249 250/* Different ways to start the next instruction. */ 251#define SEQ 0 252#define NONSEQ 1 253#define PCINCEDSEQ 2 254#define PCINCEDNONSEQ 3 255#define PRIMEPIPE 4 256#define RESUME 8 257 258#define NORMALCYCLE state->NextInstr = 0 259#define BUSUSEDN state->NextInstr |= 1 /* The next fetch will be an N cycle. */ 260#define BUSUSEDINCPCS \ 261 do \ 262 { \ 263 if (! state->is_v4) \ 264 { \ 265 /* A standard PC inc and an S cycle. */ \ 266 state->Reg[15] += isize; \ 267 state->NextInstr = (state->NextInstr & 0xff) | 2; \ 268 } \ 269 } \ 270 while (0) 271 272#define BUSUSEDINCPCN \ 273 do \ 274 { \ 275 if (state->is_v4) \ 276 BUSUSEDN; \ 277 else \ 278 { \ 279 /* A standard PC inc and an N cycle. */ \ 280 state->Reg[15] += isize; \ 281 state->NextInstr |= 3; \ 282 } \ 283 } \ 284 while (0) 285 286#define INCPC \ 287 do \ 288 { \ 289 /* A standard PC inc. */ \ 290 state->Reg[15] += isize; \ 291 state->NextInstr |= 2; \ 292 } \ 293 while (0) 294 295#define FLUSHPIPE state->NextInstr |= PRIMEPIPE 296 297/* Cycle based emulation. */ 298 299#define OUTPUTCP(i,a,b) 300#define NCYCLE 301#define SCYCLE 302#define ICYCLE 303#define CCYCLE 304#define NEXTCYCLE(c) 305 306/* Macros to extract parts of instructions. */ 307#define DESTReg (BITS (12, 15)) 308#define LHSReg (BITS (16, 19)) 309#define RHSReg (BITS ( 0, 3)) 310 311#define DEST (state->Reg[DESTReg]) 312 313#ifdef MODE32 314#ifdef MODET 315#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg])) 316#else 317#define LHS (state->Reg[LHSReg]) 318#endif 319#else 320#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg])) 321#endif 322 323#define MULDESTReg (BITS (16, 19)) 324#define MULLHSReg (BITS ( 0, 3)) 325#define MULRHSReg (BITS ( 8, 11)) 326#define MULACCReg (BITS (12, 15)) 327 328#define DPImmRHS (ARMul_ImmedTable[BITS(0, 11)]) 329#define DPSImmRHS temp = BITS(0,11) ; \ 330 rhs = ARMul_ImmedTable[temp] ; \ 331 if (temp > 255) /* There was a shift. */ \ 332 ASSIGNC (rhs >> 31) ; 333 334#ifdef MODE32 335#define DPRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ 336 : GetDPRegRHS (state, instr)) 337#define DPSRegRHS ((BITS (4,11) == 0) ? state->Reg[RHSReg] \ 338 : GetDPSRegRHS (state, instr)) 339#else 340#define DPRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 341 : GetDPRegRHS (state, instr)) 342#define DPSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 343 : GetDPSRegRHS (state, instr)) 344#endif 345 346#define LSBase state->Reg[LHSReg] 347#define LSImmRHS (BITS(0,11)) 348 349#ifdef MODE32 350#define LSRegRHS ((BITS (4, 11) == 0) ? state->Reg[RHSReg] \ 351 : GetLSRegRHS (state, instr)) 352#else 353#define LSRegRHS ((BITS (0, 11) < 15) ? state->Reg[RHSReg] \ 354 : GetLSRegRHS (state, instr)) 355#endif 356 357#define LSMNumRegs ((ARMword) ARMul_BitList[BITS (0, 7)] + \ 358 (ARMword) ARMul_BitList[BITS (8, 15)] ) 359#define LSMBaseFirst ((LHSReg == 0 && BIT (0)) || \ 360 (BIT (LHSReg) && BITS (0, LHSReg - 1) == 0)) 361 362#define SWAPSRC (state->Reg[RHSReg]) 363 364#define LSCOff (BITS (0, 7) << 2) 365#define CPNum BITS (8, 11) 366 367/* Determine if access to coprocessor CP is permitted. 368 The XScale has a register in CP15 which controls access to CP0 - CP13. */ 369#define CP_ACCESS_ALLOWED(STATE, CP) \ 370 ( ((CP) >= 14) \ 371 || (! (STATE)->is_XScale) \ 372 || (read_cp15_reg (15, 0, 1) & (1 << (CP)))) 373 374/* Macro to rotate n right by b bits. */ 375#define ROTATER(n, b) (((n) >> (b)) | ((n) << (32 - (b)))) 376 377/* Macros to store results of instructions. */ 378#define WRITEDEST(d) \ 379 do \ 380 { \ 381 if (DESTReg == 15) \ 382 WriteR15 (state, d); \ 383 else \ 384 DEST = d; \ 385 } \ 386 while (0) 387 388#define WRITESDEST(d) \ 389 do \ 390 { \ 391 if (DESTReg == 15) \ 392 WriteSR15 (state, d); \ 393 else \ 394 { \ 395 DEST = d; \ 396 ARMul_NegZero (state, d); \ 397 } \ 398 } \ 399 while (0) 400 401#define WRITEDESTB(d) \ 402 do \ 403 { \ 404 if (DESTReg == 15) \ 405 WriteR15Branch (state, d); \ 406 else \ 407 DEST = d; \ 408 } \ 409 while (0) 410 411#define BYTETOBUS(data) ((data & 0xff) | \ 412 ((data & 0xff) << 8) | \ 413 ((data & 0xff) << 16) | \ 414 ((data & 0xff) << 24)) 415 416#define BUSTOBYTE(address, data) \ 417 do \ 418 { \ 419 if (state->bigendSig) \ 420 temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff; \ 421 else \ 422 temp = (data >> ((address & 3) << 3)) & 0xff; \ 423 } \ 424 while (0) 425 426#define LOADMULT(instr, address, wb) LoadMult (state, instr, address, wb) 427#define LOADSMULT(instr, address, wb) LoadSMult (state, instr, address, wb) 428#define STOREMULT(instr, address, wb) StoreMult (state, instr, address, wb) 429#define STORESMULT(instr, address, wb) StoreSMult (state, instr, address, wb) 430 431#define POSBRANCH ((instr & 0x7fffff) << 2) 432#define NEGBRANCH ((0xff000000 |(instr & 0xffffff)) << 2) 433 434 435/* Values for Emulate. */ 436#define STOP 0 /* stop */ 437#define CHANGEMODE 1 /* change mode */ 438#define ONCE 2 /* execute just one interation */ 439#define RUN 3 /* continuous execution */ 440 441/* Stuff that is shared across modes. */ 442extern unsigned ARMul_MultTable[]; /* Number of I cycles for a mult. */ 443extern ARMword ARMul_ImmedTable[]; /* Immediate DP LHS values. */ 444extern char ARMul_BitList[]; /* Number of bits in a byte table. */ 445 446#define EVENTLISTSIZE 1024L 447 448/* Thumb support. */ 449typedef enum 450{ 451 t_undefined, /* Undefined Thumb instruction. */ 452 t_decoded, /* Instruction decoded to ARM equivalent. */ 453 t_branch /* Thumb branch (already processed). */ 454} 455tdstate; 456 457/* Macros to scrutinize instructions. */ 458#define UNDEF_Test 459#define UNDEF_Shift 460#define UNDEF_MSRPC 461#define UNDEF_MRSPC 462#define UNDEF_MULPCDest 463#define UNDEF_MULDestEQOp1 464#define UNDEF_LSRBPC 465#define UNDEF_LSRBaseEQOffWb 466#define UNDEF_LSRBaseEQDestWb 467#define UNDEF_LSRPCBaseWb 468#define UNDEF_LSRPCOffWb 469#define UNDEF_LSMNoRegs 470#define UNDEF_LSMPCBase 471#define UNDEF_LSMUserBankWb 472#define UNDEF_LSMBaseInListWb 473#define UNDEF_SWPPC 474#define UNDEF_CoProHS 475#define UNDEF_MCRPC 476#define UNDEF_LSCPCBaseWb 477#define UNDEF_UndefNotBounced 478#define UNDEF_ShortInt 479#define UNDEF_IllegalMode 480#define UNDEF_Prog32SigChange 481#define UNDEF_Data32SigChange 482 483/* Prototypes for exported functions. */ 484extern unsigned ARMul_NthReg (ARMword, unsigned); 485extern int AddOverflow (ARMword, ARMword, ARMword); 486extern int SubOverflow (ARMword, ARMword, ARMword); 487extern ARMword ARMul_Emulate26 (ARMul_State *); 488extern ARMword ARMul_Emulate32 (ARMul_State *); 489extern unsigned IntPending (ARMul_State *); 490extern void ARMul_CPSRAltered (ARMul_State *); 491extern void ARMul_R15Altered (ARMul_State *); 492extern ARMword ARMul_GetPC (ARMul_State *); 493extern ARMword ARMul_GetNextPC (ARMul_State *); 494extern ARMword ARMul_GetR15 (ARMul_State *); 495extern ARMword ARMul_GetCPSR (ARMul_State *); 496extern void ARMul_EnvokeEvent (ARMul_State *); 497extern unsigned long ARMul_Time (ARMul_State *); 498extern void ARMul_NegZero (ARMul_State *, ARMword); 499extern void ARMul_SetPC (ARMul_State *, ARMword); 500extern void ARMul_SetR15 (ARMul_State *, ARMword); 501extern void ARMul_SetCPSR (ARMul_State *, ARMword); 502extern ARMword ARMul_GetSPSR (ARMul_State *, ARMword); 503extern void ARMul_Abort26 (ARMul_State *, ARMword); 504extern void ARMul_Abort32 (ARMul_State *, ARMword); 505extern ARMword ARMul_MRC (ARMul_State *, ARMword); 506extern void ARMul_CDP (ARMul_State *, ARMword); 507extern void ARMul_LDC (ARMul_State *, ARMword, ARMword); 508extern void ARMul_STC (ARMul_State *, ARMword, ARMword); 509extern void ARMul_MCR (ARMul_State *, ARMword, ARMword); 510extern void ARMul_SetSPSR (ARMul_State *, ARMword, ARMword); 511extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); 512extern ARMword ARMul_Align (ARMul_State *, ARMword, ARMword); 513extern ARMword ARMul_SwitchMode (ARMul_State *, ARMword, ARMword); 514extern void ARMul_MSRCpsr (ARMul_State *, ARMword, ARMword); 515extern void ARMul_SubOverflow (ARMul_State *, ARMword, ARMword, ARMword); 516extern void ARMul_AddOverflow (ARMul_State *, ARMword, ARMword, ARMword); 517extern void ARMul_SubCarry (ARMul_State *, ARMword, ARMword, ARMword); 518extern void ARMul_AddCarry (ARMul_State *, ARMword, ARMword, ARMword); 519extern tdstate ARMul_ThumbDecode (ARMul_State *, ARMword, ARMword, ARMword *); 520extern ARMword ARMul_GetReg (ARMul_State *, unsigned, unsigned); 521extern void ARMul_SetReg (ARMul_State *, unsigned, unsigned, ARMword); 522extern void ARMul_ScheduleEvent (ARMul_State *, unsigned long, unsigned (*) (ARMul_State *)); 523/* Coprocessor support functions. */ 524extern unsigned ARMul_CoProInit (ARMul_State *); 525extern void ARMul_CoProExit (ARMul_State *); 526extern void ARMul_CoProAttach (ARMul_State *, unsigned, ARMul_CPInits *, ARMul_CPExits *, 527 ARMul_LDCs *, ARMul_STCs *, ARMul_MRCs *, ARMul_MCRs *, 528 ARMul_CDPs *, ARMul_CPReads *, ARMul_CPWrites *); 529extern void ARMul_CoProDetach (ARMul_State *, unsigned); 530extern ARMword read_cp15_reg (unsigned, unsigned, unsigned); 531 532extern unsigned DSPLDC4 (ARMul_State *, unsigned, ARMword, ARMword); 533extern unsigned DSPMCR4 (ARMul_State *, unsigned, ARMword, ARMword); 534extern unsigned DSPMRC4 (ARMul_State *, unsigned, ARMword, ARMword *); 535extern unsigned DSPSTC4 (ARMul_State *, unsigned, ARMword, ARMword *); 536extern unsigned DSPCDP4 (ARMul_State *, unsigned, ARMword); 537extern unsigned DSPMCR5 (ARMul_State *, unsigned, ARMword, ARMword); 538extern unsigned DSPMRC5 (ARMul_State *, unsigned, ARMword, ARMword *); 539extern unsigned DSPLDC5 (ARMul_State *, unsigned, ARMword, ARMword); 540extern unsigned DSPSTC5 (ARMul_State *, unsigned, ARMword, ARMword *); 541extern unsigned DSPCDP5 (ARMul_State *, unsigned, ARMword); 542extern unsigned DSPMCR6 (ARMul_State *, unsigned, ARMword, ARMword); 543extern unsigned DSPMRC6 (ARMul_State *, unsigned, ARMword, ARMword *); 544extern unsigned DSPCDP6 (ARMul_State *, unsigned, ARMword); 545