i386-opc.h revision 1.1.1.8 
1/* Declarations for Intel 80386 opcode table
2   Copyright (C) 2007-2019 Free Software Foundation, Inc.
3
4   This file is part of the GNU opcodes library.
5
6   This library is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3, or (at your option)
9   any later version.
10
11   It is distributed in the hope that it will be useful, but WITHOUT
12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14   License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with GAS; see the file COPYING.  If not, write to the Free
18   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19   02110-1301, USA.  */
20
21#include "opcode/i386.h"
22#ifdef HAVE_LIMITS_H
23#include <limits.h>
24#endif
25
26#ifndef CHAR_BIT
27#define CHAR_BIT 8
28#endif
29
30/* Position of cpu flags bitfiled.  */
31
32enum
33{
34  /* i186 or better required */
35  Cpu186 = 0,
36  /* i286 or better required */
37  Cpu286,
38  /* i386 or better required */
39  Cpu386,
40  /* i486 or better required */
41  Cpu486,
42  /* i585 or better required */
43  Cpu586,
44  /* i686 or better required */
45  Cpu686,
46  /* CMOV Instruction support required */
47  CpuCMOV,
48  /* FXSR Instruction support required */
49  CpuFXSR,
50  /* CLFLUSH Instruction support required */
51  CpuClflush,
52  /* NOP Instruction support required */
53  CpuNop,
54  /* SYSCALL Instructions support required */
55  CpuSYSCALL,
56  /* Floating point support required */
57  Cpu8087,
58  /* i287 support required */
59  Cpu287,
60  /* i387 support required */
61  Cpu387,
62  /* i686 and floating point support required */
63  Cpu687,
64  /* SSE3 and floating point support required */
65  CpuFISTTP,
66  /* MMX support required */
67  CpuMMX,
68  /* SSE support required */
69  CpuSSE,
70  /* SSE2 support required */
71  CpuSSE2,
72  /* 3dnow! support required */
73  Cpu3dnow,
74  /* 3dnow! Extensions support required */
75  Cpu3dnowA,
76  /* SSE3 support required */
77  CpuSSE3,
78  /* VIA PadLock required */
79  CpuPadLock,
80  /* AMD Secure Virtual Machine Ext-s required */
81  CpuSVME,
82  /* VMX Instructions required */
83  CpuVMX,
84  /* SMX Instructions required */
85  CpuSMX,
86  /* SSSE3 support required */
87  CpuSSSE3,
88  /* SSE4a support required */
89  CpuSSE4a,
90  /* ABM New Instructions required */
91  CpuABM,
92  /* SSE4.1 support required */
93  CpuSSE4_1,
94  /* SSE4.2 support required */
95  CpuSSE4_2,
96  /* AVX support required */
97  CpuAVX,
98  /* AVX2 support required */
99  CpuAVX2,
100  /* Intel AVX-512 Foundation Instructions support required */
101  CpuAVX512F,
102  /* Intel AVX-512 Conflict Detection Instructions support required */
103  CpuAVX512CD,
104  /* Intel AVX-512 Exponential and Reciprocal Instructions support
105     required */
106  CpuAVX512ER,
107  /* Intel AVX-512 Prefetch Instructions support required */
108  CpuAVX512PF,
109  /* Intel AVX-512 VL Instructions support required.  */
110  CpuAVX512VL,
111  /* Intel AVX-512 DQ Instructions support required.  */
112  CpuAVX512DQ,
113  /* Intel AVX-512 BW Instructions support required.  */
114  CpuAVX512BW,
115  /* Intel L1OM support required */
116  CpuL1OM,
117  /* Intel K1OM support required */
118  CpuK1OM,
119  /* Intel IAMCU support required */
120  CpuIAMCU,
121  /* Xsave/xrstor New Instructions support required */
122  CpuXsave,
123  /* Xsaveopt New Instructions support required */
124  CpuXsaveopt,
125  /* AES support required */
126  CpuAES,
127  /* PCLMUL support required */
128  CpuPCLMUL,
129  /* FMA support required */
130  CpuFMA,
131  /* FMA4 support required */
132  CpuFMA4,
133  /* XOP support required */
134  CpuXOP,
135  /* LWP support required */
136  CpuLWP,
137  /* BMI support required */
138  CpuBMI,
139  /* TBM support required */
140  CpuTBM,
141  /* MOVBE Instruction support required */
142  CpuMovbe,
143  /* CMPXCHG16B instruction support required.  */
144  CpuCX16,
145  /* EPT Instructions required */
146  CpuEPT,
147  /* RDTSCP Instruction support required */
148  CpuRdtscp,
149  /* FSGSBASE Instructions required */
150  CpuFSGSBase,
151  /* RDRND Instructions required */
152  CpuRdRnd,
153  /* F16C Instructions required */
154  CpuF16C,
155  /* Intel BMI2 support required */
156  CpuBMI2,
157  /* LZCNT support required */
158  CpuLZCNT,
159  /* HLE support required */
160  CpuHLE,
161  /* RTM support required */
162  CpuRTM,
163  /* INVPCID Instructions required */
164  CpuINVPCID,
165  /* VMFUNC Instruction required */
166  CpuVMFUNC,
167  /* Intel MPX Instructions required  */
168  CpuMPX,
169  /* 64bit support available, used by -march= in assembler.  */
170  CpuLM,
171  /* RDRSEED instruction required.  */
172  CpuRDSEED,
173  /* Multi-presisionn add-carry instructions are required.  */
174  CpuADX,
175  /* Supports prefetchw and prefetch instructions.  */
176  CpuPRFCHW,
177  /* SMAP instructions required.  */
178  CpuSMAP,
179  /* SHA instructions required.  */
180  CpuSHA,
181  /* CLFLUSHOPT instruction required */
182  CpuClflushOpt,
183  /* XSAVES/XRSTORS instruction required */
184  CpuXSAVES,
185  /* XSAVEC instruction required */
186  CpuXSAVEC,
187  /* PREFETCHWT1 instruction required */
188  CpuPREFETCHWT1,
189  /* SE1 instruction required */
190  CpuSE1,
191  /* CLWB instruction required */
192  CpuCLWB,
193  /* Intel AVX-512 IFMA Instructions support required.  */
194  CpuAVX512IFMA,
195  /* Intel AVX-512 VBMI Instructions support required.  */
196  CpuAVX512VBMI,
197  /* Intel AVX-512 4FMAPS Instructions support required.  */
198  CpuAVX512_4FMAPS,
199  /* Intel AVX-512 4VNNIW Instructions support required.  */
200  CpuAVX512_4VNNIW,
201  /* Intel AVX-512 VPOPCNTDQ Instructions support required.  */
202  CpuAVX512_VPOPCNTDQ,
203  /* Intel AVX-512 VBMI2 Instructions support required.  */
204  CpuAVX512_VBMI2,
205  /* Intel AVX-512 VNNI Instructions support required.  */
206  CpuAVX512_VNNI,
207  /* Intel AVX-512 BITALG Instructions support required.  */
208  CpuAVX512_BITALG,
209  /* mwaitx instruction required */
210  CpuMWAITX,
211  /* Clzero instruction required */
212  CpuCLZERO,
213  /* OSPKE instruction required */
214  CpuOSPKE,
215  /* RDPID instruction required */
216  CpuRDPID,
217  /* PTWRITE instruction required */
218  CpuPTWRITE,
219  /* CET instructions support required */
220  CpuIBT,
221  CpuSHSTK,
222  /* GFNI instructions required */
223  CpuGFNI,
224  /* VAES instructions required */
225  CpuVAES,
226  /* VPCLMULQDQ instructions required */
227  CpuVPCLMULQDQ,
228  /* WBNOINVD instructions required */
229  CpuWBNOINVD,
230  /* PCONFIG instructions required */
231  CpuPCONFIG,
232  /* WAITPKG instructions required */
233  CpuWAITPKG,
234  /* CLDEMOTE instruction required */
235  CpuCLDEMOTE,
236  /* MOVDIRI instruction support required */
237  CpuMOVDIRI,
238  /* MOVDIRR64B instruction required */
239  CpuMOVDIR64B,
240  /* 64bit support required  */
241  Cpu64,
242  /* Not supported in the 64bit mode  */
243  CpuNo64,
244  /* The last bitfield in i386_cpu_flags.  */
245  CpuMax = CpuNo64
246};
247
248#define CpuNumOfUints \
249  (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
250#define CpuNumOfBits \
251  (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
252
253/* If you get a compiler error for zero width of the unused field,
254   comment it out.  */
255#define CpuUnused	(CpuMax + 1)
256
257/* We can check if an instruction is available with array instead
258   of bitfield. */
259typedef union i386_cpu_flags
260{
261  struct
262    {
263      unsigned int cpui186:1;
264      unsigned int cpui286:1;
265      unsigned int cpui386:1;
266      unsigned int cpui486:1;
267      unsigned int cpui586:1;
268      unsigned int cpui686:1;
269      unsigned int cpucmov:1;
270      unsigned int cpufxsr:1;
271      unsigned int cpuclflush:1;
272      unsigned int cpunop:1;
273      unsigned int cpusyscall:1;
274      unsigned int cpu8087:1;
275      unsigned int cpu287:1;
276      unsigned int cpu387:1;
277      unsigned int cpu687:1;
278      unsigned int cpufisttp:1;
279      unsigned int cpummx:1;
280      unsigned int cpusse:1;
281      unsigned int cpusse2:1;
282      unsigned int cpua3dnow:1;
283      unsigned int cpua3dnowa:1;
284      unsigned int cpusse3:1;
285      unsigned int cpupadlock:1;
286      unsigned int cpusvme:1;
287      unsigned int cpuvmx:1;
288      unsigned int cpusmx:1;
289      unsigned int cpussse3:1;
290      unsigned int cpusse4a:1;
291      unsigned int cpuabm:1;
292      unsigned int cpusse4_1:1;
293      unsigned int cpusse4_2:1;
294      unsigned int cpuavx:1;
295      unsigned int cpuavx2:1;
296      unsigned int cpuavx512f:1;
297      unsigned int cpuavx512cd:1;
298      unsigned int cpuavx512er:1;
299      unsigned int cpuavx512pf:1;
300      unsigned int cpuavx512vl:1;
301      unsigned int cpuavx512dq:1;
302      unsigned int cpuavx512bw:1;
303      unsigned int cpul1om:1;
304      unsigned int cpuk1om:1;
305      unsigned int cpuiamcu:1;
306      unsigned int cpuxsave:1;
307      unsigned int cpuxsaveopt:1;
308      unsigned int cpuaes:1;
309      unsigned int cpupclmul:1;
310      unsigned int cpufma:1;
311      unsigned int cpufma4:1;
312      unsigned int cpuxop:1;
313      unsigned int cpulwp:1;
314      unsigned int cpubmi:1;
315      unsigned int cputbm:1;
316      unsigned int cpumovbe:1;
317      unsigned int cpucx16:1;
318      unsigned int cpuept:1;
319      unsigned int cpurdtscp:1;
320      unsigned int cpufsgsbase:1;
321      unsigned int cpurdrnd:1;
322      unsigned int cpuf16c:1;
323      unsigned int cpubmi2:1;
324      unsigned int cpulzcnt:1;
325      unsigned int cpuhle:1;
326      unsigned int cpurtm:1;
327      unsigned int cpuinvpcid:1;
328      unsigned int cpuvmfunc:1;
329      unsigned int cpumpx:1;
330      unsigned int cpulm:1;
331      unsigned int cpurdseed:1;
332      unsigned int cpuadx:1;
333      unsigned int cpuprfchw:1;
334      unsigned int cpusmap:1;
335      unsigned int cpusha:1;
336      unsigned int cpuclflushopt:1;
337      unsigned int cpuxsaves:1;
338      unsigned int cpuxsavec:1;
339      unsigned int cpuprefetchwt1:1;
340      unsigned int cpuse1:1;
341      unsigned int cpuclwb:1;
342      unsigned int cpuavx512ifma:1;
343      unsigned int cpuavx512vbmi:1;
344      unsigned int cpuavx512_4fmaps:1;
345      unsigned int cpuavx512_4vnniw:1;
346      unsigned int cpuavx512_vpopcntdq:1;
347      unsigned int cpuavx512_vbmi2:1;
348      unsigned int cpuavx512_vnni:1;
349      unsigned int cpuavx512_bitalg:1;
350      unsigned int cpumwaitx:1;
351      unsigned int cpuclzero:1;
352      unsigned int cpuospke:1;
353      unsigned int cpurdpid:1;
354      unsigned int cpuptwrite:1;
355      unsigned int cpuibt:1;
356      unsigned int cpushstk:1;
357      unsigned int cpugfni:1;
358      unsigned int cpuvaes:1;
359      unsigned int cpuvpclmulqdq:1;
360      unsigned int cpuwbnoinvd:1;
361      unsigned int cpupconfig:1;
362      unsigned int cpuwaitpkg:1;
363      unsigned int cpucldemote:1;
364      unsigned int cpumovdiri:1;
365      unsigned int cpumovdir64b:1;
366      unsigned int cpu64:1;
367      unsigned int cpuno64:1;
368#ifdef CpuUnused
369      unsigned int unused:(CpuNumOfBits - CpuUnused);
370#endif
371    } bitfield;
372  unsigned int array[CpuNumOfUints];
373} i386_cpu_flags;
374
375/* Position of opcode_modifier bits.  */
376
377enum
378{
379  /* has direction bit. */
380  D = 0,
381  /* set if operands can be words or dwords encoded the canonical way */
382  W,
383  /* load form instruction. Must be placed before store form.  */
384  Load,
385  /* insn has a modrm byte. */
386  Modrm,
387  /* register is in low 3 bits of opcode */
388  ShortForm,
389  /* special case for jump insns.  */
390  Jump,
391  /* call and jump */
392  JumpDword,
393  /* loop and jecxz */
394  JumpByte,
395  /* special case for intersegment leaps/calls */
396  JumpInterSegment,
397  /* FP insn memory format bit, sized by 0x4 */
398  FloatMF,
399  /* src/dest swap for floats. */
400  FloatR,
401  /* needs size prefix if in 32-bit mode */
402#define SIZE16 1
403  /* needs size prefix if in 16-bit mode */
404#define SIZE32 2
405  /* needs size prefix if in 64-bit mode */
406#define SIZE64 3
407  Size,
408  /* check register size.  */
409  CheckRegSize,
410  /* instruction ignores operand size prefix and in Intel mode ignores
411     mnemonic size suffix check.  */
412  IgnoreSize,
413  /* default insn size depends on mode */
414  DefaultSize,
415  /* b suffix on instruction illegal */
416  No_bSuf,
417  /* w suffix on instruction illegal */
418  No_wSuf,
419  /* l suffix on instruction illegal */
420  No_lSuf,
421  /* s suffix on instruction illegal */
422  No_sSuf,
423  /* q suffix on instruction illegal */
424  No_qSuf,
425  /* long double suffix on instruction illegal */
426  No_ldSuf,
427  /* instruction needs FWAIT */
428  FWait,
429  /* quick test for string instructions */
430  IsString,
431  /* quick test if branch instruction is MPX supported */
432  BNDPrefixOk,
433  /* quick test if NOTRACK prefix is supported */
434  NoTrackPrefixOk,
435  /* quick test for lockable instructions */
436  IsLockable,
437  /* fake an extra reg operand for clr, imul and special register
438     processing for some instructions.  */
439  RegKludge,
440  /* An implicit xmm0 as the first operand */
441  Implicit1stXmm0,
442  /* The HLE prefix is OK:
443     1. With a LOCK prefix.
444     2. With or without a LOCK prefix.
445     3. With a RELEASE (0xf3) prefix.
446   */
447#define HLEPrefixNone		0
448#define HLEPrefixLock		1
449#define HLEPrefixAny		2
450#define HLEPrefixRelease	3
451  HLEPrefixOk,
452  /* An instruction on which a "rep" prefix is acceptable.  */
453  RepPrefixOk,
454  /* Convert to DWORD */
455  ToDword,
456  /* Convert to QWORD */
457  ToQword,
458  /* Address prefix changes register operand */
459  AddrPrefixOpReg,
460  /* opcode is a prefix */
461  IsPrefix,
462  /* instruction has extension in 8 bit imm */
463  ImmExt,
464  /* instruction don't need Rex64 prefix.  */
465  NoRex64,
466  /* instruction require Rex64 prefix.  */
467  Rex64,
468  /* deprecated fp insn, gets a warning */
469  Ugh,
470  /* insn has VEX prefix:
471	1: 128bit VEX prefix (or operand dependent).
472	2: 256bit VEX prefix.
473	3: Scalar VEX prefix.
474   */
475#define VEX128		1
476#define VEX256		2
477#define VEXScalar	3
478  Vex,
479  /* How to encode VEX.vvvv:
480     0: VEX.vvvv must be 1111b.
481     1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
482	the content of source registers will be preserved.
483	VEX.DDS.  The second register operand is encoded in VEX.vvvv
484	where the content of first source register will be overwritten
485	by the result.
486	VEX.NDD2.  The second destination register operand is encoded in
487	VEX.vvvv for instructions with 2 destination register operands.
488	For assembler, there are no difference between VEX.NDS, VEX.DDS
489	and VEX.NDD2.
490     2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
491     instructions with 1 destination register operand.
492     3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
493	of the operands can access a memory location.
494   */
495#define VEXXDS	1
496#define VEXNDD	2
497#define VEXLWP	3
498  VexVVVV,
499  /* How the VEX.W bit is used:
500     0: Set by the REX.W bit.
501     1: VEX.W0.  Should always be 0.
502     2: VEX.W1.  Should always be 1.
503     3: VEX.WIG. The VEX.W bit is ignored.
504   */
505#define VEXW0	1
506#define VEXW1	2
507#define VEXWIG	3
508  VexW,
509  /* VEX opcode prefix:
510     0: VEX 0x0F opcode prefix.
511     1: VEX 0x0F38 opcode prefix.
512     2: VEX 0x0F3A opcode prefix
513     3: XOP 0x08 opcode prefix.
514     4: XOP 0x09 opcode prefix
515     5: XOP 0x0A opcode prefix.
516   */
517#define VEX0F		0
518#define VEX0F38		1
519#define VEX0F3A		2
520#define XOP08		3
521#define XOP09		4
522#define XOP0A		5
523  VexOpcode,
524  /* number of VEX source operands:
525     0: <= 2 source operands.
526     1: 2 XOP source operands.
527     2: 3 source operands.
528   */
529#define XOP2SOURCES	1
530#define VEX3SOURCES	2
531  VexSources,
532  /* Instruction with vector SIB byte:
533	1: 128bit vector register.
534	2: 256bit vector register.
535	3: 512bit vector register.
536   */
537#define VecSIB128	1
538#define VecSIB256	2
539#define VecSIB512	3
540  VecSIB,
541  /* SSE to AVX support required */
542  SSE2AVX,
543  /* No AVX equivalent */
544  NoAVX,
545
546  /* insn has EVEX prefix:
547	1: 512bit EVEX prefix.
548	2: 128bit EVEX prefix.
549	3: 256bit EVEX prefix.
550	4: Length-ignored (LIG) EVEX prefix.
551	5: Length determined from actual operands.
552   */
553#define EVEX512                1
554#define EVEX128                2
555#define EVEX256                3
556#define EVEXLIG                4
557#define EVEXDYN                5
558  EVex,
559
560  /* AVX512 masking support:
561	1: Zeroing or merging masking depending on operands.
562	2: Merging-masking.
563	3: Both zeroing and merging masking.
564   */
565#define DYNAMIC_MASKING 1
566#define MERGING_MASKING 2
567#define BOTH_MASKING    3
568  Masking,
569
570  /* AVX512 broadcast support.  The number of bytes to broadcast is
571     1 << (Broadcast - 1):
572	1: Byte broadcast.
573	2: Word broadcast.
574	3: Dword broadcast.
575	4: Qword broadcast.
576   */
577#define BYTE_BROADCAST	1
578#define WORD_BROADCAST	2
579#define DWORD_BROADCAST	3
580#define QWORD_BROADCAST	4
581  Broadcast,
582
583  /* Static rounding control is supported.  */
584  StaticRounding,
585
586  /* Supress All Exceptions is supported.  */
587  SAE,
588
589  /* Compressed Disp8*N attribute.  */
590#define DISP8_SHIFT_VL 7
591  Disp8MemShift,
592
593  /* Default mask isn't allowed.  */
594  NoDefMask,
595
596  /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
597     It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
598   */
599  ImplicitQuadGroup,
600
601  /* Support encoding optimization.  */
602  Optimize,
603
604  /* AT&T mnemonic.  */
605  ATTMnemonic,
606  /* AT&T syntax.  */
607  ATTSyntax,
608  /* Intel syntax.  */
609  IntelSyntax,
610  /* AMD64.  */
611  AMD64,
612  /* Intel64.  */
613  Intel64,
614  /* The last bitfield in i386_opcode_modifier.  */
615  Opcode_Modifier_Max
616};
617
618typedef struct i386_opcode_modifier
619{
620  unsigned int d:1;
621  unsigned int w:1;
622  unsigned int load:1;
623  unsigned int modrm:1;
624  unsigned int shortform:1;
625  unsigned int jump:1;
626  unsigned int jumpdword:1;
627  unsigned int jumpbyte:1;
628  unsigned int jumpintersegment:1;
629  unsigned int floatmf:1;
630  unsigned int floatr:1;
631  unsigned int size:2;
632  unsigned int checkregsize:1;
633  unsigned int ignoresize:1;
634  unsigned int defaultsize:1;
635  unsigned int no_bsuf:1;
636  unsigned int no_wsuf:1;
637  unsigned int no_lsuf:1;
638  unsigned int no_ssuf:1;
639  unsigned int no_qsuf:1;
640  unsigned int no_ldsuf:1;
641  unsigned int fwait:1;
642  unsigned int isstring:1;
643  unsigned int bndprefixok:1;
644  unsigned int notrackprefixok:1;
645  unsigned int islockable:1;
646  unsigned int regkludge:1;
647  unsigned int implicit1stxmm0:1;
648  unsigned int hleprefixok:2;
649  unsigned int repprefixok:1;
650  unsigned int todword:1;
651  unsigned int toqword:1;
652  unsigned int addrprefixopreg:1;
653  unsigned int isprefix:1;
654  unsigned int immext:1;
655  unsigned int norex64:1;
656  unsigned int rex64:1;
657  unsigned int ugh:1;
658  unsigned int vex:2;
659  unsigned int vexvvvv:2;
660  unsigned int vexw:2;
661  unsigned int vexopcode:3;
662  unsigned int vexsources:2;
663  unsigned int vecsib:2;
664  unsigned int sse2avx:1;
665  unsigned int noavx:1;
666  unsigned int evex:3;
667  unsigned int masking:2;
668  unsigned int broadcast:3;
669  unsigned int staticrounding:1;
670  unsigned int sae:1;
671  unsigned int disp8memshift:3;
672  unsigned int nodefmask:1;
673  unsigned int implicitquadgroup:1;
674  unsigned int optimize:1;
675  unsigned int attmnemonic:1;
676  unsigned int attsyntax:1;
677  unsigned int intelsyntax:1;
678  unsigned int amd64:1;
679  unsigned int intel64:1;
680} i386_opcode_modifier;
681
682/* Position of operand_type bits.  */
683
684enum
685{
686  /* Register (qualified by Byte, Word, etc) */
687  Reg = 0,
688  /* MMX register */
689  RegMMX,
690  /* Vector registers */
691  RegSIMD,
692  /* Vector Mask registers */
693  RegMask,
694  /* Control register */
695  Control,
696  /* Debug register */
697  Debug,
698  /* Test register */
699  Test,
700  /* 2 bit segment register */
701  SReg2,
702  /* 3 bit segment register */
703  SReg3,
704  /* 1 bit immediate */
705  Imm1,
706  /* 8 bit immediate */
707  Imm8,
708  /* 8 bit immediate sign extended */
709  Imm8S,
710  /* 16 bit immediate */
711  Imm16,
712  /* 32 bit immediate */
713  Imm32,
714  /* 32 bit immediate sign extended */
715  Imm32S,
716  /* 64 bit immediate */
717  Imm64,
718  /* 8bit/16bit/32bit displacements are used in different ways,
719     depending on the instruction.  For jumps, they specify the
720     size of the PC relative displacement, for instructions with
721     memory operand, they specify the size of the offset relative
722     to the base register, and for instructions with memory offset
723     such as `mov 1234,%al' they specify the size of the offset
724     relative to the segment base.  */
725  /* 8 bit displacement */
726  Disp8,
727  /* 16 bit displacement */
728  Disp16,
729  /* 32 bit displacement */
730  Disp32,
731  /* 32 bit signed displacement */
732  Disp32S,
733  /* 64 bit displacement */
734  Disp64,
735  /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
736  Acc,
737  /* Register which can be used for base or index in memory operand.  */
738  BaseIndex,
739  /* Register to hold in/out port addr = dx */
740  InOutPortReg,
741  /* Register to hold shift count = cl */
742  ShiftCount,
743  /* Absolute address for jump.  */
744  JumpAbsolute,
745  /* String insn operand with fixed es segment */
746  EsSeg,
747  /* RegMem is for instructions with a modrm byte where the register
748     destination operand should be encoded in the mod and regmem fields.
749     Normally, it will be encoded in the reg field. We add a RegMem
750     flag to the destination register operand to indicate that it should
751     be encoded in the regmem field.  */
752  RegMem,
753  /* Memory.  */
754  Mem,
755  /* BYTE size. */
756  Byte,
757  /* WORD size. 2 byte */
758  Word,
759  /* DWORD size. 4 byte */
760  Dword,
761  /* FWORD size. 6 byte */
762  Fword,
763  /* QWORD size. 8 byte */
764  Qword,
765  /* TBYTE size. 10 byte */
766  Tbyte,
767  /* XMMWORD size. */
768  Xmmword,
769  /* YMMWORD size. */
770  Ymmword,
771  /* ZMMWORD size.  */
772  Zmmword,
773  /* Unspecified memory size.  */
774  Unspecified,
775  /* Any memory size.  */
776  Anysize,
777
778  /* Vector 4 bit immediate.  */
779  Vec_Imm4,
780
781  /* Bound register.  */
782  RegBND,
783
784  /* The number of bitfields in i386_operand_type.  */
785  OTNum
786};
787
788#define OTNumOfUints \
789  ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
790#define OTNumOfBits \
791  (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
792
793/* If you get a compiler error for zero width of the unused field,
794   comment it out.  */
795#define OTUnused		OTNum
796
797typedef union i386_operand_type
798{
799  struct
800    {
801      unsigned int reg:1;
802      unsigned int regmmx:1;
803      unsigned int regsimd:1;
804      unsigned int regmask:1;
805      unsigned int control:1;
806      unsigned int debug:1;
807      unsigned int test:1;
808      unsigned int sreg2:1;
809      unsigned int sreg3:1;
810      unsigned int imm1:1;
811      unsigned int imm8:1;
812      unsigned int imm8s:1;
813      unsigned int imm16:1;
814      unsigned int imm32:1;
815      unsigned int imm32s:1;
816      unsigned int imm64:1;
817      unsigned int disp8:1;
818      unsigned int disp16:1;
819      unsigned int disp32:1;
820      unsigned int disp32s:1;
821      unsigned int disp64:1;
822      unsigned int acc:1;
823      unsigned int baseindex:1;
824      unsigned int inoutportreg:1;
825      unsigned int shiftcount:1;
826      unsigned int jumpabsolute:1;
827      unsigned int esseg:1;
828      unsigned int regmem:1;
829      unsigned int byte:1;
830      unsigned int word:1;
831      unsigned int dword:1;
832      unsigned int fword:1;
833      unsigned int qword:1;
834      unsigned int tbyte:1;
835      unsigned int xmmword:1;
836      unsigned int ymmword:1;
837      unsigned int zmmword:1;
838      unsigned int unspecified:1;
839      unsigned int anysize:1;
840      unsigned int vec_imm4:1;
841      unsigned int regbnd:1;
842#ifdef OTUnused
843      unsigned int unused:(OTNumOfBits - OTUnused);
844#endif
845    } bitfield;
846  unsigned int array[OTNumOfUints];
847} i386_operand_type;
848
849typedef struct insn_template
850{
851  /* instruction name sans width suffix ("mov" for movl insns) */
852  char *name;
853
854  /* how many operands */
855  unsigned int operands;
856
857  /* base_opcode is the fundamental opcode byte without optional
858     prefix(es).  */
859  unsigned int base_opcode;
860#define Opcode_D	0x2 /* Direction bit:
861			       set if Reg --> Regmem;
862			       unset if Regmem --> Reg. */
863#define Opcode_FloatR	0x8 /* Bit to swap src/dest for float insns. */
864#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
865#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
866#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
867
868  /* extension_opcode is the 3 bit extension for group <n> insns.
869     This field is also used to store the 8-bit opcode suffix for the
870     AMD 3DNow! instructions.
871     If this template has no extension opcode (the usual case) use None
872     Instructions */
873  unsigned int extension_opcode;
874#define None 0xffff		/* If no extension_opcode is possible.  */
875
876  /* Opcode length.  */
877  unsigned char opcode_length;
878
879  /* cpu feature flags */
880  i386_cpu_flags cpu_flags;
881
882  /* the bits in opcode_modifier are used to generate the final opcode from
883     the base_opcode.  These bits also are used to detect alternate forms of
884     the same instruction */
885  i386_opcode_modifier opcode_modifier;
886
887  /* operand_types[i] describes the type of operand i.  This is made
888     by OR'ing together all of the possible type masks.  (e.g.
889     'operand_types[i] = Reg|Imm' specifies that operand i can be
890     either a register or an immediate operand.  */
891  i386_operand_type operand_types[MAX_OPERANDS];
892}
893insn_template;
894
895extern const insn_template i386_optab[];
896
897/* these are for register name --> number & type hash lookup */
898typedef struct
899{
900  char *reg_name;
901  i386_operand_type reg_type;
902  unsigned char reg_flags;
903#define RegRex	    0x1  /* Extended register.  */
904#define RegRex64    0x2  /* Extended 8 bit register.  */
905#define RegVRex	    0x4  /* Extended vector register.  */
906  unsigned char reg_num;
907#define RegIP	((unsigned char ) ~0)
908/* EIZ and RIZ are fake index registers.  */
909#define RegIZ	(RegIP - 1)
910/* FLAT is a fake segment register (Intel mode).  */
911#define RegFlat     ((unsigned char) ~0)
912  signed char dw2_regnum[2];
913#define Dw2Inval (-1)
914}
915reg_entry;
916
917/* Entries in i386_regtab.  */
918#define REGNAM_AL 1
919#define REGNAM_AX 25
920#define REGNAM_EAX 41
921
922extern const reg_entry i386_regtab[];
923extern const unsigned int i386_regtab_size;
924
925typedef struct
926{
927  char *seg_name;
928  unsigned int seg_prefix;
929}
930seg_entry;
931
932extern const seg_entry cs;
933extern const seg_entry ds;
934extern const seg_entry ss;
935extern const seg_entry es;
936extern const seg_entry fs;
937extern const seg_entry gs;
938