i386-opc.h revision 1.1.1.5
1/* Declarations for Intel 80386 opcode table 2 Copyright (C) 2007-2015 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21#include "opcode/i386.h" 22#ifdef HAVE_LIMITS_H 23#include <limits.h> 24#endif 25 26#ifndef CHAR_BIT 27#define CHAR_BIT 8 28#endif 29 30/* Position of cpu flags bitfiled. */ 31 32enum 33{ 34 /* i186 or better required */ 35 Cpu186 = 0, 36 /* i286 or better required */ 37 Cpu286, 38 /* i386 or better required */ 39 Cpu386, 40 /* i486 or better required */ 41 Cpu486, 42 /* i585 or better required */ 43 Cpu586, 44 /* i686 or better required */ 45 Cpu686, 46 /* CLFLUSH Instruction support required */ 47 CpuClflush, 48 /* NOP Instruction support required */ 49 CpuNop, 50 /* SYSCALL Instructions support required */ 51 CpuSYSCALL, 52 /* Floating point support required */ 53 Cpu8087, 54 /* i287 support required */ 55 Cpu287, 56 /* i387 support required */ 57 Cpu387, 58 /* i686 and floating point support required */ 59 Cpu687, 60 /* SSE3 and floating point support required */ 61 CpuFISTTP, 62 /* MMX support required */ 63 CpuMMX, 64 /* SSE support required */ 65 CpuSSE, 66 /* SSE2 support required */ 67 CpuSSE2, 68 /* 3dnow! support required */ 69 Cpu3dnow, 70 /* 3dnow! Extensions support required */ 71 Cpu3dnowA, 72 /* SSE3 support required */ 73 CpuSSE3, 74 /* VIA PadLock required */ 75 CpuPadLock, 76 /* AMD Secure Virtual Machine Ext-s required */ 77 CpuSVME, 78 /* VMX Instructions required */ 79 CpuVMX, 80 /* SMX Instructions required */ 81 CpuSMX, 82 /* SSSE3 support required */ 83 CpuSSSE3, 84 /* SSE4a support required */ 85 CpuSSE4a, 86 /* ABM New Instructions required */ 87 CpuABM, 88 /* SSE4.1 support required */ 89 CpuSSE4_1, 90 /* SSE4.2 support required */ 91 CpuSSE4_2, 92 /* AVX support required */ 93 CpuAVX, 94 /* AVX2 support required */ 95 CpuAVX2, 96 /* Intel AVX-512 Foundation Instructions support required */ 97 CpuAVX512F, 98 /* Intel AVX-512 Conflict Detection Instructions support required */ 99 CpuAVX512CD, 100 /* Intel AVX-512 Exponential and Reciprocal Instructions support 101 required */ 102 CpuAVX512ER, 103 /* Intel AVX-512 Prefetch Instructions support required */ 104 CpuAVX512PF, 105 /* Intel AVX-512 VL Instructions support required. */ 106 CpuAVX512VL, 107 /* Intel AVX-512 DQ Instructions support required. */ 108 CpuAVX512DQ, 109 /* Intel AVX-512 BW Instructions support required. */ 110 CpuAVX512BW, 111 /* Intel L1OM support required */ 112 CpuL1OM, 113 /* Intel K1OM support required */ 114 CpuK1OM, 115 /* Intel IAMCU support required */ 116 CpuIAMCU, 117 /* Xsave/xrstor New Instructions support required */ 118 CpuXsave, 119 /* Xsaveopt New Instructions support required */ 120 CpuXsaveopt, 121 /* AES support required */ 122 CpuAES, 123 /* PCLMUL support required */ 124 CpuPCLMUL, 125 /* FMA support required */ 126 CpuFMA, 127 /* FMA4 support required */ 128 CpuFMA4, 129 /* XOP support required */ 130 CpuXOP, 131 /* LWP support required */ 132 CpuLWP, 133 /* BMI support required */ 134 CpuBMI, 135 /* TBM support required */ 136 CpuTBM, 137 /* MOVBE Instruction support required */ 138 CpuMovbe, 139 /* CMPXCHG16B instruction support required. */ 140 CpuCX16, 141 /* EPT Instructions required */ 142 CpuEPT, 143 /* RDTSCP Instruction support required */ 144 CpuRdtscp, 145 /* FSGSBASE Instructions required */ 146 CpuFSGSBase, 147 /* RDRND Instructions required */ 148 CpuRdRnd, 149 /* F16C Instructions required */ 150 CpuF16C, 151 /* Intel BMI2 support required */ 152 CpuBMI2, 153 /* LZCNT support required */ 154 CpuLZCNT, 155 /* HLE support required */ 156 CpuHLE, 157 /* RTM support required */ 158 CpuRTM, 159 /* INVPCID Instructions required */ 160 CpuINVPCID, 161 /* VMFUNC Instruction required */ 162 CpuVMFUNC, 163 /* Intel MPX Instructions required */ 164 CpuMPX, 165 /* 64bit support available, used by -march= in assembler. */ 166 CpuLM, 167 /* RDRSEED instruction required. */ 168 CpuRDSEED, 169 /* Multi-presisionn add-carry instructions are required. */ 170 CpuADX, 171 /* Supports prefetchw and prefetch instructions. */ 172 CpuPRFCHW, 173 /* SMAP instructions required. */ 174 CpuSMAP, 175 /* SHA instructions required. */ 176 CpuSHA, 177 /* VREX support required */ 178 CpuVREX, 179 /* CLFLUSHOPT instruction required */ 180 CpuClflushOpt, 181 /* XSAVES/XRSTORS instruction required */ 182 CpuXSAVES, 183 /* XSAVEC instruction required */ 184 CpuXSAVEC, 185 /* PREFETCHWT1 instruction required */ 186 CpuPREFETCHWT1, 187 /* SE1 instruction required */ 188 CpuSE1, 189 /* CLWB instruction required */ 190 CpuCLWB, 191 /* PCOMMIT instruction required */ 192 CpuPCOMMIT, 193 /* Intel AVX-512 IFMA Instructions support required. */ 194 CpuAVX512IFMA, 195 /* Intel AVX-512 VBMI Instructions support required. */ 196 CpuAVX512VBMI, 197 /* mwaitx instruction required */ 198 CpuMWAITX, 199 /* Clzero instruction required */ 200 CpuCLZERO, 201 /* 64bit support required */ 202 Cpu64, 203 /* Not supported in the 64bit mode */ 204 CpuNo64, 205 /* AMD64 support required */ 206 CpuAMD64, 207 /* Intel64 support required */ 208 CpuIntel64, 209 /* The last bitfield in i386_cpu_flags. */ 210 CpuMax = CpuNo64 211}; 212 213#define CpuNumOfUints \ 214 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) 215#define CpuNumOfBits \ 216 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) 217 218/* If you get a compiler error for zero width of the unused field, 219 comment it out. */ 220#define CpuUnused (CpuMax + 1) 221 222/* We can check if an instruction is available with array instead 223 of bitfield. */ 224typedef union i386_cpu_flags 225{ 226 struct 227 { 228 unsigned int cpui186:1; 229 unsigned int cpui286:1; 230 unsigned int cpui386:1; 231 unsigned int cpui486:1; 232 unsigned int cpui586:1; 233 unsigned int cpui686:1; 234 unsigned int cpuclflush:1; 235 unsigned int cpunop:1; 236 unsigned int cpusyscall:1; 237 unsigned int cpu8087:1; 238 unsigned int cpu287:1; 239 unsigned int cpu387:1; 240 unsigned int cpu687:1; 241 unsigned int cpufisttp:1; 242 unsigned int cpummx:1; 243 unsigned int cpusse:1; 244 unsigned int cpusse2:1; 245 unsigned int cpua3dnow:1; 246 unsigned int cpua3dnowa:1; 247 unsigned int cpusse3:1; 248 unsigned int cpupadlock:1; 249 unsigned int cpusvme:1; 250 unsigned int cpuvmx:1; 251 unsigned int cpusmx:1; 252 unsigned int cpussse3:1; 253 unsigned int cpusse4a:1; 254 unsigned int cpuabm:1; 255 unsigned int cpusse4_1:1; 256 unsigned int cpusse4_2:1; 257 unsigned int cpuavx:1; 258 unsigned int cpuavx2:1; 259 unsigned int cpuavx512f:1; 260 unsigned int cpuavx512cd:1; 261 unsigned int cpuavx512er:1; 262 unsigned int cpuavx512pf:1; 263 unsigned int cpuavx512vl:1; 264 unsigned int cpuavx512dq:1; 265 unsigned int cpuavx512bw:1; 266 unsigned int cpul1om:1; 267 unsigned int cpuk1om:1; 268 unsigned int cpuiamcu:1; 269 unsigned int cpuxsave:1; 270 unsigned int cpuxsaveopt:1; 271 unsigned int cpuaes:1; 272 unsigned int cpupclmul:1; 273 unsigned int cpufma:1; 274 unsigned int cpufma4:1; 275 unsigned int cpuxop:1; 276 unsigned int cpulwp:1; 277 unsigned int cpubmi:1; 278 unsigned int cputbm:1; 279 unsigned int cpumovbe:1; 280 unsigned int cpucx16:1; 281 unsigned int cpuept:1; 282 unsigned int cpurdtscp:1; 283 unsigned int cpufsgsbase:1; 284 unsigned int cpurdrnd:1; 285 unsigned int cpuf16c:1; 286 unsigned int cpubmi2:1; 287 unsigned int cpulzcnt:1; 288 unsigned int cpuhle:1; 289 unsigned int cpurtm:1; 290 unsigned int cpuinvpcid:1; 291 unsigned int cpuvmfunc:1; 292 unsigned int cpumpx:1; 293 unsigned int cpulm:1; 294 unsigned int cpurdseed:1; 295 unsigned int cpuadx:1; 296 unsigned int cpuprfchw:1; 297 unsigned int cpusmap:1; 298 unsigned int cpusha:1; 299 unsigned int cpuvrex:1; 300 unsigned int cpuclflushopt:1; 301 unsigned int cpuxsaves:1; 302 unsigned int cpuxsavec:1; 303 unsigned int cpuprefetchwt1:1; 304 unsigned int cpuse1:1; 305 unsigned int cpuclwb:1; 306 unsigned int cpupcommit:1; 307 unsigned int cpuavx512ifma:1; 308 unsigned int cpuavx512vbmi:1; 309 unsigned int cpumwaitx:1; 310 unsigned int cpuclzero:1; 311 unsigned int cpu64:1; 312 unsigned int cpuno64:1; 313 unsigned int cpuamd64:1; 314 unsigned int cpuintel64:1; 315#ifdef CpuUnused 316 unsigned int unused:(CpuNumOfBits - CpuUnused); 317#endif 318 } bitfield; 319 unsigned int array[CpuNumOfUints]; 320} i386_cpu_flags; 321 322/* Position of opcode_modifier bits. */ 323 324enum 325{ 326 /* has direction bit. */ 327 D = 0, 328 /* set if operands can be words or dwords encoded the canonical way */ 329 W, 330 /* Skip the current insn and use the next insn in i386-opc.tbl to swap 331 operand in encoding. */ 332 S, 333 /* insn has a modrm byte. */ 334 Modrm, 335 /* register is in low 3 bits of opcode */ 336 ShortForm, 337 /* special case for jump insns. */ 338 Jump, 339 /* call and jump */ 340 JumpDword, 341 /* loop and jecxz */ 342 JumpByte, 343 /* special case for intersegment leaps/calls */ 344 JumpInterSegment, 345 /* FP insn memory format bit, sized by 0x4 */ 346 FloatMF, 347 /* src/dest swap for floats. */ 348 FloatR, 349 /* has float insn direction bit. */ 350 FloatD, 351 /* needs size prefix if in 32-bit mode */ 352 Size16, 353 /* needs size prefix if in 16-bit mode */ 354 Size32, 355 /* needs size prefix if in 64-bit mode */ 356 Size64, 357 /* check register size. */ 358 CheckRegSize, 359 /* instruction ignores operand size prefix and in Intel mode ignores 360 mnemonic size suffix check. */ 361 IgnoreSize, 362 /* default insn size depends on mode */ 363 DefaultSize, 364 /* b suffix on instruction illegal */ 365 No_bSuf, 366 /* w suffix on instruction illegal */ 367 No_wSuf, 368 /* l suffix on instruction illegal */ 369 No_lSuf, 370 /* s suffix on instruction illegal */ 371 No_sSuf, 372 /* q suffix on instruction illegal */ 373 No_qSuf, 374 /* long double suffix on instruction illegal */ 375 No_ldSuf, 376 /* instruction needs FWAIT */ 377 FWait, 378 /* quick test for string instructions */ 379 IsString, 380 /* quick test if branch instruction is MPX supported */ 381 BNDPrefixOk, 382 /* quick test for lockable instructions */ 383 IsLockable, 384 /* fake an extra reg operand for clr, imul and special register 385 processing for some instructions. */ 386 RegKludge, 387 /* The first operand must be xmm0 */ 388 FirstXmm0, 389 /* An implicit xmm0 as the first operand */ 390 Implicit1stXmm0, 391 /* The HLE prefix is OK: 392 1. With a LOCK prefix. 393 2. With or without a LOCK prefix. 394 3. With a RELEASE (0xf3) prefix. 395 */ 396#define HLEPrefixNone 0 397#define HLEPrefixLock 1 398#define HLEPrefixAny 2 399#define HLEPrefixRelease 3 400 HLEPrefixOk, 401 /* An instruction on which a "rep" prefix is acceptable. */ 402 RepPrefixOk, 403 /* Convert to DWORD */ 404 ToDword, 405 /* Convert to QWORD */ 406 ToQword, 407 /* Address prefix changes operand 0 */ 408 AddrPrefixOp0, 409 /* opcode is a prefix */ 410 IsPrefix, 411 /* instruction has extension in 8 bit imm */ 412 ImmExt, 413 /* instruction don't need Rex64 prefix. */ 414 NoRex64, 415 /* instruction require Rex64 prefix. */ 416 Rex64, 417 /* deprecated fp insn, gets a warning */ 418 Ugh, 419 /* insn has VEX prefix: 420 1: 128bit VEX prefix. 421 2: 256bit VEX prefix. 422 3: Scalar VEX prefix. 423 */ 424#define VEX128 1 425#define VEX256 2 426#define VEXScalar 3 427 Vex, 428 /* How to encode VEX.vvvv: 429 0: VEX.vvvv must be 1111b. 430 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where 431 the content of source registers will be preserved. 432 VEX.DDS. The second register operand is encoded in VEX.vvvv 433 where the content of first source register will be overwritten 434 by the result. 435 VEX.NDD2. The second destination register operand is encoded in 436 VEX.vvvv for instructions with 2 destination register operands. 437 For assembler, there are no difference between VEX.NDS, VEX.DDS 438 and VEX.NDD2. 439 2. VEX.NDD. Register destination is encoded in VEX.vvvv for 440 instructions with 1 destination register operand. 441 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one 442 of the operands can access a memory location. 443 */ 444#define VEXXDS 1 445#define VEXNDD 2 446#define VEXLWP 3 447 VexVVVV, 448 /* How the VEX.W bit is used: 449 0: Set by the REX.W bit. 450 1: VEX.W0. Should always be 0. 451 2: VEX.W1. Should always be 1. 452 */ 453#define VEXW0 1 454#define VEXW1 2 455 VexW, 456 /* VEX opcode prefix: 457 0: VEX 0x0F opcode prefix. 458 1: VEX 0x0F38 opcode prefix. 459 2: VEX 0x0F3A opcode prefix 460 3: XOP 0x08 opcode prefix. 461 4: XOP 0x09 opcode prefix 462 5: XOP 0x0A opcode prefix. 463 */ 464#define VEX0F 0 465#define VEX0F38 1 466#define VEX0F3A 2 467#define XOP08 3 468#define XOP09 4 469#define XOP0A 5 470 VexOpcode, 471 /* number of VEX source operands: 472 0: <= 2 source operands. 473 1: 2 XOP source operands. 474 2: 3 source operands. 475 */ 476#define XOP2SOURCES 1 477#define VEX3SOURCES 2 478 VexSources, 479 /* instruction has VEX 8 bit imm */ 480 VexImmExt, 481 /* Instruction with vector SIB byte: 482 1: 128bit vector register. 483 2: 256bit vector register. 484 3: 512bit vector register. 485 */ 486#define VecSIB128 1 487#define VecSIB256 2 488#define VecSIB512 3 489 VecSIB, 490 /* SSE to AVX support required */ 491 SSE2AVX, 492 /* No AVX equivalent */ 493 NoAVX, 494 495 /* insn has EVEX prefix: 496 1: 512bit EVEX prefix. 497 2: 128bit EVEX prefix. 498 3: 256bit EVEX prefix. 499 4: Length-ignored (LIG) EVEX prefix. 500 */ 501#define EVEX512 1 502#define EVEX128 2 503#define EVEX256 3 504#define EVEXLIG 4 505 EVex, 506 507 /* AVX512 masking support: 508 1: Zeroing-masking. 509 2: Merging-masking. 510 3: Both zeroing and merging masking. 511 */ 512#define ZEROING_MASKING 1 513#define MERGING_MASKING 2 514#define BOTH_MASKING 3 515 Masking, 516 517 /* Input element size of vector insn: 518 0: 32bit. 519 1: 64bit. 520 */ 521 VecESize, 522 523 /* Broadcast factor. 524 0: No broadcast. 525 1: 1to16 broadcast. 526 2: 1to8 broadcast. 527 */ 528#define NO_BROADCAST 0 529#define BROADCAST_1TO16 1 530#define BROADCAST_1TO8 2 531#define BROADCAST_1TO4 3 532#define BROADCAST_1TO2 4 533 Broadcast, 534 535 /* Static rounding control is supported. */ 536 StaticRounding, 537 538 /* Supress All Exceptions is supported. */ 539 SAE, 540 541 /* Copressed Disp8*N attribute. */ 542 Disp8MemShift, 543 544 /* Default mask isn't allowed. */ 545 NoDefMask, 546 547 /* Compatible with old (<= 2.8.1) versions of gcc */ 548 OldGcc, 549 /* AT&T mnemonic. */ 550 ATTMnemonic, 551 /* AT&T syntax. */ 552 ATTSyntax, 553 /* Intel syntax. */ 554 IntelSyntax, 555 /* The last bitfield in i386_opcode_modifier. */ 556 Opcode_Modifier_Max 557}; 558 559typedef struct i386_opcode_modifier 560{ 561 unsigned int d:1; 562 unsigned int w:1; 563 unsigned int s:1; 564 unsigned int modrm:1; 565 unsigned int shortform:1; 566 unsigned int jump:1; 567 unsigned int jumpdword:1; 568 unsigned int jumpbyte:1; 569 unsigned int jumpintersegment:1; 570 unsigned int floatmf:1; 571 unsigned int floatr:1; 572 unsigned int floatd:1; 573 unsigned int size16:1; 574 unsigned int size32:1; 575 unsigned int size64:1; 576 unsigned int checkregsize:1; 577 unsigned int ignoresize:1; 578 unsigned int defaultsize:1; 579 unsigned int no_bsuf:1; 580 unsigned int no_wsuf:1; 581 unsigned int no_lsuf:1; 582 unsigned int no_ssuf:1; 583 unsigned int no_qsuf:1; 584 unsigned int no_ldsuf:1; 585 unsigned int fwait:1; 586 unsigned int isstring:1; 587 unsigned int bndprefixok:1; 588 unsigned int islockable:1; 589 unsigned int regkludge:1; 590 unsigned int firstxmm0:1; 591 unsigned int implicit1stxmm0:1; 592 unsigned int hleprefixok:2; 593 unsigned int repprefixok:1; 594 unsigned int todword:1; 595 unsigned int toqword:1; 596 unsigned int addrprefixop0:1; 597 unsigned int isprefix:1; 598 unsigned int immext:1; 599 unsigned int norex64:1; 600 unsigned int rex64:1; 601 unsigned int ugh:1; 602 unsigned int vex:2; 603 unsigned int vexvvvv:2; 604 unsigned int vexw:2; 605 unsigned int vexopcode:3; 606 unsigned int vexsources:2; 607 unsigned int veximmext:1; 608 unsigned int vecsib:2; 609 unsigned int sse2avx:1; 610 unsigned int noavx:1; 611 unsigned int evex:3; 612 unsigned int masking:2; 613 unsigned int vecesize:1; 614 unsigned int broadcast:3; 615 unsigned int staticrounding:1; 616 unsigned int sae:1; 617 unsigned int disp8memshift:3; 618 unsigned int nodefmask:1; 619 unsigned int oldgcc:1; 620 unsigned int attmnemonic:1; 621 unsigned int attsyntax:1; 622 unsigned int intelsyntax:1; 623} i386_opcode_modifier; 624 625/* Position of operand_type bits. */ 626 627enum 628{ 629 /* 8bit register */ 630 Reg8 = 0, 631 /* 16bit register */ 632 Reg16, 633 /* 32bit register */ 634 Reg32, 635 /* 64bit register */ 636 Reg64, 637 /* Floating pointer stack register */ 638 FloatReg, 639 /* MMX register */ 640 RegMMX, 641 /* SSE register */ 642 RegXMM, 643 /* AVX registers */ 644 RegYMM, 645 /* AVX512 registers */ 646 RegZMM, 647 /* Vector Mask registers */ 648 RegMask, 649 /* Control register */ 650 Control, 651 /* Debug register */ 652 Debug, 653 /* Test register */ 654 Test, 655 /* 2 bit segment register */ 656 SReg2, 657 /* 3 bit segment register */ 658 SReg3, 659 /* 1 bit immediate */ 660 Imm1, 661 /* 8 bit immediate */ 662 Imm8, 663 /* 8 bit immediate sign extended */ 664 Imm8S, 665 /* 16 bit immediate */ 666 Imm16, 667 /* 32 bit immediate */ 668 Imm32, 669 /* 32 bit immediate sign extended */ 670 Imm32S, 671 /* 64 bit immediate */ 672 Imm64, 673 /* 8bit/16bit/32bit displacements are used in different ways, 674 depending on the instruction. For jumps, they specify the 675 size of the PC relative displacement, for instructions with 676 memory operand, they specify the size of the offset relative 677 to the base register, and for instructions with memory offset 678 such as `mov 1234,%al' they specify the size of the offset 679 relative to the segment base. */ 680 /* 8 bit displacement */ 681 Disp8, 682 /* 16 bit displacement */ 683 Disp16, 684 /* 32 bit displacement */ 685 Disp32, 686 /* 32 bit signed displacement */ 687 Disp32S, 688 /* 64 bit displacement */ 689 Disp64, 690 /* Accumulator %al/%ax/%eax/%rax */ 691 Acc, 692 /* Floating pointer top stack register %st(0) */ 693 FloatAcc, 694 /* Register which can be used for base or index in memory operand. */ 695 BaseIndex, 696 /* Register to hold in/out port addr = dx */ 697 InOutPortReg, 698 /* Register to hold shift count = cl */ 699 ShiftCount, 700 /* Absolute address for jump. */ 701 JumpAbsolute, 702 /* String insn operand with fixed es segment */ 703 EsSeg, 704 /* RegMem is for instructions with a modrm byte where the register 705 destination operand should be encoded in the mod and regmem fields. 706 Normally, it will be encoded in the reg field. We add a RegMem 707 flag to the destination register operand to indicate that it should 708 be encoded in the regmem field. */ 709 RegMem, 710 /* Memory. */ 711 Mem, 712 /* BYTE memory. */ 713 Byte, 714 /* WORD memory. 2 byte */ 715 Word, 716 /* DWORD memory. 4 byte */ 717 Dword, 718 /* FWORD memory. 6 byte */ 719 Fword, 720 /* QWORD memory. 8 byte */ 721 Qword, 722 /* TBYTE memory. 10 byte */ 723 Tbyte, 724 /* XMMWORD memory. */ 725 Xmmword, 726 /* YMMWORD memory. */ 727 Ymmword, 728 /* ZMMWORD memory. */ 729 Zmmword, 730 /* Unspecified memory size. */ 731 Unspecified, 732 /* Any memory size. */ 733 Anysize, 734 735 /* Vector 4 bit immediate. */ 736 Vec_Imm4, 737 738 /* Bound register. */ 739 RegBND, 740 741 /* Vector 8bit displacement */ 742 Vec_Disp8, 743 744 /* The last bitfield in i386_operand_type. */ 745 OTMax 746}; 747 748#define OTNumOfUints \ 749 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) 750#define OTNumOfBits \ 751 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) 752 753/* If you get a compiler error for zero width of the unused field, 754 comment it out. */ 755#define OTUnused (OTMax + 1) 756 757typedef union i386_operand_type 758{ 759 struct 760 { 761 unsigned int reg8:1; 762 unsigned int reg16:1; 763 unsigned int reg32:1; 764 unsigned int reg64:1; 765 unsigned int floatreg:1; 766 unsigned int regmmx:1; 767 unsigned int regxmm:1; 768 unsigned int regymm:1; 769 unsigned int regzmm:1; 770 unsigned int regmask:1; 771 unsigned int control:1; 772 unsigned int debug:1; 773 unsigned int test:1; 774 unsigned int sreg2:1; 775 unsigned int sreg3:1; 776 unsigned int imm1:1; 777 unsigned int imm8:1; 778 unsigned int imm8s:1; 779 unsigned int imm16:1; 780 unsigned int imm32:1; 781 unsigned int imm32s:1; 782 unsigned int imm64:1; 783 unsigned int disp8:1; 784 unsigned int disp16:1; 785 unsigned int disp32:1; 786 unsigned int disp32s:1; 787 unsigned int disp64:1; 788 unsigned int acc:1; 789 unsigned int floatacc:1; 790 unsigned int baseindex:1; 791 unsigned int inoutportreg:1; 792 unsigned int shiftcount:1; 793 unsigned int jumpabsolute:1; 794 unsigned int esseg:1; 795 unsigned int regmem:1; 796 unsigned int mem:1; 797 unsigned int byte:1; 798 unsigned int word:1; 799 unsigned int dword:1; 800 unsigned int fword:1; 801 unsigned int qword:1; 802 unsigned int tbyte:1; 803 unsigned int xmmword:1; 804 unsigned int ymmword:1; 805 unsigned int zmmword:1; 806 unsigned int unspecified:1; 807 unsigned int anysize:1; 808 unsigned int vec_imm4:1; 809 unsigned int regbnd:1; 810 unsigned int vec_disp8:1; 811#ifdef OTUnused 812 unsigned int unused:(OTNumOfBits - OTUnused); 813#endif 814 } bitfield; 815 unsigned int array[OTNumOfUints]; 816} i386_operand_type; 817 818typedef struct insn_template 819{ 820 /* instruction name sans width suffix ("mov" for movl insns) */ 821 char *name; 822 823 /* how many operands */ 824 unsigned int operands; 825 826 /* base_opcode is the fundamental opcode byte without optional 827 prefix(es). */ 828 unsigned int base_opcode; 829#define Opcode_D 0x2 /* Direction bit: 830 set if Reg --> Regmem; 831 unset if Regmem --> Reg. */ 832#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ 833#define Opcode_FloatD 0x400 /* Direction bit for float insns. */ 834 835 /* extension_opcode is the 3 bit extension for group <n> insns. 836 This field is also used to store the 8-bit opcode suffix for the 837 AMD 3DNow! instructions. 838 If this template has no extension opcode (the usual case) use None 839 Instructions */ 840 unsigned int extension_opcode; 841#define None 0xffff /* If no extension_opcode is possible. */ 842 843 /* Opcode length. */ 844 unsigned char opcode_length; 845 846 /* cpu feature flags */ 847 i386_cpu_flags cpu_flags; 848 849 /* the bits in opcode_modifier are used to generate the final opcode from 850 the base_opcode. These bits also are used to detect alternate forms of 851 the same instruction */ 852 i386_opcode_modifier opcode_modifier; 853 854 /* operand_types[i] describes the type of operand i. This is made 855 by OR'ing together all of the possible type masks. (e.g. 856 'operand_types[i] = Reg|Imm' specifies that operand i can be 857 either a register or an immediate operand. */ 858 i386_operand_type operand_types[MAX_OPERANDS]; 859} 860insn_template; 861 862extern const insn_template i386_optab[]; 863 864/* these are for register name --> number & type hash lookup */ 865typedef struct 866{ 867 char *reg_name; 868 i386_operand_type reg_type; 869 unsigned char reg_flags; 870#define RegRex 0x1 /* Extended register. */ 871#define RegRex64 0x2 /* Extended 8 bit register. */ 872#define RegVRex 0x4 /* Extended vector register. */ 873 unsigned char reg_num; 874#define RegRip ((unsigned char ) ~0) 875#define RegEip (RegRip - 1) 876/* EIZ and RIZ are fake index registers. */ 877#define RegEiz (RegEip - 1) 878#define RegRiz (RegEiz - 1) 879/* FLAT is a fake segment register (Intel mode). */ 880#define RegFlat ((unsigned char) ~0) 881 signed char dw2_regnum[2]; 882#define Dw2Inval (-1) 883} 884reg_entry; 885 886/* Entries in i386_regtab. */ 887#define REGNAM_AL 1 888#define REGNAM_AX 25 889#define REGNAM_EAX 41 890 891extern const reg_entry i386_regtab[]; 892extern const unsigned int i386_regtab_size; 893 894typedef struct 895{ 896 char *seg_name; 897 unsigned int seg_prefix; 898} 899seg_entry; 900 901extern const seg_entry cs; 902extern const seg_entry ds; 903extern const seg_entry ss; 904extern const seg_entry es; 905extern const seg_entry fs; 906extern const seg_entry gs; 907