1/* Xtensa configuration settings. 2 Copyright (C) 2022 Free Software Foundation, Inc. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 2, or (at your option) 7 any later version. 8 9 This program is distributed in the hope that it will be useful, but 10 WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 12 General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, write to the Free Software 16 Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 17 18#ifndef XTENSA_DYNCONFIG_H 19#define XTENSA_DYNCONFIG_H 20 21#ifdef __cplusplus 22extern "C" { 23#endif 24 25/* 26 * Config versioning. 27 * 28 * When new config entries need to be passed through dynconfig 29 * create new xtensa_config_v<N> structure and put them there. 30 * Declare new function xtensa_get_config_v<N> (void). 31 * Define corresponding X*HAL_* macros by accessing xtensa_get_config_v<N> (). 32 * Define macro XTENSA_CONFIG_V<N>_ENTRY_LIST by listing 33 * XTENSA_CONFIG_ENTRY for every entry in the new structure. 34 * Add constant definition for the new xtensa_config_v<N> to the 35 * XTENSA_CONFIG_INSTANCE_LIST. 36 * Add XTENSA_CONFIG_V<N>_ENTRY_LIST to the XTENSA_CONFIG_ENTRY_LIST. 37 * 38 * On the user side (gcc/binutils/...) add definition for the function 39 * xtensa_get_config_v<N> (void). 40 */ 41 42struct xtensa_config_v1 43{ 44 int xchal_have_be; 45 int xchal_have_density; 46 int xchal_have_const16; 47 int xchal_have_abs; 48 int xchal_have_addx; 49 int xchal_have_l32r; 50 int xshal_use_absolute_literals; 51 int xshal_have_text_section_literals; 52 int xchal_have_mac16; 53 int xchal_have_mul16; 54 int xchal_have_mul32; 55 int xchal_have_mul32_high; 56 int xchal_have_div32; 57 int xchal_have_nsa; 58 int xchal_have_minmax; 59 int xchal_have_sext; 60 int xchal_have_loops; 61 int xchal_have_threadptr; 62 int xchal_have_release_sync; 63 int xchal_have_s32c1i; 64 int xchal_have_booleans; 65 int xchal_have_fp; 66 int xchal_have_fp_div; 67 int xchal_have_fp_recip; 68 int xchal_have_fp_sqrt; 69 int xchal_have_fp_rsqrt; 70 int xchal_have_fp_postinc; 71 int xchal_have_dfp; 72 int xchal_have_dfp_div; 73 int xchal_have_dfp_recip; 74 int xchal_have_dfp_sqrt; 75 int xchal_have_dfp_rsqrt; 76 int xchal_have_windowed; 77 int xchal_num_aregs; 78 int xchal_have_wide_branches; 79 int xchal_have_predicted_branches; 80 int xchal_icache_size; 81 int xchal_dcache_size; 82 int xchal_icache_linesize; 83 int xchal_dcache_linesize; 84 int xchal_icache_linewidth; 85 int xchal_dcache_linewidth; 86 int xchal_dcache_is_writeback; 87 int xchal_have_mmu; 88 int xchal_mmu_min_pte_page_size; 89 int xchal_have_debug; 90 int xchal_num_ibreak; 91 int xchal_num_dbreak; 92 int xchal_debuglevel; 93 int xchal_max_instruction_size; 94 int xchal_inst_fetch_width; 95 int xshal_abi; 96 int xthal_abi_windowed; 97 int xthal_abi_call0; 98}; 99 100struct xtensa_config_v2 101{ 102 int xchal_m_stage; 103 int xtensa_march_latest; 104 int xtensa_march_earliest; 105}; 106 107typedef struct xtensa_isa_internal_struct xtensa_isa_internal; 108 109extern const void *xtensa_load_config (const char *name, 110 const void *no_plugin_def, 111 const void *no_name_def); 112extern const struct xtensa_config_v1 *xtensa_get_config_v1 (void); 113extern const struct xtensa_config_v2 *xtensa_get_config_v2 (void); 114 115#ifdef XTENSA_CONFIG_DEFINITION 116 117#ifndef XCHAL_HAVE_MUL32_HIGH 118#define XCHAL_HAVE_MUL32_HIGH 0 119#endif 120 121#ifndef XCHAL_HAVE_RELEASE_SYNC 122#define XCHAL_HAVE_RELEASE_SYNC 0 123#endif 124 125#ifndef XCHAL_HAVE_S32C1I 126#define XCHAL_HAVE_S32C1I 0 127#endif 128 129#ifndef XCHAL_HAVE_THREADPTR 130#define XCHAL_HAVE_THREADPTR 0 131#endif 132 133#ifndef XCHAL_HAVE_FP_POSTINC 134#define XCHAL_HAVE_FP_POSTINC 0 135#endif 136 137#ifndef XCHAL_HAVE_DFP 138#define XCHAL_HAVE_DFP 0 139#endif 140 141#ifndef XCHAL_HAVE_DFP_DIV 142#define XCHAL_HAVE_DFP_DIV 0 143#endif 144 145#ifndef XCHAL_HAVE_DFP_RECIP 146#define XCHAL_HAVE_DFP_RECIP 0 147#endif 148 149#ifndef XCHAL_HAVE_DFP_SQRT 150#define XCHAL_HAVE_DFP_SQRT 0 151#endif 152 153#ifndef XCHAL_HAVE_DFP_RSQRT 154#define XCHAL_HAVE_DFP_RSQRT 0 155#endif 156 157#ifndef XSHAL_HAVE_TEXT_SECTION_LITERALS 158#define XSHAL_HAVE_TEXT_SECTION_LITERALS 0 159#endif 160 161#ifndef XCHAL_MMU_MIN_PTE_PAGE_SIZE 162#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 1 163#endif 164 165#ifndef XTHAL_ABI_WINDOWED 166#define XTHAL_ABI_WINDOWED 0 167#endif 168 169#ifndef XTHAL_ABI_CALL0 170#define XTHAL_ABI_CALL0 1 171#endif 172 173#ifndef XCHAL_M_STAGE 174#define XCHAL_M_STAGE 0 175#endif 176 177#ifndef XTENSA_MARCH_LATEST 178#define XTENSA_MARCH_LATEST 0 179#endif 180 181#ifndef XTENSA_MARCH_EARLIEST 182#define XTENSA_MARCH_EARLIEST 0 183#endif 184 185#define XTENSA_CONFIG_ENTRY(a) a 186 187#define XTENSA_CONFIG_V1_ENTRY_LIST \ 188 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_BE), \ 189 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DENSITY), \ 190 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_CONST16), \ 191 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_ABS), \ 192 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_ADDX), \ 193 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_L32R), \ 194 XTENSA_CONFIG_ENTRY(XSHAL_USE_ABSOLUTE_LITERALS), \ 195 XTENSA_CONFIG_ENTRY(XSHAL_HAVE_TEXT_SECTION_LITERALS), \ 196 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MAC16), \ 197 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MUL16), \ 198 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MUL32), \ 199 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MUL32_HIGH), \ 200 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DIV32), \ 201 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_NSA), \ 202 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MINMAX), \ 203 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_SEXT), \ 204 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_LOOPS), \ 205 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_THREADPTR), \ 206 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_RELEASE_SYNC), \ 207 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_S32C1I), \ 208 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_BOOLEANS), \ 209 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP), \ 210 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_DIV), \ 211 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_RECIP), \ 212 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_SQRT), \ 213 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_RSQRT), \ 214 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_FP_POSTINC), \ 215 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP), \ 216 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_DIV), \ 217 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_RECIP), \ 218 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_SQRT), \ 219 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DFP_RSQRT), \ 220 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_WINDOWED), \ 221 XTENSA_CONFIG_ENTRY(XCHAL_NUM_AREGS), \ 222 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_WIDE_BRANCHES), \ 223 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_PREDICTED_BRANCHES), \ 224 XTENSA_CONFIG_ENTRY(XCHAL_ICACHE_SIZE), \ 225 XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_SIZE), \ 226 XTENSA_CONFIG_ENTRY(XCHAL_ICACHE_LINESIZE), \ 227 XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_LINESIZE), \ 228 XTENSA_CONFIG_ENTRY(XCHAL_ICACHE_LINEWIDTH), \ 229 XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_LINEWIDTH), \ 230 XTENSA_CONFIG_ENTRY(XCHAL_DCACHE_IS_WRITEBACK), \ 231 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_MMU), \ 232 XTENSA_CONFIG_ENTRY(XCHAL_MMU_MIN_PTE_PAGE_SIZE), \ 233 XTENSA_CONFIG_ENTRY(XCHAL_HAVE_DEBUG), \ 234 XTENSA_CONFIG_ENTRY(XCHAL_NUM_IBREAK), \ 235 XTENSA_CONFIG_ENTRY(XCHAL_NUM_DBREAK), \ 236 XTENSA_CONFIG_ENTRY(XCHAL_DEBUGLEVEL), \ 237 XTENSA_CONFIG_ENTRY(XCHAL_MAX_INSTRUCTION_SIZE), \ 238 XTENSA_CONFIG_ENTRY(XCHAL_INST_FETCH_WIDTH), \ 239 XTENSA_CONFIG_ENTRY(XSHAL_ABI), \ 240 XTENSA_CONFIG_ENTRY(XTHAL_ABI_WINDOWED), \ 241 XTENSA_CONFIG_ENTRY(XTHAL_ABI_CALL0) 242 243#define XTENSA_CONFIG_V2_ENTRY_LIST \ 244 XTENSA_CONFIG_ENTRY(XCHAL_M_STAGE), \ 245 XTENSA_CONFIG_ENTRY(XTENSA_MARCH_LATEST), \ 246 XTENSA_CONFIG_ENTRY(XTENSA_MARCH_EARLIEST) 247 248#define XTENSA_CONFIG_INSTANCE_LIST \ 249const struct xtensa_config_v1 xtensa_config_v1 = { \ 250 XTENSA_CONFIG_V1_ENTRY_LIST, \ 251}; \ 252const struct xtensa_config_v2 xtensa_config_v2 = { \ 253 XTENSA_CONFIG_V2_ENTRY_LIST, \ 254} 255 256#define XTENSA_CONFIG_ENTRY_LIST \ 257 XTENSA_CONFIG_V1_ENTRY_LIST, \ 258 XTENSA_CONFIG_V2_ENTRY_LIST 259 260#else /* XTENSA_CONFIG_DEFINITION */ 261 262#undef XCHAL_HAVE_BE 263#define XCHAL_HAVE_BE (xtensa_get_config_v1 ()->xchal_have_be) 264 265#undef XCHAL_HAVE_DENSITY 266#define XCHAL_HAVE_DENSITY (xtensa_get_config_v1 ()->xchal_have_density) 267 268#undef XCHAL_HAVE_CONST16 269#define XCHAL_HAVE_CONST16 (xtensa_get_config_v1 ()->xchal_have_const16) 270 271#undef XCHAL_HAVE_ABS 272#define XCHAL_HAVE_ABS (xtensa_get_config_v1 ()->xchal_have_abs) 273 274#undef XCHAL_HAVE_ADDX 275#define XCHAL_HAVE_ADDX (xtensa_get_config_v1 ()->xchal_have_addx) 276 277#undef XCHAL_HAVE_L32R 278#define XCHAL_HAVE_L32R (xtensa_get_config_v1 ()->xchal_have_l32r) 279 280#undef XSHAL_USE_ABSOLUTE_LITERALS 281#define XSHAL_USE_ABSOLUTE_LITERALS (xtensa_get_config_v1 ()->xshal_use_absolute_literals) 282 283#undef XSHAL_HAVE_TEXT_SECTION_LITERALS 284#define XSHAL_HAVE_TEXT_SECTION_LITERALS (xtensa_get_config_v1 ()->xshal_have_text_section_literals) 285 286#undef XCHAL_HAVE_MAC16 287#define XCHAL_HAVE_MAC16 (xtensa_get_config_v1 ()->xchal_have_mac16) 288 289#undef XCHAL_HAVE_MUL16 290#define XCHAL_HAVE_MUL16 (xtensa_get_config_v1 ()->xchal_have_mul16) 291 292#undef XCHAL_HAVE_MUL32 293#define XCHAL_HAVE_MUL32 (xtensa_get_config_v1 ()->xchal_have_mul32) 294 295#undef XCHAL_HAVE_MUL32_HIGH 296#define XCHAL_HAVE_MUL32_HIGH (xtensa_get_config_v1 ()->xchal_have_mul32_high) 297 298#undef XCHAL_HAVE_DIV32 299#define XCHAL_HAVE_DIV32 (xtensa_get_config_v1 ()->xchal_have_div32) 300 301#undef XCHAL_HAVE_NSA 302#define XCHAL_HAVE_NSA (xtensa_get_config_v1 ()->xchal_have_nsa) 303 304#undef XCHAL_HAVE_MINMAX 305#define XCHAL_HAVE_MINMAX (xtensa_get_config_v1 ()->xchal_have_minmax) 306 307#undef XCHAL_HAVE_SEXT 308#define XCHAL_HAVE_SEXT (xtensa_get_config_v1 ()->xchal_have_sext) 309 310#undef XCHAL_HAVE_LOOPS 311#define XCHAL_HAVE_LOOPS (xtensa_get_config_v1 ()->xchal_have_loops) 312 313#undef XCHAL_HAVE_THREADPTR 314#define XCHAL_HAVE_THREADPTR (xtensa_get_config_v1 ()->xchal_have_threadptr) 315 316#undef XCHAL_HAVE_RELEASE_SYNC 317#define XCHAL_HAVE_RELEASE_SYNC (xtensa_get_config_v1 ()->xchal_have_release_sync) 318 319#undef XCHAL_HAVE_S32C1I 320#define XCHAL_HAVE_S32C1I (xtensa_get_config_v1 ()->xchal_have_s32c1i) 321 322#undef XCHAL_HAVE_BOOLEANS 323#define XCHAL_HAVE_BOOLEANS (xtensa_get_config_v1 ()->xchal_have_booleans) 324 325#undef XCHAL_HAVE_FP 326#define XCHAL_HAVE_FP (xtensa_get_config_v1 ()->xchal_have_fp) 327 328#undef XCHAL_HAVE_FP_DIV 329#define XCHAL_HAVE_FP_DIV (xtensa_get_config_v1 ()->xchal_have_fp_div) 330 331#undef XCHAL_HAVE_FP_RECIP 332#define XCHAL_HAVE_FP_RECIP (xtensa_get_config_v1 ()->xchal_have_fp_recip) 333 334#undef XCHAL_HAVE_FP_SQRT 335#define XCHAL_HAVE_FP_SQRT (xtensa_get_config_v1 ()->xchal_have_fp_sqrt) 336 337#undef XCHAL_HAVE_FP_RSQRT 338#define XCHAL_HAVE_FP_RSQRT (xtensa_get_config_v1 ()->xchal_have_fp_rsqrt) 339 340#undef XCHAL_HAVE_FP_POSTINC 341#define XCHAL_HAVE_FP_POSTINC (xtensa_get_config_v1 ()->xchal_have_fp_postinc) 342 343#undef XCHAL_HAVE_DFP 344#define XCHAL_HAVE_DFP (xtensa_get_config_v1 ()->xchal_have_dfp) 345 346#undef XCHAL_HAVE_DFP_DIV 347#define XCHAL_HAVE_DFP_DIV (xtensa_get_config_v1 ()->xchal_have_dfp_div) 348 349#undef XCHAL_HAVE_DFP_RECIP 350#define XCHAL_HAVE_DFP_RECIP (xtensa_get_config_v1 ()->xchal_have_dfp_recip) 351 352#undef XCHAL_HAVE_DFP_SQRT 353#define XCHAL_HAVE_DFP_SQRT (xtensa_get_config_v1 ()->xchal_have_dfp_sqrt) 354 355#undef XCHAL_HAVE_DFP_RSQRT 356#define XCHAL_HAVE_DFP_RSQRT (xtensa_get_config_v1 ()->xchal_have_dfp_rsqrt) 357 358#undef XCHAL_HAVE_WINDOWED 359#define XCHAL_HAVE_WINDOWED (xtensa_get_config_v1 ()->xchal_have_windowed) 360 361#undef XCHAL_NUM_AREGS 362#define XCHAL_NUM_AREGS (xtensa_get_config_v1 ()->xchal_num_aregs) 363 364#undef XCHAL_HAVE_WIDE_BRANCHES 365#define XCHAL_HAVE_WIDE_BRANCHES (xtensa_get_config_v1 ()->xchal_have_wide_branches) 366 367#undef XCHAL_HAVE_PREDICTED_BRANCHES 368#define XCHAL_HAVE_PREDICTED_BRANCHES (xtensa_get_config_v1 ()->xchal_have_predicted_branches) 369 370 371#undef XCHAL_ICACHE_SIZE 372#define XCHAL_ICACHE_SIZE (xtensa_get_config_v1 ()->xchal_icache_size) 373 374#undef XCHAL_DCACHE_SIZE 375#define XCHAL_DCACHE_SIZE (xtensa_get_config_v1 ()->xchal_dcache_size) 376 377#undef XCHAL_ICACHE_LINESIZE 378#define XCHAL_ICACHE_LINESIZE (xtensa_get_config_v1 ()->xchal_icache_linesize) 379 380#undef XCHAL_DCACHE_LINESIZE 381#define XCHAL_DCACHE_LINESIZE (xtensa_get_config_v1 ()->xchal_dcache_linesize) 382 383#undef XCHAL_ICACHE_LINEWIDTH 384#define XCHAL_ICACHE_LINEWIDTH (xtensa_get_config_v1 ()->xchal_icache_linewidth) 385 386#undef XCHAL_DCACHE_LINEWIDTH 387#define XCHAL_DCACHE_LINEWIDTH (xtensa_get_config_v1 ()->xchal_dcache_linewidth) 388 389#undef XCHAL_DCACHE_IS_WRITEBACK 390#define XCHAL_DCACHE_IS_WRITEBACK (xtensa_get_config_v1 ()->xchal_dcache_is_writeback) 391 392 393#undef XCHAL_HAVE_MMU 394#define XCHAL_HAVE_MMU (xtensa_get_config_v1 ()->xchal_have_mmu) 395 396#undef XCHAL_MMU_MIN_PTE_PAGE_SIZE 397#define XCHAL_MMU_MIN_PTE_PAGE_SIZE (xtensa_get_config_v1 ()->xchal_mmu_min_pte_page_size) 398 399 400#undef XCHAL_HAVE_DEBUG 401#define XCHAL_HAVE_DEBUG (xtensa_get_config_v1 ()->xchal_have_debug) 402 403#undef XCHAL_NUM_IBREAK 404#define XCHAL_NUM_IBREAK (xtensa_get_config_v1 ()->xchal_num_ibreak) 405 406#undef XCHAL_NUM_DBREAK 407#define XCHAL_NUM_DBREAK (xtensa_get_config_v1 ()->xchal_num_dbreak) 408 409#undef XCHAL_DEBUGLEVEL 410#define XCHAL_DEBUGLEVEL (xtensa_get_config_v1 ()->xchal_debuglevel) 411 412 413#undef XCHAL_MAX_INSTRUCTION_SIZE 414#define XCHAL_MAX_INSTRUCTION_SIZE (xtensa_get_config_v1 ()->xchal_max_instruction_size) 415 416#undef XCHAL_INST_FETCH_WIDTH 417#define XCHAL_INST_FETCH_WIDTH (xtensa_get_config_v1 ()->xchal_inst_fetch_width) 418 419 420#undef XSHAL_ABI 421#undef XTHAL_ABI_WINDOWED 422#undef XTHAL_ABI_CALL0 423#define XSHAL_ABI (xtensa_get_config_v1 ()->xshal_abi) 424#define XTHAL_ABI_WINDOWED (xtensa_get_config_v1 ()->xthal_abi_windowed) 425#define XTHAL_ABI_CALL0 (xtensa_get_config_v1 ()->xthal_abi_call0) 426 427 428#undef XCHAL_M_STAGE 429#define XCHAL_M_STAGE (xtensa_get_config_v2 ()->xchal_m_stage) 430 431#undef XTENSA_MARCH_LATEST 432#define XTENSA_MARCH_LATEST (xtensa_get_config_v2 ()->xtensa_march_latest) 433 434#undef XTENSA_MARCH_EARLIEST 435#define XTENSA_MARCH_EARLIEST (xtensa_get_config_v2 ()->xtensa_march_earliest) 436 437#endif /* XTENSA_CONFIG_DEFINITION */ 438 439#ifdef __cplusplus 440} 441#endif 442#endif /* !XTENSA_DYNCONFIG_H */ 443