score-inst.h revision 1.1.1.7
1245450Sganbold/* score-inst.h -- Score Instructions Table 2245450Sganbold Copyright (C) 2006-2022 Free Software Foundation, Inc. 3245450Sganbold Contributed by: 4245450Sganbold Brain.lin (brain.lin@sunplusct.com) 5245450Sganbold Mei Ligang (ligang@sunnorth.com.cn) 6245450Sganbold Pei-Lin Tsai (pltsai@sunplus.com) 7245450Sganbold 8245450Sganbold This file is part of GAS, the GNU Assembler. 9245450Sganbold 10245450Sganbold GAS is free software; you can redistribute it and/or modify 11245450Sganbold it under the terms of the GNU General Public License as published by 12245450Sganbold the Free Software Foundation; either version 3, or (at your option) 13245450Sganbold any later version. 14245450Sganbold 15245450Sganbold GAS is distributed in the hope that it will be useful, 16245450Sganbold but WITHOUT ANY WARRANTY; without even the implied warranty of 17245450Sganbold MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18245450Sganbold GNU General Public License for more details. 19245450Sganbold 20245450Sganbold You should have received a copy of the GNU General Public License 21245450Sganbold along with GAS; see the file COPYING3. If not, write to the Free 22245450Sganbold Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 23245450Sganbold 02110-1301, USA. */ 24245450Sganbold 25245450Sganbold#ifndef SCORE_INST_H 26245450Sganbold#define SCORE_INST_H 27245450Sganbold 28245450Sganbold#define LDST_UNALIGN_MASK 0x0000007f 29245450Sganbold#define UA_LCB 0x00000060 30245450Sganbold#define UA_LCW 0x00000062 31245450Sganbold#define UA_LCE 0x00000066 32245900Sganbold#define UA_SCB 0x00000068 33245900Sganbold#define UA_SCW 0x0000006a 34245450Sganbold#define UA_SCE 0x0000006e 35245450Sganbold#define UA_LL 0x0000000c 36245450Sganbold#define UA_SC 0x0000000e 37245450Sganbold#define LDST16_RR_MASK 0x0000000f 38245450Sganbold#define N16_LW 8 39245450Sganbold#define N16_LH 9 40245450Sganbold#define N16_POP 10 41245450Sganbold#define N16_LBU 11 42245450Sganbold#define N16_SW 12 43245450Sganbold#define N16_SH 13 44245450Sganbold#define N16_PUSH 14 45245450Sganbold#define N16_SB 15 46245450Sganbold#define LDST16_RI_MASK 0x7007 47245450Sganbold#define N16_LWP 0x7000 48245450Sganbold#define N16_LHP 0x7001 49245450Sganbold#define N16_LBUP 0x7003 50245450Sganbold#define N16_SWP 0x7004 51245450Sganbold#define N16_SHP 0x7005 52245450Sganbold#define N16_SBP 0x7007 53245450Sganbold#define N16_LIU 0x5000 54245450Sganbold 55245450Sganbold#define OPC_PSEUDOLDST_MASK 0x00000007 56245450Sganbold 57245900Sganboldenum 58245450Sganbold{ 59245450Sganbold INSN_LW = 0, 60245450Sganbold INSN_LH = 1, 61245450Sganbold INSN_LHU = 2, 62245450Sganbold INSN_LB = 3, 63245450Sganbold INSN_SW = 4, 64246057Sganbold INSN_SH = 5, 65246057Sganbold INSN_LBU = 6, 66246057Sganbold INSN_SB = 7, 67246057Sganbold}; 68246057Sganbold 69246057Sganbold/* Sub opcdoe opcode. */ 70246057Sganboldenum 71245450Sganbold{ 72245900Sganbold INSN16_LBU = 11, 73245450Sganbold INSN16_LH = 9, 74245450Sganbold INSN16_LW = 8, 75245450Sganbold INSN16_SB = 15, 76245450Sganbold INSN16_SH = 13, 77245450Sganbold INSN16_SW = 12, 78245450Sganbold}; 79246660Sgonzo 80246660Sgonzoenum 81246660Sgonzo{ 82246660Sgonzo LDST_NOUPDATE = 0, 83246660Sgonzo LDST_PRE = 1, 84246660Sgonzo LDST_POST = 2, 85246342Sganbold}; 86246342Sganbold 87246342Sganboldenum score_insn_type 88246342Sganbold{ 89246342Sganbold Rd_I4, 90246342Sganbold Rd_I5, 91246342Sganbold Rd_rvalueBP_I5, 92246342Sganbold Rd_lvalueBP_I5, 93246342Sganbold Rd_Rs_I5, 94245450Sganbold x_Rs_I5, 95245900Sganbold x_I5_x, 96245450Sganbold Rd_I8, 97245450Sganbold Rd_Rs_I14, 98245450Sganbold I15, 99245450Sganbold Rd_I16, 100245450Sganbold Rd_I30, 101245450Sganbold Rd_I32, 102245900Sganbold Rd_rvalueRs_SI10, 103245450Sganbold Rd_lvalueRs_SI10, 104245450Sganbold Rd_rvalueRs_preSI12, 105245450Sganbold Rd_rvalueRs_postSI12, 106245450Sganbold Rd_lvalueRs_preSI12, 107245450Sganbold Rd_lvalueRs_postSI12, 108245450Sganbold Rd_Rs_SI14, 109245450Sganbold Rd_rvalueRs_SI15, 110245450Sganbold Rd_lvalueRs_SI15, 111245450Sganbold Rd_SI5, 112245450Sganbold Rd_SI6, 113245450Sganbold Rd_SI16, 114245450Sganbold PC_DISP8div2, 115245450Sganbold PC_DISP11div2, 116245450Sganbold PC_DISP19div2, 117245450Sganbold PC_DISP24div2, 118245450Sganbold Rd_Rs_Rs, 119245450Sganbold x_Rs_x, 120245450Sganbold x_Rs_Rs, 121245450Sganbold Rd_Rs_x, 122245450Sganbold Rd_x_Rs, 123245450Sganbold Rd_x_x, 124245450Sganbold Rd_Rs, 125245450Sganbold Rd_HighRs, 126245450Sganbold Rd_lvalueRs, 127 Rd_rvalueRs, 128 Rd_lvalue32Rs, 129 Rd_rvalue32Rs, 130 x_Rs, 131 NO_OPD, 132 NO16_OPD, 133 OP5_rvalueRs_SI15, 134 I5_Rs_Rs_I5_OP5, 135 x_rvalueRs_post4, 136 Rd_rvalueRs_post4, 137 Rd_x_I5, 138 Rd_lvalueRs_post4, 139 x_lvalueRs_post4, 140 Rd_LowRs, 141 Rd_Rs_Rs_imm, 142 Insn_Type_PCE, 143 Insn_Type_SYN, 144 Insn_GP, 145 Insn_PIC, 146 Insn_internal, 147 Insn_BCMP, 148 Ra_I9_I5, 149}; 150 151enum score_data_type 152{ 153 _IMM4 = 0, 154 _IMM5, 155 _IMM8, 156 _IMM14, 157 _IMM15, 158 _IMM16, 159 _SIMM10 = 6, 160 _SIMM12, 161 _SIMM14, 162 _SIMM15, 163 _SIMM16, 164 _SIMM14_NEG = 11, 165 _IMM16_NEG, 166 _SIMM16_NEG, 167 _IMM20, 168 _IMM25, 169 _DISP8div2 = 16, 170 _DISP11div2, 171 _DISP19div2, 172 _DISP24div2, 173 _VALUE, 174 _VALUE_HI16, 175 _VALUE_LO16, 176 _VALUE_LDST_LO16 = 23, 177 _SIMM16_LA, 178 _IMM5_RSHIFT_1, 179 _IMM5_RSHIFT_2, 180 _SIMM16_LA_POS, 181 _IMM5_RANGE_8_31, 182 _IMM10_RSHIFT_2, 183 _GP_IMM15 = 30, 184 _GP_IMM14 = 31, 185 _SIMM16_pic = 42, /* Index in score_df_range. */ 186 _IMM16_LO16_pic = 43, 187 _IMM16_pic = 44, 188 189 _SIMM5 = 45, 190 _SIMM6 = 46, 191 _IMM32 = 47, 192 _SIMM32 = 48, 193 _IMM11 = 49, 194 _IMM5_MULTI_LOAD = 50, 195}; 196 197#define REG_TMP 1 198 199#define OP_REG_TYPE (1 << 6) 200#define OP_IMM_TYPE (1 << 7) 201#define OP_SH_REGD (OP_REG_TYPE |20) 202#define OP_SH_REGS1 (OP_REG_TYPE |15) 203#define OP_SH_REGS2 (OP_REG_TYPE |10) 204#define OP_SH_I (OP_IMM_TYPE | 1) 205#define OP_SH_RI15 (OP_IMM_TYPE | 0) 206#define OP_SH_I12 (OP_IMM_TYPE | 3) 207#define OP_SH_DISP24 (OP_IMM_TYPE | 1) 208#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15) 209#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1) 210#define OP_SH_I5 (OP_IMM_TYPE |10) 211#define OP_SH_I10 (OP_IMM_TYPE | 5) 212#define OP_SH_COPID (OP_IMM_TYPE | 5) 213#define OP_SH_TRAPI5 (OP_IMM_TYPE |15) 214#define OP_SH_I15 (OP_IMM_TYPE |10) 215 216#define OP16_SH_REGD (OP_REG_TYPE | 8) 217#define OP16_SH_REGS1 (OP_REG_TYPE | 4) 218#define OP16_SH_I45 (OP_IMM_TYPE | 3) 219#define OP16_SH_I8 (OP_IMM_TYPE | 0) 220#define OP16_SH_DISP8 (OP_IMM_TYPE | 0) 221#define OP16_SH_DISP11 (OP_IMM_TYPE | 1) 222 223enum insn_class 224{ 225 INSN_CLASS_16, 226 INSN_CLASS_32, 227 INSN_CLASS_48, 228 INSN_CLASS_PCE, 229 INSN_CLASS_SYN 230}; 231 232/* s3_s7: Globals for both tc-score.c and elf32-score.c. */ 233extern int score3; 234extern int score7; 235 236#endif 237