mips.h revision 1.1.1.5
1/* mips.h. Mips opcode list for GDB, the GNU debugger. 2 Copyright (C) 1993-2016 Free Software Foundation, Inc. 3 Contributed by Ralph Campbell and OSF 4 Commented and modified by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 3, 11 or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING3. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 21 MA 02110-1301, USA. */ 22 23#ifndef _MIPS_H_ 24#define _MIPS_H_ 25 26#include "bfd.h" 27 28#ifdef __cplusplus 29extern "C" { 30#endif 31 32/* These are bit masks and shift counts to use to access the various 33 fields of an instruction. To retrieve the X field of an 34 instruction, use the expression 35 (i >> OP_SH_X) & OP_MASK_X 36 To set the same field (to j), use 37 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) 38 39 Make sure you use fields that are appropriate for the instruction, 40 of course. 41 42 The 'i' format uses OP, RS, RT and IMMEDIATE. 43 44 The 'j' format uses OP and TARGET. 45 46 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. 47 48 The 'b' format uses OP, RS, RT and DELTA. 49 50 The floating point 'i' format uses OP, RS, RT and IMMEDIATE. 51 52 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. 53 54 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the 55 breakpoint instruction are not defined; Kane says the breakpoint 56 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers 57 only use ten bits). An optional two-operand form of break/sdbbp 58 allows the lower ten bits to be set too, and MIPS32 and later 59 architectures allow 20 bits to be set with a signal operand 60 (using CODE20). 61 62 The syscall instruction uses CODE20. 63 64 The general coprocessor instructions use COPZ. */ 65 66#define OP_MASK_OP 0x3f 67#define OP_SH_OP 26 68#define OP_MASK_RS 0x1f 69#define OP_SH_RS 21 70#define OP_MASK_FR 0x1f 71#define OP_SH_FR 21 72#define OP_MASK_FMT 0x1f 73#define OP_SH_FMT 21 74#define OP_MASK_BCC 0x7 75#define OP_SH_BCC 18 76#define OP_MASK_CODE 0x3ff 77#define OP_SH_CODE 16 78#define OP_MASK_CODE2 0x3ff 79#define OP_SH_CODE2 6 80#define OP_MASK_RT 0x1f 81#define OP_SH_RT 16 82#define OP_MASK_FT 0x1f 83#define OP_SH_FT 16 84#define OP_MASK_CACHE 0x1f 85#define OP_SH_CACHE 16 86#define OP_MASK_RD 0x1f 87#define OP_SH_RD 11 88#define OP_MASK_FS 0x1f 89#define OP_SH_FS 11 90#define OP_MASK_PREFX 0x1f 91#define OP_SH_PREFX 11 92#define OP_MASK_CCC 0x7 93#define OP_SH_CCC 8 94#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ 95#define OP_SH_CODE20 6 96#define OP_MASK_SHAMT 0x1f 97#define OP_SH_SHAMT 6 98#define OP_MASK_EXTLSB OP_MASK_SHAMT 99#define OP_SH_EXTLSB OP_SH_SHAMT 100#define OP_MASK_STYPE OP_MASK_SHAMT 101#define OP_SH_STYPE OP_SH_SHAMT 102#define OP_MASK_FD 0x1f 103#define OP_SH_FD 6 104#define OP_MASK_TARGET 0x3ffffff 105#define OP_SH_TARGET 0 106#define OP_MASK_COPZ 0x1ffffff 107#define OP_SH_COPZ 0 108#define OP_MASK_IMMEDIATE 0xffff 109#define OP_SH_IMMEDIATE 0 110#define OP_MASK_DELTA 0xffff 111#define OP_SH_DELTA 0 112#define OP_MASK_FUNCT 0x3f 113#define OP_SH_FUNCT 0 114#define OP_MASK_SPEC 0x3f 115#define OP_SH_SPEC 0 116#define OP_SH_LOCC 8 /* FP condition code. */ 117#define OP_SH_HICC 18 /* FP condition code. */ 118#define OP_MASK_CC 0x7 119#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ 120#define OP_MASK_COP1NORM 0x1 /* a single bit. */ 121#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ 122#define OP_MASK_COP1SPEC 0xf 123#define OP_MASK_COP1SCLR 0x4 124#define OP_MASK_COP1CMP 0x3 125#define OP_SH_COP1CMP 4 126#define OP_SH_FORMAT 21 /* FP short format field. */ 127#define OP_MASK_FORMAT 0x7 128#define OP_SH_TRUE 16 129#define OP_MASK_TRUE 0x1 130#define OP_SH_GE 17 131#define OP_MASK_GE 0x01 132#define OP_SH_UNSIGNED 16 133#define OP_MASK_UNSIGNED 0x1 134#define OP_SH_HINT 16 135#define OP_MASK_HINT 0x1f 136#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ 137#define OP_MASK_MMI 0x3f 138#define OP_SH_MMISUB 6 139#define OP_MASK_MMISUB 0x1f 140#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ 141#define OP_SH_PERFREG 1 142#define OP_SH_SEL 0 /* Coprocessor select field. */ 143#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ 144#define OP_SH_CODE19 6 /* 19 bit wait code. */ 145#define OP_MASK_CODE19 0x7ffff 146#define OP_SH_ALN 21 147#define OP_MASK_ALN 0x7 148#define OP_SH_VSEL 21 149#define OP_MASK_VSEL 0x1f 150#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, 151 but 0x8-0xf don't select bytes. */ 152#define OP_SH_VECBYTE 22 153#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ 154#define OP_SH_VECALIGN 21 155#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ 156#define OP_SH_INSMSB 11 157#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 158#define OP_SH_EXTMSBD 11 159 160/* MIPS DSP ASE */ 161#define OP_SH_DSPACC 11 162#define OP_MASK_DSPACC 0x3 163#define OP_SH_DSPACC_S 21 164#define OP_MASK_DSPACC_S 0x3 165#define OP_SH_DSPSFT 20 166#define OP_MASK_DSPSFT 0x3f 167#define OP_SH_DSPSFT_7 19 168#define OP_MASK_DSPSFT_7 0x7f 169#define OP_SH_SA3 21 170#define OP_MASK_SA3 0x7 171#define OP_SH_SA4 21 172#define OP_MASK_SA4 0xf 173#define OP_SH_IMM8 16 174#define OP_MASK_IMM8 0xff 175#define OP_SH_IMM10 16 176#define OP_MASK_IMM10 0x3ff 177#define OP_SH_WRDSP 11 178#define OP_MASK_WRDSP 0x3f 179#define OP_SH_RDDSP 16 180#define OP_MASK_RDDSP 0x3f 181#define OP_SH_BP 11 182#define OP_MASK_BP 0x3 183 184/* MIPS MT ASE */ 185#define OP_SH_MT_U 5 186#define OP_MASK_MT_U 0x1 187#define OP_SH_MT_H 4 188#define OP_MASK_MT_H 0x1 189#define OP_SH_MTACC_T 18 190#define OP_MASK_MTACC_T 0x3 191#define OP_SH_MTACC_D 13 192#define OP_MASK_MTACC_D 0x3 193 194/* MIPS MCU ASE */ 195#define OP_MASK_3BITPOS 0x7 196#define OP_SH_3BITPOS 12 197#define OP_MASK_OFFSET12 0xfff 198#define OP_SH_OFFSET12 0 199 200#define OP_OP_COP0 0x10 201#define OP_OP_COP1 0x11 202#define OP_OP_COP2 0x12 203#define OP_OP_COP3 0x13 204#define OP_OP_LWC1 0x31 205#define OP_OP_LWC2 0x32 206#define OP_OP_LWC3 0x33 /* a.k.a. pref */ 207#define OP_OP_LDC1 0x35 208#define OP_OP_LDC2 0x36 209#define OP_OP_LDC3 0x37 /* a.k.a. ld */ 210#define OP_OP_SWC1 0x39 211#define OP_OP_SWC2 0x3a 212#define OP_OP_SWC3 0x3b 213#define OP_OP_SDC1 0x3d 214#define OP_OP_SDC2 0x3e 215#define OP_OP_SDC3 0x3f /* a.k.a. sd */ 216 217/* MIPS VIRT ASE */ 218#define OP_MASK_CODE10 0x3ff 219#define OP_SH_CODE10 11 220 221/* Values in the 'VSEL' field. */ 222#define MDMX_FMTSEL_IMM_QH 0x1d 223#define MDMX_FMTSEL_IMM_OB 0x1e 224#define MDMX_FMTSEL_VEC_QH 0x15 225#define MDMX_FMTSEL_VEC_OB 0x16 226 227/* UDI */ 228#define OP_SH_UDI1 6 229#define OP_MASK_UDI1 0x1f 230#define OP_SH_UDI2 6 231#define OP_MASK_UDI2 0x3ff 232#define OP_SH_UDI3 6 233#define OP_MASK_UDI3 0x7fff 234#define OP_SH_UDI4 6 235#define OP_MASK_UDI4 0xfffff 236 237/* Octeon */ 238#define OP_SH_BBITIND 16 239#define OP_MASK_BBITIND 0x1f 240#define OP_SH_CINSPOS 6 241#define OP_MASK_CINSPOS 0x1f 242#define OP_SH_CINSLM1 11 243#define OP_MASK_CINSLM1 0x1f 244#define OP_SH_SEQI 6 245#define OP_MASK_SEQI 0x3ff 246 247/* Loongson */ 248#define OP_SH_OFFSET_A 6 249#define OP_MASK_OFFSET_A 0xff 250#define OP_SH_OFFSET_B 3 251#define OP_MASK_OFFSET_B 0xff 252#define OP_SH_OFFSET_C 6 253#define OP_MASK_OFFSET_C 0x1ff 254#define OP_SH_RZ 0 255#define OP_MASK_RZ 0x1f 256#define OP_SH_FZ 0 257#define OP_MASK_FZ 0x1f 258 259/* Every MICROMIPSOP_X definition requires a corresponding OP_X 260 definition, and vice versa. This simplifies various parts 261 of the operand handling in GAS. The fields below only exist 262 in the microMIPS encoding, so define each one to have an empty 263 range. */ 264#define OP_MASK_TRAP 0 265#define OP_SH_TRAP 0 266#define OP_MASK_OFFSET10 0 267#define OP_SH_OFFSET10 0 268#define OP_MASK_RS3 0 269#define OP_SH_RS3 0 270#define OP_MASK_MB 0 271#define OP_SH_MB 0 272#define OP_MASK_MC 0 273#define OP_SH_MC 0 274#define OP_MASK_MD 0 275#define OP_SH_MD 0 276#define OP_MASK_ME 0 277#define OP_SH_ME 0 278#define OP_MASK_MF 0 279#define OP_SH_MF 0 280#define OP_MASK_MG 0 281#define OP_SH_MG 0 282#define OP_MASK_MH 0 283#define OP_SH_MH 0 284#define OP_MASK_MJ 0 285#define OP_SH_MJ 0 286#define OP_MASK_ML 0 287#define OP_SH_ML 0 288#define OP_MASK_MM 0 289#define OP_SH_MM 0 290#define OP_MASK_MN 0 291#define OP_SH_MN 0 292#define OP_MASK_MP 0 293#define OP_SH_MP 0 294#define OP_MASK_MQ 0 295#define OP_SH_MQ 0 296#define OP_MASK_IMMA 0 297#define OP_SH_IMMA 0 298#define OP_MASK_IMMB 0 299#define OP_SH_IMMB 0 300#define OP_MASK_IMMC 0 301#define OP_SH_IMMC 0 302#define OP_MASK_IMMF 0 303#define OP_SH_IMMF 0 304#define OP_MASK_IMMG 0 305#define OP_SH_IMMG 0 306#define OP_MASK_IMMH 0 307#define OP_SH_IMMH 0 308#define OP_MASK_IMMI 0 309#define OP_SH_IMMI 0 310#define OP_MASK_IMMJ 0 311#define OP_SH_IMMJ 0 312#define OP_MASK_IMML 0 313#define OP_SH_IMML 0 314#define OP_MASK_IMMM 0 315#define OP_SH_IMMM 0 316#define OP_MASK_IMMN 0 317#define OP_SH_IMMN 0 318#define OP_MASK_IMMO 0 319#define OP_SH_IMMO 0 320#define OP_MASK_IMMP 0 321#define OP_SH_IMMP 0 322#define OP_MASK_IMMQ 0 323#define OP_SH_IMMQ 0 324#define OP_MASK_IMMU 0 325#define OP_SH_IMMU 0 326#define OP_MASK_IMMW 0 327#define OP_SH_IMMW 0 328#define OP_MASK_IMMX 0 329#define OP_SH_IMMX 0 330#define OP_MASK_IMMY 0 331#define OP_SH_IMMY 0 332 333/* Enhanced VA Scheme */ 334#define OP_SH_EVAOFFSET 7 335#define OP_MASK_EVAOFFSET 0x1ff 336 337/* Enumerates the various types of MIPS operand. */ 338enum mips_operand_type { 339 /* Described by mips_int_operand. */ 340 OP_INT, 341 342 /* Described by mips_mapped_int_operand. */ 343 OP_MAPPED_INT, 344 345 /* Described by mips_msb_operand. */ 346 OP_MSB, 347 348 /* Described by mips_reg_operand. */ 349 OP_REG, 350 351 /* Like OP_REG, but can be omitted if the register is the same as the 352 previous operand. */ 353 OP_OPTIONAL_REG, 354 355 /* Described by mips_reg_pair_operand. */ 356 OP_REG_PAIR, 357 358 /* Described by mips_pcrel_operand. */ 359 OP_PCREL, 360 361 /* A performance register. The field is 5 bits in size, but the supported 362 values are much more restricted. */ 363 OP_PERF_REG, 364 365 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts 366 as a normal 9-bit signed offset that is multiplied by four, but there 367 are four special cases: 368 369 -2 * 4 => -258 * 4 370 -1 * 4 => -257 * 4 371 0 * 4 => 256 * 4 372 1 * 4 => 257 * 4. */ 373 OP_ADDIUSP_INT, 374 375 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two 376 5-bit register fields, both of which must be set to the destination 377 register. */ 378 OP_CLO_CLZ_DEST, 379 380 /* A register list for a microMIPS LWM or SWM instruction. The operand 381 size determines whether the 16-bit or 32-bit encoding is required. */ 382 OP_LWM_SWM_LIST, 383 384 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */ 385 OP_ENTRY_EXIT_LIST, 386 387 /* The register list and frame size for a MIPS16 SAVE or RESTORE 388 instruction. */ 389 OP_SAVE_RESTORE_LIST, 390 391 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions: 392 393 V Meaning 394 ----- ------- 395 0EEE0 8 copies of $vN[E], OB format 396 0EE01 4 copies of $vN[E], QH format 397 10110 all 8 elements of $vN, OB format 398 10101 all 4 elements of $vN, QH format 399 11110 8 copies of immediate N, OB format 400 11101 4 copies of immediate N, QH format. */ 401 OP_MDMX_IMM_REG, 402 403 /* A register operand that must match the destination register. */ 404 OP_REPEAT_DEST_REG, 405 406 /* A register operand that must match the previous register. */ 407 OP_REPEAT_PREV_REG, 408 409 /* $pc, which has no encoding in the architectural instruction. */ 410 OP_PC, 411 412 /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines 413 which. */ 414 OP_VU0_SUFFIX, 415 416 /* Like OP_VU0_SUFFIX, but used when the operand's value has already 417 been set. Any suffix used here must match the previous value. */ 418 OP_VU0_MATCH_SUFFIX, 419 420 /* An index selected by an integer, e.g. [1]. */ 421 OP_IMM_INDEX, 422 423 /* An index selected by a register, e.g. [$2]. */ 424 OP_REG_INDEX, 425 426 /* The operand spans two 5-bit register fields, both of which must be set to 427 the source register. */ 428 OP_SAME_RS_RT, 429 430 /* Described by mips_prev_operand. */ 431 OP_CHECK_PREV, 432 433 /* A register operand that must not be zero. */ 434 OP_NON_ZERO_REG 435}; 436 437/* Enumerates the types of MIPS register. */ 438enum mips_reg_operand_type { 439 /* General registers $0-$31. Software names like $at can also be used. */ 440 OP_REG_GP, 441 442 /* Floating-point registers $f0-$f31. */ 443 OP_REG_FP, 444 445 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes 446 can also be written $fcc0-$fcc7. */ 447 OP_REG_CCC, 448 449 /* FPRs used in a vector capacity. They can be written $f0-$f31 450 or $v0-$v31, although the latter form is not used for the VR5400 451 vector instructions. */ 452 OP_REG_VEC, 453 454 /* DSP accumulator registers $ac0-$ac3. */ 455 OP_REG_ACC, 456 457 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can 458 also be used in some contexts. */ 459 OP_REG_COPRO, 460 461 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can 462 also be used in some contexts. */ 463 OP_REG_HW, 464 465 /* Floating-point registers $vf0-$vf31. */ 466 OP_REG_VF, 467 468 /* Integer registers $vi0-$vi31. */ 469 OP_REG_VI, 470 471 /* R5900 VU0 registers $I, $Q, $R and $ACC. */ 472 OP_REG_R5900_I, 473 OP_REG_R5900_Q, 474 OP_REG_R5900_R, 475 OP_REG_R5900_ACC, 476 477 /* MSA registers $w0-$w31. */ 478 OP_REG_MSA, 479 480 /* MSA control registers $0-$31. */ 481 OP_REG_MSA_CTRL 482}; 483 484/* Base class for all operands. */ 485struct mips_operand 486{ 487 /* The type of the operand. */ 488 enum mips_operand_type type; 489 490 /* The operand occupies SIZE bits of the instruction, starting at LSB. */ 491 unsigned short size; 492 unsigned short lsb; 493}; 494 495/* Describes an integer operand with a regular encoding pattern. */ 496struct mips_int_operand 497{ 498 struct mips_operand root; 499 500 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT. 501 The cyclically previous field value encodes 1 << SHIFT less than that, 502 and so on. E.g. 503 504 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves, 505 but 15 encodes -1. 506 507 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is 508 shifted left two places. 509 510 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except 511 that 0 encodes 8. 512 513 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */ 514 unsigned int max_val; 515 int bias; 516 unsigned int shift; 517 518 /* True if the operand should be printed as hex rather than decimal. */ 519 bfd_boolean print_hex; 520}; 521 522/* Uses a lookup table to describe a small integer operand. */ 523struct mips_mapped_int_operand 524{ 525 struct mips_operand root; 526 527 /* Maps each encoding value to the integer that it represents. */ 528 const int *int_map; 529 530 /* True if the operand should be printed as hex rather than decimal. */ 531 bfd_boolean print_hex; 532}; 533 534/* An operand that encodes the most significant bit position of a bitfield. 535 Given a bitfield that spans bits [MSB, LSB], some operands of this type 536 encode MSB directly while others encode MSB - LSB. Each operand of this 537 type is preceded by an integer operand that specifies LSB. 538 539 The assembly form varies between instructions. For some instructions, 540 such as EXT, the operand is written as the bitfield size. For others, 541 such as EXTS, it is written in raw MSB - LSB form. */ 542struct mips_msb_operand 543{ 544 struct mips_operand root; 545 546 /* The assembly-level operand encoded by a field value of 0. */ 547 int bias; 548 549 /* True if the operand encodes MSB directly, false if it encodes 550 MSB - LSB. */ 551 bfd_boolean add_lsb; 552 553 /* The maximum value of MSB + 1. */ 554 unsigned int opsize; 555}; 556 557/* Describes a single register operand. */ 558struct mips_reg_operand 559{ 560 struct mips_operand root; 561 562 /* The type of register. */ 563 enum mips_reg_operand_type reg_type; 564 565 /* If nonnull, REG_MAP[N] gives the register associated with encoding N, 566 otherwise the encoding is the same as the register number. */ 567 const unsigned char *reg_map; 568}; 569 570/* Describes an operand that which must match a condition based on the 571 previous operand. */ 572struct mips_check_prev_operand 573{ 574 struct mips_operand root; 575 576 bfd_boolean greater_than_ok; 577 bfd_boolean less_than_ok; 578 bfd_boolean equal_ok; 579 bfd_boolean zero_ok; 580}; 581 582/* Describes an operand that encodes a pair of registers. */ 583struct mips_reg_pair_operand 584{ 585 struct mips_operand root; 586 587 /* The type of register. */ 588 enum mips_reg_operand_type reg_type; 589 590 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */ 591 unsigned char *reg1_map; 592 unsigned char *reg2_map; 593}; 594 595/* Describes an operand that is calculated relative to a base PC. 596 The base PC is usually the address of the following instruction, 597 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */ 598struct mips_pcrel_operand 599{ 600 /* Encodes the offset. */ 601 struct mips_int_operand root; 602 603 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC', 604 which is then added to the offset encoded by ROOT. */ 605 unsigned int align_log2 : 8; 606 607 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then 608 reinstated. This is true for jumps and branches and false for 609 PC-relative data instructions. */ 610 unsigned int include_isa_bit : 1; 611 612 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted. 613 This is true for JALX and false otherwise. */ 614 unsigned int flip_isa_bit : 1; 615}; 616 617/* Return true if the assembly syntax allows OPERAND to be omitted. */ 618 619static inline bfd_boolean 620mips_optional_operand_p (const struct mips_operand *operand) 621{ 622 return (operand->type == OP_OPTIONAL_REG 623 || operand->type == OP_REPEAT_PREV_REG); 624} 625 626/* Return a version of INSN in which the field specified by OPERAND 627 has value UVAL. */ 628 629static inline unsigned int 630mips_insert_operand (const struct mips_operand *operand, unsigned int insn, 631 unsigned int uval) 632{ 633 unsigned int mask; 634 635 mask = (1 << operand->size) - 1; 636 insn &= ~(mask << operand->lsb); 637 insn |= (uval & mask) << operand->lsb; 638 return insn; 639} 640 641/* Extract OPERAND from instruction INSN. */ 642 643static inline unsigned int 644mips_extract_operand (const struct mips_operand *operand, unsigned int insn) 645{ 646 return (insn >> operand->lsb) & ((1 << operand->size) - 1); 647} 648 649/* UVAL is the value encoded by OPERAND. Return it in signed form. */ 650 651static inline int 652mips_signed_operand (const struct mips_operand *operand, unsigned int uval) 653{ 654 unsigned int sign_bit, mask; 655 656 mask = (1 << operand->size) - 1; 657 sign_bit = 1 << (operand->size - 1); 658 return ((uval + sign_bit) & mask) - sign_bit; 659} 660 661/* Return the integer that OPERAND encodes as UVAL. */ 662 663static inline int 664mips_decode_int_operand (const struct mips_int_operand *operand, 665 unsigned int uval) 666{ 667 uval |= (operand->max_val - uval) & -(1 << operand->root.size); 668 uval += operand->bias; 669 uval <<= operand->shift; 670 return uval; 671} 672 673/* Return the maximum value that can be encoded by OPERAND. */ 674 675static inline int 676mips_int_operand_max (const struct mips_int_operand *operand) 677{ 678 return (operand->max_val + operand->bias) << operand->shift; 679} 680 681/* Return the minimum value that can be encoded by OPERAND. */ 682 683static inline int 684mips_int_operand_min (const struct mips_int_operand *operand) 685{ 686 unsigned int mask; 687 688 mask = (1 << operand->root.size) - 1; 689 return mips_int_operand_max (operand) - (mask << operand->shift); 690} 691 692/* Return the register that OPERAND encodes as UVAL. */ 693 694static inline int 695mips_decode_reg_operand (const struct mips_reg_operand *operand, 696 unsigned int uval) 697{ 698 if (operand->reg_map) 699 uval = operand->reg_map[uval]; 700 return uval; 701} 702 703/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC. 704 Return the address that it encodes. */ 705 706static inline bfd_vma 707mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand, 708 bfd_vma base_pc, unsigned int uval) 709{ 710 bfd_vma addr; 711 712 addr = base_pc & -(1 << operand->align_log2); 713 addr += mips_decode_int_operand (&operand->root, uval); 714 if (operand->include_isa_bit) 715 addr |= base_pc & 1; 716 if (operand->flip_isa_bit) 717 addr ^= 1; 718 return addr; 719} 720 721/* This structure holds information for a particular instruction. */ 722 723struct mips_opcode 724{ 725 /* The name of the instruction. */ 726 const char *name; 727 /* A string describing the arguments for this instruction. */ 728 const char *args; 729 /* The basic opcode for the instruction. When assembling, this 730 opcode is modified by the arguments to produce the actual opcode 731 that is used. If pinfo is INSN_MACRO, then this is 0. */ 732 unsigned long match; 733 /* If pinfo is not INSN_MACRO, then this is a bit mask for the 734 relevant portions of the opcode when disassembling. If the 735 actual opcode anded with the match field equals the opcode field, 736 then we have found the correct instruction. If pinfo is 737 INSN_MACRO, then this field is the macro identifier. */ 738 unsigned long mask; 739 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection 740 of bits describing the instruction, notably any relevant hazard 741 information. */ 742 unsigned long pinfo; 743 /* A collection of additional bits describing the instruction. */ 744 unsigned long pinfo2; 745 /* A collection of bits describing the instruction sets of which this 746 instruction or macro is a member. */ 747 unsigned long membership; 748 /* A collection of bits describing the ASE of which this instruction 749 or macro is a member. */ 750 unsigned long ase; 751 /* A collection of bits describing the instruction sets of which this 752 instruction or macro is not a member. */ 753 unsigned long exclusions; 754}; 755 756/* These are the characters which may appear in the args field of an 757 instruction. They appear in the order in which the fields appear 758 when the instruction is used. Commas and parentheses in the args 759 string are ignored when assembling, and written into the output 760 when disassembling. 761 762 Each of these characters corresponds to a mask field defined above. 763 764 "1" 5 bit sync type (OP_*_STYPE) 765 "<" 5 bit shift amount (OP_*_SHAMT) 766 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) 767 "a" 26 bit target address (OP_*_TARGET) 768 "+i" likewise, but flips bit 0 769 "b" 5 bit base register (OP_*_RS) 770 "c" 10 bit breakpoint code (OP_*_CODE) 771 "d" 5 bit destination register specifier (OP_*_RD) 772 "h" 5 bit prefx hint (OP_*_PREFX) 773 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) 774 "j" 16 bit signed immediate (OP_*_DELTA) 775 "k" 5 bit cache opcode in target register position (OP_*_CACHE) 776 "o" 16 bit signed offset (OP_*_DELTA) 777 "p" 16 bit PC relative branch target address (OP_*_DELTA) 778 "q" 10 bit extra breakpoint code (OP_*_CODE2) 779 "r" 5 bit same register used as both source and target (OP_*_RS) 780 "s" 5 bit source register specifier (OP_*_RS) 781 "t" 5 bit target register (OP_*_RT) 782 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) 783 "v" 5 bit same register used as both source and destination (OP_*_RS) 784 "w" 5 bit same register used as both target and destination (OP_*_RT) 785 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT 786 (used by clo and clz) 787 "C" 25 bit coprocessor function code (OP_*_COPZ) 788 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) 789 "J" 19 bit wait function code (OP_*_CODE19) 790 "x" accept and ignore register name 791 "z" must be zero register 792 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) 793 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes 794 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for 795 microMIPS compatibility). 796 Enforces: 0 <= pos < 32. 797 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). 798 Requires that "+A" or "+E" occur first to set position. 799 Enforces: 0 < (pos+size) <= 32. 800 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). 801 Requires that "+A" or "+E" occur first to set position. 802 Enforces: 0 < (pos+size) <= 32. 803 (Also used by "dext" w/ different limits, but limits for 804 that are checked by the M_DEXT macro.) 805 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). 806 Enforces: 32 <= pos < 64. 807 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). 808 Requires that "+A" or "+E" occur first to set position. 809 Enforces: 32 < (pos+size) <= 64. 810 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). 811 Requires that "+A" or "+E" occur first to set position. 812 Enforces: 32 < (pos+size) <= 64. 813 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). 814 Requires that "+A" or "+E" occur first to set position. 815 Enforces: 32 < (pos+size) <= 64. 816 817 Floating point instructions: 818 "D" 5 bit destination register (OP_*_FD) 819 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) 820 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) 821 "S" 5 bit fs source 1 register (OP_*_FS) 822 "T" 5 bit ft source 2 register (OP_*_FT) 823 "R" 5 bit fr source 3 register (OP_*_FR) 824 "V" 5 bit same register used as floating source and destination (OP_*_FS) 825 "W" 5 bit same register used as floating target and destination (OP_*_FT) 826 827 Coprocessor instructions: 828 "E" 5 bit target register (OP_*_RT) 829 "G" 5 bit destination register (OP_*_RD) 830 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) 831 "P" 5 bit performance-monitor register (OP_*_PERFREG) 832 "e" 5 bit vector register byte specifier (OP_*_VECBYTE) 833 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) 834 835 Macro instructions: 836 "A" General 32 bit expression 837 "I" 32 bit immediate (value placed in imm_expr). 838 "F" 64 bit floating point constant in .rdata 839 "L" 64 bit floating point constant in .lit8 840 "f" 32 bit floating point constant 841 "l" 32 bit floating point constant in .lit4 842 843 MDMX and VR5400 instruction operands (note that while these use the 844 FP register fields, the MDMX instructions accept both $fN and $vN names 845 for the registers): 846 "O" alignment offset (OP_*_ALN) 847 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) 848 "X" destination register (OP_*_FD) 849 "Y" source register (OP_*_FS) 850 "Z" source register (OP_*_FT) 851 852 R5900 VU0 Macromode instructions: 853 "+5" 5 bit floating point register (FD) 854 "+6" 5 bit floating point register (FS) 855 "+7" 5 bit floating point register (FT) 856 "+8" 5 bit integer register (FD) 857 "+9" 5 bit integer register (FS) 858 "+0" 5 bit integer register (FT) 859 "+K" match an existing 4-bit channel mask starting at bit 21 860 "+L" 2-bit channel index starting at bit 21 861 "+M" 2-bit channel index starting at bit 23 862 "+N" match an existing 2-bit channel index starting at bit 0 863 "+f" 15 bit immediate for VCALLMS 864 "+g" 5 bit signed immediate for VIADDI 865 "+m" $ACC register (syntax only) 866 "+q" $Q register (syntax only) 867 "+r" $R register (syntax only) 868 "+y" $I register (syntax only) 869 "#+" "++" decorator in ($reg++) sequence 870 "#-" "--" decorator in (--$reg) sequence 871 872 DSP ASE usage: 873 "2" 2 bit unsigned immediate for byte align (OP_*_BP) 874 "3" 3 bit unsigned immediate (OP_*_SA3) 875 "4" 4 bit unsigned immediate (OP_*_SA4) 876 "5" 8 bit unsigned immediate (OP_*_IMM8) 877 "6" 5 bit unsigned immediate (OP_*_RS) 878 "7" 2 bit dsp accumulator register (OP_*_DSPACC) 879 "8" 6 bit unsigned immediate (OP_*_WRDSP) 880 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) 881 "0" 6 bit signed immediate (OP_*_DSPSFT) 882 ":" 7 bit signed immediate (OP_*_DSPSFT_7) 883 "'" 6 bit unsigned immediate (OP_*_RDDSP) 884 "@" 10 bit signed immediate (OP_*_IMM10) 885 886 MT ASE usage: 887 "!" 1 bit usermode flag (OP_*_MT_U) 888 "$" 1 bit load high flag (OP_*_MT_H) 889 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) 890 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) 891 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) 892 "+t" 5 bit coprocessor 0 destination register (OP_*_RT) 893 894 MCU ASE usage: 895 "~" 12 bit offset (OP_*_OFFSET12) 896 "\" 3 bit position for aset and aclr (OP_*_3BITPOS) 897 898 VIRT ASE usage: 899 "+J" 10-bit hypcall code (OP_*CODE10) 900 901 UDI immediates: 902 "+1" UDI immediate bits 6-10 903 "+2" UDI immediate bits 6-15 904 "+3" UDI immediate bits 6-20 905 "+4" UDI immediate bits 6-25 906 907 Octeon: 908 "+x" Bit index field of bbit. Enforces: 0 <= index < 32. 909 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, 910 otherwise skips to next candidate. 911 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. 912 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if 913 32 <= pos < 64, otherwise skips to next candidate. 914 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. 915 "+s" Length-minus-one field of cins32/exts32. Requires msb position 916 of the field to be <= 31. 917 "+S" Length-minus-one field of cins/exts. Requires msb position 918 of the field to be <= 63. 919 920 Loongson-3A: 921 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) 922 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) 923 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) 924 "+z" 5-bit rz register (OP_*_RZ) 925 "+Z" 5-bit fz register (OP_*_FZ) 926 927 Enhanced VA Scheme: 928 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) 929 930 MSA Extension: 931 "+d" 5-bit MSA register (FD) 932 "+e" 5-bit MSA register (FS) 933 "+h" 5-bit MSA register (FT) 934 "+k" 5-bit GPR at bit 6 935 "+l" 5-bit MSA control register at bit 6 936 "+n" 5-bit MSA control register at bit 11 937 "+o" 4-bit vector element index at bit 16 938 "+u" 3-bit vector element index at bit 16 939 "+v" 2-bit vector element index at bit 16 940 "+w" 1-bit vector element index at bit 16 941 "+T" (-512 .. 511) << 0 at bit 16 942 "+U" (-512 .. 511) << 1 at bit 16 943 "+V" (-512 .. 511) << 2 at bit 16 944 "+W" (-512 .. 511) << 3 at bit 16 945 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 946 "+!" 3 bit unsigned bit position at bit 16 947 "+@" 4 bit unsigned bit position at bit 16 948 "+#" 6 bit unsigned bit position at bit 16 949 "+$" 5 bit unsigned immediate at bit 16 950 "+%" 5 bit signed immediate at bit 16 951 "+^" 10 bit signed immediate at bit 11 952 "+&" 0 vector element index 953 "+*" 5-bit register vector element index at bit 16 954 "+|" 8-bit mask at bit 16 955 956 MIPS R6: 957 "+:" 11-bit mask at bit 0 958 "+'" 26 bit PC relative branch target address 959 "+"" 21 bit PC relative branch target address 960 "+;" 5 bit same register in both OP_*_RS and OP_*_RT 961 "+I" 2bit unsigned bit position at bit 6 962 "+O" 3bit unsigned bit position at bit 6 963 "+R" must be program counter 964 "-a" (-262144 .. 262143) << 2 at bit 0 965 "-b" (-131072 .. 131071) << 3 at bit 0 966 "-d" Same as destination register GP 967 "-s" 5 bit source register specifier (OP_*_RS) not $0 968 "-t" 5 bit source register specifier (OP_*_RT) not $0 969 "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS 970 "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS 971 "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS 972 "-x" 5 bit source register specifier (OP_*_RT) greater than or 973 equal to OP_*_RS 974 "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS 975 "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0 976 "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0 977 978 Other: 979 "()" parens surrounding optional value 980 "," separates operands 981 "+" Start of extension sequence. 982 983 Characters used so far, for quick reference when adding more: 984 "1234567890" 985 "%[]<>(),+-:'@!#$*&\~" 986 "ABCDEFGHIJKLMNOPQRSTUVWXYZ" 987 "abcdefghijklopqrstuvwxz" 988 989 Extension character sequences used so far ("+" followed by the 990 following), for quick reference when adding more: 991 "1234567890" 992 "~!@#$%^&*|:'";" 993 "ABCEFGHIJKLMNOPQRSTUVWXZ" 994 "abcdefghijklmnopqrstuvwxyz" 995 996 Extension character sequences used so far ("-" followed by the 997 following), for quick reference when adding more: 998 "AB" 999 "abdstuvwxy" 1000*/ 1001 1002/* These are the bits which may be set in the pinfo field of an 1003 instructions, if it is not equal to INSN_MACRO. */ 1004 1005/* Writes to operand number N. */ 1006#define INSN_WRITE_SHIFT 0 1007#define INSN_WRITE_1 0x00000001 1008#define INSN_WRITE_2 0x00000002 1009#define INSN_WRITE_ALL 0x00000003 1010/* Reads from operand number N. */ 1011#define INSN_READ_SHIFT 2 1012#define INSN_READ_1 0x00000004 1013#define INSN_READ_2 0x00000008 1014#define INSN_READ_3 0x00000010 1015#define INSN_READ_4 0x00000020 1016#define INSN_READ_ALL 0x0000003c 1017/* Modifies general purpose register 31. */ 1018#define INSN_WRITE_GPR_31 0x00000040 1019/* Modifies coprocessor condition code. */ 1020#define INSN_WRITE_COND_CODE 0x00000080 1021/* Reads coprocessor condition code. */ 1022#define INSN_READ_COND_CODE 0x00000100 1023/* TLB operation. */ 1024#define INSN_TLB 0x00000200 1025/* Reads coprocessor register other than floating point register. */ 1026#define INSN_COP 0x00000400 1027/* Instruction loads value from memory. */ 1028#define INSN_LOAD_MEMORY 0x00000800 1029/* Instruction loads value from coprocessor, (may require delay). */ 1030#define INSN_LOAD_COPROC 0x00001000 1031/* Instruction has unconditional branch delay slot. */ 1032#define INSN_UNCOND_BRANCH_DELAY 0x00002000 1033/* Instruction has conditional branch delay slot. */ 1034#define INSN_COND_BRANCH_DELAY 0x00004000 1035/* Conditional branch likely: if branch not taken, insn nullified. */ 1036#define INSN_COND_BRANCH_LIKELY 0x00008000 1037/* Moves to coprocessor register, (may require delay). */ 1038#define INSN_COPROC_MOVE 0x00010000 1039/* Loads coprocessor register from memory, requiring delay. */ 1040#define INSN_COPROC_MEMORY_DELAY 0x00020000 1041/* Reads the HI register. */ 1042#define INSN_READ_HI 0x00040000 1043/* Reads the LO register. */ 1044#define INSN_READ_LO 0x00080000 1045/* Modifies the HI register. */ 1046#define INSN_WRITE_HI 0x00100000 1047/* Modifies the LO register. */ 1048#define INSN_WRITE_LO 0x00200000 1049/* Not to be placed in a branch delay slot, either architecturally 1050 or for ease of handling (such as with instructions that take a trap). */ 1051#define INSN_NO_DELAY_SLOT 0x00400000 1052/* Instruction stores value into memory. */ 1053#define INSN_STORE_MEMORY 0x00800000 1054/* Instruction uses single precision floating point. */ 1055#define FP_S 0x01000000 1056/* Instruction uses double precision floating point. */ 1057#define FP_D 0x02000000 1058/* Instruction is part of the tx39's integer multiply family. */ 1059#define INSN_MULT 0x04000000 1060/* Reads general purpose register 24. */ 1061#define INSN_READ_GPR_24 0x08000000 1062/* Writes to general purpose register 24. */ 1063#define INSN_WRITE_GPR_24 0x10000000 1064/* A user-defined instruction. */ 1065#define INSN_UDI 0x20000000 1066/* Instruction is actually a macro. It should be ignored by the 1067 disassembler, and requires special treatment by the assembler. */ 1068#define INSN_MACRO 0xffffffff 1069 1070/* These are the bits which may be set in the pinfo2 field of an 1071 instruction. */ 1072 1073/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ 1074#define INSN2_ALIAS 0x00000001 1075/* Instruction reads MDMX accumulator. */ 1076#define INSN2_READ_MDMX_ACC 0x00000002 1077/* Instruction writes MDMX accumulator. */ 1078#define INSN2_WRITE_MDMX_ACC 0x00000004 1079/* Macro uses single-precision floating-point instructions. This should 1080 only be set for macros. For instructions, FP_S in pinfo carries the 1081 same information. */ 1082#define INSN2_M_FP_S 0x00000008 1083/* Macro uses double-precision floating-point instructions. This should 1084 only be set for macros. For instructions, FP_D in pinfo carries the 1085 same information. */ 1086#define INSN2_M_FP_D 0x00000010 1087/* Instruction has a branch delay slot that requires a 16-bit instruction. */ 1088#define INSN2_BRANCH_DELAY_16BIT 0x00000020 1089/* Instruction has a branch delay slot that requires a 32-bit instruction. */ 1090#define INSN2_BRANCH_DELAY_32BIT 0x00000040 1091/* Writes to the stack pointer ($29). */ 1092#define INSN2_WRITE_SP 0x00000080 1093/* Reads from the stack pointer ($29). */ 1094#define INSN2_READ_SP 0x00000100 1095/* Reads the RA ($31) register. */ 1096#define INSN2_READ_GPR_31 0x00000200 1097/* Reads the program counter ($pc). */ 1098#define INSN2_READ_PC 0x00000400 1099/* Is an unconditional branch insn. */ 1100#define INSN2_UNCOND_BRANCH 0x00000800 1101/* Is a conditional branch insn. */ 1102#define INSN2_COND_BRANCH 0x00001000 1103/* Reads from $16. This is true of the MIPS16 0x6500 nop. */ 1104#define INSN2_READ_GPR_16 0x00002000 1105/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */ 1106#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000 1107/* Instruction has a forbidden slot. */ 1108#define INSN2_FORBIDDEN_SLOT 0x00008000 1109 1110/* Masks used to mark instructions to indicate which MIPS ISA level 1111 they were introduced in. INSN_ISA_MASK masks an enumeration that 1112 specifies the base ISA level(s). The remainder of a 32-bit 1113 word constructed using these macros is a bitmask of the remaining 1114 INSN_* values below. */ 1115 1116#define INSN_ISA_MASK 0x0000001ful 1117 1118/* We cannot start at zero due to ISA_UNKNOWN below. */ 1119#define INSN_ISA1 1 1120#define INSN_ISA2 2 1121#define INSN_ISA3 3 1122#define INSN_ISA4 4 1123#define INSN_ISA5 5 1124#define INSN_ISA32 6 1125#define INSN_ISA32R2 7 1126#define INSN_ISA32R3 8 1127#define INSN_ISA32R5 9 1128#define INSN_ISA32R6 10 1129#define INSN_ISA64 11 1130#define INSN_ISA64R2 12 1131#define INSN_ISA64R3 13 1132#define INSN_ISA64R5 14 1133#define INSN_ISA64R6 15 1134/* Below this point the INSN_* values correspond to combinations of ISAs. 1135 They are only for use in the opcodes table to indicate membership of 1136 a combination of ISAs that cannot be expressed using the usual inclusion 1137 ordering on the above INSN_* values. */ 1138#define INSN_ISA3_32 16 1139#define INSN_ISA3_32R2 17 1140#define INSN_ISA4_32 18 1141#define INSN_ISA4_32R2 19 1142#define INSN_ISA5_32R2 20 1143 1144/* The R6 definitions shown below state that they support all previous ISAs. 1145 This is not actually true as some instructions are removed in R6. 1146 The problem is that the removed instructions in R6 come from different 1147 ISAs. One approach to solve this would be to describe in the membership 1148 field of the opcode table the different ISAs an instruction belongs to. 1149 This would require us to create a large amount of different ISA 1150 combinations which is hard to manage. A cleaner approach (which is 1151 implemented here) is to say that R6 is an extension of R5 and then to 1152 deal with the removed instructions by adding instruction exclusions 1153 for R6 in the opcode table. */ 1154 1155/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */ 1156 1157#define ISAF(X) (1 << (INSN_ISA##X - 1)) 1158#define INSN_UPTO1 ISAF(1) 1159#define INSN_UPTO2 INSN_UPTO1 | ISAF(2) 1160#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2) 1161#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2) 1162#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2) 1163#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32) 1164#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \ 1165 | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2) 1166#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3) 1167#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5) 1168#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6) 1169#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32) 1170#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2) 1171#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3) 1172#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5) 1173#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6) 1174 1175/* The same information in table form: bit INSN_ISA<X> - 1 of index 1176 INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */ 1177static const unsigned int mips_isa_table[] = { 1178 INSN_UPTO1, 1179 INSN_UPTO2, 1180 INSN_UPTO3, 1181 INSN_UPTO4, 1182 INSN_UPTO5, 1183 INSN_UPTO32, 1184 INSN_UPTO32R2, 1185 INSN_UPTO32R3, 1186 INSN_UPTO32R5, 1187 INSN_UPTO32R6, 1188 INSN_UPTO64, 1189 INSN_UPTO64R2, 1190 INSN_UPTO64R3, 1191 INSN_UPTO64R5, 1192 INSN_UPTO64R6 1193}; 1194#undef ISAF 1195 1196/* Masks used for Chip specific instructions. */ 1197#define INSN_CHIP_MASK 0xc3ff0f20 1198 1199/* Cavium Networks Octeon instructions. */ 1200#define INSN_OCTEON 0x00000800 1201#define INSN_OCTEONP 0x00000200 1202#define INSN_OCTEON2 0x00000100 1203#define INSN_OCTEON3 0x00000040 1204 1205/* MIPS R5900 instruction */ 1206#define INSN_5900 0x00004000 1207 1208/* MIPS R4650 instruction. */ 1209#define INSN_4650 0x00010000 1210/* LSI R4010 instruction. */ 1211#define INSN_4010 0x00020000 1212/* NEC VR4100 instruction. */ 1213#define INSN_4100 0x00040000 1214/* Toshiba R3900 instruction. */ 1215#define INSN_3900 0x00080000 1216/* MIPS R10000 instruction. */ 1217#define INSN_10000 0x00100000 1218/* Broadcom SB-1 instruction. */ 1219#define INSN_SB1 0x00200000 1220/* NEC VR4111/VR4181 instruction. */ 1221#define INSN_4111 0x00400000 1222/* NEC VR4120 instruction. */ 1223#define INSN_4120 0x00800000 1224/* NEC VR5400 instruction. */ 1225#define INSN_5400 0x01000000 1226/* NEC VR5500 instruction. */ 1227#define INSN_5500 0x02000000 1228 1229/* ST Microelectronics Loongson 2E. */ 1230#define INSN_LOONGSON_2E 0x40000000 1231/* ST Microelectronics Loongson 2F. */ 1232#define INSN_LOONGSON_2F 0x80000000 1233/* Loongson 3A. */ 1234#define INSN_LOONGSON_3A 0x00000400 1235/* RMI Xlr instruction */ 1236#define INSN_XLR 0x00000020 1237 1238/* DSP ASE */ 1239#define ASE_DSP 0x00000001 1240#define ASE_DSP64 0x00000002 1241/* DSP R2 ASE */ 1242#define ASE_DSPR2 0x00000004 1243/* Enhanced VA Scheme */ 1244#define ASE_EVA 0x00000008 1245/* MCU (MicroController) ASE */ 1246#define ASE_MCU 0x00000010 1247/* MDMX ASE */ 1248#define ASE_MDMX 0x00000020 1249/* MIPS-3D ASE */ 1250#define ASE_MIPS3D 0x00000040 1251/* MT ASE */ 1252#define ASE_MT 0x00000080 1253/* SmartMIPS ASE */ 1254#define ASE_SMARTMIPS 0x00000100 1255/* Virtualization ASE */ 1256#define ASE_VIRT 0x00000200 1257#define ASE_VIRT64 0x00000400 1258/* MSA Extension */ 1259#define ASE_MSA 0x00000800 1260#define ASE_MSA64 0x00001000 1261/* eXtended Physical Address (XPA) Extension. */ 1262#define ASE_XPA 0x00002000 1263#define ASE_DSPR3 0x00004000 1264 1265/* MIPS ISA defines, use instead of hardcoding ISA level. */ 1266 1267#define ISA_UNKNOWN 0 /* Gas internal use. */ 1268#define ISA_MIPS1 INSN_ISA1 1269#define ISA_MIPS2 INSN_ISA2 1270#define ISA_MIPS3 INSN_ISA3 1271#define ISA_MIPS4 INSN_ISA4 1272#define ISA_MIPS5 INSN_ISA5 1273 1274#define ISA_MIPS32 INSN_ISA32 1275#define ISA_MIPS64 INSN_ISA64 1276 1277#define ISA_MIPS32R2 INSN_ISA32R2 1278#define ISA_MIPS32R3 INSN_ISA32R3 1279#define ISA_MIPS32R5 INSN_ISA32R5 1280#define ISA_MIPS64R2 INSN_ISA64R2 1281#define ISA_MIPS64R3 INSN_ISA64R3 1282#define ISA_MIPS64R5 INSN_ISA64R5 1283 1284#define ISA_MIPS32R6 INSN_ISA32R6 1285#define ISA_MIPS64R6 INSN_ISA64R6 1286 1287/* CPU defines, use instead of hardcoding processor number. Keep this 1288 in sync with bfd/archures.c in order for machine selection to work. */ 1289#define CPU_UNKNOWN 0 /* Gas internal use. */ 1290#define CPU_R3000 3000 1291#define CPU_R3900 3900 1292#define CPU_R4000 4000 1293#define CPU_R4010 4010 1294#define CPU_VR4100 4100 1295#define CPU_R4111 4111 1296#define CPU_VR4120 4120 1297#define CPU_R4300 4300 1298#define CPU_R4400 4400 1299#define CPU_R4600 4600 1300#define CPU_R4650 4650 1301#define CPU_R5000 5000 1302#define CPU_VR5400 5400 1303#define CPU_VR5500 5500 1304#define CPU_R5900 5900 1305#define CPU_R6000 6000 1306#define CPU_RM7000 7000 1307#define CPU_R8000 8000 1308#define CPU_RM9000 9000 1309#define CPU_R10000 10000 1310#define CPU_R12000 12000 1311#define CPU_R14000 14000 1312#define CPU_R16000 16000 1313#define CPU_MIPS16 16 1314#define CPU_MIPS32 32 1315#define CPU_MIPS32R2 33 1316#define CPU_MIPS32R3 34 1317#define CPU_MIPS32R5 36 1318#define CPU_MIPS32R6 37 1319#define CPU_MIPS5 5 1320#define CPU_MIPS64 64 1321#define CPU_MIPS64R2 65 1322#define CPU_MIPS64R3 66 1323#define CPU_MIPS64R5 68 1324#define CPU_MIPS64R6 69 1325#define CPU_SB1 12310201 /* octal 'SB', 01. */ 1326#define CPU_LOONGSON_2E 3001 1327#define CPU_LOONGSON_2F 3002 1328#define CPU_LOONGSON_3A 3003 1329#define CPU_OCTEON 6501 1330#define CPU_OCTEONP 6601 1331#define CPU_OCTEON2 6502 1332#define CPU_OCTEON3 6503 1333#define CPU_XLR 887682 /* decimal 'XLR' */ 1334 1335/* Return true if the given CPU is included in INSN_* mask MASK. */ 1336 1337static inline bfd_boolean 1338cpu_is_member (int cpu, unsigned int mask) 1339{ 1340 switch (cpu) 1341 { 1342 case CPU_R4650: 1343 case CPU_RM7000: 1344 case CPU_RM9000: 1345 return (mask & INSN_4650) != 0; 1346 1347 case CPU_R4010: 1348 return (mask & INSN_4010) != 0; 1349 1350 case CPU_VR4100: 1351 return (mask & INSN_4100) != 0; 1352 1353 case CPU_R3900: 1354 return (mask & INSN_3900) != 0; 1355 1356 case CPU_R10000: 1357 case CPU_R12000: 1358 case CPU_R14000: 1359 case CPU_R16000: 1360 return (mask & INSN_10000) != 0; 1361 1362 case CPU_SB1: 1363 return (mask & INSN_SB1) != 0; 1364 1365 case CPU_R4111: 1366 return (mask & INSN_4111) != 0; 1367 1368 case CPU_VR4120: 1369 return (mask & INSN_4120) != 0; 1370 1371 case CPU_VR5400: 1372 return (mask & INSN_5400) != 0; 1373 1374 case CPU_VR5500: 1375 return (mask & INSN_5500) != 0; 1376 1377 case CPU_R5900: 1378 return (mask & INSN_5900) != 0; 1379 1380 case CPU_LOONGSON_2E: 1381 return (mask & INSN_LOONGSON_2E) != 0; 1382 1383 case CPU_LOONGSON_2F: 1384 return (mask & INSN_LOONGSON_2F) != 0; 1385 1386 case CPU_LOONGSON_3A: 1387 return (mask & INSN_LOONGSON_3A) != 0; 1388 1389 case CPU_OCTEON: 1390 return (mask & INSN_OCTEON) != 0; 1391 1392 case CPU_OCTEONP: 1393 return (mask & INSN_OCTEONP) != 0; 1394 1395 case CPU_OCTEON2: 1396 return (mask & INSN_OCTEON2) != 0; 1397 1398 case CPU_OCTEON3: 1399 return (mask & INSN_OCTEON3) != 0; 1400 1401 case CPU_XLR: 1402 return (mask & INSN_XLR) != 0; 1403 1404 case CPU_MIPS32R6: 1405 return (mask & INSN_ISA_MASK) == INSN_ISA32R6; 1406 1407 case CPU_MIPS64R6: 1408 return ((mask & INSN_ISA_MASK) == INSN_ISA32R6) 1409 || ((mask & INSN_ISA_MASK) == INSN_ISA64R6); 1410 1411 default: 1412 return FALSE; 1413 } 1414} 1415 1416/* Test for membership in an ISA including chip specific ISAs. INSN 1417 is pointer to an element of the opcode table; ISA is the specified 1418 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to 1419 test, or zero if no CPU specific ISA test is desired. Return true 1420 if instruction INSN is available to the given ISA and CPU. */ 1421 1422static inline bfd_boolean 1423opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) 1424{ 1425 if (!cpu_is_member (cpu, insn->exclusions)) 1426 { 1427 /* Test for ISA level compatibility. */ 1428 if ((isa & INSN_ISA_MASK) != 0 1429 && (insn->membership & INSN_ISA_MASK) != 0 1430 && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] 1431 >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) 1432 return TRUE; 1433 1434 /* Test for ASE compatibility. */ 1435 if ((ase & insn->ase) != 0) 1436 return TRUE; 1437 1438 /* Test for processor-specific extensions. */ 1439 if (cpu_is_member (cpu, insn->membership)) 1440 return TRUE; 1441 } 1442 return FALSE; 1443} 1444 1445/* This is a list of macro expanded instructions. 1446 1447 _I appended means immediate 1448 _A appended means target address of a jump 1449 _AB appended means address with (possibly zero) base register 1450 _D appended means 64 bit floating point constant 1451 _S appended means 32 bit floating point constant. */ 1452 1453enum 1454{ 1455 M_ABS, 1456 M_ACLR_AB, 1457 M_ADD_I, 1458 M_ADDU_I, 1459 M_AND_I, 1460 M_ASET_AB, 1461 M_BALIGN, 1462 M_BC1FL, 1463 M_BC1TL, 1464 M_BC2FL, 1465 M_BC2TL, 1466 M_BEQ, 1467 M_BEQ_I, 1468 M_BEQL, 1469 M_BEQL_I, 1470 M_BGE, 1471 M_BGEL, 1472 M_BGE_I, 1473 M_BGEL_I, 1474 M_BGEU, 1475 M_BGEUL, 1476 M_BGEU_I, 1477 M_BGEUL_I, 1478 M_BGEZ, 1479 M_BGEZL, 1480 M_BGEZALL, 1481 M_BGT, 1482 M_BGTL, 1483 M_BGT_I, 1484 M_BGTL_I, 1485 M_BGTU, 1486 M_BGTUL, 1487 M_BGTU_I, 1488 M_BGTUL_I, 1489 M_BGTZ, 1490 M_BGTZL, 1491 M_BLE, 1492 M_BLEL, 1493 M_BLE_I, 1494 M_BLEL_I, 1495 M_BLEU, 1496 M_BLEUL, 1497 M_BLEU_I, 1498 M_BLEUL_I, 1499 M_BLEZ, 1500 M_BLEZL, 1501 M_BLT, 1502 M_BLTL, 1503 M_BLT_I, 1504 M_BLTL_I, 1505 M_BLTU, 1506 M_BLTUL, 1507 M_BLTU_I, 1508 M_BLTUL_I, 1509 M_BLTZ, 1510 M_BLTZL, 1511 M_BLTZALL, 1512 M_BNE, 1513 M_BNEL, 1514 M_BNE_I, 1515 M_BNEL_I, 1516 M_CACHE_AB, 1517 M_CACHEE_AB, 1518 M_DABS, 1519 M_DADD_I, 1520 M_DADDU_I, 1521 M_DDIV_3, 1522 M_DDIV_3I, 1523 M_DDIVU_3, 1524 M_DDIVU_3I, 1525 M_DIV_3, 1526 M_DIV_3I, 1527 M_DIVU_3, 1528 M_DIVU_3I, 1529 M_DLA_AB, 1530 M_DLCA_AB, 1531 M_DLI, 1532 M_DMUL, 1533 M_DMUL_I, 1534 M_DMULO, 1535 M_DMULO_I, 1536 M_DMULOU, 1537 M_DMULOU_I, 1538 M_DREM_3, 1539 M_DREM_3I, 1540 M_DREMU_3, 1541 M_DREMU_3I, 1542 M_DSUB_I, 1543 M_DSUBU_I, 1544 M_DSUBU_I_2, 1545 M_J_A, 1546 M_JAL_1, 1547 M_JAL_2, 1548 M_JAL_A, 1549 M_JALS_1, 1550 M_JALS_2, 1551 M_JALS_A, 1552 M_JRADDIUSP, 1553 M_JRC, 1554 M_L_DAB, 1555 M_LA_AB, 1556 M_LB_AB, 1557 M_LBE_AB, 1558 M_LBU_AB, 1559 M_LBUE_AB, 1560 M_LCA_AB, 1561 M_LD_AB, 1562 M_LDC1_AB, 1563 M_LDC2_AB, 1564 M_LQC2_AB, 1565 M_LDC3_AB, 1566 M_LDL_AB, 1567 M_LDM_AB, 1568 M_LDP_AB, 1569 M_LDR_AB, 1570 M_LH_AB, 1571 M_LHE_AB, 1572 M_LHU_AB, 1573 M_LHUE_AB, 1574 M_LI, 1575 M_LI_D, 1576 M_LI_DD, 1577 M_LI_S, 1578 M_LI_SS, 1579 M_LL_AB, 1580 M_LLD_AB, 1581 M_LLE_AB, 1582 M_LQ_AB, 1583 M_LW_AB, 1584 M_LWE_AB, 1585 M_LWC0_AB, 1586 M_LWC1_AB, 1587 M_LWC2_AB, 1588 M_LWC3_AB, 1589 M_LWL_AB, 1590 M_LWLE_AB, 1591 M_LWM_AB, 1592 M_LWP_AB, 1593 M_LWR_AB, 1594 M_LWRE_AB, 1595 M_LWU_AB, 1596 M_MSGSND, 1597 M_MSGLD, 1598 M_MSGLD_T, 1599 M_MSGWAIT, 1600 M_MSGWAIT_T, 1601 M_MOVE, 1602 M_MOVEP, 1603 M_MUL, 1604 M_MUL_I, 1605 M_MULO, 1606 M_MULO_I, 1607 M_MULOU, 1608 M_MULOU_I, 1609 M_NOR_I, 1610 M_OR_I, 1611 M_PREF_AB, 1612 M_PREFE_AB, 1613 M_REM_3, 1614 M_REM_3I, 1615 M_REMU_3, 1616 M_REMU_3I, 1617 M_DROL, 1618 M_ROL, 1619 M_DROL_I, 1620 M_ROL_I, 1621 M_DROR, 1622 M_ROR, 1623 M_DROR_I, 1624 M_ROR_I, 1625 M_S_DA, 1626 M_S_DAB, 1627 M_S_S, 1628 M_SAA_AB, 1629 M_SAAD_AB, 1630 M_SC_AB, 1631 M_SCD_AB, 1632 M_SCE_AB, 1633 M_SD_AB, 1634 M_SDC1_AB, 1635 M_SDC2_AB, 1636 M_SQC2_AB, 1637 M_SDC3_AB, 1638 M_SDL_AB, 1639 M_SDM_AB, 1640 M_SDP_AB, 1641 M_SDR_AB, 1642 M_SEQ, 1643 M_SEQ_I, 1644 M_SGE, 1645 M_SGE_I, 1646 M_SGEU, 1647 M_SGEU_I, 1648 M_SGT, 1649 M_SGT_I, 1650 M_SGTU, 1651 M_SGTU_I, 1652 M_SLE, 1653 M_SLE_I, 1654 M_SLEU, 1655 M_SLEU_I, 1656 M_SLT_I, 1657 M_SLTU_I, 1658 M_SNE, 1659 M_SNE_I, 1660 M_SB_AB, 1661 M_SBE_AB, 1662 M_SH_AB, 1663 M_SHE_AB, 1664 M_SQ_AB, 1665 M_SW_AB, 1666 M_SWE_AB, 1667 M_SWC0_AB, 1668 M_SWC1_AB, 1669 M_SWC2_AB, 1670 M_SWC3_AB, 1671 M_SWL_AB, 1672 M_SWLE_AB, 1673 M_SWM_AB, 1674 M_SWP_AB, 1675 M_SWR_AB, 1676 M_SWRE_AB, 1677 M_SUB_I, 1678 M_SUBU_I, 1679 M_SUBU_I_2, 1680 M_TEQ_I, 1681 M_TGE_I, 1682 M_TGEU_I, 1683 M_TLT_I, 1684 M_TLTU_I, 1685 M_TNE_I, 1686 M_TRUNCWD, 1687 M_TRUNCWS, 1688 M_ULD_AB, 1689 M_ULH_AB, 1690 M_ULHU_AB, 1691 M_ULW_AB, 1692 M_USH_AB, 1693 M_USW_AB, 1694 M_USD_AB, 1695 M_XOR_I, 1696 M_COP0, 1697 M_COP1, 1698 M_COP2, 1699 M_COP3, 1700 M_NUM_MACROS 1701}; 1702 1703 1704/* The order of overloaded instructions matters. Label arguments and 1705 register arguments look the same. Instructions that can have either 1706 for arguments must apear in the correct order in this table for the 1707 assembler to pick the right one. In other words, entries with 1708 immediate operands must apear after the same instruction with 1709 registers. 1710 1711 Many instructions are short hand for other instructions (i.e., The 1712 jal <register> instruction is short for jalr <register>). */ 1713 1714extern const struct mips_operand mips_vu0_channel_mask; 1715extern const struct mips_operand *decode_mips_operand (const char *); 1716extern const struct mips_opcode mips_builtin_opcodes[]; 1717extern const int bfd_mips_num_builtin_opcodes; 1718extern struct mips_opcode *mips_opcodes; 1719extern int bfd_mips_num_opcodes; 1720#define NUMOPCODES bfd_mips_num_opcodes 1721 1722 1723/* The rest of this file adds definitions for the mips16 TinyRISC 1724 processor. */ 1725 1726/* These are the bitmasks and shift counts used for the different 1727 fields in the instruction formats. Other than OP, no masks are 1728 provided for the fixed portions of an instruction, since they are 1729 not needed. 1730 1731 The I format uses IMM11. 1732 1733 The RI format uses RX and IMM8. 1734 1735 The RR format uses RX, and RY. 1736 1737 The RRI format uses RX, RY, and IMM5. 1738 1739 The RRR format uses RX, RY, and RZ. 1740 1741 The RRI_A format uses RX, RY, and IMM4. 1742 1743 The SHIFT format uses RX, RY, and SHAMT. 1744 1745 The I8 format uses IMM8. 1746 1747 The I8_MOVR32 format uses RY and REGR32. 1748 1749 The IR_MOV32R format uses REG32R and MOV32Z. 1750 1751 The I64 format uses IMM8. 1752 1753 The RI64 format uses RY and IMM5. 1754 */ 1755 1756#define MIPS16OP_MASK_OP 0x1f 1757#define MIPS16OP_SH_OP 11 1758#define MIPS16OP_MASK_IMM11 0x7ff 1759#define MIPS16OP_SH_IMM11 0 1760#define MIPS16OP_MASK_RX 0x7 1761#define MIPS16OP_SH_RX 8 1762#define MIPS16OP_MASK_IMM8 0xff 1763#define MIPS16OP_SH_IMM8 0 1764#define MIPS16OP_MASK_RY 0x7 1765#define MIPS16OP_SH_RY 5 1766#define MIPS16OP_MASK_IMM5 0x1f 1767#define MIPS16OP_SH_IMM5 0 1768#define MIPS16OP_MASK_RZ 0x7 1769#define MIPS16OP_SH_RZ 2 1770#define MIPS16OP_MASK_IMM4 0xf 1771#define MIPS16OP_SH_IMM4 0 1772#define MIPS16OP_MASK_REGR32 0x1f 1773#define MIPS16OP_SH_REGR32 0 1774#define MIPS16OP_MASK_REG32R 0x1f 1775#define MIPS16OP_SH_REG32R 3 1776#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) 1777#define MIPS16OP_MASK_MOVE32Z 0x7 1778#define MIPS16OP_SH_MOVE32Z 0 1779#define MIPS16OP_MASK_IMM6 0x3f 1780#define MIPS16OP_SH_IMM6 5 1781 1782/* These are the characters which may appears in the args field of a MIPS16 1783 instruction. They appear in the order in which the fields appear when the 1784 instruction is used. Commas and parentheses in the args string are ignored 1785 when assembling, and written into the output when disassembling. 1786 1787 "y" 3 bit register (MIPS16OP_*_RY) 1788 "x" 3 bit register (MIPS16OP_*_RX) 1789 "z" 3 bit register (MIPS16OP_*_RZ) 1790 "Z" 3 bit register (MIPS16OP_*_MOVE32Z) 1791 "v" 3 bit same register as source and destination (MIPS16OP_*_RX) 1792 "w" 3 bit same register as source and destination (MIPS16OP_*_RY) 1793 "0" zero register ($0) 1794 "S" stack pointer ($sp or $29) 1795 "P" program counter 1796 "R" return address register ($ra or $31) 1797 "X" 5 bit MIPS register (MIPS16OP_*_REGR32) 1798 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) 1799 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) 1800 "a" 26 bit jump address 1801 "i" likewise, but flips bit 0 1802 "e" 11 bit extension value 1803 "l" register list for entry instruction 1804 "L" register list for exit instruction 1805 1806 "I" an immediate value used for macros 1807 1808 The remaining codes may be extended. Except as otherwise noted, 1809 the full extended operand is a 16 bit signed value. 1810 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) 1811 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) 1812 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) 1813 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) 1814 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) 1815 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) 1816 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) 1817 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) 1818 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) 1819 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) 1820 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) 1821 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) 1822 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) 1823 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) 1824 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) 1825 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) 1826 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) 1827 "q" 11 bit branch address (MIPS16OP_*_IMM11) 1828 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) 1829 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) 1830 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) 1831 "m" 7 bit register list for save instruction (18 bit extended) 1832 "M" 7 bit register list for restore instruction (18 bit extended) 1833 1834 Characters used so far, for quick reference when adding more: 1835 " 456 8 0" 1836 "[]<>" 1837 "ABCDE HI KLM P RS UVWXYZ" 1838 "a e ijklm pq vwxyz" 1839 */ 1840 1841/* Save/restore encoding for the args field when all 4 registers are 1842 either saved as arguments or saved/restored as statics. */ 1843#define MIPS16_ALL_ARGS 0xe 1844#define MIPS16_ALL_STATICS 0xb 1845 1846/* The following flags have the same value for the mips16 opcode 1847 table: 1848 1849 INSN_ISA3 1850 1851 INSN_UNCOND_BRANCH_DELAY 1852 INSN_COND_BRANCH_DELAY 1853 INSN_COND_BRANCH_LIKELY (never used) 1854 INSN_READ_HI 1855 INSN_READ_LO 1856 INSN_WRITE_HI 1857 INSN_WRITE_LO 1858 INSN_TRAP 1859 FP_D (never used) 1860 */ 1861 1862extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean); 1863extern const struct mips_opcode mips16_opcodes[]; 1864extern const int bfd_mips16_num_opcodes; 1865 1866/* These are the bit masks and shift counts used for the different fields 1867 in the microMIPS instruction formats. No masks are provided for the 1868 fixed portions of an instruction, since they are not needed. */ 1869 1870#define MICROMIPSOP_MASK_IMMEDIATE 0xffff 1871#define MICROMIPSOP_SH_IMMEDIATE 0 1872#define MICROMIPSOP_MASK_DELTA 0xffff 1873#define MICROMIPSOP_SH_DELTA 0 1874#define MICROMIPSOP_MASK_CODE10 0x3ff 1875#define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ 1876#define MICROMIPSOP_MASK_TRAP 0xf 1877#define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ 1878#define MICROMIPSOP_MASK_SHAMT 0x1f 1879#define MICROMIPSOP_SH_SHAMT 11 1880#define MICROMIPSOP_MASK_TARGET 0x3ffffff 1881#define MICROMIPSOP_SH_TARGET 0 1882#define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ 1883#define MICROMIPSOP_SH_EXTLSB 6 1884#define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ 1885#define MICROMIPSOP_SH_EXTMSBD 11 1886#define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ 1887#define MICROMIPSOP_SH_INSMSB 11 1888#define MICROMIPSOP_MASK_CODE 0x3ff 1889#define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ 1890#define MICROMIPSOP_MASK_CODE2 0x3ff 1891#define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ 1892#define MICROMIPSOP_MASK_CACHE 0x1f 1893#define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ 1894#define MICROMIPSOP_MASK_SEL 0x7 1895#define MICROMIPSOP_SH_SEL 11 1896#define MICROMIPSOP_MASK_OFFSET12 0xfff 1897#define MICROMIPSOP_SH_OFFSET12 0 1898#define MICROMIPSOP_MASK_3BITPOS 0x7 1899#define MICROMIPSOP_SH_3BITPOS 21 1900#define MICROMIPSOP_MASK_STYPE 0x1f 1901#define MICROMIPSOP_SH_STYPE 16 1902#define MICROMIPSOP_MASK_OFFSET10 0x3ff 1903#define MICROMIPSOP_SH_OFFSET10 6 1904#define MICROMIPSOP_MASK_RS 0x1f 1905#define MICROMIPSOP_SH_RS 16 1906#define MICROMIPSOP_MASK_RT 0x1f 1907#define MICROMIPSOP_SH_RT 21 1908#define MICROMIPSOP_MASK_RD 0x1f 1909#define MICROMIPSOP_SH_RD 11 1910#define MICROMIPSOP_MASK_FS 0x1f 1911#define MICROMIPSOP_SH_FS 16 1912#define MICROMIPSOP_MASK_FT 0x1f 1913#define MICROMIPSOP_SH_FT 21 1914#define MICROMIPSOP_MASK_FD 0x1f 1915#define MICROMIPSOP_SH_FD 11 1916#define MICROMIPSOP_MASK_FR 0x1f 1917#define MICROMIPSOP_SH_FR 6 1918#define MICROMIPSOP_MASK_RS3 0x1f 1919#define MICROMIPSOP_SH_RS3 6 1920#define MICROMIPSOP_MASK_PREFX 0x1f 1921#define MICROMIPSOP_SH_PREFX 11 1922#define MICROMIPSOP_MASK_BCC 0x7 1923#define MICROMIPSOP_SH_BCC 18 1924#define MICROMIPSOP_MASK_CCC 0x7 1925#define MICROMIPSOP_SH_CCC 13 1926#define MICROMIPSOP_MASK_COPZ 0x7fffff 1927#define MICROMIPSOP_SH_COPZ 3 1928 1929#define MICROMIPSOP_MASK_MB 0x7 1930#define MICROMIPSOP_SH_MB 23 1931#define MICROMIPSOP_MASK_MC 0x7 1932#define MICROMIPSOP_SH_MC 4 1933#define MICROMIPSOP_MASK_MD 0x7 1934#define MICROMIPSOP_SH_MD 7 1935#define MICROMIPSOP_MASK_ME 0x7 1936#define MICROMIPSOP_SH_ME 1 1937#define MICROMIPSOP_MASK_MF 0x7 1938#define MICROMIPSOP_SH_MF 3 1939#define MICROMIPSOP_MASK_MG 0x7 1940#define MICROMIPSOP_SH_MG 0 1941#define MICROMIPSOP_MASK_MH 0x7 1942#define MICROMIPSOP_SH_MH 7 1943#define MICROMIPSOP_MASK_MJ 0x1f 1944#define MICROMIPSOP_SH_MJ 0 1945#define MICROMIPSOP_MASK_ML 0x7 1946#define MICROMIPSOP_SH_ML 4 1947#define MICROMIPSOP_MASK_MM 0x7 1948#define MICROMIPSOP_SH_MM 1 1949#define MICROMIPSOP_MASK_MN 0x7 1950#define MICROMIPSOP_SH_MN 4 1951#define MICROMIPSOP_MASK_MP 0x1f 1952#define MICROMIPSOP_SH_MP 5 1953#define MICROMIPSOP_MASK_MQ 0x7 1954#define MICROMIPSOP_SH_MQ 7 1955 1956#define MICROMIPSOP_MASK_IMMA 0x7f 1957#define MICROMIPSOP_SH_IMMA 0 1958#define MICROMIPSOP_MASK_IMMB 0x7 1959#define MICROMIPSOP_SH_IMMB 1 1960#define MICROMIPSOP_MASK_IMMC 0xf 1961#define MICROMIPSOP_SH_IMMC 0 1962#define MICROMIPSOP_MASK_IMMD 0x3ff 1963#define MICROMIPSOP_SH_IMMD 0 1964#define MICROMIPSOP_MASK_IMME 0x7f 1965#define MICROMIPSOP_SH_IMME 0 1966#define MICROMIPSOP_MASK_IMMF 0xf 1967#define MICROMIPSOP_SH_IMMF 0 1968#define MICROMIPSOP_MASK_IMMG 0xf 1969#define MICROMIPSOP_SH_IMMG 0 1970#define MICROMIPSOP_MASK_IMMH 0xf 1971#define MICROMIPSOP_SH_IMMH 0 1972#define MICROMIPSOP_MASK_IMMI 0x7f 1973#define MICROMIPSOP_SH_IMMI 0 1974#define MICROMIPSOP_MASK_IMMJ 0xf 1975#define MICROMIPSOP_SH_IMMJ 0 1976#define MICROMIPSOP_MASK_IMML 0xf 1977#define MICROMIPSOP_SH_IMML 0 1978#define MICROMIPSOP_MASK_IMMM 0x7 1979#define MICROMIPSOP_SH_IMMM 1 1980#define MICROMIPSOP_MASK_IMMN 0x3 1981#define MICROMIPSOP_SH_IMMN 4 1982#define MICROMIPSOP_MASK_IMMO 0xf 1983#define MICROMIPSOP_SH_IMMO 0 1984#define MICROMIPSOP_MASK_IMMP 0x1f 1985#define MICROMIPSOP_SH_IMMP 0 1986#define MICROMIPSOP_MASK_IMMQ 0x7fffff 1987#define MICROMIPSOP_SH_IMMQ 0 1988#define MICROMIPSOP_MASK_IMMU 0x1f 1989#define MICROMIPSOP_SH_IMMU 0 1990#define MICROMIPSOP_MASK_IMMW 0x3f 1991#define MICROMIPSOP_SH_IMMW 1 1992#define MICROMIPSOP_MASK_IMMX 0xf 1993#define MICROMIPSOP_SH_IMMX 1 1994#define MICROMIPSOP_MASK_IMMY 0x1ff 1995#define MICROMIPSOP_SH_IMMY 1 1996 1997/* MIPS DSP ASE */ 1998#define MICROMIPSOP_MASK_DSPACC 0x3 1999#define MICROMIPSOP_SH_DSPACC 14 2000#define MICROMIPSOP_MASK_DSPSFT 0x3f 2001#define MICROMIPSOP_SH_DSPSFT 16 2002#define MICROMIPSOP_MASK_SA3 0x7 2003#define MICROMIPSOP_SH_SA3 13 2004#define MICROMIPSOP_MASK_SA4 0xf 2005#define MICROMIPSOP_SH_SA4 12 2006#define MICROMIPSOP_MASK_IMM8 0xff 2007#define MICROMIPSOP_SH_IMM8 13 2008#define MICROMIPSOP_MASK_IMM10 0x3ff 2009#define MICROMIPSOP_SH_IMM10 16 2010#define MICROMIPSOP_MASK_WRDSP 0x3f 2011#define MICROMIPSOP_SH_WRDSP 14 2012#define MICROMIPSOP_MASK_BP 0x3 2013#define MICROMIPSOP_SH_BP 14 2014 2015/* Placeholders for fields that only exist in the traditional 32-bit 2016 instruction encoding; see the comment above for details. */ 2017#define MICROMIPSOP_MASK_CODE20 0 2018#define MICROMIPSOP_SH_CODE20 0 2019#define MICROMIPSOP_MASK_PERFREG 0 2020#define MICROMIPSOP_SH_PERFREG 0 2021#define MICROMIPSOP_MASK_CODE19 0 2022#define MICROMIPSOP_SH_CODE19 0 2023#define MICROMIPSOP_MASK_ALN 0 2024#define MICROMIPSOP_SH_ALN 0 2025#define MICROMIPSOP_MASK_VECBYTE 0 2026#define MICROMIPSOP_SH_VECBYTE 0 2027#define MICROMIPSOP_MASK_VECALIGN 0 2028#define MICROMIPSOP_SH_VECALIGN 0 2029#define MICROMIPSOP_MASK_DSPACC_S 0 2030#define MICROMIPSOP_SH_DSPACC_S 0 2031#define MICROMIPSOP_MASK_DSPSFT_7 0 2032#define MICROMIPSOP_SH_DSPSFT_7 0 2033#define MICROMIPSOP_MASK_RDDSP 0 2034#define MICROMIPSOP_SH_RDDSP 0 2035#define MICROMIPSOP_MASK_MT_U 0 2036#define MICROMIPSOP_SH_MT_U 0 2037#define MICROMIPSOP_MASK_MT_H 0 2038#define MICROMIPSOP_SH_MT_H 0 2039#define MICROMIPSOP_MASK_MTACC_T 0 2040#define MICROMIPSOP_SH_MTACC_T 0 2041#define MICROMIPSOP_MASK_MTACC_D 0 2042#define MICROMIPSOP_SH_MTACC_D 0 2043#define MICROMIPSOP_MASK_BBITIND 0 2044#define MICROMIPSOP_SH_BBITIND 0 2045#define MICROMIPSOP_MASK_CINSPOS 0 2046#define MICROMIPSOP_SH_CINSPOS 0 2047#define MICROMIPSOP_MASK_CINSLM1 0 2048#define MICROMIPSOP_SH_CINSLM1 0 2049#define MICROMIPSOP_MASK_SEQI 0 2050#define MICROMIPSOP_SH_SEQI 0 2051#define MICROMIPSOP_SH_OFFSET_A 0 2052#define MICROMIPSOP_MASK_OFFSET_A 0 2053#define MICROMIPSOP_SH_OFFSET_B 0 2054#define MICROMIPSOP_MASK_OFFSET_B 0 2055#define MICROMIPSOP_SH_OFFSET_C 0 2056#define MICROMIPSOP_MASK_OFFSET_C 0 2057#define MICROMIPSOP_SH_RZ 0 2058#define MICROMIPSOP_MASK_RZ 0 2059#define MICROMIPSOP_SH_FZ 0 2060#define MICROMIPSOP_MASK_FZ 0 2061 2062/* microMIPS Enhanced VA Scheme */ 2063#define MICROMIPSOP_SH_EVAOFFSET 0 2064#define MICROMIPSOP_MASK_EVAOFFSET 0x1ff 2065 2066/* These are the characters which may appears in the args field of a microMIPS 2067 instruction. They appear in the order in which the fields appear 2068 when the instruction is used. Commas and parentheses in the args 2069 string are ignored when assembling, and written into the output 2070 when disassembling. 2071 2072 The followings are for 16-bit microMIPS instructions. 2073 2074 "ma" must be $28 2075 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 2076 The same register used as both source and target. 2077 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 2078 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 2079 The same register used as both source and target. 2080 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 2081 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 2082 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7 2083 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 2084 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 2085 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 2086 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 2087 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 2088 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 2089 "mr" must be program counter 2090 "ms" must be $29 2091 "mt" must be the same as the previous register 2092 "mx" must be the same as the destination register 2093 "my" must be $31 2094 "mz" must be $0 2095 2096 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) 2097 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) 2098 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, 2099 32768, 65535) (MICROMIPSOP_*_IMMC) 2100 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) 2101 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) 2102 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) 2103 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) 2104 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) 2105 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) 2106 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) 2107 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2108 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) 2109 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) 2110 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) 2111 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) 2112 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) 2113 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) 2114 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) 2115 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) 2116 "mZ" must be zero 2117 2118 In most cases 32-bit microMIPS instructions use the same characters 2119 as MIPS (with ADDIUPC being a notable exception, but there are some 2120 others too). 2121 2122 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) 2123 "1" 5-bit sync type (MICROMIPSOP_*_STYPE) 2124 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) 2125 ">" shift amount between 32 and 63, stored after subtracting 32 2126 (MICROMIPSOP_*_SHAMT) 2127 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) 2128 "|" 4-bit trap code (MICROMIPSOP_*_TRAP) 2129 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) 2130 "a" 26-bit target address (MICROMIPSOP_*_TARGET) 2131 "+i" likewise, but flips bit 0 2132 "b" 5-bit base register (MICROMIPSOP_*_RS) 2133 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) 2134 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) 2135 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) 2136 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) 2137 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) 2138 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) 2139 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) 2140 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) 2141 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) 2142 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) 2143 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) 2144 "s" 5-bit source register specifier (MICROMIPSOP_*_RS) 2145 "t" 5-bit target register (MICROMIPSOP_*_RT) 2146 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) 2147 "v" 5-bit same register used as both source and destination 2148 (MICROMIPSOP_*_RS) 2149 "w" 5-bit same register used as both target and destination 2150 (MICROMIPSOP_*_RT) 2151 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) 2152 "z" must be zero register 2153 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) 2154 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) 2155 2156 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes 2157 LSB (MICROMIPSOP_*_EXTLSB). 2158 Enforces: 0 <= pos < 32. 2159 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). 2160 Requires that "+A" or "+E" occur first to set position. 2161 Enforces: 0 < (pos+size) <= 32. 2162 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2163 Requires that "+A" or "+E" occur first to set position. 2164 Enforces: 0 < (pos+size) <= 32. 2165 (Also used by DEXT w/ different limits, but limits for 2166 that are checked by the M_DEXT macro.) 2167 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). 2168 Enforces: 32 <= pos < 64. 2169 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). 2170 Requires that "+A" or "+E" occur first to set position. 2171 Enforces: 32 < (pos+size) <= 64. 2172 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). 2173 Requires that "+A" or "+E" occur first to set position. 2174 Enforces: 32 < (pos+size) <= 64. 2175 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). 2176 Requires that "+A" or "+E" occur first to set position. 2177 Enforces: 32 < (pos+size) <= 64. 2178 "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code 2179 (MICROMIPSOP_*_CODE10) 2180 2181 PC-relative addition (ADDIUPC) instruction: 2182 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) 2183 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 2184 2185 Floating point instructions: 2186 "D" 5-bit destination register (MICROMIPSOP_*_FD) 2187 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) 2188 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) 2189 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) 2190 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) 2191 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) 2192 "V" 5-bit same register used as floating source and destination or target 2193 (MICROMIPSOP_*_FS) 2194 2195 Coprocessor instructions: 2196 "E" 5-bit target register (MICROMIPSOP_*_RT) 2197 "G" 5-bit source register (MICROMIPSOP_*_RS) 2198 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) 2199 2200 Macro instructions: 2201 "A" general 32 bit expression 2202 "I" 32-bit immediate (value placed in imm_expr). 2203 "F" 64-bit floating point constant in .rdata 2204 "L" 64-bit floating point constant in .lit8 2205 "f" 32-bit floating point constant 2206 "l" 32-bit floating point constant in .lit4 2207 2208 DSP ASE usage: 2209 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) 2210 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) 2211 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) 2212 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) 2213 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) 2214 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) 2215 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) 2216 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) 2217 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) 2218 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) 2219 2220 microMIPS Enhanced VA Scheme: 2221 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) 2222 2223 MSA Extension: 2224 "+d" 5-bit MSA register (FD) 2225 "+e" 5-bit MSA register (FS) 2226 "+h" 5-bit MSA register (FT) 2227 "+k" 5-bit GPR at bit 6 2228 "+l" 5-bit MSA control register at bit 6 2229 "+n" 5-bit MSA control register at bit 11 2230 "+o" 4-bit vector element index at bit 16 2231 "+u" 3-bit vector element index at bit 16 2232 "+v" 2-bit vector element index at bit 16 2233 "+w" 1-bit vector element index at bit 16 2234 "+x" 5-bit shift amount at bit 16 2235 "+T" (-512 .. 511) << 0 at bit 16 2236 "+U" (-512 .. 511) << 1 at bit 16 2237 "+V" (-512 .. 511) << 2 at bit 16 2238 "+W" (-512 .. 511) << 3 at bit 16 2239 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6 2240 "+!" 3 bit unsigned bit position at bit 16 2241 "+@" 4 bit unsigned bit position at bit 16 2242 "+#" 6 bit unsigned bit position at bit 16 2243 "+$" 5 bit unsigned immediate at bit 16 2244 "+%" 5 bit signed immediate at bit 16 2245 "+^" 10 bit signed immediate at bit 11 2246 "+&" 0 vector element index 2247 "+*" 5-bit register vector element index at bit 16 2248 "+|" 8-bit mask at bit 16 2249 2250 Other: 2251 "()" parens surrounding optional value 2252 "," separates operands 2253 "+" start of extension sequence 2254 "m" start of microMIPS extension sequence 2255 2256 Characters used so far, for quick reference when adding more: 2257 "12345678 0" 2258 "<>(),+-.@\^|~" 2259 "ABCDEFGHI KLMN RST V " 2260 "abcd f hijklmnopqrstuvw yz" 2261 2262 Extension character sequences used so far ("+" followed by the 2263 following), for quick reference when adding more: 2264 "" 2265 "~!@#$%^&*|" 2266 "ABCEFGHJTUVW" 2267 "dehijklnouvwx" 2268 2269 Extension character sequences used so far ("m" followed by the 2270 following), for quick reference when adding more: 2271 "" 2272 "" 2273 " BCDEFGHIJ LMNOPQ U WXYZ" 2274 " bcdefghij lmn pq st xyz" 2275 2276 Extension character sequences used so far ("-" followed by the 2277 following), for quick reference when adding more: 2278 "" 2279 "" 2280 <none so far> 2281*/ 2282 2283extern const struct mips_operand *decode_micromips_operand (const char *); 2284extern const struct mips_opcode micromips_opcodes[]; 2285extern const int bfd_micromips_num_opcodes; 2286 2287/* A NOP insn impemented as "or at,at,zero". 2288 Used to implement -mfix-loongson2f. */ 2289#define LOONGSON2F_NOP_INSN 0x00200825 2290 2291#ifdef __cplusplus 2292} 2293#endif 2294 2295#endif /* _MIPS_H_ */ 2296