1/* Header file for targets using CGEN: Cpu tools GENerator. 2 3 Copyright (C) 1996-2022 Free Software Foundation, Inc. 4 5 This file is part of GDB, the GNU debugger, and the GNU Binutils. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License along 18 with this program; if not, write to the Free Software Foundation, Inc., 19 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 20 21#ifndef OPCODE_CGEN_H 22#define OPCODE_CGEN_H 23 24#include "symcat.h" 25#include "cgen/bitset.h" 26 27#include <stdint.h> 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33/* ??? This file requires bfd.h but only to get bfd_vma. 34 Seems like an awful lot to require just to get such a fundamental type. 35 Perhaps the definition of bfd_vma can be moved outside of bfd.h. 36 Or perhaps one could duplicate its definition in another file. 37 Until such time, this file conditionally compiles definitions that require 38 bfd_vma using __BFD_H_SEEN__. */ 39 40/* Enums must be defined before they can be used. 41 Allow them to be used in struct definitions, even though the enum must 42 be defined elsewhere. 43 If CGEN_ARCH isn't defined, this file is being included by something other 44 than <arch>-desc.h. */ 45 46/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. 47 The lack of spaces in the arg list is important for non-stdc systems. 48 This file is included by <arch>-desc.h. 49 It can be included independently of <arch>-desc.h, in which case the arch 50 dependent portions will be declared as "unknown_cgen_foo". */ 51 52#ifndef CGEN_SYM 53#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) 54#endif 55 56/* This file contains the static (unchanging) pieces and as much other stuff 57 as we can reasonably put here. It's generally cleaner to put stuff here 58 rather than having it machine generated if possible. */ 59 60/* The assembler syntax is made up of expressions (duh...). 61 At the lowest level the values are mnemonics, register names, numbers, etc. 62 Above that are subexpressions, if any (an example might be the 63 "effective address" in m68k cpus). Subexpressions are wip. 64 At the second highest level are the insns themselves. Above that are 65 pseudo-insns, synthetic insns, and macros, if any. */ 66 67/* Lots of cpu's have a fixed insn size, or one which rarely changes, 68 and it's generally easier to handle these by treating the insn as an 69 integer type, rather than an array of characters. So we allow targets 70 to control this. When an integer type the value is in host byte order, 71 when an array of characters the value is in target byte order. */ 72 73typedef unsigned int CGEN_INSN_INT; 74typedef int64_t CGEN_INSN_LGSINT; /* large/long SINT */ 75typedef uint64_t CGEN_INSN_LGUINT; /* large/long UINT */ 76 77#if CGEN_INT_INSN_P 78typedef CGEN_INSN_INT CGEN_INSN_BYTES; 79typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; 80#else 81typedef unsigned char *CGEN_INSN_BYTES; 82typedef unsigned char *CGEN_INSN_BYTES_PTR; 83#endif 84 85#ifdef __GNUC__ 86#define CGEN_INLINE __inline__ 87#else 88#define CGEN_INLINE 89#endif 90 91enum cgen_endian 92{ 93 CGEN_ENDIAN_UNKNOWN, 94 CGEN_ENDIAN_LITTLE, 95 CGEN_ENDIAN_BIG 96}; 97 98/* Forward decl. */ 99 100typedef struct cgen_insn CGEN_INSN; 101 102/* Opaque pointer version for use by external world. */ 103 104typedef struct cgen_cpu_desc *CGEN_CPU_DESC; 105 106/* Attributes. 107 Attributes are used to describe various random things associated with 108 an object (ifield, hardware, operand, insn, whatever) and are specified 109 as name/value pairs. 110 Integer attributes computed at compile time are currently all that's 111 supported, though adding string attributes and run-time computation is 112 straightforward. Integer attribute values are always host int's 113 (signed or unsigned). For portability, this means 32 bits. 114 Integer attributes are further categorized as boolean, bitset, integer, 115 and enum types. Boolean attributes appear frequently enough that they're 116 recorded in one host int. This limits the maximum number of boolean 117 attributes to 32, though that's a *lot* of attributes. */ 118 119/* Type of attribute values. */ 120 121typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE; 122typedef int CGEN_ATTR_VALUE_ENUM_TYPE; 123typedef union 124{ 125 CGEN_ATTR_VALUE_BITSET_TYPE bitset; 126 CGEN_ATTR_VALUE_ENUM_TYPE nonbitset; 127} CGEN_ATTR_VALUE_TYPE; 128 129/* Struct to record attribute information. */ 130 131typedef struct 132{ 133 /* Boolean attributes. */ 134 unsigned int bool_; 135 /* Non-boolean integer attributes. */ 136 CGEN_ATTR_VALUE_TYPE nonbool[1]; 137} CGEN_ATTR; 138 139/* Define a structure member for attributes with N non-boolean entries. 140 There is no maximum number of non-boolean attributes. 141 There is a maximum of 32 boolean attributes (since they are all recorded 142 in one host int). */ 143 144#define CGEN_ATTR_TYPE(n) \ 145struct { unsigned int bool_; \ 146 CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } 147 148/* Return the boolean attributes. */ 149 150#define CGEN_ATTR_BOOLS(a) ((a)->bool_) 151 152/* Non-boolean attribute numbers are offset by this much. */ 153 154#define CGEN_ATTR_NBOOL_OFFSET 32 155 156/* Given a boolean attribute number, return its mask. */ 157 158#define CGEN_ATTR_MASK(attr) (1 << (attr)) 159 160/* Return the value of boolean attribute ATTR in ATTRS. */ 161 162#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) 163 164/* Return value of attribute ATTR in ATTR_TABLE for OBJ. 165 OBJ is a pointer to the entity that has the attributes 166 (??? not used at present but is reserved for future purposes - eventually 167 the goal is to allow recording attributes in source form and computing 168 them lazily at runtime, not sure of the details yet). */ 169 170#define CGEN_ATTR_VALUE(obj, attr_table, attr) \ 171((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ 172 ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ 173 : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset)) 174#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \ 175 ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset) 176 177/* Attribute name/value tables. 178 These are used to assist parsing of descriptions at run-time. */ 179 180typedef struct 181{ 182 const char * name; 183 unsigned value; 184} CGEN_ATTR_ENTRY; 185 186/* For each domain (ifld,hw,operand,insn), list of attributes. */ 187 188typedef struct 189{ 190 const char * name; 191 const CGEN_ATTR_ENTRY * dfault; 192 const CGEN_ATTR_ENTRY * vals; 193} CGEN_ATTR_TABLE; 194 195/* Instruction set variants. */ 196 197typedef struct { 198 const char *name; 199 200 /* Default instruction size (in bits). 201 This is used by the assembler when it encounters an unknown insn. */ 202 unsigned int default_insn_bitsize; 203 204 /* Base instruction size (in bits). 205 For non-LIW cpus this is generally the length of the smallest insn. 206 For LIW cpus its wip (work-in-progress). For the m32r its 32. */ 207 unsigned int base_insn_bitsize; 208 209 /* Minimum/maximum instruction size (in bits). */ 210 unsigned int min_insn_bitsize; 211 unsigned int max_insn_bitsize; 212} CGEN_ISA; 213 214/* Machine variants. */ 215 216typedef struct { 217 const char *name; 218 /* The argument to bfd_arch_info->scan. */ 219 const char *bfd_name; 220 /* one of enum mach_attr */ 221 int num; 222 /* parameter from mach->cpu */ 223 unsigned int insn_chunk_bitsize; 224} CGEN_MACH; 225 226/* Parse result (also extraction result). 227 228 The result of parsing an insn is stored here. 229 To generate the actual insn, this is passed to the insert handler. 230 When printing an insn, the result of extraction is stored here. 231 To print the insn, this is passed to the print handler. 232 233 It is machine generated so we don't define it here, 234 but we do need a forward decl for the handler fns. 235 236 There is one member for each possible field in the insn. 237 The type depends on the field. 238 Also recorded here is the computed length of the insn for architectures 239 where it varies. 240*/ 241 242typedef struct cgen_fields CGEN_FIELDS; 243 244/* Total length of the insn, as recorded in the `fields' struct. */ 245/* ??? The field insert handler has lots of opportunities for optimization 246 if it ever gets inlined. On architectures where insns all have the same 247 size, may wish to detect that and make this macro a constant - to allow 248 further optimizations. */ 249 250#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) 251 252/* Extraction support for variable length insn sets. */ 253 254/* When disassembling we don't know the number of bytes to read at the start. 255 So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest 256 are read when needed. This struct controls this. It is basically the 257 disassemble_info stuff, except that we provide a cache for values already 258 read (since bytes can typically be read several times to fetch multiple 259 operands that may be in them), and that extraction of fields is needed 260 in contexts other than disassembly. */ 261 262typedef struct { 263 /* A pointer to the disassemble_info struct. 264 We don't require dis-asm.h so we use void * for the type here. 265 If NULL, BYTES is full of valid data (VALID == -1). */ 266 void *dis_info; 267 /* Points to a working buffer of sufficient size. */ 268 unsigned char *insn_bytes; 269 /* Mask of bytes that are valid in INSN_BYTES. */ 270 unsigned int valid; 271} CGEN_EXTRACT_INFO; 272 273/* Associated with each insn or expression is a set of "handlers" for 274 performing operations like parsing, printing, etc. These require a bfd_vma 275 value to be passed around but we don't want all applications to need bfd.h. 276 So this stuff is only provided if bfd.h has been included. */ 277 278/* Parse handler. 279 CD is a cpu table descriptor. 280 INSN is a pointer to a struct describing the insn being parsed. 281 STRP is a pointer to a pointer to the text being parsed. 282 FIELDS is a pointer to a cgen_fields struct in which the results are placed. 283 If the expression is successfully parsed, *STRP is updated. 284 If not it is left alone. 285 The result is NULL if success or an error message. */ 286typedef const char * (cgen_parse_fn) 287 (CGEN_CPU_DESC, const CGEN_INSN *insn_, 288 const char **strp_, CGEN_FIELDS *fields_); 289 290/* Insert handler. 291 CD is a cpu table descriptor. 292 INSN is a pointer to a struct describing the insn being parsed. 293 FIELDS is a pointer to a cgen_fields struct from which the values 294 are fetched. 295 INSNP is a pointer to a buffer in which to place the insn. 296 PC is the pc value of the insn. 297 The result is an error message or NULL if success. */ 298 299#ifdef __BFD_H_SEEN__ 300typedef const char * (cgen_insert_fn) 301 (CGEN_CPU_DESC, const CGEN_INSN *insn_, 302 CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, 303 bfd_vma pc_); 304#else 305typedef const char * (cgen_insert_fn) (); 306#endif 307 308/* Extract handler. 309 CD is a cpu table descriptor. 310 INSN is a pointer to a struct describing the insn being parsed. 311 The second argument is a pointer to a struct controlling extraction 312 (only used for variable length insns). 313 EX_INFO is a pointer to a struct for controlling reading of further 314 bytes for the insn. 315 BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). 316 FIELDS is a pointer to a cgen_fields struct in which the results are placed. 317 PC is the pc value of the insn. 318 The result is the length of the insn in bits or zero if not recognized. */ 319 320#ifdef __BFD_H_SEEN__ 321typedef int (cgen_extract_fn) 322 (CGEN_CPU_DESC, const CGEN_INSN *insn_, 323 CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, 324 CGEN_FIELDS *fields_, bfd_vma pc_); 325#else 326typedef int (cgen_extract_fn) (); 327#endif 328 329/* Print handler. 330 CD is a cpu table descriptor. 331 INFO is a pointer to the disassembly info. 332 Eg: disassemble_info. It's defined as `PTR' so this file can be included 333 without dis-asm.h. 334 INSN is a pointer to a struct describing the insn being printed. 335 FIELDS is a pointer to a cgen_fields struct. 336 PC is the pc value of the insn. 337 LEN is the length of the insn, in bits. */ 338 339#ifdef __BFD_H_SEEN__ 340typedef void (cgen_print_fn) 341 (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, 342 CGEN_FIELDS *fields_, bfd_vma pc_, int len_); 343#else 344typedef void (cgen_print_fn) (); 345#endif 346 347/* Parse/insert/extract/print handlers. 348 349 Indices into the handler tables. 350 We could use pointers here instead, but 90% of them are generally identical 351 and that's a lot of redundant data. Making these unsigned char indices 352 into tables of pointers saves a bit of space. 353 Using indices also keeps assembler code out of the disassembler and 354 vice versa. */ 355 356struct cgen_opcode_handler 357{ 358 unsigned char parse, insert, extract, print; 359}; 360 361/* Assembler interface. 362 363 The interface to the assembler is intended to be clean in the sense that 364 libopcodes.a is a standalone entity and could be used with any assembler. 365 Not that one would necessarily want to do that but rather that it helps 366 keep a clean interface. The interface will obviously be slanted towards 367 GAS, but at least it's a start. 368 ??? Note that one possible user of the assembler besides GAS is GDB. 369 370 Parsing is controlled by the assembler which calls 371 CGEN_SYM (assemble_insn). If it can parse and build the entire insn 372 it doesn't call back to the assembler. If it needs/wants to call back 373 to the assembler, cgen_parse_operand_fn is called which can either 374 375 - return a number to be inserted in the insn 376 - return a "register" value to be inserted 377 (the register might not be a register per pe) 378 - queue the argument and return a marker saying the expression has been 379 queued (eg: a fix-up) 380 - return an error message indicating the expression wasn't recognizable 381 382 The result is an error message or NULL for success. 383 The parsed value is stored in the bfd_vma *. */ 384 385/* Values for indicating what the caller wants. */ 386 387enum cgen_parse_operand_type 388{ 389 CGEN_PARSE_OPERAND_INIT, 390 CGEN_PARSE_OPERAND_INTEGER, 391 CGEN_PARSE_OPERAND_ADDRESS, 392 CGEN_PARSE_OPERAND_SYMBOLIC 393}; 394 395/* Values for indicating what was parsed. */ 396 397enum cgen_parse_operand_result 398{ 399 CGEN_PARSE_OPERAND_RESULT_NUMBER, 400 CGEN_PARSE_OPERAND_RESULT_REGISTER, 401 CGEN_PARSE_OPERAND_RESULT_QUEUED, 402 CGEN_PARSE_OPERAND_RESULT_ERROR 403}; 404 405#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ 406typedef const char * (cgen_parse_operand_fn) 407 (CGEN_CPU_DESC, 408 enum cgen_parse_operand_type, const char **, int, int, 409 enum cgen_parse_operand_result *, bfd_vma *); 410#else 411typedef const char * (cgen_parse_operand_fn) (); 412#endif 413 414/* Set the cgen_parse_operand_fn callback. */ 415 416extern void cgen_set_parse_operand_fn 417 (CGEN_CPU_DESC, cgen_parse_operand_fn); 418 419/* Called before trying to match a table entry with the insn. */ 420 421extern void cgen_init_parse_operand (CGEN_CPU_DESC); 422 423/* Operand values (keywords, integers, symbols, etc.) */ 424 425/* Types of assembler elements. */ 426 427enum cgen_asm_type 428{ 429 CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX 430}; 431 432#ifndef CGEN_ARCH 433enum cgen_hw_type { CGEN_HW_MAX }; 434#endif 435 436/* List of hardware elements. */ 437 438typedef struct 439{ 440 char *name; 441 enum cgen_hw_type type; 442 /* There is currently no example where both index specs and value specs 443 are required, so for now both are clumped under "asm_data". */ 444 enum cgen_asm_type asm_type; 445 void *asm_data; 446#ifndef CGEN_HW_NBOOL_ATTRS 447#define CGEN_HW_NBOOL_ATTRS 1 448#endif 449 CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; 450#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) 451} CGEN_HW_ENTRY; 452 453/* Return value of attribute ATTR in HW. */ 454 455#define CGEN_HW_ATTR_VALUE(hw, attr) \ 456CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) 457 458/* Table of hardware elements for selected mach, computed at runtime. 459 enum cgen_hw_type is an index into this table (specifically `entries'). */ 460 461typedef struct { 462 /* Pointer to null terminated table of all compiled in entries. */ 463 const CGEN_HW_ENTRY *init_entries; 464 unsigned int entry_size; /* since the attribute member is variable sized */ 465 /* Array of all entries, initial and run-time added. */ 466 const CGEN_HW_ENTRY **entries; 467 /* Number of elements in `entries'. */ 468 unsigned int num_entries; 469 /* For now, xrealloc is called each time a new entry is added at runtime. 470 ??? May wish to keep track of some slop to reduce the number of calls to 471 xrealloc, except that there's unlikely to be many and not expected to be 472 in speed critical code. */ 473} CGEN_HW_TABLE; 474 475extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name 476 (CGEN_CPU_DESC, const char *); 477extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num 478 (CGEN_CPU_DESC, unsigned int); 479 480/* This struct is used to describe things like register names, etc. */ 481 482typedef struct cgen_keyword_entry 483{ 484 /* Name (as in register name). */ 485 char * name; 486 487 /* Value (as in register number). 488 The value cannot be -1 as that is used to indicate "not found". 489 IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ 490 int value; 491 492 /* Attributes. 493 This should, but technically needn't, appear last. It is a variable sized 494 array in that one architecture may have 1 nonbool attribute and another 495 may have more. Having this last means the non-architecture specific code 496 needn't care. The goal is to eventually record 497 attributes in their raw form, evaluate them at run-time, and cache the 498 values, so this worry will go away anyway. */ 499 /* ??? Moving this last should be done by treating keywords like insn lists 500 and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ 501 /* FIXME: Not used yet. */ 502#ifndef CGEN_KEYWORD_NBOOL_ATTRS 503#define CGEN_KEYWORD_NBOOL_ATTRS 1 504#endif 505 CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; 506 507 /* ??? Putting these here means compiled in entries can't be const. 508 Not a really big deal, but something to consider. */ 509 /* Next name hash table entry. */ 510 struct cgen_keyword_entry *next_name; 511 /* Next value hash table entry. */ 512 struct cgen_keyword_entry *next_value; 513} CGEN_KEYWORD_ENTRY; 514 515/* Top level struct for describing a set of related keywords 516 (e.g. register names). 517 518 This struct supports run-time entry of new values, and hashed lookups. */ 519 520typedef struct cgen_keyword 521{ 522 /* Pointer to initial [compiled in] values. */ 523 CGEN_KEYWORD_ENTRY *init_entries; 524 525 /* Number of entries in `init_entries'. */ 526 unsigned int num_init_entries; 527 528 /* Hash table used for name lookup. */ 529 CGEN_KEYWORD_ENTRY **name_hash_table; 530 531 /* Hash table used for value lookup. */ 532 CGEN_KEYWORD_ENTRY **value_hash_table; 533 534 /* Number of entries in the hash_tables. */ 535 unsigned int hash_table_size; 536 537 /* Pointer to null keyword "" entry if present. */ 538 const CGEN_KEYWORD_ENTRY *null_entry; 539 540 /* String containing non-alphanumeric characters used 541 in keywords. 542 At present, the highest number of entries used is 1. */ 543 char nonalpha_chars[8]; 544} CGEN_KEYWORD; 545 546/* Structure used for searching. */ 547 548typedef struct 549{ 550 /* Table being searched. */ 551 const CGEN_KEYWORD *table; 552 553 /* Specification of what is being searched for. */ 554 const char *spec; 555 556 /* Current index in hash table. */ 557 unsigned int current_hash; 558 559 /* Current element in current hash chain. */ 560 CGEN_KEYWORD_ENTRY *current_entry; 561} CGEN_KEYWORD_SEARCH; 562 563/* Lookup a keyword from its name. */ 564 565const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name 566 (CGEN_KEYWORD *, const char *); 567 568/* Lookup a keyword from its value. */ 569 570const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value 571 (CGEN_KEYWORD *, int); 572 573/* Add a keyword. */ 574 575void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); 576 577/* Keyword searching. 578 This can be used to retrieve every keyword, or a subset. */ 579 580CGEN_KEYWORD_SEARCH cgen_keyword_search_init 581 (CGEN_KEYWORD *, const char *); 582const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next 583 (CGEN_KEYWORD_SEARCH *); 584 585/* Operand value support routines. */ 586 587extern const char *cgen_parse_keyword 588 (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); 589#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ 590extern const char *cgen_parse_signed_integer 591 (CGEN_CPU_DESC, const char **, int, long *); 592extern const char *cgen_parse_unsigned_integer 593 (CGEN_CPU_DESC, const char **, int, unsigned long *); 594extern const char *cgen_parse_address 595 (CGEN_CPU_DESC, const char **, int, int, 596 enum cgen_parse_operand_result *, bfd_vma *); 597extern const char *cgen_validate_signed_integer 598 (long, long, long); 599extern const char *cgen_validate_unsigned_integer 600 (unsigned long, unsigned long, unsigned long); 601#endif 602 603/* Operand modes. */ 604 605/* ??? This duplicates the values in arch.h. Revisit. 606 These however need the CGEN_ prefix [as does everything in this file]. */ 607/* ??? Targets may need to add their own modes so we may wish to move this 608 to <arch>-opc.h, or add a hook. */ 609 610enum cgen_mode { 611 CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ 612 CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, 613 CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, 614 CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, 615 CGEN_MODE_TARGET_MAX, 616 CGEN_MODE_INT, CGEN_MODE_UINT, 617 CGEN_MODE_MAX 618}; 619 620/* FIXME: Until simulator is updated. */ 621 622#define CGEN_MODE_VM CGEN_MODE_VOID 623 624/* Operands. */ 625 626#ifndef CGEN_ARCH 627enum cgen_operand_type { CGEN_OPERAND_MAX }; 628#endif 629 630/* "nil" indicator for the operand instance table */ 631#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX 632 633/* A tree of these structs represents the multi-ifield 634 structure of an operand's hw-index value, if it exists. */ 635 636struct cgen_ifld; 637 638typedef struct cgen_maybe_multi_ifield 639{ 640 int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); 641 n: indexed by array of more cgen_maybe_multi_ifields. */ 642 union 643 { 644 const void *p; 645 const struct cgen_maybe_multi_ifield * multi; 646 const struct cgen_ifld * leaf; 647 } val; 648} 649CGEN_MAYBE_MULTI_IFLD; 650 651/* This struct defines each entry in the operand table. */ 652 653typedef struct 654{ 655 /* Name as it appears in the syntax string. */ 656 char *name; 657 658 /* Operand type. */ 659 enum cgen_operand_type type; 660 661 /* The hardware element associated with this operand. */ 662 enum cgen_hw_type hw_type; 663 664 /* FIXME: We don't yet record ifield definitions, which we should. 665 When we do it might make sense to delete start/length (since they will 666 be duplicated in the ifield's definition) and replace them with a 667 pointer to the ifield entry. */ 668 669 /* Bit position. 670 This is just a hint, and may be unused in more complex operands. 671 May be unused for a modifier. */ 672 unsigned char start; 673 674 /* The number of bits in the operand. 675 This is just a hint, and may be unused in more complex operands. 676 May be unused for a modifier. */ 677 unsigned char length; 678 679 /* The (possibly-multi) ifield used as an index for this operand, if it 680 is indexed by a field at all. This substitutes / extends the start and 681 length fields above, but unsure at this time whether they are used 682 anywhere. */ 683 CGEN_MAYBE_MULTI_IFLD index_fields; 684#if 0 /* ??? Interesting idea but relocs tend to get too complicated, 685 and ABI dependent, for simple table lookups to work. */ 686 /* Ideally this would be the internal (external?) reloc type. */ 687 int reloc_type; 688#endif 689 690 /* Attributes. 691 This should, but technically needn't, appear last. It is a variable sized 692 array in that one architecture may have 1 nonbool attribute and another 693 may have more. Having this last means the non-architecture specific code 694 needn't care, now or tomorrow. The goal is to eventually record 695 attributes in their raw form, evaluate them at run-time, and cache the 696 values, so this worry will go away anyway. */ 697#ifndef CGEN_OPERAND_NBOOL_ATTRS 698#define CGEN_OPERAND_NBOOL_ATTRS 1 699#endif 700 CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; 701#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) 702} CGEN_OPERAND; 703 704/* Return value of attribute ATTR in OPERAND. */ 705 706#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ 707CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) 708 709/* Table of operands for selected mach/isa, computed at runtime. 710 enum cgen_operand_type is an index into this table (specifically 711 `entries'). */ 712 713typedef struct { 714 /* Pointer to null terminated table of all compiled in entries. */ 715 const CGEN_OPERAND *init_entries; 716 unsigned int entry_size; /* since the attribute member is variable sized */ 717 /* Array of all entries, initial and run-time added. */ 718 const CGEN_OPERAND **entries; 719 /* Number of elements in `entries'. */ 720 unsigned int num_entries; 721 /* For now, xrealloc is called each time a new entry is added at runtime. 722 ??? May wish to keep track of some slop to reduce the number of calls to 723 xrealloc, except that there's unlikely to be many and not expected to be 724 in speed critical code. */ 725} CGEN_OPERAND_TABLE; 726 727extern const CGEN_OPERAND * cgen_operand_lookup_by_name 728 (CGEN_CPU_DESC, const char *); 729extern const CGEN_OPERAND * cgen_operand_lookup_by_num 730 (CGEN_CPU_DESC, int); 731 732/* Instruction operand instances. 733 734 For each instruction, a list of the hardware elements that are read and 735 written are recorded. */ 736 737/* The type of the instance. */ 738 739enum cgen_opinst_type { 740 /* End of table marker. */ 741 CGEN_OPINST_END = 0, 742 CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT 743}; 744 745typedef struct 746{ 747 /* Input or output indicator. */ 748 enum cgen_opinst_type type; 749 750 /* Name of operand. */ 751 const char *name; 752 753 /* The hardware element referenced. */ 754 enum cgen_hw_type hw_type; 755 756 /* The mode in which the operand is being used. */ 757 enum cgen_mode mode; 758 759 /* The operand table entry CGEN_OPERAND_NIL if there is none 760 (i.e. an explicit hardware reference). */ 761 enum cgen_operand_type op_type; 762 763 /* If `operand' is "nil", the index (e.g. into array of registers). */ 764 int index; 765 766 /* Attributes. 767 ??? This perhaps should be a real attribute struct but there's 768 no current need, so we save a bit of space and just have a set of 769 flags. The interface is such that this can easily be made attributes 770 should it prove useful. */ 771 unsigned int attrs; 772#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) 773/* Return value of attribute ATTR in OPINST. */ 774#define CGEN_OPINST_ATTR(opinst, attr) \ 775((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) 776/* Operand is conditionally referenced (read/written). */ 777#define CGEN_OPINST_COND_REF 1 778} CGEN_OPINST; 779 780/* Syntax string. 781 782 Each insn format and subexpression has one of these. 783 784 The syntax "string" consists of characters (n > 0 && n < 128), and operand 785 values (n >= 128), and is terminated by 0. Operand values are 128 + index 786 into the operand table. The operand table doesn't exist in C, per se, as 787 the data is recorded in the parse/insert/extract/print switch statements. */ 788 789/* This should be at least as large as necessary for any target. */ 790#define CGEN_MAX_SYNTAX_ELEMENTS 48 791 792/* A target may know its own precise maximum. Assert that it falls below 793 the above limit. */ 794#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 795#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS 796#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" 797#endif 798#endif 799 800typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; 801 802typedef struct 803{ 804 CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; 805} CGEN_SYNTAX; 806 807#define CGEN_SYNTAX_STRING(syn) (syn->syntax) 808#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) 809#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) 810#define CGEN_SYNTAX_FIELD(c) ((c) - 128) 811#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) 812 813/* ??? I can't currently think of any case where the mnemonic doesn't come 814 first [and if one ever doesn't building the hash tables will be tricky]. 815 However, we treat mnemonics as just another operand of the instruction. 816 A value of 1 means "this is where the mnemonic appears". 1 isn't 817 special other than it's a non-printable ASCII char. */ 818 819#define CGEN_SYNTAX_MNEMONIC 1 820#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) 821 822/* Instruction fields. 823 824 ??? We currently don't allow adding fields at run-time. 825 Easy to fix when needed. */ 826 827typedef struct cgen_ifld { 828 /* Enum of ifield. */ 829 int num; 830#define CGEN_IFLD_NUM(f) ((f)->num) 831 832 /* Name of the field, distinguishes it from all other fields. */ 833 const char *name; 834#define CGEN_IFLD_NAME(f) ((f)->name) 835 836 /* Default offset, in bits, from the start of the insn to the word 837 containing the field. */ 838 int word_offset; 839#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) 840 841 /* Default length of the word containing the field. */ 842 int word_size; 843#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) 844 845 /* Default starting bit number. 846 Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ 847 int start; 848#define CGEN_IFLD_START(f) ((f)->start) 849 850 /* Length of the field, in bits. */ 851 int length; 852#define CGEN_IFLD_LENGTH(f) ((f)->length) 853 854#ifndef CGEN_IFLD_NBOOL_ATTRS 855#define CGEN_IFLD_NBOOL_ATTRS 1 856#endif 857 CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; 858#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) 859} CGEN_IFLD; 860 861/* Return value of attribute ATTR in IFLD. */ 862#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ 863CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) 864 865/* Instruction data. */ 866 867/* Instruction formats. 868 869 Instructions are grouped by format. Associated with an instruction is its 870 format. Each insn's opcode table entry contains a format table entry. 871 ??? There is usually very few formats compared with the number of insns, 872 so one can reduce the size of the opcode table by recording the format table 873 as a separate entity. Given that we currently don't, format table entries 874 are also distinguished by their operands. This increases the size of the 875 table, but reduces the number of tables. It's all minutiae anyway so it 876 doesn't really matter [at this point in time]. 877 878 ??? Support for variable length ISA's is wip. */ 879 880/* Accompanying each iformat description is a list of its fields. */ 881 882typedef struct { 883 const CGEN_IFLD *ifld; 884#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) 885} CGEN_IFMT_IFLD; 886 887/* This should be at least as large as necessary for any target. */ 888#define CGEN_MAX_IFMT_OPERANDS 16 889 890/* A target may know its own precise maximum. Assert that it falls below 891 the above limit. */ 892#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS 893#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS 894#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" 895#endif 896#endif 897 898 899typedef struct 900{ 901 /* Length that MASK and VALUE have been calculated to 902 [VALUE is recorded elsewhere]. 903 Normally it is base_insn_bitsize. On [V]LIW architectures where the base 904 insn size may be larger than the size of an insn, this field is less than 905 base_insn_bitsize. */ 906 unsigned char mask_length; 907#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) 908 909 /* Total length of instruction, in bits. */ 910 unsigned char length; 911#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) 912 913 /* Mask to apply to the first MASK_LENGTH bits. 914 Each insn's value is stored with the insn. 915 The first step in recognizing an insn for disassembly is 916 (opcode & mask) == value. */ 917 CGEN_INSN_INT mask; 918#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) 919 920 /* Instruction fields. 921 +1 for trailing NULL. */ 922 CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; 923#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) 924} CGEN_IFMT; 925 926/* Instruction values. */ 927 928typedef struct 929{ 930 /* The opcode portion of the base insn. */ 931 CGEN_INSN_INT base_value; 932 933#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS 934 /* Extra opcode values beyond base_value. */ 935 unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; 936#endif 937} CGEN_IVALUE; 938 939/* Instruction opcode table. 940 This contains the syntax and format data of an instruction. */ 941 942/* ??? Some ports already have an opcode table yet still need to use the rest 943 of what cgen_insn has. Plus keeping the opcode data with the operand 944 instance data can create a pretty big file. So we keep them separately. 945 Not sure this is a good idea in the long run. */ 946 947typedef struct 948{ 949 /* Indices into parse/insert/extract/print handler tables. */ 950 struct cgen_opcode_handler handlers; 951#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) 952 953 /* Syntax string. */ 954 CGEN_SYNTAX syntax; 955#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) 956 957 /* Format entry. */ 958 const CGEN_IFMT *format; 959#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) 960#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) 961#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) 962#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) 963 964 /* Instruction opcode value. */ 965 CGEN_IVALUE value; 966#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) 967#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) 968#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) 969} CGEN_OPCODE; 970 971/* Instruction attributes. 972 This is made a published type as applications can cache a pointer to 973 the attributes for speed. */ 974 975#ifndef CGEN_INSN_NBOOL_ATTRS 976#define CGEN_INSN_NBOOL_ATTRS 1 977#endif 978typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; 979 980/* Enum of architecture independent attributes. */ 981 982#ifndef CGEN_ARCH 983/* ??? Numbers here are recorded in two places. */ 984typedef enum cgen_insn_attr { 985 CGEN_INSN_ALIAS = 0 986} CGEN_INSN_ATTR; 987#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) 988#endif 989 990/* This struct defines each entry in the instruction table. */ 991 992typedef struct 993{ 994 /* Each real instruction is enumerated. */ 995 /* ??? This may go away in time. */ 996 int num; 997#define CGEN_INSN_NUM(insn) ((insn)->base->num) 998 999 /* Name of entry (that distinguishes it from all other entries). */ 1000 /* ??? If mnemonics have operands, try to print full mnemonic. */ 1001 const char *name; 1002#define CGEN_INSN_NAME(insn) ((insn)->base->name) 1003 1004 /* Mnemonic. This is used when parsing and printing the insn. 1005 In the case of insns that have operands on the mnemonics, this is 1006 only the constant part. E.g. for conditional execution of an `add' insn, 1007 where the full mnemonic is addeq, addne, etc., and the condition is 1008 treated as an operand, this is only "add". */ 1009 const char *mnemonic; 1010#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) 1011 1012 /* Total length of instruction, in bits. */ 1013 int bitsize; 1014#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) 1015 1016#if 0 /* ??? Disabled for now as there is a problem with embedded newlines 1017 and the table is already pretty big. Should perhaps be moved 1018 to a file of its own. */ 1019 /* Semantics, as RTL. */ 1020 /* ??? Plain text or bytecodes? */ 1021 /* ??? Note that the operand instance table could be computed at run-time 1022 if we parse this and cache the results. Something to eventually do. */ 1023 const char *rtx; 1024#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) 1025#endif 1026 1027 /* Attributes. 1028 This must appear last. It is a variable sized array in that one 1029 architecture may have 1 nonbool attribute and another may have more. 1030 Having this last means the non-architecture specific code needn't 1031 care. The goal is to eventually record attributes in their raw form, 1032 evaluate them at run-time, and cache the values, so this worry will go 1033 away anyway. */ 1034 CGEN_INSN_ATTR_TYPE attrs; 1035#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) 1036/* Return value of attribute ATTR in INSN. */ 1037#define CGEN_INSN_ATTR_VALUE(insn, attr) \ 1038CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) 1039#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ 1040 CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) 1041} CGEN_IBASE; 1042 1043/* Return non-zero if INSN is the "invalid" insn marker. */ 1044 1045#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) 1046 1047/* Main struct contain instruction information. 1048 BASE is always present, the rest is present only if asked for. */ 1049 1050struct cgen_insn 1051{ 1052 /* ??? May be of use to put a type indicator here. 1053 Then this struct could different info for different classes of insns. */ 1054 /* ??? A speedup can be had by moving `base' into this struct. 1055 Maybe later. */ 1056 const CGEN_IBASE *base; 1057 const CGEN_OPCODE *opcode; 1058 const CGEN_OPINST *opinst; 1059 1060 /* Regex to disambiguate overloaded opcodes */ 1061 void *rx; 1062#define CGEN_INSN_RX(insn) ((insn)->rx) 1063#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) 1064}; 1065 1066/* Instruction lists. 1067 This is used for adding new entries and for creating the hash lists. */ 1068 1069typedef struct cgen_insn_list 1070{ 1071 struct cgen_insn_list *next; 1072 const CGEN_INSN *insn; 1073} CGEN_INSN_LIST; 1074 1075/* Table of instructions. */ 1076 1077typedef struct 1078{ 1079 const CGEN_INSN *init_entries; 1080 unsigned int entry_size; /* since the attribute member is variable sized */ 1081 unsigned int num_init_entries; 1082 CGEN_INSN_LIST *new_entries; 1083} CGEN_INSN_TABLE; 1084 1085/* Return number of instructions. This includes any added at run-time. */ 1086 1087extern int cgen_insn_count (CGEN_CPU_DESC); 1088extern int cgen_macro_insn_count (CGEN_CPU_DESC); 1089 1090/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ 1091 1092/* Fetch INSN's operand instance table. */ 1093/* ??? Doesn't handle insns added at runtime. */ 1094#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) 1095 1096/* Return INSN's opcode table entry. */ 1097#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) 1098 1099/* Return INSN's handler data. */ 1100#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) 1101 1102/* Return INSN's syntax. */ 1103#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) 1104 1105/* Return size of base mask in bits. */ 1106#define CGEN_INSN_MASK_BITSIZE(insn) \ 1107 CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) 1108 1109/* Return mask of base part of INSN. */ 1110#define CGEN_INSN_BASE_MASK(insn) \ 1111 CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) 1112 1113/* Return value of base part of INSN. */ 1114#define CGEN_INSN_BASE_VALUE(insn) \ 1115 CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) 1116 1117/* Standard way to test whether INSN is supported by MACH. 1118 MACH is one of enum mach_attr. 1119 The "|1" is because the base mach is always selected. */ 1120#define CGEN_INSN_MACH_HAS_P(insn, mach) \ 1121((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) 1122 1123/* Macro instructions. 1124 Macro insns aren't real insns, they map to one or more real insns. 1125 E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or 1126 some such. 1127 1128 Macro insns can expand to nothing (e.g. a nop that is optimized away). 1129 This is useful in multi-insn macros that build a constant in a register. 1130 Of course this isn't the default behaviour and must be explicitly enabled. 1131 1132 Assembly of macro-insns is relatively straightforward. Disassembly isn't. 1133 However, disassembly of at least some kinds of macro insns is important 1134 in order that the disassembled code preserve the readability of the original 1135 insn. What is attempted here is to disassemble all "simple" macro-insns, 1136 where "simple" is currently defined to mean "expands to one real insn". 1137 1138 Simple macro-insns are handled specially. They are emitted as ALIAS's 1139 of real insns. This simplifies their handling since there's usually more 1140 of them than any other kind of macro-insn, and proper disassembly of them 1141 falls out for free. */ 1142 1143/* For each macro-insn there may be multiple expansion possibilities, 1144 depending on the arguments. This structure is accessed via the `data' 1145 member of CGEN_INSN. */ 1146 1147typedef struct cgen_minsn_expansion { 1148 /* Function to do the expansion. 1149 If the expansion fails (e.g. "no match") NULL is returned. 1150 Space for the expansion is obtained with malloc. 1151 It is up to the caller to free it. */ 1152 const char * (* fn) 1153 (const struct cgen_minsn_expansion *, 1154 const char *, const char **, int *, 1155 CGEN_OPERAND **); 1156#define CGEN_MIEXPN_FN(ex) ((ex)->fn) 1157 1158 /* Instruction(s) the macro expands to. 1159 The format of STR is defined by FN. 1160 It is typically the assembly code of the real insn, but it could also be 1161 the original Scheme expression or a tokenized form of it (with FN being 1162 an appropriate interpreter). */ 1163 const char * str; 1164#define CGEN_MIEXPN_STR(ex) ((ex)->str) 1165} CGEN_MINSN_EXPANSION; 1166 1167/* Normal expander. 1168 When supported, this function will convert the input string to another 1169 string and the parser will be invoked recursively. The output string 1170 may contain further macro invocations. */ 1171 1172extern const char * cgen_expand_macro_insn 1173 (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, 1174 const char *, const char **, int *, CGEN_OPERAND **); 1175 1176/* The assembler insn table is hashed based on some function of the mnemonic 1177 (the actually hashing done is up to the target, but we provide a few 1178 examples like the first letter or a function of the entire mnemonic). */ 1179 1180extern CGEN_INSN_LIST * cgen_asm_lookup_insn 1181 (CGEN_CPU_DESC, const char *); 1182#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) 1183#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) 1184 1185/* The disassembler insn table is hashed based on some function of machine 1186 instruction (the actually hashing done is up to the target). */ 1187 1188extern CGEN_INSN_LIST * cgen_dis_lookup_insn 1189 (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); 1190/* FIXME: delete these two */ 1191#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) 1192#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) 1193 1194/* The CPU description. 1195 A copy of this is created when the cpu table is "opened". 1196 All global state information is recorded here. 1197 Access macros are provided for "public" members. */ 1198 1199typedef struct cgen_cpu_desc 1200{ 1201 /* Bitmap of selected machine(s) (a la BFD machine number). */ 1202 int machs; 1203 1204 /* Bitmap of selected isa(s). */ 1205 CGEN_BITSET *isas; 1206#define CGEN_CPU_ISAS(cd) ((cd)->isas) 1207 1208 /* Current endian. */ 1209 enum cgen_endian endian; 1210#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) 1211 1212 /* Current insn endian. */ 1213 enum cgen_endian insn_endian; 1214#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) 1215 1216 /* Word size (in bits). */ 1217 /* ??? Or maybe maximum word size - might we ever need to allow a cpu table 1218 to be opened for both sparc32/sparc64? 1219 ??? Another alternative is to create a table of selected machs and 1220 lazily fetch the data from there. */ 1221 unsigned int word_bitsize; 1222 1223 /* Instruction chunk size (in bits), for purposes of endianness 1224 conversion. */ 1225 unsigned int insn_chunk_bitsize; 1226 1227 /* Indicator if sizes are unknown. 1228 This is used by default_insn_bitsize,base_insn_bitsize if there is a 1229 difference between the selected isa's. */ 1230#define CGEN_SIZE_UNKNOWN 65535 1231 1232 /* Default instruction size (in bits). 1233 This is used by the assembler when it encounters an unknown insn. */ 1234 unsigned int default_insn_bitsize; 1235 1236 /* Base instruction size (in bits). 1237 For non-LIW cpus this is generally the length of the smallest insn. 1238 For LIW cpus its wip (work-in-progress). For the m32r its 32. */ 1239 unsigned int base_insn_bitsize; 1240 1241 /* Minimum/maximum instruction size (in bits). */ 1242 unsigned int min_insn_bitsize; 1243 unsigned int max_insn_bitsize; 1244 1245 /* Instruction set variants. */ 1246 const CGEN_ISA *isa_table; 1247 1248 /* Machine variants. */ 1249 const CGEN_MACH *mach_table; 1250 1251 /* Hardware elements. */ 1252 CGEN_HW_TABLE hw_table; 1253 1254 /* Instruction fields. */ 1255 const CGEN_IFLD *ifld_table; 1256 1257 /* Operands. */ 1258 CGEN_OPERAND_TABLE operand_table; 1259 1260 /* Main instruction table. */ 1261 CGEN_INSN_TABLE insn_table; 1262#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) 1263 1264 /* Macro instructions are defined separately and are combined with real 1265 insns during hash table computation. */ 1266 CGEN_INSN_TABLE macro_insn_table; 1267 1268 /* Copy of CGEN_INT_INSN_P. */ 1269 int int_insn_p; 1270 1271 /* Called to rebuild the tables after something has changed. */ 1272 void (*rebuild_tables) (CGEN_CPU_DESC); 1273 1274 /* Operand parser callback. */ 1275 cgen_parse_operand_fn * parse_operand_fn; 1276 1277 /* Parse/insert/extract/print cover fns for operands. */ 1278 const char * (*parse_operand) 1279 (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); 1280#ifdef __BFD_H_SEEN__ 1281 const char * (*insert_operand) 1282 (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, 1283 CGEN_INSN_BYTES_PTR, bfd_vma pc_); 1284 int (*extract_operand) 1285 (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, 1286 CGEN_FIELDS *fields_, bfd_vma pc_); 1287 void (*print_operand) 1288 (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, 1289 void const *attrs_, bfd_vma pc_, int length_); 1290#else 1291 const char * (*insert_operand) (); 1292 int (*extract_operand) (); 1293 void (*print_operand) (); 1294#endif 1295#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) 1296#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) 1297#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) 1298#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) 1299 1300 /* Size of CGEN_FIELDS struct. */ 1301 unsigned int sizeof_fields; 1302#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) 1303 1304 /* Set the bitsize field. */ 1305 void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); 1306#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) 1307 1308 /* CGEN_FIELDS accessors. */ 1309 int (*get_int_operand) 1310 (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); 1311 void (*set_int_operand) 1312 (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); 1313#ifdef __BFD_H_SEEN__ 1314 bfd_vma (*get_vma_operand) 1315 (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); 1316 void (*set_vma_operand) 1317 (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); 1318#else 1319 long (*get_vma_operand) (); 1320 void (*set_vma_operand) (); 1321#endif 1322#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) 1323#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) 1324#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) 1325#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) 1326 1327 /* Instruction parse/insert/extract/print handlers. */ 1328 /* FIXME: make these types uppercase. */ 1329 cgen_parse_fn * const *parse_handlers; 1330 cgen_insert_fn * const *insert_handlers; 1331 cgen_extract_fn * const *extract_handlers; 1332 cgen_print_fn * const *print_handlers; 1333#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) 1334#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) 1335#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) 1336#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) 1337 1338 /* Return non-zero if insn should be added to hash table. */ 1339 int (* asm_hash_p) (const CGEN_INSN *); 1340 1341 /* Assembler hash function. */ 1342 unsigned int (* asm_hash) (const char *); 1343 1344 /* Number of entries in assembler hash table. */ 1345 unsigned int asm_hash_size; 1346 1347 /* Return non-zero if insn should be added to hash table. */ 1348 int (* dis_hash_p) (const CGEN_INSN *); 1349 1350 /* Disassembler hash function. */ 1351 unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); 1352 1353 /* Number of entries in disassembler hash table. */ 1354 unsigned int dis_hash_size; 1355 1356 /* Assembler instruction hash table. */ 1357 CGEN_INSN_LIST **asm_hash_table; 1358 CGEN_INSN_LIST *asm_hash_table_entries; 1359 1360 /* Disassembler instruction hash table. */ 1361 CGEN_INSN_LIST **dis_hash_table; 1362 CGEN_INSN_LIST *dis_hash_table_entries; 1363 1364 /* This field could be turned into a bitfield if room for other flags is needed. */ 1365 unsigned int signed_overflow_ok_p; 1366 1367} CGEN_CPU_TABLE; 1368 1369/* wip */ 1370#ifndef CGEN_WORD_ENDIAN 1371#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) 1372#endif 1373#ifndef CGEN_INSN_WORD_ENDIAN 1374#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) 1375#endif 1376 1377/* Prototypes of major functions. */ 1378/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. 1379 Not the init fns though, as that would drag in things that mightn't be 1380 used and might not even exist. */ 1381 1382/* Argument types to cpu_open. */ 1383 1384enum cgen_cpu_open_arg { 1385 CGEN_CPU_OPEN_END, 1386 /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ 1387 CGEN_CPU_OPEN_ISAS, 1388 /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ 1389 CGEN_CPU_OPEN_MACHS, 1390 /* Select machine, arg is mach's bfd name. 1391 Multiple machines can be specified by repeated use. */ 1392 CGEN_CPU_OPEN_BFDMACH, 1393 /* Select endian, arg is CGEN_ENDIAN_*. */ 1394 CGEN_CPU_OPEN_ENDIAN, 1395 /* Select instruction endian, arg is CGEN_ENDIAN_*. */ 1396 CGEN_CPU_OPEN_INSN_ENDIAN, 1397}; 1398 1399/* Open a cpu descriptor table for use. 1400 ??? We only support ISO C stdargs here, not K&R. 1401 Laziness, plus experiment to see if anything requires K&R - eventually 1402 K&R will no longer be supported - e.g. GDB is currently trying this. */ 1403 1404extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); 1405 1406/* Cover fn to handle simple case. */ 1407 1408extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) 1409 (const char *mach_name_, enum cgen_endian endian_); 1410 1411/* Close it. */ 1412 1413extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); 1414 1415/* Initialize the opcode table for use. 1416 Called by init_asm/init_dis. */ 1417 1418extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); 1419 1420/* build the insn selection regex. 1421 called by init_opcode_table */ 1422 1423extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); 1424 1425/* Initialize the ibld table for use. 1426 Called by init_asm/init_dis. */ 1427 1428extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); 1429 1430/* Initialize an cpu table for assembler or disassembler use. 1431 These must be called immediately after cpu_open. */ 1432 1433extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); 1434extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); 1435 1436/* Initialize the operand instance table for use. */ 1437 1438extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); 1439 1440/* Assemble an instruction. */ 1441 1442extern const CGEN_INSN * CGEN_SYM (assemble_insn) 1443 (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, 1444 CGEN_INSN_BYTES_PTR, char **); 1445 1446extern const CGEN_KEYWORD CGEN_SYM (operand_mach); 1447extern int CGEN_SYM (get_mach) (const char *); 1448 1449/* Operand index computation. */ 1450extern const CGEN_INSN * cgen_lookup_insn 1451 (CGEN_CPU_DESC, const CGEN_INSN * insn_, 1452 CGEN_INSN_INT int_value_, unsigned char *bytes_value_, 1453 int length_, CGEN_FIELDS *fields_, int alias_p_); 1454extern void cgen_get_insn_operands 1455 (CGEN_CPU_DESC, const CGEN_INSN * insn_, 1456 const CGEN_FIELDS *fields_, int *indices_); 1457extern const CGEN_INSN * cgen_lookup_get_insn_operands 1458 (CGEN_CPU_DESC, const CGEN_INSN *insn_, 1459 CGEN_INSN_INT int_value_, unsigned char *bytes_value_, 1460 int length_, int *indices_, CGEN_FIELDS *fields_); 1461 1462/* Cover fns to bfd_get/set. */ 1463 1464extern CGEN_INSN_INT cgen_get_insn_value 1465 (CGEN_CPU_DESC, unsigned char *, int, int); 1466extern void cgen_put_insn_value 1467 (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int); 1468 1469extern CGEN_INSN_INT cgen_get_base_insn_value 1470 (CGEN_CPU_DESC, unsigned char *, int); 1471extern void cgen_put_base_insn_value 1472 (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); 1473 1474/* Read in a cpu description file. 1475 ??? For future concerns, including adding instructions to the assembler/ 1476 disassembler at run-time. */ 1477 1478extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); 1479 1480/* Allow signed overflow of instruction fields. */ 1481extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); 1482 1483/* Generate an error message if a signed field in an instruction overflows. */ 1484extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); 1485 1486/* Will an error message be generated if a signed field in an instruction overflows ? */ 1487extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); 1488 1489#ifdef __cplusplus 1490} 1491#endif 1492 1493#endif /* OPCODE_CGEN_H */ 1494