1# Hitachi H8 testcase 'bra'
2# mach(): all
3# as(h8300):	--defsym sim_cpu=0
4# as(h8300h):	--defsym sim_cpu=1
5# as(h8300s):	--defsym sim_cpu=2
6# as(h8sx):	--defsym sim_cpu=3
7# ld(h8300h):	-m h8300helf
8# ld(h8300s):	-m h8300self
9# ld(h8sx):	-m h8300sxelf
10
11	.include "testutils.inc"
12
13	start
14.if (sim_cpu == h8sx)
15	.data
16	.align 4
17disp8:	.long	tgt_reg8
18disp16:	.long	tgt_reg16
19disp32:	.long	tgt_reg32
20dslot:	.byte	0
21	.text
22.endif
23
24bra_8:
25	set_grs_a5a5		; Fill all general regs with a fixed pattern
26	set_ccr_zero
27
28	;;  bra dd:8		; 8-bit displacement
29	bra tgt_8:8
30;;;	.word	0x40xx		; where "xx" is tgt_8 - '.'.
31	fail
32
33tgt_8:
34	test_cc_clear
35	test_gr_a5a5 0		; Make sure other general regs not disturbed
36	test_gr_a5a5 1
37	test_gr_a5a5 2
38	test_gr_a5a5 3
39	test_gr_a5a5 4
40	test_gr_a5a5 5
41	test_gr_a5a5 6
42	test_gr_a5a5 7
43
44.if (sim_cpu)			; not available in h8/300 mode
45bra_16:
46	set_grs_a5a5		; Fill all general regs with a fixed pattern
47	set_ccr_zero
48
49	;;  bra dd:16		; 16-bit displacement
50	bra tgt_24:16	; NOTE: hard-coded to avoid relaxing.
51;;; 	.word 0x5800
52;;; 	.word tgt_24 - .
53	fail
54
55tgt_24:
56	test_cc_clear
57	test_gr_a5a5 0		; Make sure other general regs not disturbed
58	test_gr_a5a5 1
59	test_gr_a5a5 2
60	test_gr_a5a5 3
61	test_gr_a5a5 4
62	test_gr_a5a5 5
63	test_gr_a5a5 6
64	test_gr_a5a5 7
65.endif
66
67.if	(sim_cpu == h8sx)
68bra_reg8:
69	set_grs_a5a5		; Fill all general regs with a fixed pattern
70	set_ccr_zero
71
72	;;  bra rn.b		; 8-bit register indirect
73	sub.l	#src8, @disp8
74	mov.l	@disp8, er5
75	bra	r5l.b
76;;; 	.word	0x5955
77src8:	fail
78
79tgt_reg8:
80	test_cc_clear
81	test_gr_a5a5 0		; Make sure other general regs not disturbed
82	test_gr_a5a5 1
83	test_gr_a5a5 2
84	test_gr_a5a5 3
85	test_gr_a5a5 4
86;;; 	test_h_gr32 tgt_reg8 er5
87	test_gr_a5a5 6
88	test_gr_a5a5 7
89
90bra_reg16:
91	set_grs_a5a5		; Fill all general regs with a fixed pattern
92	set_ccr_zero
93
94	;;  bra rn.w		; 16-bit register indirect
95	sub.l	#src16, @disp16
96	mov.l	@disp16, er5
97	bra	r5.w
98;;; 	.word	0x5956
99src16:	fail
100
101tgt_reg16:
102	test_cc_clear
103	test_gr_a5a5 0		; Make sure other general regs not disturbed
104	test_gr_a5a5 1
105	test_gr_a5a5 2
106	test_gr_a5a5 3
107	test_gr_a5a5 4
108;;; 	test_h_gr32 tgt_reg16 er5
109	test_gr_a5a5 6
110	test_gr_a5a5 7
111
112bra_reg32:
113	set_grs_a5a5		; Fill all general regs with a fixed pattern
114	set_ccr_zero
115
116	;;  bra ern		; 32-bit register indirect
117	sub.l	#src32, @disp32
118	mov.l	@disp32, er5
119	bra	er5.l
120;;; 	.word	0x5957
121src32:	fail
122
123tgt_reg32:
124	test_cc_clear
125	test_gr_a5a5 0		; Make sure other general regs not disturbed
126	test_gr_a5a5 1
127	test_gr_a5a5 2
128	test_gr_a5a5 3
129	test_gr_a5a5 4
130;;; 	test_gr_a5a5 5
131	test_gr_a5a5 6
132	test_gr_a5a5 7
133
134bra_s:	set_grs_a5a5
135	set_ccr_zero
136
137	bra/s	tgt_post_delay
138;;; 	.word	0x4017
139	;; The following instruction is in the delay slot, and should execute.
140	mov.b	#1, @dslot
141	;; After this, the next instructions should not execute.
142	fail
143
144tgt_post_delay:
145	test_cc_clear
146	cmp.b	#0, @dslot	; Should be non-zero if delay slot executed.
147	bne	dslot_ok
148	fail
149
150dslot_ok:
151	test_gr_a5a5 0		; Make sure all general regs not disturbed
152	test_gr_a5a5 1
153	test_gr_a5a5 2
154	test_gr_a5a5 3
155	test_gr_a5a5 4
156	test_gr_a5a5 5
157	test_gr_a5a5 6
158	test_gr_a5a5 7
159
160.endif
161
162	pass
163	exit 0
164
165