c_cc_flagdreg_mvbrsft_sn.s revision 1.1 
1//Original:/proj/frio/dv/testcases/core/c_cc_flagdreg_mvbrsft_sn/c_cc_flagdreg_mvbrsft_sn.dsp
2// Spec Reference: cc: set (ccflag & cc2dreg) used (ccmv & brcc & dsp32sft)
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8	imm32 r0, 0xa08d2311;
9	imm32 r1, 0x10120040;
10	imm32 r2, 0x62b61557;
11	imm32 r3, 0x07300007;
12	imm32 r4, 0x00740088;
13	imm32 r5, 0x609950aa;
14	imm32 r6, 0x20bb06cc;
15	imm32 r7, 0xd90e108f;
16
17	imm32 p1, 0x1401101f;
18	imm32 p2, 0x3204108e;
19	imm32 p3, 0xd93f1084;
20	imm32 p4, 0xeb04106f;
21	imm32 p5, 0xa90e5089;
22
23	ASTAT = R0;
24
25	CC = R1;	// cc2dreg
26	R2.H = ( A1 = R2.L * R3.L ), A0 = R2.H * R3.L;	// dsp32mac
27	I0 = P1;	// regmv
28	IF CC R1 = R3;	// ccmov
29	CC = ! CC;	// cc2dreg
30	R4.H = R1.L + R0.L (S);	// dsp32alu
31	M0 = P2;	// regmv
32	IF CC R3 = R2;	// ccmov
33	CC = R0 < R1;	// ccflag
34	R4.L = R5.L << 1;	// dsp32shiftimm
35	I0 += M0;	// dagmodim
36	R2 = R0 + R2;	// comp3op dr plus dr
37	IF CC R4 = R5;	// ccmov
38	CC = R2 == R3;	// ccflag
39	R7 = R1.L * R4.L, R6 = R1.H * R4.H;	// dsp32mult
40	R5 = R0 + R2;	// comp3op dr plus dr
41	BITCLR( R6 , 1 );
42	IF CC R4 = R5;	// ccmov
43	CC = R0;	// cc2dreg
44	A1 = R2.L * R3.L, A0 += R2.L * R3.H;	// dsp32mac
45	IF !CC JUMP LABEL1;	// branch on
46	CC = ! CC;	// cc2dreg
47	P1.L = 0x3000;	// ldimmhalf
48	A0 += A1 (W32);	// dsp32alu a0 + a1
49	IF !CC JUMP LABEL2 (BP);	// branch
50LABEL1:
51	R6 = R6 + R2;
52	JUMP.S END;
53LABEL2:
54	R7 = R5 - R7;
55	CC = R0 < R1;	// ccflag
56	P2 = A0.w;
57	IF CC JUMP END (BP);	// branch
58	P3 = A1.w;
59	R5 = R5 + R7;
60
61END:
62
63	CHECKREG r0, 0xA08D2311;
64	CHECKREG r1, 0x07300007;
65	CHECKREG r2, 0xA08E3868;
66	CHECKREG r3, 0x07300007;
67	CHECKREG r4, 0x609950AA;
68	CHECKREG r5, 0x411B5B79;
69	CHECKREG r6, 0x056C9760;
70	CHECKREG r7, 0x4116F22D;
71	CHECKREG p1, 0x14013000;
72	CHECKREG p2, 0x033352A4;
73	CHECKREG p3, 0xD93F1084;
74
75	imm32 r0, 0x408d2711;
76	imm32 r1, 0x15124040;
77	imm32 r2, 0x62661557;
78	imm32 r3, 0x073b0007;
79	imm32 r4, 0x01f49088;
80	imm32 r5, 0x6e2959aa;
81	imm32 r6, 0xa0b506cc;
82	imm32 r7, 0x00000002;
83
84	CC = R1;	// cc2dreg
85	P1 = -15;	// compi2opp_pr_eq_i7
86	R2 = ROT R2 BY 1;	// dsp32shiftim_rot
87	CC = ! CC;	// cc2dreg
88	R3 >>= R7;	// alu2op sft
89	R4 = ROT R0 BY -3;	// dsp32shiftim_rot
90	CC = R0 < R1;	// ccflag
91	R3 = ( A1 = R7.L * R4.L ),  R2 = ( A0 = R7.H * R4.H )  (S2RND);	// dsp32mac pair
92	R5 = R0 + R2;	// comp3op dr plus dr
93	R6 = ROT R4 BY 5;	// dsp32shiftim_rot
94	CC = R2 == R3;	// ccflag
95	P2 = R1;	// regmv
96	R4.H = R1.L + R3.H (S);	// dsp32alu
97	I0 = P1;	// regmv
98	IF CC R4 = R5;	// ccmov
99	CC = R0;	// cc2dreg
100	R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR);	// dsp32alu sft
101	I0 += 2;
102	P3 = I0;
103	R3.L = R5.L << 1;	// dsp32shiftimm
104	R7 = ROT R6 BY R7.L;	// dsp32shiftim_rot
105
106	CHECKREG r0, 0x408D2711;
107	CHECKREG r1, 0x2ACFF368;
108	CHECKREG r2, 0x00000000;
109	CHECKREG r3, 0xFFFD4E22;
110	CHECKREG r4, 0x403DA4E2;
111	CHECKREG r5, 0x408D2711;
112	CHECKREG r6, 0x15BD33A8;
113	CHECKREG r7, 0x56F4CEA2;
114	CHECKREG p1, 0xFFFFFFF1;
115	CHECKREG p2, 0x15124040;
116	CHECKREG p3, 0xFFFFFFF3;
117
118	pass
119