1# Hitachi H8 testcase 'sub.b'
2# mach(): all
3# as(h8300):	--defsym sim_cpu=0
4# as(h8300h):	--defsym sim_cpu=1
5# as(h8300s):	--defsym sim_cpu=2
6# as(h8sx):	--defsym sim_cpu=3
7# ld(h8300h):	-m h8300helf
8# ld(h8300s):	-m h8300self
9# ld(h8sx):	-m h8300sxelf
10
11	.include "testutils.inc"
12
13	# Instructions tested:
14	# sub.b #xx:8, rd	; <illegal>
15	# sub.b #xx:8, @erd	;         7 d rd ???? a ???? xxxxxxxx
16	# sub.b #xx:8, @erd+	; 0 1 7 4 6 c rd 1??? a ???? xxxxxxxx
17	# sub.b #xx:8, @erd-	; 0 1 7 6 6 c rd 1??? a ???? xxxxxxxx
18	# sub.b rs, rd		;                     1 8 rs rd
19	# sub.b reg8, @erd	;         7 d rd ???? 1 8 rs ????
20	# sub.b reg8, @erd+	;         0 1 7     9 8 rd 3 rs
21	# sub.b reg8, @erd-	;         0 1 7     9 a rd 3 rs
22	#
23
24	# Coming soon:
25	# sub.b #xx:8, @+erd	; 0 1 7 5 6 c rd 1??? a ???? xxxxxxxx
26	# sub.b #xx:8, @-erd	; 0 1 7 7 6 c rd 1??? a ???? xxxxxxxx
27	# sub.b reg8, @+erd	;         0 1 7     9 9 rd 3 rs
28	# sub.b reg8, @-erd	;         0 1 7     9 b rd 3 rs
29	# ...
30
31.data
32pre_byte:	.byte 0
33byte_dest:	.byte 0xa5
34post_byte:	.byte 0
35
36	start
37
38.if (0)				; Guess what?  Sub.b immediate reg8 is illegal!
39sub_b_imm8_reg:
40	set_grs_a5a5		; Fill all general regs with a fixed pattern
41	;;  fixme set ccr
42
43	;;  sub.b #xx:8,Rd
44	sub.b	#5, r0l		; Immediate 8-bit operand
45
46	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
47	test_h_gr16 0xa5a0 r0	; sub result:	a5 - 5
48.if (sim_cpu)			; non-zero means h8300h, s, or sx
49	test_h_gr32 0xa5a5a5a0 er0	; sub result:	 a5 - 5
50.endif
51	test_gr_a5a5 1		; Make sure other general regs not disturbed
52	test_gr_a5a5 2
53	test_gr_a5a5 3
54	test_gr_a5a5 4
55	test_gr_a5a5 5
56	test_gr_a5a5 6
57	test_gr_a5a5 7
58.endif
59
60.if (sim_cpu == h8sx)
61sub_b_imm8_rdind:
62	set_grs_a5a5		; Fill all general regs with a fixed pattern
63	set_ccr_zero
64
65	;;  sub.b #xx:8,@eRd
66	mov	#byte_dest, er0
67	sub.b	#5:8, @er0	; Immediate 8-bit src, reg indirect dst
68;;; 	.word	0x7d00
69;;; 	.word	0xa105
70
71	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
72	test_ovf_clear
73	test_zero_clear
74	test_neg_set
75
76	test_h_gr32 byte_dest, er0	; er0 still contains address
77	test_gr_a5a5 1		; Make sure other general regs not disturbed
78	test_gr_a5a5 2
79	test_gr_a5a5 3
80	test_gr_a5a5 4
81	test_gr_a5a5 5
82	test_gr_a5a5 6
83	test_gr_a5a5 7
84
85	;; Now check the result of the sub to memory.
86	sub.b	r0l, r0l
87	mov.b	@byte_dest, r0l
88	cmp.b	#0xa0, r0l
89	beq	.L1
90	fail
91.L1:
92
93sub_b_imm8_rdpostinc:
94	set_grs_a5a5		; Fill all general regs with a fixed pattern
95	set_ccr_zero
96
97	;;  sub.b #xx:8,@eRd+
98	mov	#byte_dest, er0
99	sub.b	#5:8, @er0+	; Immediate 8-bit src, reg post-incr dest
100;;; 	.word	0x0174
101;;; 	.word	0x6c08
102;;; 	.word	0xa105
103
104	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
105	test_ovf_clear
106	test_zero_clear
107	test_neg_set
108
109	test_h_gr32 post_byte, er0	; er0 still contains address plus one
110	test_gr_a5a5 1		; Make sure other general regs not disturbed
111	test_gr_a5a5 2
112	test_gr_a5a5 3
113	test_gr_a5a5 4
114	test_gr_a5a5 5
115	test_gr_a5a5 6
116	test_gr_a5a5 7
117
118	;; Now check the result of the sub to memory.
119	sub.b	r0l, r0l
120	mov.b	@byte_dest, r0l
121	cmp.b	#0x9b, r0l
122	beq	.L2
123	fail
124.L2:
125
126sub_b_imm8_rdpostdec:
127	set_grs_a5a5		; Fill all general regs with a fixed pattern
128	set_ccr_zero
129
130	;;  sub.b #xx:8,@eRd-
131	mov	#byte_dest, er0
132	sub.b	#5:8, @er0-	; Immediate 8-bit src, reg post-decr dest
133;;; 	.word	0x0176
134;;; 	.word	0x6c08
135;;; 	.word	0xa105
136
137	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
138	test_ovf_clear
139	test_zero_clear
140	test_neg_set
141
142	test_h_gr32 pre_byte, er0	; er0 still contains address minus one
143	test_gr_a5a5 1		; Make sure other general regs not disturbed
144	test_gr_a5a5 2
145	test_gr_a5a5 3
146	test_gr_a5a5 4
147	test_gr_a5a5 5
148	test_gr_a5a5 6
149	test_gr_a5a5 7
150
151	;; Now check the result of the sub to memory.
152	sub.b	r0l, r0l
153	mov.b	@byte_dest, r0l
154	cmp.b	#0x96, r0l
155	beq	.L3
156	fail
157.L3:
158
159.endif
160
161sub_b_reg8_reg8:
162	set_grs_a5a5		; Fill all general regs with a fixed pattern
163	;;  fixme set ccr
164
165	;;  sub.b Rs,Rd
166	mov.b	#5, r0h
167	sub.b	r0h, r0l	; Register operand
168
169	;; fixme test ccr	; H=0 N=1 Z=0 V=0 C=0
170	test_h_gr16 0x05a0 r0	; sub result:	a5 - 5
171.if (sim_cpu)			; non-zero means h8300h, s, or sx
172	test_h_gr32 0xa5a505a0 er0	; sub result:	a5 - 5
173.endif
174	test_gr_a5a5 1		; Make sure other general regs not disturbed
175	test_gr_a5a5 2
176	test_gr_a5a5 3
177	test_gr_a5a5 4
178	test_gr_a5a5 5
179	test_gr_a5a5 6
180	test_gr_a5a5 7
181
182.if (sim_cpu == h8sx)
183sub_b_reg8_rdind:
184	set_grs_a5a5		; Fill all general regs with a fixed pattern
185	set_ccr_zero
186
187	;;  sub.b rs8,@eRd	; Subx to register indirect
188	mov	#byte_dest, er0
189	mov	#5, r1l
190	sub.b	r1l, @er0	; reg8 src, reg indirect dest
191;;; 	.word	0x7d00
192;;; 	.word	0x1890
193
194	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
195	test_ovf_clear
196	test_zero_clear
197	test_neg_set
198
199	test_h_gr32 byte_dest er0	; er0 still contains address
200	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
201
202	test_gr_a5a5 2		; Make sure other general regs not disturbed
203	test_gr_a5a5 3
204	test_gr_a5a5 4
205	test_gr_a5a5 5
206	test_gr_a5a5 6
207	test_gr_a5a5 7
208
209	;; Now check the result of the sub to memory.
210	sub.b	r0l, r0l
211	mov.b	@byte_dest, r0l
212	cmp.b	#0x91, r0l
213	beq	.L4
214	fail
215.L4:
216
217sub_b_reg8_rdpostinc:
218	set_grs_a5a5		; Fill all general regs with a fixed pattern
219	set_ccr_zero
220
221	;;  sub.b rs8,@eRd+	; Subx to register indirect
222	mov	#byte_dest, er0
223	mov	#5, r1l
224	sub.b	r1l, @er0+	; reg8 src, reg indirect dest
225;;; 	.word	0x0179
226;;; 	.word	0x8039
227
228	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
229	test_ovf_clear
230	test_zero_clear
231	test_neg_set
232
233	test_h_gr32 post_byte er0	; er0 still contains address plus one
234	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
235
236	test_gr_a5a5 2		; Make sure other general regs not disturbed
237	test_gr_a5a5 3
238	test_gr_a5a5 4
239	test_gr_a5a5 5
240	test_gr_a5a5 6
241	test_gr_a5a5 7
242
243	;; Now check the result of the sub to memory.
244	sub.b	r0l, r0l
245	mov.b	@byte_dest, r0l
246	cmp.b	#0x8c, r0l
247	beq	.L5
248	fail
249.L5:
250	;; special case same register
251	mov.l	#byte_dest, er0
252	mov.b	@er0, r1h
253	mov.b	r1h, r2l
254	mov.b	r0l, r1l
255	sub.b	r0l, @er0+
256	inc.b	r1l
257	sub.b	r1l, r1h
258	mov.b	@byte_dest, r0l
259	cmp.b	r1h, r0l
260	beq	.L25
261	fail
262.L25:
263	mov.b	r2l, @byte_dest
264
265sub_b_reg8_rdpostdec:
266	set_grs_a5a5		; Fill all general regs with a fixed pattern
267	set_ccr_zero
268
269	;;  sub.b rs8,@eRd-	; Subx to register indirect
270	mov	#byte_dest, er0
271	mov	#5, r1l
272	sub.b	r1l, @er0-	; reg8 src, reg indirect dest
273;;; 	.word	0x0179
274;;; 	.word	0xa039
275
276	test_carry_clear	; H=0 N=1 Z=0 V=0 C=0
277	test_ovf_clear
278	test_zero_clear
279	test_neg_set
280
281	test_h_gr32 pre_byte er0	; er0 still contains address minus one
282	test_h_gr32 0xa5a5a505 er1	; er1 has the test load
283
284	test_gr_a5a5 2		; Make sure other general regs not disturbed
285	test_gr_a5a5 3
286	test_gr_a5a5 4
287	test_gr_a5a5 5
288	test_gr_a5a5 6
289	test_gr_a5a5 7
290
291	;; Now check the result of the sub to memory.
292	sub.b	r0l, r0l
293	mov.b	@byte_dest, r0l
294	cmp.b	#0x87, r0l
295	beq	.L6
296	fail
297.L6:
298	;; special case same register
299	mov.l	#byte_dest, er0
300	mov.b	@er0, r1h
301	mov.b	r0l, r1l
302	sub.b	r0l, @er0-
303	dec.b	r1l
304	sub.b	r1l, r1h
305	mov.b	@byte_dest, r0l
306	cmp.b	r1h, r0l
307	beq	.L26
308	fail
309.L26:
310
311.endif
312
313	pass
314
315	exit 0
316