1//Original:/proj/frio/dv/testcases/seq/se_ssstep_dagprotviol/se_ssstep_dagprotviol.dsp
2// Description: prioritize DAG Protection Violation and Supervisor Single Step
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10//
11// Constants and Defines
12//
13
14include(gen_int.inc)
15include(selfcheck.inc)
16include(std.inc)
17include(mmrs.inc)
18include(symtable.inc)
19
20#ifndef STACKSIZE
21#define STACKSIZE 0x10   // change for how much stack you need
22#endif
23#ifndef ITABLE
24#define ITABLE 0xF0000000
25#endif
26
27GEN_INT_INIT(ITABLE) // set location for interrupt table
28
29//
30// Reset/Bootstrap Code
31//   (Here we should set the processor operating modes, initialize registers,
32//    etc.)
33//
34
35BOOT:
36INIT_R_REGS(0);     // initialize general purpose regs
37
38INIT_P_REGS(0);     // initialize the pointers
39
40INIT_I_REGS(0);     // initialize the dsp address regs
41INIT_M_REGS(0);
42INIT_L_REGS(0);
43INIT_B_REGS(0);
44
45CLI R1;           // inhibit events during MMR writes
46
47LD32_LABEL(sp, USTACK);   // setup the user stack pointer
48USP = SP;
49
50LD32_LABEL(sp, KSTACK);   // setup the kernel stack pointer
51FP = SP;        // and frame pointer
52
53LD32(p0, EVT0);      // Setup Event Vectors and Handlers
54
55    P0 += 4;            // EVT0 not used (Emulation)
56
57    P0 += 4;            // EVT1 not used (Reset)
58
59LD32_LABEL(r0, NHANDLE);  // NMI Handler (Int2)
60    [ P0 ++ ] = R0;
61
62LD32_LABEL(r0, XHANDLE);  // Exception Handler (Int3)
63    [ P0 ++ ] = R0;
64
65    P0 += 4;            // EVT4 not used (Global Interrupt Enable)
66
67LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
68    [ P0 ++ ] = R0;
69
70LD32_LABEL(r0, THANDLE);  // Timer Handler (Int6)
71    [ P0 ++ ] = R0;
72
73LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
74    [ P0 ++ ] = R0;
75
76LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
77    [ P0 ++ ] = R0;
78
79LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
80    [ P0 ++ ] = R0;
81
82LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
83    [ P0 ++ ] = R0;
84
85LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
86    [ P0 ++ ] = R0;
87
88LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
89    [ P0 ++ ] = R0;
90
91LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
92    [ P0 ++ ] = R0;
93
94LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
95    [ P0 ++ ] = R0;
96
97LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
98    [ P0 ++ ] = R0;
99
100LD32(p0, EVT_OVERRIDE);
101    R0 = 0;
102    [ P0 ++ ] = R0;
103
104    R1 = -1;     // Change this to mask interrupts (*)
105CSYNC;       // wait for MMR writes to finish
106STI R1;      // sync and reenable events (implicit write to IMASK)
107
108DUMMY:
109
110    R0 = 0 (Z);
111
112LT0 = r0;       // set loop counters to something deterministic
113LB0 = r0;
114LC0 = r0;
115LT1 = r0;
116LB1 = r0;
117LC1 = r0;
118
119ASTAT = r0;     // reset other internal regs
120RETS = r0;      // prevent X's breaking LINK instruction
121
122    R0 = 1;
123SYSCFG = r0;    // enable ssstep
124
125
126// The following code sets up the test for running in USER mode
127
128LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
129                        // ReturnFromInterrupt (RTI)
130RETI = r0;      // We need to load the return address
131
132// Comment the following line for a USER Mode test
133
134//    JUMP    STARTSUP;   // jump to code start for SUPERVISOR mode
135
136RTI;
137
138STARTSUP:
139LD32_LABEL(p1, BEGIN);
140
141LD32(p0, EVT15);
142
143CLI R1;   // inhibit events during write to MMR
144    [ P0 ] = P1;  // IVG15 (General) handler (Int 15) load with start
145CSYNC;      // wait for it
146STI R1;     // reenable events with proper imask
147
148RAISE 15;       // after we RTI, INT 15 should be taken
149
150RTI;
151
152//
153// The Main Program
154//
155
156STARTUSER:
157
158LINK 0;     // change for how much stack frame space you need.
159
160JUMP BEGIN;
161
162//*********************************************************************
163
164BEGIN:
165
166                // COMMENT the following line for USER MODE tests
167//    [--sp] = RETI;  // enable interrupts in supervisor mode
168
169                // **** YOUR CODE GOES HERE ****
170
171    // PUT YOUR TEST HERE!
172
173NOP;
174    I0 += 2;
175    I1 += 2;
176    I2 += 2;
177    R7 = [ P0 ];          // cause DAG PROTECTION VIOLATION (p0 is an MMR)
178    I3 += 2;
179
180
181EXCPT 2;             // turn off SSSTEP
182
183CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC);
184
185CHECKREG(r5, 7); // check the flag  (# SSSTEP)
186CHECKREG(r4, 1); // check the flag  (# illegal opcodes)
187
188END:
189dbg_pass;            // End the test
190
191//*********************************************************************
192
193//
194// Handlers for Events
195//
196
197NHANDLE:            // NMI Handler 2
198RTN;
199
200XHANDLE:            // Exception Handler 3
201
202    [ -- SP ] = ASTAT; // save what we damage
203    [ -- SP ] = ( R7:6 );
204    R7 = SEQSTAT;
205    R7 <<= 26;
206    R7 >>= 26;      // only want EXCAUSE
207    R6 = 0x02;      // EXCAUSE 0x02 means EXCPT 2
208CC = r7 == r6;
209IF CC JUMP EXCPT2;
210
211    R6 = 0x10;      // EXCAUSE 0x10 means Single Step
212CC = r7 == r6;
213IF CC JUMP SSSTEP (BP);
214
215    R6 = 0x23;      // EXCAUSE 0x23 means DAG Protection Violation
216CC = r7 == r6;
217IF CC JUMP DAGPROTVIOL (BP);
218
219JUMP.S OUT;       // if the EXCAUSE is wrong the test will infinite loop
220
221EXCPT2:             // turn off SSSTEP
222    R7 = 0;
223SYSCFG = r7;
224JUMP.S OUT;
225
226SSSTEP:
227    R5 += 1;         // increment a counter
228JUMP.S OUT;
229
230DAGPROTVIOL:
231    R7 = RETX;
232    R7 += 2;
233RETX = R7;      // skip offending instruction
234
235    R4 += 1;        // increment another counter
236
237OUT:
238    ( R7:6 ) = [ SP ++ ];
239ASTAT = [sp++];
240RTX;
241
242HWHANDLE:           // HW Error Handler 5
243RTI;
244
245THANDLE:            // Timer Handler 6
246RTI;
247
248I7HANDLE:           // IVG 7 Handler
249RTI;
250
251I8HANDLE:           // IVG 8 Handler
252RTI;
253
254I9HANDLE:           // IVG 9 Handler
255RTI;
256
257I10HANDLE:          // IVG 10 Handler
258RTI;
259
260I11HANDLE:          // IVG 11 Handler
261RTI;
262
263I12HANDLE:          // IVG 12 Handler
264RTI;
265
266I13HANDLE:          // IVG 13 Handler
267RTI;
268
269I14HANDLE:          // IVG 14 Handler
270RTI;
271
272I15HANDLE:          // IVG 15 Handler
273RTI;
274
275
276    // padding for the icache
277
278EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0; EXCPT 0;
279
280//
281// Data Segment
282//
283
284.section MEM_DATA_ADDR_1 //.data 0xE0000000,"aw"
285DATA:
286    .space (0x10);
287
288DATADUMMY:
289    .space (0x10);
290
291// Stack Segments (Both Kernel and User)
292
293    .space (STACKSIZE);
294KSTACK:
295
296    .space (STACKSIZE);
297USTACK:
298