1//Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_a0alr/c_dsp32shiftim_a0alr.dsp
2// Spec Reference: dsp32shift a0 ashift, lshift, rot
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8	R0 = 0;
9	ASTAT = R0;
10
11	imm32 r0, 0x11140000;
12	imm32 r1, 0x012C003E;
13	imm32 r2, 0x81359E24;
14	imm32 r3, 0x81459E24;
15	imm32 r4, 0xD159E268;
16	imm32 r5, 0x51626AF2;
17	imm32 r6, 0x9176AF36;
18	imm32 r7, 0xE18BFF86;
19
20	R0.L = 0;
21	A0 = 0;
22	A0.L = R1.L;
23	A0.H = R1.H;
24	A0 = A0 << 0;	/* a0 = 0x00000000 */
25	R1 = A0.w;	/* r5 = 0x00000000 */
26	CHECKREG r1, 0x012C003E;
27
28	R1.L = 1;
29	A0.L = R2.L;
30	A0.H = R2.H;
31	A0 = A0 << 1;	/* a0 = 0x00000000 */
32	R2 = A0.w;	/* r5 = 0x00000000 */
33	CHECKREG r2, 0x026B3C48;
34
35	R2.L = 15;
36	A0.L = R3.L;
37	A0.H = R3.H;
38	A0 = A0 << 15;	/* a0 = 0x00000000 */
39	R3 = A0.w;	/* r5 = 0x00000000 */
40	CHECKREG r3, 0xCF120000;
41
42	R3.L = 31;
43	A0.L = R4.L;
44	A0.H = R4.H;
45	A0 = A0 << 31;	/* a0 = 0x00000000 */
46	R4 = A0.w;	/* r5 = 0x00000000 */
47	CHECKREG r4, 0x00000000;
48
49	R4.L = -1;
50	A0.L = R5.L;
51	A0.H = R5.H;
52	A0 = A0 >>> 1;	/* a0 = 0x00000000 */
53	R5 = A0.w;	/* r5 = 0x00000000 */
54	CHECKREG r5, 0x28B13579;
55
56	R5.L = -16;
57	A0 = 0;
58	A0.L = R6.L;
59	A0.H = R6.H;
60	A0 = A0 >>> 16;	/* a0 = 0x00000000 */
61	R6 = A0.w;	/* r5 = 0x00000000 */
62	CHECKREG r6, 0x00009176;
63
64	R6.L = -31;
65	A0.L = R7.L;
66	A0.H = R7.H;
67	A0 = A0 >>> 31;	/* a0 = 0x00000000 */
68	R0 = A0.w;	/* r5 = 0x00000000 */
69	CHECKREG r0, 0x00000001;
70
71	R7.L = -32;
72	A0.L = R0.L;
73	A0.H = R0.H;
74	.dw 0xC683		//  .dw 0xC683		// A0 = A0 >>> 32;
75	.dw 0x0100
76	R7 = A0.w;	/* r5 = 0x00000000 */
77	CHECKREG r7, 0x00000000;
78
79	imm32 r0, 0x12340000;
80	imm32 r1, 0x028C003E;
81	imm32 r2, 0x82159E24;
82	imm32 r3, 0x82159E24;
83	imm32 r4, 0xD259E268;
84	imm32 r5, 0x52E26AF2;
85	imm32 r6, 0x9226AF36;
86	imm32 r7, 0xE26BFF86;
87
88	R0.L = 0;
89	A0 = 0;
90	A0.L = R1.L;
91	A0.H = R1.H;
92	A0 = A0 << 0;	/* a0 = 0x00000000 */
93	R1 = A0.w;	/* r5 = 0x00000000 */
94	CHECKREG r1, 0x028C003E;
95
96	R1.L = 1;
97	A0.L = R2.L;
98	A0.H = R2.H;
99	A0 = A0 << 3;	/* a0 = 0x00000000 */
100	R2 = A0.w;	/* r5 = 0x00000000 */
101	CHECKREG r2, 0x10ACF120;
102
103	R2.L = 15;
104	A0.L = R3.L;
105	A0.H = R3.H;
106	A0 = A0 << 15;	/* a0 = 0x00000000 */
107	R3 = A0.w;	/* r5 = 0x00000000 */
108	CHECKREG r3, 0xCF120000;
109
110	R3.L = 31;
111	A0.L = R4.L;
112	A0.H = R4.H;
113	A0 = A0 << 31;	/* a0 = 0x00000000 */
114	R4 = A0.w;	/* r5 = 0x00000000 */
115	CHECKREG r4, 0x00000000;
116
117	R4.L = -1;
118	A0.L = R5.L;
119	A0.H = R5.H;
120	A0 = A0 >> 1;	/* a0 = 0x00000000 */
121	R5 = A0.w;	/* r5 = 0x00000000 */
122	CHECKREG r5, 0x29713579;
123
124	R5.L = -16;
125	A0 = 0;
126	A0.L = R6.L;
127	A0.H = R6.H;
128	A0 = A0 >> 16;	/* a0 = 0x00000000 */
129	R6 = A0.w;	/* r5 = 0x00000000 */
130	CHECKREG r6, 0x00009226;
131
132	R6.L = -31;
133	A0.L = R7.L;
134	A0.H = R7.H;
135	A0 = A0 >> 31;	/* a0 = 0x00000000 */
136	R7 = A0.w;	/* r5 = 0x00000000 */
137	CHECKREG r7, 0x00000001;
138
139	R7.L = -32;
140	A0.L = R0.L;
141	A0.H = R0.H;
142	.dw 0xC683
143	.dw 0x4100		// A0 = A0 >> 32;
144	R0 = A0.w;	/* r5 = 0x00000000 */
145	CHECKREG r0, 0x00000000;
146
147	imm32 r0, 0x13340000;
148	imm32 r1, 0x038C003E;
149	imm32 r2, 0x83159E24;
150	imm32 r3, 0x83159E24;
151	imm32 r4, 0xD359E268;
152	imm32 r5, 0x53E26AF2;
153	imm32 r6, 0x9326AF36;
154	imm32 r7, 0xE36BFF86;
155
156	R0.L = 0;
157	A0 = 0;
158	A0.L = R1.L;
159	A0.H = R1.H;
160	A0 = ROT A0 BY 0;	/* a0 = 0x00000000 */
161	R1 = A0.w;	/* r5 = 0x00000000 */
162	CHECKREG r1, 0x038C003E;
163
164	R1.L = 1;
165	A0.L = R2.L;
166	A0.H = R2.H;
167	A0 = ROT A0 BY 1;	/* a0 = 0x00000000 */
168	R2 = A0.w;	/* r5 = 0x00000000 */
169	CHECKREG r2, 0x062B3C48;
170
171	R2.L = 15;
172	A0.L = R3.L;
173	A0.H = R3.H;
174	A0 = ROT A0 BY 15;	/* a0 = 0x00000000 */
175	R3 = A0.w;	/* r5 = 0x00000000 */
176	CHECKREG r3, 0xCF120060;
177
178	R3.L = 31;
179	A0.L = R4.L;
180	A0.H = R4.H;
181	A0 = ROT A0 BY 31;	/* a0 = 0x00000000 */
182	R4 = A0.w;	/* r5 = 0x00000000 */
183	CHECKREG r4, 0x62B4D678;
184
185	R4.L = -1;
186	A0.L = R5.L;
187	A0.H = R5.H;
188	A0 = ROT A0 BY -1;	/* a0 = 0x00000000 */
189	R5 = A0.w;	/* r5 = 0x00000000 */
190	CHECKREG r5, 0x29F13579;
191
192	R5.L = -16;
193	A0.L = R6.L;
194	A0.H = R6.H;
195	A0 = ROT A0 BY -16;	/* a0 = 0x00000000 */
196	R6 = A0.w;	/* r5 = 0x00000000 */
197	CHECKREG r6, 0x6C9A9326;
198
199	R6.L = -31;
200	A0.L = R7.L;
201	A0.H = R7.H;
202	A0 = ROT A0 BY -31;	/* a0 = 0x00000000 */
203	R7 = A0.w;	/* r5 = 0x00000000 */
204	CHECKREG r7, 0xAFFE1ABD;
205
206	R7.L = -32;
207	A0.L = R0.L;
208	A0.H = R0.H;
209	A0 = ROT A0 BY -32;	/* a0 = 0x00000000 */
210	R0 = A0.w;	/* r5 = 0x00000000 */
211	CHECKREG r0, 0x6800018D;
212
213	pass
214