1139825Simp//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a0_m/c_dsp32mac_pair_a0_m.dsp
2103620Sgrehan// Spec Reference: dsp32mac pair a0 m (M, MNOP)
3103620Sgrehan# mach: bfin
4103620Sgrehan
5103620Sgrehan.include "testutils.inc"
6103620Sgrehan	start
7103620Sgrehan
8103620Sgrehan	A1 = A0 = 0;
9103620Sgrehan
10103620Sgrehan// The result accumulated in A       , and stored to a reg half
11103620Sgrehan	imm32 r0, 0x63545abd;
12103620Sgrehan	imm32 r1, 0x86bcfec7;
13103620Sgrehan	imm32 r2, 0xa8645679;
14103620Sgrehan	imm32 r3, 0x00860007;
15103620Sgrehan	imm32 r4, 0xefb86569;
16103620Sgrehan	imm32 r5, 0x1235860b;
17103620Sgrehan	imm32 r6, 0x000c086d;
18103620Sgrehan	imm32 r7, 0x678e0086;
19103620Sgrehan	A1 += R1.L * R0.L (M), R6 = ( A0 = R1.L * R0.L );
20103620Sgrehan	P5 = A1.w;
21103620Sgrehan	P1 = A0.w;
22103620Sgrehan	A1 = R2.L * R3.L (M), R0 = ( A0 = R2.H * R3.L );
23103620Sgrehan	P2 = A0.w;
24103620Sgrehan	A1 -= R7.L * R4.L (M), R2 = ( A0 += R7.H * R4.H );
25103620Sgrehan	P3 = A0.w;
26103620Sgrehan	A1 += R6.L * R5.L (M), R4 = ( A0 += R6.L * R5.H );
27103620Sgrehan	P4 = A0.w;
28103620Sgrehan	CHECKREG r0, 0xFFFB3578;
29103620Sgrehan	CHECKREG r1, 0x86BCFEC7;
30103620Sgrehan	CHECKREG r2, 0xF2CF3598;
31103620Sgrehan	CHECKREG r3, 0x00860007;
32103620Sgrehan	CHECKREG r4, 0xF70DA834;
33103620Sgrehan	CHECKREG r5, 0x1235860B;
34103620Sgrehan	CHECKREG r6, 0xFF221DD6;
35103620Sgrehan	CHECKREG r7, 0x678E0086;
36103620Sgrehan	CHECKREG p1, 0xFF221DD6;
37103620Sgrehan	CHECKREG p2, 0xFFFB3578;
38103620Sgrehan	CHECKREG p3, 0xF2CF3598;
39103620Sgrehan	CHECKREG p4, 0xF70DA834;
40103620Sgrehan	CHECKREG p5, 0xFF910EEB;
41103620Sgrehan
42103620Sgrehan	imm32 r0, 0x98764abd;
43103620Sgrehan	imm32 r1, 0xa1bcf4c7;
44103620Sgrehan	imm32 r2, 0xa1145649;
45103620Sgrehan	imm32 r3, 0x00010005;
46103620Sgrehan	imm32 r4, 0xefbc1569;
47103620Sgrehan	imm32 r5, 0x1235010b;
48103620Sgrehan	imm32 r6, 0x000c001d;
49103620Sgrehan	imm32 r7, 0x678e0001;
50160722Smarcel	R4 = ( A0 -= R1.L * R0.L );
51160722Smarcel	P1 = A0.w;
52103620Sgrehan	R0 = ( A0 = R2.H * R3.L );
53160722Smarcel	P2 = A0.w;
54103620Sgrehan	R2 = ( A0 += R4.H * R5.H );
55160722Smarcel	P3 = A0.w;
56103620Sgrehan	R0 = ( A0 += R6.L * R7.H );
57160722Smarcel	P4 = A0.w;
58160722Smarcel	CHECKREG r0, 0xFFBC8F22;
59160722Smarcel	CHECKREG r1, 0xA1BCF4C7;
60103620Sgrehan	CHECKREG r2, 0xFFA518F6;
61103620Sgrehan	CHECKREG r3, 0x00010005;
62103620Sgrehan	CHECKREG r4, 0xFD9B2E5E;
63103620Sgrehan	CHECKREG r5, 0x1235010B;
64160722Smarcel	CHECKREG r6, 0x000C001D;
65160722Smarcel	CHECKREG r7, 0x678E0001;
66160722Smarcel	CHECKREG p1, 0xFD9B2E5E;
67160722Smarcel	CHECKREG p2, 0xFFFC4AC8;
68103620Sgrehan	CHECKREG p3, 0xFFA518F6;
69103620Sgrehan	CHECKREG p4, 0xFFBC8F22;
70103620Sgrehan
71160722Smarcel	imm32 r0, 0x7136459d;
72103620Sgrehan	imm32 r1, 0xabd69ec7;
73160722Smarcel	imm32 r2, 0x71145679;
74160722Smarcel	imm32 r3, 0x08010007;
75103620Sgrehan	imm32 r4, 0xef9c1569;
76160722Smarcel	imm32 r5, 0x1225010b;
77103620Sgrehan	imm32 r6, 0x0003401d;
78103620Sgrehan	imm32 r7, 0x678e0561;
79103620Sgrehan	A1 += R1.H * R0.L (M), R4 = ( A0 = R1.L * R0.L );
80160722Smarcel	P1 = A0.w;
81160722Smarcel	R6 = ( A0 -= R2.H * R3.L );
82103620Sgrehan	P2 = A0.w;
83103620Sgrehan	A1 = R4.H * R5.L (M), R0 = ( A0 += R4.H * R5.H );
84160722Smarcel	P3 = A0.w;
85103620Sgrehan	R4 = ( A0 += R6.L * R7.H );
86103620Sgrehan	P4 = A0.w;
87160722Smarcel	CHECKREG r0, 0xC39B0E3E;
88	CHECKREG r1, 0xABD69EC7;
89	CHECKREG r2, 0x71145679;
90	CHECKREG r3, 0x08010007;
91	CHECKREG r4, 0xA26DF406;
92	CHECKREG r5, 0x1225010B;
93	CHECKREG r6, 0xCB19D6FE;
94	CHECKREG r7, 0x678E0561;
95	CHECKREG p1, 0xCB200616;
96	CHECKREG p2, 0xCB19D6FE;
97	CHECKREG p3, 0xC39B0E3E;
98	CHECKREG p4, 0xA26DF406;
99
100	imm32 r0, 0x123489bd;
101	imm32 r1, 0x91bcfec7;
102	imm32 r2, 0xa9145679;
103	imm32 r3, 0xd0910007;
104	imm32 r4, 0xedb91569;
105	imm32 r5, 0xd235910b;
106	imm32 r6, 0x0d0c0999;
107	imm32 r7, 0x67de0009;
108	R0 = ( A0 = R5.L * R3.L );
109	P1 = A0.w;
110	A1 = R2.H * R1.H (M), R2 = ( A0 = R2.H * R1.L );
111	P2 = A0.w;
112	A1 = R7.H * R0.H (M), R4 = ( A0 -= R7.H * R0.H );
113	P3 = A0.w;
114	R6 = ( A0 += R4.L * R6.H );
115	P4 = A0.w;
116	CHECKREG r0, 0xFFF9EE9A;
117	CHECKREG r1, 0x91BCFEC7;
118	CHECKREG r2, 0x00D48D18;
119	CHECKREG r3, 0xD0910007;
120	CHECKREG r4, 0x00DA3B3C;
121	CHECKREG r5, 0xD235910B;
122	CHECKREG r6, 0x06E3E0DC;
123	CHECKREG r7, 0x67DE0009;
124	CHECKREG p1, 0xFFF9EE9A;
125	CHECKREG p2, 0x00D48D18;
126	CHECKREG p3, 0x00DA3B3C;
127	CHECKREG p4, 0x06E3E0DC;
128
129	pass
130