1//Original:/testcases/core/c_dsp32mac_dr_a1_is/c_dsp32mac_dr_a1_is.dsp 2// Spec Reference: dsp32mac dr_a1 is ((scale by 2 signed int) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11A1 = A0 = 0; 12 13// The result accumulated in A1 , and stored to a reg half 14imm32 r0, 0xa3545abd; 15imm32 r1, 0xbdbcfec7; 16imm32 r2, 0xc1248679; 17imm32 r3, 0xd0069007; 18imm32 r4, 0xefbc4569; 19imm32 r5, 0xcd35500b; 20imm32 r6, 0xe00c800d; 21imm32 r7, 0xf78e900f; 22R0.H = ( A1 = R1.L * R0.L ), A0 = R1.L * R0.L (ISS2); 23R1 = A1.w; 24R2.H = ( A1 -= R2.L * R3.H ), A0 = R2.H * R3.L (ISS2); 25R3 = A1.w; 26R4.H = ( A1 += R4.H * R5.L ), A0 -= R4.H * R5.H (ISS2); 27R5 = A1.w; 28R6.H = ( A1 += R6.H * R7.H ), A0 += R6.L * R7.H (ISS2); 29R7 = A1.w; 30CHECKREG r0, 0x80005ABD; 31CHECKREG r1, 0xFF910EEB; 32CHECKREG r2, 0x80008679; 33CHECKREG r3, 0xE8CA9815; 34CHECKREG r4, 0x80004569; 35CHECKREG r5, 0xE3B4A529; 36CHECKREG r6, 0x8000800D; 37CHECKREG r7, 0xE4C27FD1; 38 39// The result accumulated in A1, and stored to a reg half (MNOP) 40imm32 r0, 0x63548abd; 41imm32 r1, 0x7dbcfec7; 42imm32 r2, 0xC5885679; 43imm32 r3, 0xC5880000; 44imm32 r4, 0xcfbc4569; 45imm32 r5, 0xd235c00b; 46imm32 r6, 0xe00ca00d; 47imm32 r7, 0x678e700f; 48R0.H = ( A1 = R1.L * R0.L ) (ISS2); 49R1 = A1.w; 50R2.H = ( A1 += R2.L * R3.H ) (ISS2); 51R3 = A1.w; 52R4.H = ( A1 -= R4.H * R5.L ) (ISS2); 53R5 = A1.w; 54R6.H = ( A1 -= R6.H * R7.H ) (ISS2); 55R7 = A1.w; 56CHECKREG r0, 0x7FFF8ABD; 57CHECKREG r1, 0x008F5EEB; 58CHECKREG r2, 0x80005679; 59CHECKREG r3, 0xECCF6C33; 60CHECKREG r4, 0x80004569; 61CHECKREG r5, 0xE0C07F1F; 62CHECKREG r6, 0x8000A00D; 63CHECKREG r7, 0xEDAD6477; 64 65// The result accumulated in A1 , and stored to a reg half (MNOP) 66imm32 r0, 0x5354babd; 67imm32 r1, 0x6dbcdec7; 68imm32 r2, 0x7124e679; 69imm32 r3, 0x80067007; 70imm32 r4, 0x9fbc4569; 71imm32 r5, 0xa235900b; 72imm32 r6, 0xb00c300d; 73imm32 r7, 0xc78ea00f; 74 R0.H = A1 , A0 -= R1.L * R0.L (ISS2); 75R1 = A1.w; 76 R2.H = A1 , A0 += R2.H * R3.L (ISS2); 77R3 = A1.w; 78 R4.H = A1 , A0 -= R4.H * R5.H (ISS2); 79R5 = A1.w; 80 R6.H = A1 , A0 = R6.L * R7.H (ISS2); 81R7 = A1.w; 82CHECKREG r0, 0x8000BABD; 83CHECKREG r1, 0xEDAD6477; 84CHECKREG r2, 0x8000E679; 85CHECKREG r3, 0xEDAD6477; 86CHECKREG r4, 0x80004569; 87CHECKREG r5, 0xEDAD6477; 88CHECKREG r6, 0x8000300D; 89CHECKREG r7, 0xEDAD6477; 90 91// The result accumulated in A1 , and stored to a reg half 92imm32 r0, 0x33545abd; 93imm32 r1, 0x5dbcfec7; 94imm32 r2, 0x71245679; 95imm32 r3, 0x90060007; 96imm32 r4, 0xafbc4569; 97imm32 r5, 0xd235900b; 98imm32 r6, 0xc00ca00d; 99imm32 r7, 0x678ed00f; 100R0.H = ( A1 = R1.L * R0.L ) (M), A0 = R1.L * R0.L (ISS2); 101R1 = A1.w; 102R2.H = ( A1 += R2.L * R3.H ) (M), A0 -= R2.H * R3.L (ISS2); 103R3 = A1.w; 104R4.H = ( A1 -= R4.H * R5.L ) (M), A0 += R4.H * R5.H (ISS2); 105R5 = A1.w; 106R6.H = ( A1 += R6.H * R7.H ) (M), A0 += R6.L * R7.H (ISS2); 107R7 = A1.w; 108CHECKREG r0, 0x80005ABD; 109CHECKREG r1, 0xFF910EEB; 110CHECKREG r2, 0x7FFF5679; 111CHECKREG r3, 0x303725C1; 112CHECKREG r4, 0x7FFF4569; 113CHECKREG r5, 0x5D60D8AD; 114CHECKREG r6, 0x7FFFA00D; 115CHECKREG r7, 0x43823355; 116 117// The result accumulated in A1 MM=0, and stored to a reg half (MNOP) 118imm32 r0, 0x92005ABD; 119imm32 r1, 0x09300000; 120imm32 r2, 0x56749679; 121imm32 r3, 0x30A95000; 122imm32 r4, 0xa0009669; 123imm32 r5, 0x01000970; 124imm32 r6, 0xdf45609D; 125imm32 r7, 0x12345679; 126R0.H = ( A1 += R1.L * R0.L ) (M,ISS2); 127R1 = A1.w; 128R2.H = ( A1 -= R2.L * R3.H ) (M,ISS2); 129R3 = A1.w; 130R4.H = ( A1 -= R4.H * R5.L ) (M,ISS2); 131R5 = A1.w; 132R6.H = ( A1 = R6.H * R7.H ) (M,ISS2); 133R7 = A1.w; 134CHECKREG r0, 0x7FFF5ABD; 135CHECKREG r1, 0x43823355; 136CHECKREG r2, 0x7FFF9679; 137CHECKREG r3, 0x57912D74; 138CHECKREG r4, 0x7FFF9669; 139CHECKREG r5, 0x5B1B2D74; 140CHECKREG r6, 0x8000609D; 141CHECKREG r7, 0xFDAC3404; 142 143 144 145pass 146