1//Original:/testcases/core/c_dsp32mac_dr_a0_iu/c_dsp32mac_dr_a0_iu.dsp 2// Spec Reference: dsp32mac dr a0 iu (unsigned int) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11A1 = A0 = 0; 12 13// The result accumulated in A , and stored to a reg half 14imm32 r0, 0x83545abd; 15imm32 r1, 0x78bcfec7; 16imm32 r2, 0xc7948679; 17imm32 r3, 0xd0799007; 18imm32 r4, 0xefb79569; 19imm32 r5, 0xcd35700b; 20imm32 r6, 0xe00c877d; 21imm32 r7, 0xf78e9097; 22A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ); 23R1 = A0.w; 24A1 -= R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ); 25R3 = A0.w; 26A1 = R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ); 27R5 = A0.w; 28A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ); 29R7 = A0.w; 30CHECKREG r0, 0x8354FF22; 31CHECKREG r1, 0xFF221DD6; 32CHECKREG r2, 0xC794315B; 33CHECKREG r3, 0x315B6A18; 34CHECKREG r4, 0xEFB72AE5; 35CHECKREG r5, 0x2AE51252; 36CHECKREG r6, 0xE00C32D9; 37CHECKREG r7, 0x32D896FE; 38 39// The result accumulated in A , and stored to a reg half (MNOP) 40imm32 r0, 0xc5548abd; 41imm32 r1, 0x7b5cfec7; 42imm32 r2, 0xa1b55679; 43imm32 r3, 0xb00b5007; 44imm32 r4, 0xcfbcb5c9; 45imm32 r5, 0x5235cb5c; 46imm32 r6, 0xe50c50b8; 47imm32 r7, 0x675e750b; 48R0.L = ( A0 = R1.L * R0.L ); 49R1 = A0.w; 50R2.L = ( A0 += R2.L * R3.H ); 51R3 = A0.w; 52R4.L = ( A0 -= R4.H * R5.L ); 53R5 = A0.w; 54R6.L = ( A0 = R6.H * R7.H ); 55R7 = A0.w; 56CHECKREG r0, 0xC554011F; 57CHECKREG r1, 0x011EBDD6; 58CHECKREG r2, 0xA1B5CB1B; 59CHECKREG r3, 0xCB1A8C3C; 60CHECKREG r4, 0xCFBCB741; 61CHECKREG r5, 0xB741151C; 62CHECKREG r6, 0xE50CEA3C; 63CHECKREG r7, 0xEA3BDCD0; 64 65// The result accumulated in A , and stored to a reg half (MNOP) 66imm32 r0, 0x4b54babd; 67imm32 r1, 0xbabcdec7; 68imm32 r2, 0xa4bbe679; 69imm32 r3, 0x8abdb007; 70imm32 r4, 0x9f4b7b69; 71imm32 r5, 0xa23487bb; 72imm32 r6, 0xb00c488b; 73imm32 r7, 0xc78ea4b8; 74R0.L = ( A0 -= R1.L * R0.L ); 75R1 = A0.w; 76R2.L = ( A0 = R2.H * R3.L ); 77R3 = A0.w; 78R4.L = ( A0 = R4.H * R5.H ); 79R5 = A0.w; 80R6.L = ( A0 += R6.L * R7.H ); 81R7 = A0.w; 82CHECKREG r0, 0x4B54D842; 83CHECKREG r1, 0xD841BEFA; 84CHECKREG r2, 0xA4BB3906; 85CHECKREG r3, 0x3906223A; 86CHECKREG r4, 0x9F4B46DE; 87CHECKREG r5, 0x46DDA278; 88CHECKREG r6, 0xB00C26E0; 89CHECKREG r7, 0x26E036AC; 90 91// The result accumulated in A , and stored to a reg half 92imm32 r0, 0x1a545abd; 93imm32 r1, 0x52fcfec7; 94imm32 r2, 0xc13f5679; 95imm32 r3, 0x9c04f007; 96imm32 r4, 0xafccec69; 97imm32 r5, 0xd23c5e1b; 98imm32 r6, 0xc00cc6e2; 99imm32 r7, 0x678edc7e; 100A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ); 101R3 = A0.w; 102A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ); 103R7 = A0.w; 104A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ); 105R5 = A0.w; 106A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ); 107R1 = A0.w; 108CHECKREG r0, 0x1A544DFA; 109CHECKREG r1, 0x4DFA5880; 110CHECKREG r2, 0xC13F2602; 111CHECKREG r3, 0x26025482; 112CHECKREG r4, 0xAFCC1CAD; 113CHECKREG r5, 0x1CAD17A0; 114CHECKREG r6, 0xC00C4F71; 115CHECKREG r7, 0x4F70B886; 116 117 118 119pass 120