1220185Sadrian//Original:/testcases/core/c_dsp32mac_dr_a0_ih/c_dsp32mac_dr_a0_ih.dsp
2220185Sadrian// Spec Reference: dsp32mac dr a0 ih (integer mutiplication with high word extraction)
3220185Sadrian# mach: bfin
4220185Sadrian
5220185Sadrian.include "testutils.inc"
6220185Sadrian	start
7220185Sadrian
8220185Sadrian
9220185Sadrian
10220185Sadrian
11220185SadrianA1 = A0 = 0;
12220185Sadrian
13220185Sadrian// The result accumulated in A , and stored to a reg half
14220185Sadrianimm32 r0, 0xf3545abd;
15220185Sadrianimm32 r1, 0x7fbcfec7;
16220185Sadrianimm32 r2, 0xc7fff679;
17220185Sadrianimm32 r3, 0xd0799007;
18220185Sadrianimm32 r4, 0xefb79f69;
19220185Sadrianimm32 r5, 0xcd35700b;
20220185Sadrianimm32 r6, 0xe00c87fd;
21220185Sadrianimm32 r7, 0xf78e909f;
22220185SadrianA1 = R1.L * R0.L, R0.L = ( A0 -= R1.L * R0.L ) (IH);
23220185SadrianR1 = A0.w;
24220185SadrianA1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (IH);
25220185SadrianR3 = A0.w;
26220185SadrianA1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (IH);
27220185SadrianR5 = A0.w;
28220185SadrianA1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (IH);
29220185SadrianR7 = A0.w;
30220185SadrianCHECKREG r0, 0xF354006F;
31220185SadrianCHECKREG r1, 0x006EF115;
32220185SadrianCHECKREG r2, 0xC7FF187F;
33220185SadrianCHECKREG r3, 0x187EE7F9;
34220185SadrianCHECKREG r4, 0xEFB71BBA;
35220185SadrianCHECKREG r5, 0x1BBA13DC;
36220185SadrianCHECKREG r6, 0xE00C1FB0;
37227413SadrianCHECKREG r7, 0x1FAF9D32;
38220185Sadrian
39220185Sadrian// The result accumulated in A , and stored to a reg half (MNOP)
40220185Sadrianimm32 r0, 0xc5548abd;
41220185Sadrianimm32 r1, 0x9b5cfec7;
42imm32 r2, 0xa9b55679;
43imm32 r3, 0xb09b5007;
44imm32 r4, 0xcfb9b5c9;
45imm32 r5, 0x52359b5c;
46imm32 r6, 0xe50c5098;
47imm32 r7, 0x675e7509;
48R0.L = ( A0 = R1.L * R0.L ) (IH);
49R1 = A0.w;
50R2.L = ( A0 += R2.L * R3.H ) (IH);
51R3 = A0.w;
52R4.L = ( A0 = R4.H * R5.L ) (IH);
53R5 = A0.w;
54R6.L = ( A0 -= R6.H * R7.H ) (IH);
55R7 = A0.w;
56CHECKREG r0, 0xC554008F;
57CHECKREG r1, 0x008F5EEB;
58CHECKREG r2, 0xA9B5E5BE;
59CHECKREG r3, 0xE5BDEA2E;
60CHECKREG r4, 0xCFB912FB;
61CHECKREG r5, 0x12FAA97C;
62CHECKREG r6, 0xE50C1DDD;
63CHECKREG r7, 0x1DDCBB14;
64
65// The result accumulated in A , and stored to a reg half (MNOP)
66imm32 r0, 0x4b54babd;
67imm32 r1, 0x12346ec7;
68imm32 r2, 0xa4bbe679;
69imm32 r3, 0x8abdb707;
70imm32 r4, 0x9f4b7b69;
71imm32 r5, 0xa234877b;
72imm32 r6, 0xb00c4887;
73imm32 r7, 0xc78ea4b8;
74R0.L = ( A0 = R1.L * R0.L ) (IH);
75R1 = A0.w;
76R2.L = ( A0 -= R2.H * R3.L ) (IH);
77R3 = A0.w;
78R4.L = ( A0 = R4.H * R5.H ) (IH);
79R5 = A0.w;
80R6.L = ( A0 += R6.L * R7.H ) (IH);
81R7 = A0.w;
82CHECKREG r0, 0x4B54E207;
83CHECKREG r1, 0xE2075EEB;
84CHECKREG r2, 0xA4BBC803;
85CHECKREG r3, 0xC80330CE;
86CHECKREG r4, 0x9F4B236F;
87CHECKREG r5, 0x236ED13C;
88CHECKREG r6, 0xB00C1371;
89CHECKREG r7, 0x1370FD1E;
90
91// The result accumulated in A , and stored to a reg half
92imm32 r0, 0x1a545abd;
93imm32 r1, 0x42fcfec7;
94imm32 r2, 0xc53f5679;
95imm32 r3, 0x9c64f007;
96imm32 r4, 0xafc7ec69;
97imm32 r5, 0xd23c891b;
98imm32 r6, 0xc00cc602;
99imm32 r7, 0x678edc7e;
100A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (IH);
101R3 = A0.w;
102A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (IH);
103R7 = A0.w;
104A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (IH);
105R5 = A0.w;
106A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (IH);
107R1 = A0.w;
108CHECKREG r0, 0x1A54EEED;
109CHECKREG r1, 0xEEED15DF;
110CHECKREG r2, 0xC53F1302;
111CHECKREG r3, 0x13020C09;
112CHECKREG r4, 0xAFC7EEE5;
113CHECKREG r5, 0xEEE57293;
114CHECKREG r6, 0xC00CFD3D;
115CHECKREG r7, 0xFD3CE337;
116
117
118
119pass
120