1//Original:/proj/frio/dv/testcases/core/c_compi2opd_flags_2/c_compi2opd_flags_2.dsp 2// Spec Reference: compi2opd dregs += imm7 flags_2 (az, an, ac, av0) 3# mach: bfin 4 5#include "test.h" 6.include "testutils.inc" 7 start 8 9 INIT_R_REGS 0; 10 11 ASTAT = R0; // initialize astat 12 13// AZ for R0 14 imm32 r0, 0x00000000; 15 R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 16 R7 = ASTAT; 17 R0 += 1; // az = 0 an = 0 ac = 0 av0 = 0 18 R6 = ASTAT; 19 R0 += -1; // az = 1 an = 0 ac = 1 av0 = 0 20 R5 = ASTAT; 21 R1 = R0; 22 R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 23 R4 = ASTAT; 24 R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 25 R3 = ASTAT; 26 CHECKREG r0, 0x00000000; 27 CHECKREG r1, 0x00000000; 28 CHECKREG r3, (_AC0|_AC0_COPY|_AZ); 29 CHECKREG r4, (_AN); 30 CHECKREG r5, (_AC0|_AC0_COPY|_AZ); 31 CHECKREG r6, 0x00000000; 32 CHECKREG r7, (_AZ); 33 34// AN, AC for R0 35 imm32 r0, 0xffffffff; 36 R0 += 1; // az = 1 an = 0 ac = 1 av0 = 0 37 R7 = ASTAT; 38 R1 = R0; 39 R0 += 0; // az = 1 an = 0 ac = 0 av0 = 0 40 R6 = ASTAT; 41 R0 += -1; // az = 0 an = 1 ac = 0 av0 = 0 42 R5 = ASTAT; 43 CHECKREG r0, 0xFFFFFFFF; 44 CHECKREG r1, 0x00000000; 45 CHECKREG r5, (_AN); 46 CHECKREG r6, (_AZ); 47 CHECKREG r7, (_AC0|_AC0_COPY|_AZ); 48 49// AC, AV0 for R0 50 imm32 r0, 0x7fffffff; 51 R0 += 1; // az = 0 an = 1 ac = 0 av0 = 1 52 R7 = ASTAT; 53 R1 = R0; 54 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 55 R6 = ASTAT; 56 R2 = R0; 57 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 0 58 R5 = ASTAT; 59 CHECKREG r0, 0x7FFFFFFE; 60 CHECKREG r1, 0x80000000; 61 CHECKREG r2, 0x7FFFFFFF; 62 CHECKREG r5, (_VS|_AC0|_AC0_COPY); 63 CHECKREG r6, (_AC0|_AC0_COPY|_V|_V_COPY|_VS); 64 CHECKREG r7, (_VS|_V|_V_COPY|_AN); 65 66// AZ, AN, AC, AV0 for R0 67 R0 = 0; 68 ASTAT = R0; 69 imm32 r0, 0x80000000; 70 R0 += -1; // az = 0 an = 0 ac = 1 av0 = 1 71 R7 = ASTAT; 72 R1 = R0; 73 R0 += 1; // az = 1 an = 1 ac = 0 av0 = 1 74 R6 = ASTAT; 75 R2 = R0; 76 R0 += 1; // az = 0 an = 1 ac = 0 av0 = 0 77 R5 = ASTAT; 78 CHECKREG r0, 0x80000001; 79 CHECKREG r1, 0x7FFFFFFF; 80 CHECKREG r2, 0x80000000; 81 CHECKREG r5, (_VS|_AN); 82 CHECKREG r6, (_VS|_V_COPY|_V|_AN); 83 CHECKREG r7, (_VS|_V_COPY|_V|_AC0|_AC0_COPY); 84 85// AZ for R0 86 imm32 r1, 0x00000000; 87 ASTAT = R1; 88 R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 89 R7 = ASTAT; 90 R1 += 1; // az = 0 an = 0 ac = 0 av0 = 0 91 R6 = ASTAT; 92 R1 += -1; // az = 1 an = 0 ac = 1 av0 = 0 93 R5 = ASTAT; 94 R0 = R1; 95 R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 96 R4 = ASTAT; 97 R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 98 R3 = ASTAT; 99 CHECKREG r0, 0x00000000; 100 CHECKREG r1, 0x00000000; 101 CHECKREG r3, (_AC0|_AC0_COPY|_AZ); 102 CHECKREG r4, (_AN); 103 CHECKREG r5, (_AC0|_AC0_COPY|_AZ); 104 CHECKREG r6, 0x00000000; 105 CHECKREG r7, (_AZ); 106 107// AN, AC for R1 108 r1 = 0; 109 ASTAT = r1; 110 imm32 r1, 0xffffffff; 111 R1 += 1; // az = 1 an = 0 ac = 1 av0 = 0 112 R7 = ASTAT; 113 R0 = R1; 114 R1 += 0; // az = 1 an = 0 ac = 0 av0 = 0 115 R6 = ASTAT; 116 R1 += -1; // az = 0 an = 1 ac = 0 av0 = 0 117 R5 = ASTAT; 118 CHECKREG r0, 0x00000000; 119 CHECKREG r1, 0xFFFFFFFF; 120 CHECKREG r5, (_AN); 121 CHECKREG r6, (_AZ); 122 CHECKREG r7, (_AC0|_AC0_COPY|_AZ); 123 124// AC, AV0 for R1 125 imm32 r1, 0x7fffffff; 126 R1 += 1; // az = 0 an = 1 ac = 0 av0 = 1 127 R7 = ASTAT; 128 R0 = R1; 129 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 130 R6 = ASTAT; 131 R2 = R1; 132 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 0 133 R5 = ASTAT; 134 CHECKREG r0, 0x80000000; 135 CHECKREG r1, 0x7FFFFFFE; 136 CHECKREG r2, 0x7FFFFFFF; 137 CHECKREG r5, (_VS|_AC0|_AC0_COPY); 138 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 139 CHECKREG r7, (_VS|_V|_V_COPY|_AN); 140 141// AZ, AN, AC, AV0 for R1 142 R1 = 0; 143 ASTAT = R1; 144 imm32 r1, 0x80000000; 145 R1 += -1; // az = 0 an = 0 ac = 1 av0 = 1 146 R7 = ASTAT; 147 R0 = R1; 148 R1 += 1; // az = 1 an = 1 ac = 0 av0 = 1 149 R6 = ASTAT; 150 R2 = R1; 151 R1 += 1; // az = 0 an = 1 ac = 0 av0 = 0 152 R5 = ASTAT; 153 CHECKREG r0, 0x7FFFFFFF; 154 CHECKREG r1, 0x80000001; 155 CHECKREG r2, 0x80000000; 156 CHECKREG r5, (_VS|_AN); 157 CHECKREG r6, (_VS|_V|_V_COPY|_AN); 158 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 159 160// AZ for R2 161 imm32 r2, 0x00000000; 162 ASTAT = R2; 163 R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 164 R7 = ASTAT; 165 R2 += 2; // az = 0 an = 0 ac = 0 av0 = 0 166 R6 = ASTAT; 167 R2 += -2; // az = 1 an = 0 ac = 1 av0 = 0 168 R5 = ASTAT; 169 R1 = R2; 170 R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 171 R4 = ASTAT; 172 R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 173 R3 = ASTAT; 174 CHECKREG r1, 0x00000000; 175 CHECKREG r2, 0x00000000; 176 CHECKREG r3, (_AC0|_AC0_COPY|_AZ); 177 CHECKREG r4, (_AN); 178 CHECKREG r5, (_AC0|_AC0_COPY|_AZ); 179 CHECKREG r6, 0x00000000; 180 CHECKREG r7, (_AZ); 181 182// AN, AC for R2 183 R2 = 0; 184 ASTAT = R2; 185 imm32 r2, 0xffffffff; 186 R2 += 2; // az = 1 an = 0 ac = 1 av0 = 0 187 R7 = ASTAT; 188 R1 = R2; 189 R2 += 0; // az = 1 an = 0 ac = 0 av0 = 0 190 R6 = ASTAT; 191 R2 += -2; // az = 0 an = 1 ac = 0 av0 = 0 192 R5 = ASTAT; 193 CHECKREG r2, 0xFFFFFFFF; 194 CHECKREG r1, (_AZ); 195 CHECKREG r5, (_AN); 196 CHECKREG r6, 0x00000000; 197 CHECKREG r7, (_AC0|_AC0_COPY); 198 199// AC, AV0 for R2 200 imm32 r2, 0x7fffffff; 201 R2 += 2; // az = 0 an = 1 ac = 0 av0 = 1 202 R7 = ASTAT; 203 R0 = R2; 204 R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 205 R6 = ASTAT; 206 R1 = R2; 207 R2 += -2; // az = 0 an = 0 ac = 1 av0 = 0 208 R5 = ASTAT; 209 CHECKREG r0, 0x80000001; 210 CHECKREG r1, 0x7FFFFFFF; 211 CHECKREG r2, 0x7FFFFFFD; 212 CHECKREG r5, (_AC0|_AC0_COPY|_VS); 213 CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); 214 CHECKREG r7, (_VS|_V|_V_COPY|_AN); 215 216// AZ, AN, AC, AV0 for R2 217 R2 = 0; 218 ASTAT = R2; 219 imm32 r2, 0x80000000; 220 R2 += -2; // az = 0 an = 0 ac = 1 av0 = 1 221 R7 = ASTAT; 222 R0 = R2; 223 R2 += 2; // az = 1 an = 1 ac = 0 av0 = 1 224 R6 = ASTAT; 225 R1 = R2; 226 R2 += 2; // az = 0 an = 1 ac = 0 av0 = 0 227 R5 = ASTAT; 228 CHECKREG r0, 0x7FFFFFFE; 229 CHECKREG r1, 0x80000000; 230 CHECKREG r2, 0x80000002; 231 CHECKREG r5, (_VS|_AN); 232 CHECKREG r6, (_VS|_V|_V_COPY|_AN); 233 CHECKREG r7, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); 234 235// AZ for R3 236 imm32 r3, 0x00000000; 237 ASTAT = R3; 238 R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 239 R7 = ASTAT; 240 R3 += 3; // az = 0 an = 0 ac = 0 av0 = 0 241 R6 = ASTAT; 242 R3 += -3; // az = 1 an = 0 ac = 1 av0 = 0 243 R5 = ASTAT; 244 R0 = R3; 245 R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 246 R4 = ASTAT; 247 R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 248 R2 = ASTAT; 249 CHECKREG r0, 0x00000000; 250 CHECKREG r2, (_AC0|_AC0_COPY|_AZ); 251 CHECKREG r3, 0x00000000; 252 CHECKREG r4, (_AN); 253 CHECKREG r5, (_AC0|_AC0_COPY|_AZ); 254 CHECKREG r6, 0x00000000; 255 CHECKREG r7, (_AZ); 256 257// AN, AC for R3 258 imm32 r3, 0xffffffff; 259 R3 += 3; // az = 1 an = 0 ac = 1 av0 = 0 260 R7 = ASTAT; 261 R0 = R3; 262 R3 += 0; // az = 1 an = 0 ac = 0 av0 = 0 263 R6 = ASTAT; 264 R3 += -3; // az = 0 an = 1 ac = 0 av0 = 0 265 R5 = ASTAT; 266 CHECKREG r0, 0x00000002; 267 CHECKREG r3, 0xFFFFFFFF; 268 CHECKREG r5, (_AN); 269 CHECKREG r6, 0x00000000; 270 CHECKREG r7, (_AC0|_AC0_COPY); 271 272// AC, AV0 for R3 273 imm32 r3, 0x7fffffff; 274 R3 += 3; // az = 0 an = 1 ac = 0 av0 = 1 275 R7 = ASTAT; 276 R0 = R3; 277 R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 278 R6 = ASTAT; 279 R1 = R3; 280 R3 += -3; // az = 0 an = 0 ac = 1 av0 = 0 281 R5 = ASTAT; 282 CHECKREG r0, 0x80000002; 283 CHECKREG r1, 0x7FFFFFFF; 284 CHECKREG r3, 0x7FFFFFFC; 285 CHECKREG r5, (_VS|_AC0|_AC0_COPY); 286 CHECKREG r6, (_AC0|_AC0_COPY|_VS|_V|_V_COPY); 287 CHECKREG r7, (_VS|_V|_V_COPY|_AN); 288 289// AZ, AN, AC, AV0 for R3 290 R3 = 0; 291 ASTAT = R3; 292 imm32 r3, 0x80000000; 293 R3 += -3; // az = 0 an = 0 ac = 1 av0 = 1 294 R7 = ASTAT; 295 R0 = R3; 296 R3 += 3; // az = 1 an = 1 ac = 0 av0 = 1 297 R6 = ASTAT; 298 R1 = R3; 299 R3 += 3; // az = 0 an = 1 ac = 0 av0 = 0 300 R5 = ASTAT; 301 CHECKREG r0, 0x7FFFFFFD; 302 CHECKREG r1, 0x80000000; 303 CHECKREG r3, 0x80000003; 304 CHECKREG r5, (_VS|_AN); 305 CHECKREG r6, (_VS|_V|_V_COPY|_AN); 306 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 307 308// AZ for R4 309 imm32 r4, 0x00000000; 310 ASTAT = R4; 311 R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 312 R7 = ASTAT; 313 R4 += 4; // az = 0 an = 0 ac = 0 av0 = 0 314 R6 = ASTAT; 315 R4 += -4; // az = 1 an = 0 ac = 1 av0 = 0 316 R5 = ASTAT; 317 R1 = R4; 318 R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 319 R3 = ASTAT; 320 R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 321 R2 = ASTAT; 322 CHECKREG r1, 0x00000000; 323 CHECKREG r2, (_AC0|_AC0_COPY|_AZ); 324 CHECKREG r3, (_AN); 325 CHECKREG r4, 0x00000000; 326 CHECKREG r5, (_AC0|_AC0_COPY|_AZ); 327 CHECKREG r6, 0x00000000; 328 CHECKREG r7, (_AZ); 329 330// AN, AC for R4 331 imm32 r4, 0xffffffff; 332 R4 += 4; // az = 1 an = 0 ac = 1 av0 = 0 333 R7 = ASTAT; 334 R1 = R4; 335 R4 += 0; // az = 1 an = 0 ac = 0 av0 = 0 336 R6 = ASTAT; 337 R4 += -4; // az = 0 an = 1 ac = 0 av0 = 0 338 R5 = ASTAT; 339 CHECKREG r1, 0x00000003; 340 CHECKREG r4, 0xFFFFFFFF; 341 CHECKREG r5, (_AN); 342 CHECKREG r6, 0x00000000; 343 CHECKREG r7, (_AC0|_AC0_COPY); 344 345// AC, AV0 for R4 346 imm32 r4, 0x7fffffff; 347 R4 += 4; // az = 0 an = 1 ac = 0 av0 = 1 348 R7 = ASTAT; 349 R1 = R4; 350 R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 351 R6 = ASTAT; 352 R2 = R4; 353 R4 += -4; // az = 0 an = 0 ac = 1 av0 = 0 354 R5 = ASTAT; 355 CHECKREG r1, 0x80000003; 356 CHECKREG r2, 0x7FFFFFFF; 357 CHECKREG r4, 0x7FFFFFFB; 358 CHECKREG r5, (_VS|_AC0|_AC0_COPY); 359 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 360 CHECKREG r7, (_VS|_V|_V_COPY|_AN); 361 362// AZ, AN, AC, AV0 for R4 363 R4 = 0; 364 ASTAT = R4; 365 imm32 r4, 0x80000000; 366 R4 += -4; // az = 0 an = 0 ac = 1 av0 = 1 367 R7 = ASTAT; 368 R1 = R4; 369 R4 += 4; // az = 1 an = 1 ac = 0 av0 = 1 370 R6 = ASTAT; 371 R2 = R4; 372 R4 += 4; // az = 0 an = 1 ac = 0 av0 = 0 373 R5 = ASTAT; 374 CHECKREG r1, 0x7FFFFFFC; 375 CHECKREG r2, 0x80000000; 376 CHECKREG r4, 0x80000004; 377 CHECKREG r5, (_VS|_AN); 378 CHECKREG r6, (_VS|_V|_V_COPY|_AN); 379 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 380 381// AZ for R5 382 imm32 r5, 0x00000000; 383 ASTAT = R5; 384 R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 385 R7 = ASTAT; 386 R5 += 5; // az = 0 an = 0 ac = 0 av0 = 0 387 R6 = ASTAT; 388 R5 += -5; // az = 1 an = 0 ac = 1 av0 = 0 389 R2 = ASTAT; 390 R0 = R5; 391 R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 392 R4 = ASTAT; 393 R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 394 R3 = ASTAT; 395 CHECKREG r0, 0x00000000; 396 CHECKREG r2, (_AC0|_AC0_COPY|_AZ); 397 CHECKREG r3, (_AC0|_AC0_COPY|_AZ); 398 CHECKREG r4, (_AN); 399 CHECKREG r5, 0x00000000; 400 CHECKREG r6, 0x00000000; 401 CHECKREG r7, (_AZ); 402 403// AN, AC for R5 404 imm32 r5, 0xffffffff; 405 R5 += 5; // az = 1 an = 0 ac = 1 av0 = 0 406 R7 = ASTAT; 407 R0 = R5; 408 R5 += 0; // az = 1 an = 0 ac = 0 av0 = 0 409 R6 = ASTAT; 410 R5 += -5; // az = 0 an = 1 ac = 0 av0 = 0 411 R4 = ASTAT; 412 CHECKREG r0, 0x00000004; 413 CHECKREG r4, (_AN); 414 CHECKREG r5, 0xFFFFFFFF; 415 CHECKREG r6, 0x00000000; 416 CHECKREG r7, (_AC0|_AC0_COPY); 417 418// AC, AV0 for R5 419 imm32 r5, 0x7fffffff; 420 R5 += 5; // az = 0 an = 1 ac = 0 av0 = 1 421 R7 = ASTAT; 422 R0 = R5; 423 R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 424 R6 = ASTAT; 425 R2 = R5; 426 R5 += -5; // az = 0 an = 0 ac = 1 av0 = 0 427 R4 = ASTAT; 428 CHECKREG r0, 0x80000004; 429 CHECKREG r2, 0x7FFFFFFF; 430 CHECKREG r4, (_VS|_AC0|_AC0_COPY); 431 CHECKREG r5, 0x7FFFFFFA; 432 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 433 CHECKREG r7, (_VS|_V|_V_COPY|_AN); 434 435// AZ, AN, AC, AV0 for R5 436 R5 = 0; 437 ASTAT = R5; 438 imm32 r5, 0x80000000; 439 R5 += -5; // az = 0 an = 0 ac = 1 av0 = 1 440 R7 = ASTAT; 441 R0 = R5; 442 R5 += 5; // az = 1 an = 1 ac = 0 av0 = 1 443 R6 = ASTAT; 444 R2 = R5; 445 R5 += 5; // az = 0 an = 1 ac = 0 av0 = 0 446 R4 = ASTAT; 447 CHECKREG r0, 0x7FFFFFFB; 448 CHECKREG r2, 0x80000000; 449 CHECKREG r4, (_VS|_AN); 450 CHECKREG r5, 0x80000005; 451 CHECKREG r6, (_VS|_V|_V_COPY|_AN); 452 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 453 454// AZ for R6 455 imm32 r6, 0x00000000; 456 ASTAT = R6; 457 R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 458 R7 = ASTAT; 459 R6 += 6; // az = 0 an = 0 ac = 0 av0 = 0 460 R0 = ASTAT; 461 R6 += -6; // az = 1 an = 0 ac = 1 av0 = 0 462 R5 = ASTAT; 463 R1 = R6; 464 R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 465 R4 = ASTAT; 466 R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 467 R3 = ASTAT; 468 CHECKREG r0, 0x00000000; 469 CHECKREG r1, 0x00000000; 470 CHECKREG r3, (_AC0|_AC0_COPY|_AZ); 471 CHECKREG r4, (_AN); 472 CHECKREG r5, (_AC0|_AC0_COPY|_AZ); 473 CHECKREG r6, 0x00000000; 474 CHECKREG r7, (_AZ); 475 476// AN, AC for R6 477 imm32 r6, 0xffffffff; 478 R6 += 6; // az = 1 an = 0 ac = 1 av0 = 0 479 R7 = ASTAT; 480 R1 = R6; 481 R6 += 0; // az = 1 an = 0 ac = 0 av0 = 0 482 R4 = ASTAT; 483 R6 += -6; // az = 0 an = 1 ac = 0 av0 = 0 484 R5 = ASTAT; 485 CHECKREG r1, 0x00000005; 486 CHECKREG r4, 0x00000000; 487 CHECKREG r5, (_AN); 488 CHECKREG r6, 0xFFFFFFFF; 489 CHECKREG r7, (_AC0|_AC0_COPY); 490 491// AC, AV0 for R6 492 imm32 r6, 0x7fffffff; 493 R6 += 6; // az = 0 an = 1 ac = 0 av0 = 1 494 R7 = ASTAT; 495 R0 = R6; 496 R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 497 R4 = ASTAT; 498 R1 = R6; 499 R6 += -6; // az = 0 an = 0 ac = 1 av0 = 0 500 R5 = ASTAT; 501 CHECKREG r0, 0x80000005; 502 CHECKREG r1, 0x7FFFFFFF; 503 CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 504 CHECKREG r5, (_VS|_AC0|_AC0_COPY); 505 CHECKREG r6, 0x7FFFFFF9; 506 CHECKREG r7, (_VS|_V|_V_COPY|_AN); 507 508// AZ, AN, AC, AV0 for R6 509 R6 = 0; 510 ASTAT = R6; 511 imm32 r6, 0x80000000; 512 R6 += -6; // az = 0 an = 0 ac = 1 av0 = 1 513 R7 = ASTAT; 514 R0 = R6; 515 R6 += 6; // az = 1 an = 1 ac = 0 av0 = 1 516 R4 = ASTAT; 517 R1 = R6; 518 R6 += 6; // az = 0 an = 1 ac = 0 av0 = 0 519 R5 = ASTAT; 520 CHECKREG r0, 0x7FFFFFFA; 521 CHECKREG r1, 0x80000000; 522 CHECKREG r4, (_VS|_V|_V_COPY|_AN); 523 CHECKREG r5, (_VS|_AN); 524 CHECKREG r6, 0x80000006; 525 CHECKREG r7, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 526 527// AZ for R7 528 imm32 r7, 0x00000000; 529 ASTAT = R7; 530 R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 531 R1 = ASTAT; 532 R7 += 7; // az = 0 an = 0 ac = 0 av0 = 0 533 R6 = ASTAT; 534 R7 += -7; // az = 1 an = 0 ac = 1 av0 = 0 535 R5 = ASTAT; 536 R0 = R7; 537 R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 538 R4 = ASTAT; 539 R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 540 R2 = ASTAT; 541 CHECKREG r0, 0x00000000; 542 CHECKREG r1, (_AZ); 543 CHECKREG r2, (_AC0|_AC0_COPY|_AZ); 544 CHECKREG r4, (_AN); 545 CHECKREG r5, (_AC0|_AC0_COPY|_AZ); 546 CHECKREG r6, 0x00000000; 547 CHECKREG r7, 0x00000000; 548 549// AN, AC for R7 550 imm32 r7, 0xffffffff; 551 R7 += 7; // az = 1 an = 0 ac = 1 av0 = 0 552 R4 = ASTAT; 553 R0 = R7; 554 R7 += 0; // az = 1 an = 0 ac = 0 av0 = 0 555 R6 = ASTAT; 556 R7 += -7; // az = 0 an = 1 ac = 0 av0 = 0 557 R5 = ASTAT; 558 CHECKREG r0, 0x00000006; 559 CHECKREG r4, (_AC0|_AC0_COPY); 560 CHECKREG r5, (_AN); 561 CHECKREG r6, 0x00000000; 562 CHECKREG r7, 0xFFFFFFFF; 563 564// AC, AV0 for R7 565 imm32 r7, 0x7fffffff; 566 R7 += 7; // az = 0 an = 1 ac = 0 av0 = 1 567 R4 = ASTAT; 568 R0 = R7; 569 R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 570 R6 = ASTAT; 571 R1 = R7; 572 R7 += -7; // az = 0 an = 0 ac = 1 av0 = 0 573 R5 = ASTAT; 574 CHECKREG r0, 0x80000006; 575 CHECKREG r1, 0x7FFFFFFF; 576 CHECKREG r4, (_VS|_V|_V_COPY|_AN); 577 CHECKREG r5, (_VS|_AC0|_AC0_COPY); 578 CHECKREG r6, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 579 CHECKREG r7, 0x7FFFFFF8; 580 581// AZ, AN, AC, AV0 for R7 582 R7 = 0; 583 ASTAT = R7; 584 imm32 r7, 0x80000000; 585 R7 += -7; // az = 0 an = 0 ac = 1 av0 = 1 586 R4 = ASTAT; 587 R0 = R7; 588 R7 += 7; // az = 1 an = 1 ac = 0 av0 = 1 589 R6 = ASTAT; 590 R1 = R7; 591 R7 += 7; // az = 0 an = 1 ac = 0 av0 = 0 592 R5 = ASTAT; 593 CHECKREG r0, 0x7FFFFFF9; 594 CHECKREG r1, 0x80000000; 595 CHECKREG r4, (_VS|_V|_V_COPY|_AC0|_AC0_COPY); 596 CHECKREG r5, (_VS|_AN); 597 CHECKREG r6, (_VS|_V|_V_COPY|_AN); 598 CHECKREG r7, 0x80000007; 599 600 pass 601