1# mach: aarch64 2 3# Check the store single 1-element structure to one lane instructions: 4# st1, st2, st3, st4. 5# Check the addressing modes: no offset, post-index immediate offset, 6# post-index register offset. 7 8.include "testutils.inc" 9 10 .data 11 .align 4 12input: 13 .word 0x04030201 14 .word 0x08070605 15 .word 0x0c0b0a09 16 .word 0x100f0e0d 17 .word 0x14131211 18 .word 0x18171615 19 .word 0x1c1b1a19 20 .word 0x201f1e1d 21output: 22 .zero 64 23 24 start 25 adrp x0, input 26 add x0, x0, :lo12:input 27 adrp x1, output 28 add x1, x1, :lo12:output 29 30 mov x2, x0 31 ldr q0, [x2], 16 32 ldr q1, [x2] 33 mov x2, x0 34 ldr q2, [x2], 16 35 ldr q3, [x2] 36 37 mov x2, x1 38 mov x3, #1 39 mov x4, #4 40 st1 {v0.b}[0], [x2], 1 41 st1 {v0.b}[1], [x2], x3 42 st1 {v0.h}[1], [x2], 2 43 st1 {v0.s}[1], [x2], x4 44 st1 {v0.d}[1], [x2] 45 ldr q4, [x1] 46 addv b4, v4.16b 47 mov x5, v4.d[0] 48 cmp x5, #136 49 bne .Lfailure 50 51 mov x2, x1 52 mov x3, #16 53 mov x4, #4 54 st2 {v0.d, v1.d}[0], [x2], x3 55 st2 {v0.s, v1.s}[2], [x2], 8 56 st2 {v0.h, v1.h}[6], [x2], x4 57 st2 {v0.b, v1.b}[14], [x2], 2 58 st2 {v0.b, v1.b}[15], [x2] 59 mov x2, x1 60 ldr q4, [x2], 16 61 ldr q5, [x2] 62 addv b4, v4.16b 63 addv b5, v5.16b 64 mov x5, v4.d[0] 65 mov x6, v5.d[0] 66 cmp x5, #200 67 bne .Lfailure 68 cmp x6, #72 69 bne .Lfailure 70 71 mov x2, x1 72 mov x3, #12 73 st3 {v0.s, v1.s, v2.s}[0], [x2], 12 74 st3 {v0.s, v1.s, v2.s}[1], [x2], x3 75 st3 {v0.s, v1.s, v2.s}[2], [x2], 12 76 st3 {v0.s, v1.s, v2.s}[3], [x2] 77 mov x2, x1 78 ldr q4, [x2], 16 79 ldr q5, [x2], 16 80 ldr q6, [x2] 81 addv b4, v4.16b 82 addv b5, v5.16b 83 addv b6, v6.16b 84 mov x4, v4.d[0] 85 mov x5, v5.d[0] 86 mov x6, v6.d[0] 87 cmp x4, #120 88 bne .Lfailure 89 cmp x5, #8 90 bne .Lfailure 91 cmp x6, #24 92 bne .Lfailure 93 94 mov x2, x1 95 mov x3, #16 96 st4 {v0.s, v1.s, v2.s, v3.s}[0], [x2], 16 97 st4 {v0.s, v1.s, v2.s, v3.s}[1], [x2], x3 98 st4 {v0.s, v1.s, v2.s, v3.s}[2], [x2], 16 99 st4 {v0.s, v1.s, v2.s, v3.s}[3], [x2] 100 mov x2, x1 101 ldr q4, [x2], 16 102 ldr q5, [x2], 16 103 ldr q6, [x2], 16 104 ldr q7, [x2] 105 addv b4, v4.16b 106 addv b5, v5.16b 107 addv b6, v6.16b 108 addv b7, v7.16b 109 mov x4, v4.d[0] 110 mov x5, v5.d[0] 111 mov x6, v6.d[0] 112 mov x7, v7.d[0] 113 cmp x4, #168 114 bne .Lfailure 115 cmp x5, #232 116 bne .Lfailure 117 cmp x6, #40 118 bne .Lfailure 119 cmp x7, #104 120 bne .Lfailure 121 122 pass 123.Lfailure: 124 fail 125