cpu.h revision 1.3
1/* CPU family header for sh64. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2015 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, see <http://www.gnu.org/licenses/>. 21 22*/ 23 24#ifndef CPU_SH64_H 25#define CPU_SH64_H 26 27/* Maximum number of instructions that are fetched at a time. 28 This is for LIW type instructions sets (e.g. m32r). */ 29#define MAX_LIW_INSNS 1 30 31/* Maximum number of instructions that can be executed in parallel. */ 32#define MAX_PARALLEL_INSNS 1 33 34/* The size of an "int" needed to hold an instruction word. 35 This is usually 32 bits, but some architectures needs 64 bits. */ 36typedef CGEN_INSN_INT CGEN_INSN_WORD; 37 38#include "cgen-engine.h" 39 40/* CPU state information. */ 41typedef struct { 42 /* Hardware elements. */ 43 struct { 44 /* Program counter */ 45 UDI h_pc; 46#define GET_H_PC() CPU (h_pc) 47#define SET_H_PC(x) \ 48do { \ 49{\ 50CPU (h_ism) = ANDDI ((x), 1);\ 51CPU (h_pc) = ANDDI ((x), INVDI (1));\ 52}\ 53;} while (0) 54 /* General purpose integer registers */ 55 DI h_gr[64]; 56#define GET_H_GR(index) ((((index) == (63))) ? (MAKEDI (0, 0)) : (CPU (h_gr[index]))) 57#define SET_H_GR(index, x) \ 58do { \ 59if ((((index)) != (63))) {\ 60CPU (h_gr[(index)]) = (x);\ 61} else {\ 62((void) 0); /*nop*/\ 63}\ 64;} while (0) 65 /* Control registers */ 66 DI h_cr[64]; 67#define GET_H_CR(index) ((((index) == (0))) ? (ZEXTSIDI (CPU (h_sr))) : (CPU (h_cr[index]))) 68#define SET_H_CR(index, x) \ 69do { \ 70if ((((index)) == (0))) {\ 71CPU (h_sr) = (x);\ 72} else {\ 73CPU (h_cr[(index)]) = (x);\ 74}\ 75;} while (0) 76 /* Status register */ 77 SI h_sr; 78#define GET_H_SR() CPU (h_sr) 79#define SET_H_SR(x) (CPU (h_sr) = (x)) 80 /* Floating point status and control register */ 81 SI h_fpscr; 82#define GET_H_FPSCR() CPU (h_fpscr) 83#define SET_H_FPSCR(x) (CPU (h_fpscr) = (x)) 84 /* Single precision floating point registers */ 85 SF h_fr[64]; 86#define GET_H_FR(a1) CPU (h_fr)[a1] 87#define SET_H_FR(a1, x) (CPU (h_fr)[a1] = (x)) 88 /* Single/Double precision floating point registers */ 89 DF h_fsd[16]; 90#define GET_H_FSD(index) ((GET_H_PRBIT ()) ? (GET_H_DRC (index)) : (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, CPU (h_fr[index])))) 91#define SET_H_FSD(index, x) \ 92do { \ 93if (GET_H_PRBIT ()) {\ 94SET_H_DRC ((index), (x));\ 95} else {\ 96SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ 97}\ 98;} while (0) 99 /* floating point registers for fmov */ 100 DF h_fmov[16]; 101#define GET_H_FMOV(index) ((NOTBI (GET_H_SZBIT ())) ? (CGEN_CPU_FPU (current_cpu)->ops->fextsfdf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, GET_H_FRC (index))) : (((((((index) & (1))) == (1))) ? (GET_H_XD (((index) & ((~ (1)))))) : (GET_H_DR (index))))) 102#define SET_H_FMOV(index, x) \ 103do { \ 104if (NOTBI (GET_H_SZBIT ())) {\ 105SET_H_FRC ((index), CGEN_CPU_FPU (current_cpu)->ops->ftruncdfsf (CGEN_CPU_FPU (current_cpu), FPCONV_DEFAULT, (x)));\ 106} else {\ 107if ((((((index)) & (1))) == (1))) {\ 108SET_H_XD ((((index)) & ((~ (1)))), (x));\ 109} else {\ 110SET_H_DR ((index), (x));\ 111}\ 112}\ 113;} while (0) 114 /* Branch target registers */ 115 DI h_tr[8]; 116#define GET_H_TR(a1) CPU (h_tr)[a1] 117#define SET_H_TR(a1, x) (CPU (h_tr)[a1] = (x)) 118 /* Current instruction set mode */ 119 BI h_ism; 120#define GET_H_ISM() CPU (h_ism) 121#define SET_H_ISM(x) \ 122do { \ 123cgen_rtx_error (current_cpu, "cannot set ism directly");\ 124;} while (0) 125 } hardware; 126#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware) 127} SH64_CPU_DATA; 128 129/* Virtual regs. */ 130 131#define GET_H_GRC(index) ANDDI (CPU (h_gr[index]), ZEXTSIDI (0xffffffff)) 132#define SET_H_GRC(index, x) \ 133do { \ 134CPU (h_gr[(index)]) = EXTSIDI ((x));\ 135;} while (0) 136#define GET_H_FRBIT() ANDSI (SRLSI (CPU (h_fpscr), 21), 1) 137#define SET_H_FRBIT(x) \ 138do { \ 139CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (21))))), SLLSI ((x), 21));\ 140;} while (0) 141#define GET_H_SZBIT() ANDSI (SRLSI (CPU (h_fpscr), 20), 1) 142#define SET_H_SZBIT(x) \ 143do { \ 144CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (20))))), SLLSI ((x), 20));\ 145;} while (0) 146#define GET_H_PRBIT() ANDSI (SRLSI (CPU (h_fpscr), 19), 1) 147#define SET_H_PRBIT(x) \ 148do { \ 149CPU (h_fpscr) = ORSI (ANDSI (CPU (h_fpscr), (~ (((1) << (19))))), SLLSI ((x), 19));\ 150;} while (0) 151#define GET_H_SBIT() ANDSI (SRLSI (CPU (h_sr), 1), 1) 152#define SET_H_SBIT(x) \ 153do { \ 154CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (2))), SLLSI ((x), 1));\ 155;} while (0) 156#define GET_H_MBIT() ANDSI (SRLSI (CPU (h_sr), 9), 1) 157#define SET_H_MBIT(x) \ 158do { \ 159CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (9))))), SLLSI ((x), 9));\ 160;} while (0) 161#define GET_H_QBIT() ANDSI (SRLSI (CPU (h_sr), 8), 1) 162#define SET_H_QBIT(x) \ 163do { \ 164CPU (h_sr) = ORSI (ANDSI (CPU (h_sr), (~ (((1) << (8))))), SLLSI ((x), 8));\ 165;} while (0) 166#define GET_H_FP(index) CPU (h_fr[index]) 167#define SET_H_FP(index, x) \ 168do { \ 169CPU (h_fr[(index)]) = (x);\ 170;} while (0) 171#define GET_H_FV(index) CPU (h_fr[index]) 172#define SET_H_FV(index, x) \ 173do { \ 174CPU (h_fr[(index)]) = (x);\ 175;} while (0) 176#define GET_H_FMTX(index) CPU (h_fr[index]) 177#define SET_H_FMTX(index, x) \ 178do { \ 179CPU (h_fr[(index)]) = (x);\ 180;} while (0) 181#define GET_H_DR(index) SUBWORDDIDF (ORDI (SLLDI (ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[index]))), 32), ZEXTSIDI (SUBWORDSFSI (CPU (h_fr[((index) + (1))]))))) 182#define SET_H_DR(index, x) \ 183do { \ 184{\ 185CPU (h_fr[(index)]) = SUBWORDSISF (SUBWORDDFSI ((x), 0));\ 186CPU (h_fr[(((index)) + (1))]) = SUBWORDSISF (SUBWORDDFSI ((x), 1));\ 187}\ 188;} while (0) 189#define GET_H_ENDIAN() sh64_endian (current_cpu) 190#define SET_H_ENDIAN(x) \ 191do { \ 192cgen_rtx_error (current_cpu, "cannot alter target byte order mid-program");\ 193;} while (0) 194#define GET_H_FRC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) 195#define SET_H_FRC(index, x) \ 196do { \ 197CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ 198;} while (0) 199#define GET_H_DRC(index) GET_H_DR (((((16) * (GET_H_FRBIT ()))) + (index))) 200#define SET_H_DRC(index, x) \ 201do { \ 202SET_H_DR (((((16) * (GET_H_FRBIT ()))) + ((index))), (x));\ 203;} while (0) 204#define GET_H_XF(index) CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))]) 205#define SET_H_XF(index, x) \ 206do { \ 207CPU (h_fr[((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index)))]) = (x);\ 208;} while (0) 209#define GET_H_XD(index) GET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + (index))) 210#define SET_H_XD(index, x) \ 211do { \ 212SET_H_DR (((((16) * (NOTBI (GET_H_FRBIT ())))) + ((index))), (x));\ 213;} while (0) 214#define GET_H_FVC(index) CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + (index))]) 215#define SET_H_FVC(index, x) \ 216do { \ 217CPU (h_fr[((((16) * (GET_H_FRBIT ()))) + ((index)))]) = (x);\ 218;} while (0) 219#define GET_H_GBR() SUBWORDDISI (CPU (h_gr[((UINT) 16)]), 1) 220#define SET_H_GBR(x) \ 221do { \ 222CPU (h_gr[((UINT) 16)]) = EXTSIDI ((x));\ 223;} while (0) 224#define GET_H_VBR() SUBWORDDISI (CPU (h_gr[((UINT) 20)]), 1) 225#define SET_H_VBR(x) \ 226do { \ 227CPU (h_gr[((UINT) 20)]) = EXTSIDI ((x));\ 228;} while (0) 229#define GET_H_PR() SUBWORDDISI (CPU (h_gr[((UINT) 18)]), 1) 230#define SET_H_PR(x) \ 231do { \ 232CPU (h_gr[((UINT) 18)]) = EXTSIDI ((x));\ 233;} while (0) 234#define GET_H_MACL() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1) 235#define SET_H_MACL(x) \ 236do { \ 237CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0)), 32), ZEXTSIDI ((x)));\ 238;} while (0) 239#define GET_H_MACH() SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 0) 240#define SET_H_MACH(x) \ 241do { \ 242CPU (h_gr[((UINT) 17)]) = ORDI (SLLDI (ZEXTSIDI ((x)), 32), ZEXTSIDI (SUBWORDDISI (CPU (h_gr[((UINT) 17)]), 1)));\ 243;} while (0) 244#define GET_H_TBIT() ANDBI (CPU (h_gr[((UINT) 19)]), 1) 245#define SET_H_TBIT(x) \ 246do { \ 247CPU (h_gr[((UINT) 19)]) = ORDI (ANDDI (CPU (h_gr[((UINT) 19)]), INVDI (1)), ZEXTBIDI ((x)));\ 248;} while (0) 249 250/* Cover fns for register access. */ 251UDI sh64_h_pc_get (SIM_CPU *); 252void sh64_h_pc_set (SIM_CPU *, UDI); 253DI sh64_h_gr_get (SIM_CPU *, UINT); 254void sh64_h_gr_set (SIM_CPU *, UINT, DI); 255SI sh64_h_grc_get (SIM_CPU *, UINT); 256void sh64_h_grc_set (SIM_CPU *, UINT, SI); 257DI sh64_h_cr_get (SIM_CPU *, UINT); 258void sh64_h_cr_set (SIM_CPU *, UINT, DI); 259SI sh64_h_sr_get (SIM_CPU *); 260void sh64_h_sr_set (SIM_CPU *, SI); 261SI sh64_h_fpscr_get (SIM_CPU *); 262void sh64_h_fpscr_set (SIM_CPU *, SI); 263BI sh64_h_frbit_get (SIM_CPU *); 264void sh64_h_frbit_set (SIM_CPU *, BI); 265BI sh64_h_szbit_get (SIM_CPU *); 266void sh64_h_szbit_set (SIM_CPU *, BI); 267BI sh64_h_prbit_get (SIM_CPU *); 268void sh64_h_prbit_set (SIM_CPU *, BI); 269BI sh64_h_sbit_get (SIM_CPU *); 270void sh64_h_sbit_set (SIM_CPU *, BI); 271BI sh64_h_mbit_get (SIM_CPU *); 272void sh64_h_mbit_set (SIM_CPU *, BI); 273BI sh64_h_qbit_get (SIM_CPU *); 274void sh64_h_qbit_set (SIM_CPU *, BI); 275SF sh64_h_fr_get (SIM_CPU *, UINT); 276void sh64_h_fr_set (SIM_CPU *, UINT, SF); 277SF sh64_h_fp_get (SIM_CPU *, UINT); 278void sh64_h_fp_set (SIM_CPU *, UINT, SF); 279SF sh64_h_fv_get (SIM_CPU *, UINT); 280void sh64_h_fv_set (SIM_CPU *, UINT, SF); 281SF sh64_h_fmtx_get (SIM_CPU *, UINT); 282void sh64_h_fmtx_set (SIM_CPU *, UINT, SF); 283DF sh64_h_dr_get (SIM_CPU *, UINT); 284void sh64_h_dr_set (SIM_CPU *, UINT, DF); 285DF sh64_h_fsd_get (SIM_CPU *, UINT); 286void sh64_h_fsd_set (SIM_CPU *, UINT, DF); 287DF sh64_h_fmov_get (SIM_CPU *, UINT); 288void sh64_h_fmov_set (SIM_CPU *, UINT, DF); 289DI sh64_h_tr_get (SIM_CPU *, UINT); 290void sh64_h_tr_set (SIM_CPU *, UINT, DI); 291BI sh64_h_endian_get (SIM_CPU *); 292void sh64_h_endian_set (SIM_CPU *, BI); 293BI sh64_h_ism_get (SIM_CPU *); 294void sh64_h_ism_set (SIM_CPU *, BI); 295SF sh64_h_frc_get (SIM_CPU *, UINT); 296void sh64_h_frc_set (SIM_CPU *, UINT, SF); 297DF sh64_h_drc_get (SIM_CPU *, UINT); 298void sh64_h_drc_set (SIM_CPU *, UINT, DF); 299SF sh64_h_xf_get (SIM_CPU *, UINT); 300void sh64_h_xf_set (SIM_CPU *, UINT, SF); 301DF sh64_h_xd_get (SIM_CPU *, UINT); 302void sh64_h_xd_set (SIM_CPU *, UINT, DF); 303SF sh64_h_fvc_get (SIM_CPU *, UINT); 304void sh64_h_fvc_set (SIM_CPU *, UINT, SF); 305SI sh64_h_gbr_get (SIM_CPU *); 306void sh64_h_gbr_set (SIM_CPU *, SI); 307SI sh64_h_vbr_get (SIM_CPU *); 308void sh64_h_vbr_set (SIM_CPU *, SI); 309SI sh64_h_pr_get (SIM_CPU *); 310void sh64_h_pr_set (SIM_CPU *, SI); 311SI sh64_h_macl_get (SIM_CPU *); 312void sh64_h_macl_set (SIM_CPU *, SI); 313SI sh64_h_mach_get (SIM_CPU *); 314void sh64_h_mach_set (SIM_CPU *, SI); 315BI sh64_h_tbit_get (SIM_CPU *); 316void sh64_h_tbit_set (SIM_CPU *, BI); 317 318/* These must be hand-written. */ 319extern CPUREG_FETCH_FN sh64_fetch_register; 320extern CPUREG_STORE_FN sh64_store_register; 321 322typedef struct { 323 int empty; 324} MODEL_SH4_DATA; 325 326typedef struct { 327 int empty; 328} MODEL_SH5_DATA; 329 330typedef struct { 331 int empty; 332} MODEL_SH5_MEDIA_DATA; 333 334/* Collection of various things for the trace handler to use. */ 335 336typedef struct trace_record { 337 IADDR pc; 338 /* FIXME:wip */ 339} TRACE_RECORD; 340 341#endif /* CPU_SH64_H */ 342