1// -*- C -*- 2 3// Simulator definition for the MIPS DSP REV 2 ASE. 4// Copyright (C) 2007-2023 Free Software Foundation, Inc. 5// Contributed by MIPS Technologies, Inc. 6// Written by Chao-ying Fu (fu@mips.com). 7// 8// This file is part of the MIPS sim 9// 10// This program is free software; you can redistribute it and/or modify 11// it under the terms of the GNU General Public License as published by 12// the Free Software Foundation; either version 3 of the License, or 13// (at your option) any later version. 14// 15// This program is distributed in the hope that it will be useful, 16// but WITHOUT ANY WARRANTY; without even the implied warranty of 17// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18// GNU General Public License for more details. 19// 20// You should have received a copy of the GNU General Public License 21// along with this program. If not, see <http://www.gnu.org/licenses/>. 22 23 24// op: 0 = ADD, 1 = SUB 25// sat: 0 = no saturation, 1 = saturation 26:function:::void:do_u_ph_op:int rd, int rs, int rt, int op, int sat 27{ 28 int i; 29 uint32_t h0; 30 uint16_t h1, h2; 31 uint32_t v1 = GPR[rs]; 32 uint32_t v2 = GPR[rt]; 33 uint32_t result = 0; 34 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 35 { 36 h1 = (uint16_t)(v1 & 0xffff); 37 h2 = (uint16_t)(v2 & 0xffff); 38 if (op == 0) // ADD 39 h0 = (uint32_t)h1 + (uint32_t)h2; 40 else // SUB 41 h0 = (uint32_t)h1 - (uint32_t)h2; 42 if (op == 0 && (h0 > (uint32_t)0x0000ffff)) // ADD SAT 43 { 44 DSPCR |= DSPCR_OUFLAG4; 45 if (sat == 1) 46 h0 = 0xffff; 47 } 48 else if (op == 1 && h1 < h2) // SUB SAT 49 { 50 DSPCR |= DSPCR_OUFLAG4; 51 if (sat == 1) 52 h0 = 0x0; 53 } 54 result |= ((uint32_t)((uint16_t)h0) << i); 55 } 56 GPR[rd] = EXTEND32 (result); 57} 58 59// op: 0 = ADD, 1 = SUB 60// round: 0 = no rounding, 1 = rounding 61:function:::void:do_uh_qb_op:int rd, int rs, int rt, int op, int round 62{ 63 int i; 64 uint32_t h0; 65 uint8_t h1, h2; 66 uint32_t v1 = GPR[rs]; 67 uint32_t v2 = GPR[rt]; 68 uint32_t result = 0; 69 for (i = 0; i < 32; i += 8, v1 >>= 8, v2 >>= 8) 70 { 71 h1 = (uint8_t)(v1 & 0xff); 72 h2 = (uint8_t)(v2 & 0xff); 73 if (op == 0) // ADD 74 h0 = (uint32_t)h1 + (uint32_t)h2; 75 else // SUB 76 h0 = (uint32_t)h1 - (uint32_t)h2; 77 if (round == 1) 78 h0 = (h0 + 1) >> 1; 79 else 80 h0 = h0 >> 1; 81 result |= ((uint32_t)((uint8_t)h0) << i); 82 } 83 GPR[rd] = EXTEND32 (result); 84} 85 86// op: 0 = EQ, 1 = LT, 2 = LE 87:function:::void:do_qb_cmpgdu:int rd, int rs, int rt, int op 88{ 89 int i, j; 90 uint32_t v1 = GPR[rs]; 91 uint32_t v2 = GPR[rt]; 92 uint8_t h1, h2; 93 uint32_t result = 0; 94 uint32_t mask; 95 for (i = 0, j = 0; i < 32; i += 8, j++, v1 >>= 8, v2 >>= 8) 96 { 97 h1 = (uint8_t)(v1 & 0xff); 98 h2 = (uint8_t)(v2 & 0xff); 99 mask = ~(1 << (DSPCR_CCOND_SHIFT + j)); 100 DSPCR &= mask; 101 if (op == 0) // EQ 102 { 103 result |= ((h1 == h2) << j); 104 DSPCR |= ((h1 == h2) << (DSPCR_CCOND_SHIFT + j)); 105 } 106 else if (op == 1) // LT 107 { 108 result |= ((h1 < h2) << j); 109 DSPCR |= ((h1 < h2) << (DSPCR_CCOND_SHIFT + j)); 110 } 111 else // LE 112 { 113 result |= ((h1 <= h2) << j); 114 DSPCR |= ((h1 <= h2) << (DSPCR_CCOND_SHIFT + j)); 115 } 116 } 117 GPR[rd] = EXTEND32 (result); 118} 119 120// op: 0 = DPA 1 = DPS 121:function:::void:do_w_ph_dot_product:int ac, int rs, int rt, int op 122{ 123 int i; 124 uint32_t v1 = GPR[rs]; 125 uint32_t v2 = GPR[rt]; 126 int16_t h1, h2; 127 int32_t result; 128 uint32_t lo = DSPLO(ac); 129 uint32_t hi = DSPHI(ac); 130 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 131 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 132 { 133 h1 = (int16_t)(v1 & 0xffff); 134 h2 = (int16_t)(v2 & 0xffff); 135 result = (int32_t)h1 * (int32_t)h2; 136 if (op == 0) // DPA 137 prod += (int64_t)result; 138 else // DPS 139 prod -= (int64_t)result; 140 } 141 DSPLO(ac) = EXTEND32 (prod); 142 DSPHI(ac) = EXTEND32 (prod >> 32); 143} 144 145// round: 0 = no rounding, 1 = rounding 146:function:::void:do_w_mulq:int rd, int rs, int rt, int round 147{ 148 uint32_t v1 = GPR[rs]; 149 uint32_t v2 = GPR[rt]; 150 int32_t w1, w2; 151 int64_t prod; 152 uint32_t result; 153 w1 = (int32_t) v1; 154 w2 = (int32_t) v2; 155 if (w1 == (int32_t) 0x80000000 && w2 == (int32_t) 0x80000000) 156 { 157 DSPCR |= DSPCR_OUFLAG5; 158 prod = 0x7fffffff; 159 } 160 else 161 { 162 prod = ((int64_t) w1 * (int64_t) w2) << 1; 163 if (round == 1) 164 prod += 0x0000000080000000LL; 165 prod = prod >> 32; 166 } 167 result = (uint32_t) prod; 168 GPR[rd] = EXTEND32 (result); 169} 170 171// round: 0 = no rounding, 1 = rounding 172:function:::void:do_precr_sra:int rt, int rs, int sa, int round 173{ 174 uint32_t v1 = GPR[rt]; 175 uint32_t v2 = GPR[rs]; 176 int32_t w1 = (int32_t) v1; 177 int32_t w2 = (int32_t) v2; 178 int32_t result; 179 if (sa != 0) 180 { 181 if (round == 1 && (w1 & (1 << (sa - 1)))) 182 w1 = (w1 >> sa) + 1; 183 else 184 w1 = w1 >> sa; 185 186 if (round == 1 && (w2 & (1 << (sa - 1)))) 187 w2 = (w2 >> sa) + 1; 188 else 189 w2 = w2 >> sa; 190 } 191 result = (w1 << 16) | (w2 & 0xffff); 192 GPR[rt] = EXTEND32 (result); 193} 194 195// round: 0 = no rounding, 1 = rounding 196:function:::void:do_qb_shra:int rd, int rt, int shift, int round 197{ 198 int i, j; 199 int8_t q0; 200 uint32_t v1 = GPR[rt]; 201 uint32_t result = 0; 202 for (i = 0; i < 32; i += 8, v1 >>= 8) 203 { 204 q0 = (int8_t)(v1 & 0xff); 205 if (shift != 0) 206 { 207 if (round == 1 && (q0 & (1 << (shift - 1)))) 208 q0 = (q0 >> shift) + 1; 209 else 210 q0 = q0 >> shift; 211 } 212 result |= ((uint32_t)((uint8_t)q0) << i); 213 } 214 GPR[rd] = EXTEND32 (result); 215} 216 217:function:::void:do_ph_shrl:int rd, int rt, int shift 218{ 219 int i, j; 220 uint16_t h0; 221 uint32_t v1 = GPR[rt]; 222 uint32_t result = 0; 223 for (i = 0; i < 32; i += 16, v1 >>= 16) 224 { 225 h0 = (uint16_t)(v1 & 0xffff); 226 h0 = h0 >> shift; 227 result |= ((uint32_t)h0 << i); 228 } 229 GPR[rd] = EXTEND32 (result); 230} 231 232// op: 0 = ADD, 1 = SUB 233// round: 0 = no rounding, 1 = rounding 234:function:::void:do_qh_ph_op:int rd, int rs, int rt, int op, int round 235{ 236 int i; 237 int32_t h0; 238 int16_t h1, h2; 239 uint32_t v1 = GPR[rs]; 240 uint32_t v2 = GPR[rt]; 241 uint32_t result = 0; 242 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 >>= 16) 243 { 244 h1 = (int16_t)(v1 & 0xffff); 245 h2 = (int16_t)(v2 & 0xffff); 246 if (op == 0) // ADD 247 h0 = (int32_t)h1 + (int32_t)h2; 248 else // SUB 249 h0 = (int32_t)h1 - (int32_t)h2; 250 if (round == 1) 251 h0 = (h0 + 1) >> 1; 252 else 253 h0 = h0 >> 1; 254 result |= ((uint32_t)((uint16_t)h0) << i); 255 } 256 GPR[rd] = EXTEND32 (result); 257} 258 259// op: 0 = ADD, 1 = SUB 260// round: 0 = no rounding, 1 = rounding 261:function:::void:do_qh_w_op:int rd, int rs, int rt, int op, int round 262{ 263 int i; 264 int64_t v0; 265 int32_t v1 = (int32_t)GPR[rs]; 266 int32_t v2 = (int32_t)GPR[rt]; 267 if (op == 0) // ADD 268 v0 = (int64_t)v1 + (int64_t)v2; 269 else // SUB 270 v0 = (int64_t)v1 - (int64_t)v2; 271 if (round == 1) 272 v0 = (v0 + 1) >> 1; 273 else 274 v0 = v0 >> 1; 275 GPR[rd] = EXTEND32 (v0); 276} 277 278// op: 0 = DPAX, 1 = DPSX 279:function:::void:do_x_w_ph_dot_product:int ac, int rs, int rt, int op 280{ 281 int i; 282 uint32_t v1 = GPR[rs]; 283 uint32_t v2 = GPR[rt]; 284 int16_t h1, h2; 285 int32_t result; 286 uint32_t lo = DSPLO(ac); 287 uint32_t hi = DSPHI(ac); 288 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 289 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) 290 { 291 h1 = (int16_t)(v1 & 0xffff); 292 h2 = (int16_t)((v2 & 0xffff0000) >> 16); 293 result = (int32_t)h1 * (int32_t)h2; 294 if (op == 0) // DPAX 295 prod += (int64_t)result; 296 else // DPSX 297 prod -= (int64_t)result; 298 } 299 DSPLO(ac) = EXTEND32 (prod); 300 DSPHI(ac) = EXTEND32 (prod >> 32); 301} 302 303// op: 0 = DPAQX, 1 = DPSQX 304// sat: 0 = no saturation, 1 = saturation of the accumulator 305:function:::void:do_qx_w_ph_dot_product:int ac, int rs, int rt, int op, int sat 306{ 307 int i; 308 uint32_t v1 = GPR[rs]; 309 uint32_t v2 = GPR[rt]; 310 int16_t h1, h2; 311 int32_t result; 312 uint32_t lo = DSPLO(ac); 313 uint32_t hi = DSPHI(ac); 314 int64_t prod = (int64_t)((((uint64_t)hi) << 32) + (uint64_t)lo); 315 int64_t max, min; 316 for (i = 0; i < 32; i += 16, v1 >>= 16, v2 <<= 16) 317 { 318 h1 = (int16_t)(v1 & 0xffff); 319 h2 = (int16_t)((v2 & 0xffff0000) >> 16); 320 if (h1 == (int16_t)0x8000 && h2 == (int16_t)0x8000) 321 { 322 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 323 result = 0x7fffffff; 324 } 325 else 326 result = ((int32_t)h1 * (int32_t)h2) << 1; 327 if (op == 0) // DPAQX 328 prod += (int64_t)result; 329 else // DPSQX 330 prod -= (int64_t)result; 331 } 332 // Saturation on the accumulator. 333 if (sat == 1) 334 { 335 max = (int64_t) 0x7fffffffLL; 336 min = (int64_t) 0xffffffff80000000LL; 337 if (prod > max) 338 { 339 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 340 prod = max; 341 } 342 else if (prod < min) 343 { 344 DSPCR |= (1 << (DSPCR_OUFLAG_SHIFT + ac)); 345 prod = min; 346 } 347 } 348 DSPLO(ac) = EXTEND32 (prod); 349 DSPHI(ac) = EXTEND32 (prod >> 32); 350} 351 352011111,00000,5.RT,5.RD,00001,010010:SPECIAL3:32::ABSQ_S.QB 353"absq_s.qb r<RD>, r<RT>" 354*dsp2: 355{ 356 do_qb_s_absq (SD_, RD, RT); 357} 358 359011111,5.RS,5.RT,5.RD,01000,010000:SPECIAL3:32::ADDU.PH 360"addu.ph r<RD>, r<RS>, r<RT>" 361*dsp2: 362{ 363 do_u_ph_op (SD_, RD, RS, RT, 0, 0); 364} 365 366011111,5.RS,5.RT,5.RD,01100,010000:SPECIAL3:32::ADDU_S.PH 367"addu_s.ph r<RD>, r<RS>, r<RT>" 368*dsp2: 369{ 370 do_u_ph_op (SD_, RD, RS, RT, 0, 1); 371} 372 373011111,5.RS,5.RT,5.RD,00000,011000:SPECIAL3:32::ADDUH.QB 374"adduh.qb r<RD>, r<RS>, r<RT>" 375*dsp2: 376{ 377 do_uh_qb_op (SD_, RD, RS, RT, 0, 0); 378} 379 380011111,5.RS,5.RT,5.RD,00010,011000:SPECIAL3:32::ADDUH_R.QB 381"adduh_r.qb r<RD>, r<RS>, r<RT>" 382*dsp2: 383{ 384 do_uh_qb_op (SD_, RD, RS, RT, 0, 1); 385} 386 387011111,5.RS,5.RT,5.SA,00000,110001:SPECIAL3:32::APPEND 388"append r<RT>, r<RS>, <SA>" 389*dsp2: 390{ 391 do_append (SD_, RT, RS, SA); 392} 393 394011111,5.RS,5.RT,000,2.BP,10000,110001:SPECIAL3:32::BALIGN 395"balign r<RT>, r<RS>, <BP>" 396*dsp2: 397{ 398 do_balign (SD_, RT, RS, BP); 399} 400 401011111,5.RS,5.RT,5.RD,11000,010001:SPECIAL3:32::CMPGDU.EQ.QB 402"cmpgdu.eq.qb r<RD>, r<RS>, r<RT>" 403*dsp2: 404{ 405 do_qb_cmpgdu (SD_, RD, RS, RT, 0); 406} 407 408011111,5.RS,5.RT,5.RD,11001,010001:SPECIAL3:32::CMPGDU.LT.QB 409"cmpgdu.lt.qb r<RD>, r<RS>, r<RT>" 410*dsp2: 411{ 412 do_qb_cmpgdu (SD_, RD, RS, RT, 1); 413} 414 415011111,5.RS,5.RT,5.RD,11010,010001:SPECIAL3:32::CMPGDU.LE.QB 416"cmpgdu.le.qb r<RD>, r<RS>, r<RT>" 417*dsp2: 418{ 419 do_qb_cmpgdu (SD_, RD, RS, RT, 2); 420} 421 422011111,5.RS,5.RT,000,2.AC,00000,110000:SPECIAL3:32::DPA.W.PH 423"dpa.w.ph ac<AC>, r<RS>, r<RT>" 424*dsp2: 425{ 426 do_w_ph_dot_product (SD_, AC, RS, RT, 0); 427} 428 429011111,5.RS,5.RT,000,2.AC,00001,110000:SPECIAL3:32::DPS.W.PH 430"dps.w.ph ac<AC>, r<RS>, r<RT>" 431*dsp2: 432{ 433 do_w_ph_dot_product (SD_, AC, RS, RT, 1); 434} 435 436011111,5.RS,5.RT,5.RD,01100,011000:SPECIAL3:32::MUL.PH 437"mul.ph r<RD>, r<RS>, r<RT>" 438*dsp2: 439{ 440 do_ph_op (SD_, RD, RS, RT, 2, 0); 441} 442 443011111,5.RS,5.RT,5.RD,01110,011000:SPECIAL3:32::MUL_S.PH 444"mul_s.ph r<RD>, r<RS>, r<RT>" 445*dsp2: 446{ 447 do_ph_op (SD_, RD, RS, RT, 2, 1); 448} 449 450011111,5.RS,5.RT,5.RD,10111,011000:SPECIAL3:32::MULQ_RS.W 451"mulq_rs.w r<RD>, r<RS>, r<RT>" 452*dsp2: 453{ 454 do_w_mulq (SD_, RD, RS, RT, 1); 455} 456 457011111,5.RS,5.RT,5.RD,11110,010000:SPECIAL3:32::MULQ_S.PH 458"mulq_s.ph r<RD>, r<RS>, r<RT>" 459*dsp2: 460{ 461 do_ph_mulq (SD_, RD, RS, RT, 0); 462} 463 464011111,5.RS,5.RT,5.RD,10110,011000:SPECIAL3:32::MULQ_S.W 465"mulq_s.w r<RD>, r<RS>, r<RT>" 466*dsp2: 467{ 468 do_w_mulq (SD_, RD, RS, RT, 0); 469} 470 471011111,5.RS,5.RT,000,2.AC,00010,110000:SPECIAL3:32::MULSA.W.PH 472"mulsa.w.ph ac<AC>, r<RS>, r<RT>" 473*dsp2: 474{ 475 do_ph_w_mulsa (SD_, AC, RS, RT); 476} 477 478011111,5.RS,5.RT,5.RD,01101,010001:SPECIAL3:32::PRECR.QB.PH 479"precr.qb.ph r<RD>, r<RS>, r<RT>" 480*dsp2: 481{ 482 do_ph_qb_precr (SD_, RD, RS, RT); 483} 484 485011111,5.RS,5.RT,5.SA,11110,010001:SPECIAL3:32::PRECR_SRA.PH.W 486"precr_sra.ph.w r<RT>, r<RS>, <SA>" 487*dsp2: 488{ 489 do_precr_sra (SD_, RT, RS, SA, 0); 490} 491 492011111,5.RS,5.RT,5.SA,11111,010001:SPECIAL3:32::PRECR_SRA_R.PH.W 493"precr_sra_r.ph.w r<RT>, r<RS>, <SA>" 494*dsp2: 495{ 496 do_precr_sra (SD_, RT, RS, SA, 1); 497} 498 499011111,5.RS,5.RT,5.SA,00001,110001:SPECIAL3:32::PREPEND 500"prepend r<RT>, r<RS>, <SA>" 501*dsp2: 502{ 503 do_prepend (SD_, RT, RS, SA); 504} 505 506011111,00,3.SHIFT3,5.RT,5.RD,00100,010011:SPECIAL3:32::SHRA.QB 507"shra.qb r<RD>, r<RT>, <SHIFT3>" 508*dsp2: 509{ 510 do_qb_shra (SD_, RD, RT, SHIFT3, 0); 511} 512 513011111,00,3.SHIFT3,5.RT,5.RD,00101,010011:SPECIAL3:32::SHRA_R.QB 514"shra_r.qb r<RD>, r<RT>, <SHIFT3>" 515*dsp2: 516{ 517 do_qb_shra (SD_, RD, RT, SHIFT3, 1); 518} 519 520011111,5.RS,5.RT,5.RD,00110,010011:SPECIAL3:32::SHRAV.QB 521"shrav.qb r<RD>, r<RT>, r<RS>" 522*dsp2: 523{ 524 do_qb_shrav (SD_, RD, RT, RS, 0); 525} 526 527011111,5.RS,5.RT,5.RD,00111,010011:SPECIAL3:32::SHRAV_R.QB 528"shrav_r.qb r<RD>, r<RT>, r<RS>" 529*dsp2: 530{ 531 do_qb_shrav (SD_, RD, RT, RS, 1); 532} 533 534011111,0,4.SHIFT4,5.RT,5.RD,11001,010011:SPECIAL3:32::SHRL.PH 535"shrl.ph r<RD>, r<RT>, <SHIFT4>" 536*dsp2: 537{ 538 do_ph_shrl (SD_, RD, RT, SHIFT4); 539} 540 541011111,5.RS,5.RT,5.RD,11011,010011:SPECIAL3:32::SHRLV.PH 542"shrlv.ph r<RD>, r<RT>, r<RS>" 543*dsp2: 544{ 545 do_ph_shrlv (SD_, RD, RT, RS); 546} 547 548011111,5.RS,5.RT,5.RD,01001,010000:SPECIAL3:32::SUBU.PH 549"subu.ph r<RD>, r<RS>, r<RT>" 550*dsp2: 551{ 552 do_u_ph_op (SD_, RD, RS, RT, 1, 0); 553} 554 555011111,5.RS,5.RT,5.RD,01101,010000:SPECIAL3:32::SUBU_S.PH 556"subu_s.ph r<RD>, r<RS>, r<RT>" 557*dsp2: 558{ 559 do_u_ph_op (SD_, RD, RS, RT, 1, 1); 560} 561 562011111,5.RS,5.RT,5.RD,00001,011000:SPECIAL3:32::SUBUH.QB 563"subuh.qb r<RD>, r<RS>, r<RT>" 564*dsp2: 565{ 566 do_uh_qb_op (SD_, RD, RS, RT, 1, 0); 567} 568 569011111,5.RS,5.RT,5.RD,00011,011000:SPECIAL3:32::SUBUH_R.QB 570"subuh_r.qb r<RD>, r<RS>, r<RT>" 571*dsp2: 572{ 573 do_uh_qb_op (SD_, RD, RS, RT, 1, 1); 574} 575 576011111,5.RS,5.RT,5.RD,01000,011000:SPECIAL3:32::ADDQH.PH 577"addqh.ph r<RD>, r<RS>, r<RT>" 578*dsp2: 579{ 580 do_qh_ph_op (SD_, RD, RS, RT, 0, 0); 581} 582 583011111,5.RS,5.RT,5.RD,01010,011000:SPECIAL3:32::ADDQH_R.PH 584"addqh_r.ph r<RD>, r<RS>, r<RT>" 585*dsp2: 586{ 587 do_qh_ph_op (SD_, RD, RS, RT, 0, 1); 588} 589 590011111,5.RS,5.RT,5.RD,10000,011000:SPECIAL3:32::ADDQH.W 591"addqh.w r<RD>, r<RS>, r<RT>" 592*dsp2: 593{ 594 do_qh_w_op (SD_, RD, RS, RT, 0, 0); 595} 596 597011111,5.RS,5.RT,5.RD,10010,011000:SPECIAL3:32::ADDQH_R.W 598"addqh_r.w r<RD>, r<RS>, r<RT>" 599*dsp2: 600{ 601 do_qh_w_op (SD_, RD, RS, RT, 0, 1); 602} 603 604011111,5.RS,5.RT,5.RD,01001,011000:SPECIAL3:32::SUBQH.PH 605"subqh.ph r<RD>, r<RS>, r<RT>" 606*dsp2: 607{ 608 do_qh_ph_op (SD_, RD, RS, RT, 1, 0); 609} 610 611011111,5.RS,5.RT,5.RD,01011,011000:SPECIAL3:32::SUBQH_R.PH 612"subqh_r.ph r<RD>, r<RS>, r<RT>" 613*dsp2: 614{ 615 do_qh_ph_op (SD_, RD, RS, RT, 1, 1); 616} 617 618011111,5.RS,5.RT,5.RD,10001,011000:SPECIAL3:32::SUBQH.W 619"subqh.w r<RD>, r<RS>, r<RT>" 620*dsp2: 621{ 622 do_qh_w_op (SD_, RD, RS, RT, 1, 0); 623} 624 625011111,5.RS,5.RT,5.RD,10011,011000:SPECIAL3:32::SUBQH_R.W 626"subqh_r.w r<RD>, r<RS>, r<RT>" 627*dsp2: 628{ 629 do_qh_w_op (SD_, RD, RS, RT, 1, 1); 630} 631 632011111,5.RS,5.RT,000,2.AC,01000,110000:SPECIAL3:32::DPAX.W.PH 633"dpax.w.ph ac<AC>, r<RS>, r<RT>" 634*dsp2: 635{ 636 do_x_w_ph_dot_product (SD_, AC, RS, RT, 0); 637} 638 639011111,5.RS,5.RT,000,2.AC,01001,110000:SPECIAL3:32::DPSX.W.PH 640"dpsx.w.ph ac<AC>, r<RS>, r<RT>" 641*dsp2: 642{ 643 do_x_w_ph_dot_product (SD_, AC, RS, RT, 1); 644} 645 646011111,5.RS,5.RT,000,2.AC,11000,110000:SPECIAL3:32::DPAQX_S.W.PH 647"dpaqx_s.w.ph ac<AC>, r<RS>, r<RT>" 648*dsp2: 649{ 650 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 0); 651} 652 653011111,5.RS,5.RT,000,2.AC,11010,110000:SPECIAL3:32::DPAQX_SA.W.PH 654"dpaqx_sa.w.ph ac<AC>, r<RS>, r<RT>" 655*dsp2: 656{ 657 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 0, 1); 658} 659 660011111,5.RS,5.RT,000,2.AC,11001,110000:SPECIAL3:32::DPSQX_S.W.PH 661"dpsqx_s.w.ph ac<AC>, r<RS>, r<RT>" 662*dsp2: 663{ 664 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 0); 665} 666 667011111,5.RS,5.RT,000,2.AC,11011,110000:SPECIAL3:32::DPSQX_SA.W.PH 668"dpsqx_sa.w.ph ac<AC>, r<RS>, r<RT>" 669*dsp2: 670{ 671 do_qx_w_ph_dot_product (SD_, AC, RS, RT, 1, 1); 672} 673