1/* Blackfin Serial Peripheral Interface (SPI) model
2
3   Copyright (C) 2010-2020 Free Software Foundation, Inc.
4   Contributed by Analog Devices, Inc.
5
6   This file is part of simulators.
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 3 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
21#include "config.h"
22
23#include "sim-main.h"
24#include "devices.h"
25#include "dv-bfin_spi.h"
26
27/* XXX: This is merely a stub.  */
28
29struct bfin_spi
30{
31  /* This top portion matches common dv_bfin struct.  */
32  bu32 base;
33  struct hw *dma_master;
34  bool acked;
35
36  struct hw_event *handler;
37  char saved_byte;
38  int saved_count;
39
40  /* Order after here is important -- matches hardware MMR layout.  */
41  bu16 BFIN_MMR_16(ctl);
42  bu16 BFIN_MMR_16(flg);
43  bu16 BFIN_MMR_16(stat);
44  bu16 BFIN_MMR_16(tdbr);
45  bu16 BFIN_MMR_16(rdbr);
46  bu16 BFIN_MMR_16(baud);
47  bu16 BFIN_MMR_16(shadow);
48};
49#define mmr_base()      offsetof(struct bfin_spi, ctl)
50#define mmr_offset(mmr) (offsetof(struct bfin_spi, mmr) - mmr_base())
51
52static const char * const mmr_names[] =
53{
54  "SPI_CTL", "SPI_FLG", "SPI_STAT", "SPI_TDBR",
55  "SPI_RDBR", "SPI_BAUD", "SPI_SHADOW",
56};
57#define mmr_name(off) mmr_names[(off) / 4]
58
59static bool
60bfin_spi_enabled (struct bfin_spi *spi)
61{
62  return (spi->ctl & SPE);
63}
64
65static bu16
66bfin_spi_timod (struct bfin_spi *spi)
67{
68  return (spi->ctl & TIMOD);
69}
70
71static unsigned
72bfin_spi_io_write_buffer (struct hw *me, const void *source, int space,
73			  address_word addr, unsigned nr_bytes)
74{
75  struct bfin_spi *spi = hw_data (me);
76  bu32 mmr_off;
77  bu32 value;
78  bu16 *valuep;
79
80  /* Invalid access mode is higher priority than missing register.  */
81  if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
82    return 0;
83
84  value = dv_load_2 (source);
85  mmr_off = addr - spi->base;
86  valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off);
87
88  HW_TRACE_WRITE ();
89
90  switch (mmr_off)
91    {
92    case mmr_offset(stat):
93      dv_w1c_2 (valuep, value, ~(SPIF | TXS | RXS));
94      break;
95    case mmr_offset(tdbr):
96      *valuep = value;
97      if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == TDBR_CORE)
98	{
99	  spi->stat |= RXS;
100	  spi->stat &= ~TXS;
101	}
102      break;
103    case mmr_offset(rdbr):
104    case mmr_offset(ctl):
105    case mmr_offset(flg):
106    case mmr_offset(baud):
107    case mmr_offset(shadow):
108      *valuep = value;
109      break;
110    default:
111      dv_bfin_mmr_invalid (me, addr, nr_bytes, true);
112      return 0;
113    }
114
115  return nr_bytes;
116}
117
118static unsigned
119bfin_spi_io_read_buffer (struct hw *me, void *dest, int space,
120			 address_word addr, unsigned nr_bytes)
121{
122  struct bfin_spi *spi = hw_data (me);
123  bu32 mmr_off;
124  bu16 *valuep;
125
126  /* Invalid access mode is higher priority than missing register.  */
127  if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
128    return 0;
129
130  mmr_off = addr - spi->base;
131  valuep = (void *)((unsigned long)spi + mmr_base() + mmr_off);
132
133  HW_TRACE_READ ();
134
135  switch (mmr_off)
136    {
137    case mmr_offset(rdbr):
138      dv_store_2 (dest, *valuep);
139      if (bfin_spi_enabled (spi) && bfin_spi_timod (spi) == RDBR_CORE)
140	spi->stat &= ~(RXS | TXS);
141      break;
142    case mmr_offset(ctl):
143    case mmr_offset(stat):
144    case mmr_offset(flg):
145    case mmr_offset(tdbr):
146    case mmr_offset(baud):
147    case mmr_offset(shadow):
148      dv_store_2 (dest, *valuep);
149      break;
150    default:
151      dv_bfin_mmr_invalid (me, addr, nr_bytes, false);
152      return 0;
153    }
154
155  return nr_bytes;
156}
157
158static unsigned
159bfin_spi_dma_read_buffer (struct hw *me, void *dest, int space,
160			  unsigned_word addr, unsigned nr_bytes)
161{
162  HW_TRACE_DMA_READ ();
163  return 0;
164}
165
166static unsigned
167bfin_spi_dma_write_buffer (struct hw *me, const void *source,
168			   int space, unsigned_word addr,
169			   unsigned nr_bytes,
170			   int violate_read_only_section)
171{
172  HW_TRACE_DMA_WRITE ();
173  return 0;
174}
175
176static const struct hw_port_descriptor bfin_spi_ports[] =
177{
178  { "stat", 0, 0, output_port, },
179  { NULL, 0, 0, 0, },
180};
181
182static void
183attach_bfin_spi_regs (struct hw *me, struct bfin_spi *spi)
184{
185  address_word attach_address;
186  int attach_space;
187  unsigned attach_size;
188  reg_property_spec reg;
189
190  if (hw_find_property (me, "reg") == NULL)
191    hw_abort (me, "Missing \"reg\" property");
192
193  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
194    hw_abort (me, "\"reg\" property must contain three addr/size entries");
195
196  hw_unit_address_to_attach_address (hw_parent (me),
197				     &reg.address,
198				     &attach_space, &attach_address, me);
199  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
200
201  if (attach_size != BFIN_MMR_SPI_SIZE)
202    hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_SPI_SIZE);
203
204  hw_attach_address (hw_parent (me),
205		     0, attach_space, attach_address, attach_size, me);
206
207  spi->base = attach_address;
208}
209
210static void
211bfin_spi_finish (struct hw *me)
212{
213  struct bfin_spi *spi;
214
215  spi = HW_ZALLOC (me, struct bfin_spi);
216
217  set_hw_data (me, spi);
218  set_hw_io_read_buffer (me, bfin_spi_io_read_buffer);
219  set_hw_io_write_buffer (me, bfin_spi_io_write_buffer);
220  set_hw_dma_read_buffer (me, bfin_spi_dma_read_buffer);
221  set_hw_dma_write_buffer (me, bfin_spi_dma_write_buffer);
222  set_hw_ports (me, bfin_spi_ports);
223
224  attach_bfin_spi_regs (me, spi);
225
226  /* Initialize the SPI.  */
227  spi->ctl  = 0x0400;
228  spi->flg  = 0xFF00;
229  spi->stat = 0x0001;
230}
231
232const struct hw_descriptor dv_bfin_spi_descriptor[] =
233{
234  {"bfin_spi", bfin_spi_finish,},
235  {NULL, NULL},
236};
237