1/* Blackfin External Bus Interface Unit (EBIU) DDR Controller (DDRC) Model.
2
3   Copyright (C) 2010-2020 Free Software Foundation, Inc.
4   Contributed by Analog Devices, Inc.
5
6   This file is part of simulators.
7
8   This program is free software; you can redistribute it and/or modify
9   it under the terms of the GNU General Public License as published by
10   the Free Software Foundation; either version 3 of the License, or
11   (at your option) any later version.
12
13   This program is distributed in the hope that it will be useful,
14   but WITHOUT ANY WARRANTY; without even the implied warranty of
15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16   GNU General Public License for more details.
17
18   You should have received a copy of the GNU General Public License
19   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
20
21#include "config.h"
22
23#include "sim-main.h"
24#include "devices.h"
25#include "dv-bfin_ebiu_ddrc.h"
26
27struct bfin_ebiu_ddrc
28{
29  bu32 base, reg_size, bank_size;
30
31  /* Order after here is important -- matches hardware MMR layout.  */
32  union {
33    struct { bu32 ddrctl0, ddrctl1, ddrctl2, ddrctl3; };
34    bu32 ddrctl[4];
35  };
36  bu32 ddrque, erradd;
37  bu16 BFIN_MMR_16(errmst);
38  bu16 BFIN_MMR_16(rstctl);
39  bu32 ddrbrc[8], ddrbwc[8];
40  bu32 ddracct, ddrtact, ddrarct;
41  bu32 ddrgc[4];
42  bu32 ddrmcen, ddrmccl;
43};
44#define mmr_base()      offsetof(struct bfin_ebiu_ddrc, ddrctl0)
45#define mmr_offset(mmr) (offsetof(struct bfin_ebiu_ddrc, mmr) - mmr_base())
46
47static const char * const mmr_names[] =
48{
49  "EBIU_DDRCTL0", "EBIU_DDRCTL1", "EBIU_DDRCTL2", "EBIU_DDRCTL3", "EBIU_DDRQUE",
50  "EBIU_ERRADD", "EBIU_ERRMST", "EBIU_RSTCTL", "EBIU_DDRBRC0", "EBIU_DDRBRC1",
51  "EBIU_DDRBRC2", "EBIU_DDRBRC3", "EBIU_DDRBRC4", "EBIU_DDRBRC5",
52  "EBIU_DDRBRC6", "EBIU_DDRBRC7", "EBIU_DDRBWC0", "EBIU_DDRBWC1"
53  "EBIU_DDRBWC2", "EBIU_DDRBWC3", "EBIU_DDRBWC4", "EBIU_DDRBWC5",
54  "EBIU_DDRBWC6", "EBIU_DDRBWC7", "EBIU_DDRACCT", "EBIU_DDRTACT",
55  "EBIU_ARCT", "EBIU_DDRGC0", "EBIU_DDRGC1", "EBIU_DDRGC2", "EBIU_DDRGC3",
56  "EBIU_DDRMCEN", "EBIU_DDRMCCL",
57};
58#define mmr_name(off) mmr_names[(off) / 4]
59
60static unsigned
61bfin_ebiu_ddrc_io_write_buffer (struct hw *me, const void *source,
62			       int space, address_word addr, unsigned nr_bytes)
63{
64  struct bfin_ebiu_ddrc *ddrc = hw_data (me);
65  bu32 mmr_off;
66  bu32 value;
67  bu16 *value16p;
68  bu32 *value32p;
69  void *valuep;
70
71  /* Invalid access mode is higher priority than missing register.  */
72  if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
73    return 0;
74
75  if (nr_bytes == 4)
76    value = dv_load_4 (source);
77  else
78    value = dv_load_2 (source);
79
80  mmr_off = addr - ddrc->base;
81  valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off);
82  value16p = valuep;
83  value32p = valuep;
84
85  HW_TRACE_WRITE ();
86
87  switch (mmr_off)
88    {
89    case mmr_offset(errmst):
90    case mmr_offset(rstctl):
91      if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
92	return 0;
93      *value16p = value;
94      break;
95    default:
96      if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
97	return 0;
98      *value32p = value;
99      break;
100    }
101
102  return nr_bytes;
103}
104
105static unsigned
106bfin_ebiu_ddrc_io_read_buffer (struct hw *me, void *dest,
107			      int space, address_word addr, unsigned nr_bytes)
108{
109  struct bfin_ebiu_ddrc *ddrc = hw_data (me);
110  bu32 mmr_off;
111  bu32 *value32p;
112  bu16 *value16p;
113  void *valuep;
114
115  /* Invalid access mode is higher priority than missing register.  */
116  if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
117    return 0;
118
119  mmr_off = addr - ddrc->base;
120  valuep = (void *)((unsigned long)ddrc + mmr_base() + mmr_off);
121  value16p = valuep;
122  value32p = valuep;
123
124  HW_TRACE_READ ();
125
126  switch (mmr_off)
127    {
128    case mmr_offset(errmst):
129    case mmr_offset(rstctl):
130      if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
131	return 0;
132      dv_store_2 (dest, *value16p);
133      break;
134    default:
135      if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
136	return 0;
137      dv_store_4 (dest, *value32p);
138      break;
139    }
140
141  return nr_bytes;
142}
143
144static void
145attach_bfin_ebiu_ddrc_regs (struct hw *me, struct bfin_ebiu_ddrc *ddrc)
146{
147  address_word attach_address;
148  int attach_space;
149  unsigned attach_size;
150  reg_property_spec reg;
151
152  if (hw_find_property (me, "reg") == NULL)
153    hw_abort (me, "Missing \"reg\" property");
154
155  if (!hw_find_reg_array_property (me, "reg", 0, &reg))
156    hw_abort (me, "\"reg\" property must contain three addr/size entries");
157
158  hw_unit_address_to_attach_address (hw_parent (me),
159				     &reg.address,
160				     &attach_space, &attach_address, me);
161  hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
162
163  if (attach_size != BFIN_MMR_EBIU_DDRC_SIZE)
164    hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EBIU_DDRC_SIZE);
165
166  hw_attach_address (hw_parent (me),
167		     0, attach_space, attach_address, attach_size, me);
168
169  ddrc->base = attach_address;
170}
171
172static void
173bfin_ebiu_ddrc_finish (struct hw *me)
174{
175  struct bfin_ebiu_ddrc *ddrc;
176
177  ddrc = HW_ZALLOC (me, struct bfin_ebiu_ddrc);
178
179  set_hw_data (me, ddrc);
180  set_hw_io_read_buffer (me, bfin_ebiu_ddrc_io_read_buffer);
181  set_hw_io_write_buffer (me, bfin_ebiu_ddrc_io_write_buffer);
182
183  attach_bfin_ebiu_ddrc_regs (me, ddrc);
184
185  /* Initialize the DDRC.  */
186  ddrc->ddrctl0 = 0x098E8411;
187  ddrc->ddrctl1 = 0x10026223;
188  ddrc->ddrctl2 = 0x00000021;
189  ddrc->ddrctl3 = 0x00000003; /* XXX: MDDR is 0x20 ...  */
190  ddrc->ddrque = 0x00001115;
191  ddrc->rstctl = 0x0002;
192}
193
194const struct hw_descriptor dv_bfin_ebiu_ddrc_descriptor[] =
195{
196  {"bfin_ebiu_ddrc", bfin_ebiu_ddrc_finish,},
197  {NULL, NULL},
198};
199