1/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2/* CPU data for iq2000. 3 4THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6Copyright (C) 1996-2020 Free Software Foundation, Inc. 7 8This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24*/ 25 26#include "sysdep.h" 27#include <stdio.h> 28#include <stdarg.h> 29#include "ansidecl.h" 30#include "bfd.h" 31#include "symcat.h" 32#include "iq2000-desc.h" 33#include "iq2000-opc.h" 34#include "opintl.h" 35#include "libiberty.h" 36#include "xregex.h" 37 38/* Attributes. */ 39 40static const CGEN_ATTR_ENTRY bool_attr[] = 41{ 42 { "#f", 0 }, 43 { "#t", 1 }, 44 { 0, 0 } 45}; 46 47static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED = 48{ 49 { "base", MACH_BASE }, 50 { "iq2000", MACH_IQ2000 }, 51 { "iq10", MACH_IQ10 }, 52 { "max", MACH_MAX }, 53 { 0, 0 } 54}; 55 56static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED = 57{ 58 { "iq2000", ISA_IQ2000 }, 59 { "max", ISA_MAX }, 60 { 0, 0 } 61}; 62 63const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] = 64{ 65 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 66 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 67 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 68 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 69 { "RESERVED", &bool_attr[0], &bool_attr[0] }, 70 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 71 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 72 { 0, 0, 0 } 73}; 74 75const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] = 76{ 77 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 78 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 79 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] }, 80 { "PC", &bool_attr[0], &bool_attr[0] }, 81 { "PROFILE", &bool_attr[0], &bool_attr[0] }, 82 { 0, 0, 0 } 83}; 84 85const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] = 86{ 87 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 88 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 89 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] }, 90 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] }, 91 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] }, 92 { "SIGNED", &bool_attr[0], &bool_attr[0] }, 93 { "NEGATIVE", &bool_attr[0], &bool_attr[0] }, 94 { "RELAX", &bool_attr[0], &bool_attr[0] }, 95 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] }, 96 { 0, 0, 0 } 97}; 98 99const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] = 100{ 101 { "MACH", & MACH_attr[0], & MACH_attr[0] }, 102 { "ALIAS", &bool_attr[0], &bool_attr[0] }, 103 { "VIRTUAL", &bool_attr[0], &bool_attr[0] }, 104 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] }, 105 { "COND-CTI", &bool_attr[0], &bool_attr[0] }, 106 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] }, 107 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] }, 108 { "RELAXABLE", &bool_attr[0], &bool_attr[0] }, 109 { "RELAXED", &bool_attr[0], &bool_attr[0] }, 110 { "NO-DIS", &bool_attr[0], &bool_attr[0] }, 111 { "PBB", &bool_attr[0], &bool_attr[0] }, 112 { "YIELD-INSN", &bool_attr[0], &bool_attr[0] }, 113 { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] }, 114 { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] }, 115 { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] }, 116 { "USES-RD", &bool_attr[0], &bool_attr[0] }, 117 { "USES-RS", &bool_attr[0], &bool_attr[0] }, 118 { "USES-RT", &bool_attr[0], &bool_attr[0] }, 119 { "USES-R31", &bool_attr[0], &bool_attr[0] }, 120 { 0, 0, 0 } 121}; 122 123/* Instruction set variants. */ 124 125static const CGEN_ISA iq2000_cgen_isa_table[] = { 126 { "iq2000", 32, 32, 32, 32 }, 127 { 0, 0, 0, 0, 0 } 128}; 129 130/* Machine variants. */ 131 132static const CGEN_MACH iq2000_cgen_mach_table[] = { 133 { "iq2000", "iq2000", MACH_IQ2000, 0 }, 134 { "iq10", "iq10", MACH_IQ10, 0 }, 135 { 0, 0, 0, 0 } 136}; 137 138static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] = 139{ 140 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 }, 141 { "%0", 0, {0, {{{0, 0}}}}, 0, 0 }, 142 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 }, 143 { "%1", 1, {0, {{{0, 0}}}}, 0, 0 }, 144 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 }, 145 { "%2", 2, {0, {{{0, 0}}}}, 0, 0 }, 146 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 }, 147 { "%3", 3, {0, {{{0, 0}}}}, 0, 0 }, 148 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 }, 149 { "%4", 4, {0, {{{0, 0}}}}, 0, 0 }, 150 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 }, 151 { "%5", 5, {0, {{{0, 0}}}}, 0, 0 }, 152 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 }, 153 { "%6", 6, {0, {{{0, 0}}}}, 0, 0 }, 154 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 }, 155 { "%7", 7, {0, {{{0, 0}}}}, 0, 0 }, 156 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 }, 157 { "%8", 8, {0, {{{0, 0}}}}, 0, 0 }, 158 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 }, 159 { "%9", 9, {0, {{{0, 0}}}}, 0, 0 }, 160 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 }, 161 { "%10", 10, {0, {{{0, 0}}}}, 0, 0 }, 162 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 }, 163 { "%11", 11, {0, {{{0, 0}}}}, 0, 0 }, 164 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 }, 165 { "%12", 12, {0, {{{0, 0}}}}, 0, 0 }, 166 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 }, 167 { "%13", 13, {0, {{{0, 0}}}}, 0, 0 }, 168 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 }, 169 { "%14", 14, {0, {{{0, 0}}}}, 0, 0 }, 170 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }, 171 { "%15", 15, {0, {{{0, 0}}}}, 0, 0 }, 172 { "r16", 16, {0, {{{0, 0}}}}, 0, 0 }, 173 { "%16", 16, {0, {{{0, 0}}}}, 0, 0 }, 174 { "r17", 17, {0, {{{0, 0}}}}, 0, 0 }, 175 { "%17", 17, {0, {{{0, 0}}}}, 0, 0 }, 176 { "r18", 18, {0, {{{0, 0}}}}, 0, 0 }, 177 { "%18", 18, {0, {{{0, 0}}}}, 0, 0 }, 178 { "r19", 19, {0, {{{0, 0}}}}, 0, 0 }, 179 { "%19", 19, {0, {{{0, 0}}}}, 0, 0 }, 180 { "r20", 20, {0, {{{0, 0}}}}, 0, 0 }, 181 { "%20", 20, {0, {{{0, 0}}}}, 0, 0 }, 182 { "r21", 21, {0, {{{0, 0}}}}, 0, 0 }, 183 { "%21", 21, {0, {{{0, 0}}}}, 0, 0 }, 184 { "r22", 22, {0, {{{0, 0}}}}, 0, 0 }, 185 { "%22", 22, {0, {{{0, 0}}}}, 0, 0 }, 186 { "r23", 23, {0, {{{0, 0}}}}, 0, 0 }, 187 { "%23", 23, {0, {{{0, 0}}}}, 0, 0 }, 188 { "r24", 24, {0, {{{0, 0}}}}, 0, 0 }, 189 { "%24", 24, {0, {{{0, 0}}}}, 0, 0 }, 190 { "r25", 25, {0, {{{0, 0}}}}, 0, 0 }, 191 { "%25", 25, {0, {{{0, 0}}}}, 0, 0 }, 192 { "r26", 26, {0, {{{0, 0}}}}, 0, 0 }, 193 { "%26", 26, {0, {{{0, 0}}}}, 0, 0 }, 194 { "r27", 27, {0, {{{0, 0}}}}, 0, 0 }, 195 { "%27", 27, {0, {{{0, 0}}}}, 0, 0 }, 196 { "r28", 28, {0, {{{0, 0}}}}, 0, 0 }, 197 { "%28", 28, {0, {{{0, 0}}}}, 0, 0 }, 198 { "r29", 29, {0, {{{0, 0}}}}, 0, 0 }, 199 { "%29", 29, {0, {{{0, 0}}}}, 0, 0 }, 200 { "r30", 30, {0, {{{0, 0}}}}, 0, 0 }, 201 { "%30", 30, {0, {{{0, 0}}}}, 0, 0 }, 202 { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }, 203 { "%31", 31, {0, {{{0, 0}}}}, 0, 0 } 204}; 205 206CGEN_KEYWORD iq2000_cgen_opval_gr_names = 207{ 208 & iq2000_cgen_opval_gr_names_entries[0], 209 64, 210 0, 0, 0, 0, "" 211}; 212 213 214/* The hardware table. */ 215 216#define A(a) (1 << CGEN_HW_##a) 217 218const CGEN_HW_ENTRY iq2000_cgen_hw_table[] = 219{ 220 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 221 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 222 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 223 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 224 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 225 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } }, 226 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 227 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 228}; 229 230#undef A 231 232 233/* The instruction field table. */ 234 235#define A(a) (1 << CGEN_IFLD_##a) 236 237const CGEN_IFLD iq2000_cgen_ifld_table[] = 238{ 239 { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 240 { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 241 { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 242 { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 243 { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 244 { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 245 { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 246 { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 247 { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 248 { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 249 { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 250 { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 251 { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 252 { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 253 { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 254 { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 255 { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 256 { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 257 { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 258 { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 259 { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 260 { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 261 { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 262 { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 263 { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 264 { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 265 { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 266 { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 267 { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 268 { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 269 { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 270 { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 271 { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 272 { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 273 { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 274 { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 275 { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 276 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } } 277}; 278 279#undef A 280 281 282 283/* multi ifield declarations */ 284 285const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD []; 286const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD []; 287const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD []; 288 289 290/* multi ifield definitions */ 291 292const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] = 293{ 294 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, 295 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 296 { 0, { (const PTR) 0 } } 297}; 298const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] = 299{ 300 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, 301 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 302 { 0, { (const PTR) 0 } } 303}; 304const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] = 305{ 306 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 307 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 308 { 0, { (const PTR) 0 } } 309}; 310 311/* The operand table. */ 312 313#define A(a) (1 << CGEN_OPERAND_##a) 314#define OPERAND(op) IQ2000_OPERAND_##op 315 316const CGEN_OPERAND iq2000_cgen_operand_table[] = 317{ 318/* pc: program counter */ 319 { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0, 320 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_NIL] } }, 321 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } }, 322/* rs: register Rs */ 323 { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5, 324 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 325 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 326/* rt: register Rt */ 327 { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5, 328 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 329 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 330/* rd: register Rd */ 331 { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5, 332 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RD] } }, 333 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 334/* rd-rs: register Rd from Rs */ 335 { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10, 336 { 2, { (const PTR) &IQ2000_F_RD_RS_MULTI_IFIELD[0] } }, 337 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 338/* rd-rt: register Rd from Rt */ 339 { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10, 340 { 2, { (const PTR) &IQ2000_F_RD_RT_MULTI_IFIELD[0] } }, 341 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 342/* rt-rs: register Rt from Rs */ 343 { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10, 344 { 2, { (const PTR) &IQ2000_F_RT_RS_MULTI_IFIELD[0] } }, 345 { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } }, 346/* shamt: shift amount */ 347 { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5, 348 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_SHAMT] } }, 349 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 350/* imm: immediate */ 351 { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16, 352 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 353 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 354/* offset: pc-relative offset */ 355 { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16, 356 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_OFFSET] } }, 357 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 358/* baseoff: base register offset */ 359 { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16, 360 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 361 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 362/* jmptarg: jump target */ 363 { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16, 364 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARG] } }, 365 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 366/* mask: mask */ 367 { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4, 368 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASK] } }, 369 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 370/* maskq10: iq10 mask */ 371 { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5, 372 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKQ10] } }, 373 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 374/* maskl: mask left */ 375 { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5, 376 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_MASKL] } }, 377 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 378/* count: count */ 379 { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7, 380 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_COUNT] } }, 381 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 382/* _index: index */ 383 { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9, 384 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_INDEX] } }, 385 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 386/* execode: execcode */ 387 { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20, 388 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_EXCODE] } }, 389 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 390/* bytecount: byte count */ 391 { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8, 392 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_BYTECOUNT] } }, 393 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 394/* cam-y: cam global opn y */ 395 { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3, 396 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Y] } }, 397 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 398/* cam-z: cam global mask z */ 399 { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3, 400 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CAM_Z] } }, 401 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 402/* cm-3func: CM 3 bit fn field */ 403 { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3, 404 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3FUNC] } }, 405 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 406/* cm-4func: CM 4 bit fn field */ 407 { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4, 408 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4FUNC] } }, 409 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 410/* cm-3z: CM 3 bit Z field */ 411 { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2, 412 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_3Z] } }, 413 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 414/* cm-4z: CM 4 bit Z field */ 415 { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3, 416 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_CM_4Z] } }, 417 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 418/* base: base register */ 419 { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5, 420 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 421 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 422/* maskr: mask right */ 423 { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5, 424 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RS] } }, 425 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 426/* bitnum: bit number */ 427 { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5, 428 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_RT] } }, 429 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 430/* hi16: high 16 bit immediate */ 431 { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16, 432 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 433 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 434/* lo16: 16 bit signed immediate, for low */ 435 { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16, 436 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 437 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 438/* mlo16: negated 16 bit signed immediate */ 439 { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16, 440 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_IMM] } }, 441 { 0, { { { (1<<MACH_BASE), 0 } } } } }, 442/* jmptargq10: iq10 21-bit jump offset */ 443 { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21, 444 { 0, { (const PTR) &iq2000_cgen_ifld_table[IQ2000_F_JTARGQ10] } }, 445 { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } }, 446/* sentinel */ 447 { 0, 0, 0, 0, 0, 448 { 0, { (const PTR) 0 } }, 449 { 0, { { { (1<<MACH_BASE), 0 } } } } } 450}; 451 452#undef A 453 454 455/* The instruction table. */ 456 457#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 458#define A(a) (1 << CGEN_INSN_##a) 459 460static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] = 461{ 462 /* Special null first entry. 463 A `num' value of zero is thus invalid. 464 Also, the special `invalid' insn resides here. */ 465 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }, 466/* add ${rd-rs},$rt */ 467 { 468 -1, "add2", "add", 32, 469 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 470 }, 471/* add $rd,$rs,$rt */ 472 { 473 IQ2000_INSN_ADD, "add", "add", 32, 474 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 475 }, 476/* addi ${rt-rs},$lo16 */ 477 { 478 -1, "addi2", "addi", 32, 479 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 480 }, 481/* addi $rt,$rs,$lo16 */ 482 { 483 IQ2000_INSN_ADDI, "addi", "addi", 32, 484 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 485 }, 486/* addiu ${rt-rs},$lo16 */ 487 { 488 -1, "addiu2", "addiu", 32, 489 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 490 }, 491/* addiu $rt,$rs,$lo16 */ 492 { 493 IQ2000_INSN_ADDIU, "addiu", "addiu", 32, 494 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 495 }, 496/* addu ${rd-rs},$rt */ 497 { 498 -1, "addu2", "addu", 32, 499 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 500 }, 501/* addu $rd,$rs,$rt */ 502 { 503 IQ2000_INSN_ADDU, "addu", "addu", 32, 504 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 505 }, 506/* ado16 ${rd-rs},$rt */ 507 { 508 -1, "ado162", "ado16", 32, 509 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 510 }, 511/* ado16 $rd,$rs,$rt */ 512 { 513 IQ2000_INSN_ADO16, "ado16", "ado16", 32, 514 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 515 }, 516/* and ${rd-rs},$rt */ 517 { 518 -1, "and2", "and", 32, 519 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 520 }, 521/* and $rd,$rs,$rt */ 522 { 523 IQ2000_INSN_AND, "and", "and", 32, 524 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 525 }, 526/* andi ${rt-rs},$lo16 */ 527 { 528 -1, "andi2", "andi", 32, 529 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 530 }, 531/* andi $rt,$rs,$lo16 */ 532 { 533 IQ2000_INSN_ANDI, "andi", "andi", 32, 534 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 535 }, 536/* andoi ${rt-rs},$lo16 */ 537 { 538 -1, "andoi2", "andoi", 32, 539 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 540 }, 541/* andoi $rt,$rs,$lo16 */ 542 { 543 IQ2000_INSN_ANDOI, "andoi", "andoi", 32, 544 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 545 }, 546/* nor ${rd-rs},$rt */ 547 { 548 -1, "nor2", "nor", 32, 549 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 550 }, 551/* nor $rd,$rs,$rt */ 552 { 553 IQ2000_INSN_NOR, "nor", "nor", 32, 554 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 555 }, 556/* or ${rd-rs},$rt */ 557 { 558 -1, "or2", "or", 32, 559 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 560 }, 561/* or $rd,$rs,$rt */ 562 { 563 IQ2000_INSN_OR, "or", "or", 32, 564 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 565 }, 566/* ori ${rt-rs},$lo16 */ 567 { 568 -1, "ori2", "ori", 32, 569 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 570 }, 571/* ori $rt,$rs,$lo16 */ 572 { 573 IQ2000_INSN_ORI, "ori", "ori", 32, 574 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 575 }, 576/* ram $rd,$rt,$shamt,$maskl,$maskr */ 577 { 578 IQ2000_INSN_RAM, "ram", "ram", 32, 579 { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 580 }, 581/* sll $rd,$rt,$shamt */ 582 { 583 IQ2000_INSN_SLL, "sll", "sll", 32, 584 { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 585 }, 586/* sllv ${rd-rt},$rs */ 587 { 588 -1, "sllv2", "sllv", 32, 589 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 590 }, 591/* sllv $rd,$rt,$rs */ 592 { 593 IQ2000_INSN_SLLV, "sllv", "sllv", 32, 594 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 595 }, 596/* slmv ${rd-rt},$rs,$shamt */ 597 { 598 -1, "slmv2", "slmv", 32, 599 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 600 }, 601/* slmv $rd,$rt,$rs,$shamt */ 602 { 603 IQ2000_INSN_SLMV, "slmv", "slmv", 32, 604 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 605 }, 606/* slt ${rd-rs},$rt */ 607 { 608 -1, "slt2", "slt", 32, 609 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 610 }, 611/* slt $rd,$rs,$rt */ 612 { 613 IQ2000_INSN_SLT, "slt", "slt", 32, 614 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 615 }, 616/* slti ${rt-rs},$imm */ 617 { 618 -1, "slti2", "slti", 32, 619 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 620 }, 621/* slti $rt,$rs,$imm */ 622 { 623 IQ2000_INSN_SLTI, "slti", "slti", 32, 624 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 625 }, 626/* sltiu ${rt-rs},$imm */ 627 { 628 -1, "sltiu2", "sltiu", 32, 629 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 630 }, 631/* sltiu $rt,$rs,$imm */ 632 { 633 IQ2000_INSN_SLTIU, "sltiu", "sltiu", 32, 634 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 635 }, 636/* sltu ${rd-rs},$rt */ 637 { 638 -1, "sltu2", "sltu", 32, 639 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 640 }, 641/* sltu $rd,$rs,$rt */ 642 { 643 IQ2000_INSN_SLTU, "sltu", "sltu", 32, 644 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 645 }, 646/* sra ${rd-rt},$shamt */ 647 { 648 -1, "sra2", "sra", 32, 649 { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 650 }, 651/* sra $rd,$rt,$shamt */ 652 { 653 IQ2000_INSN_SRA, "sra", "sra", 32, 654 { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 655 }, 656/* srav ${rd-rt},$rs */ 657 { 658 -1, "srav2", "srav", 32, 659 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 660 }, 661/* srav $rd,$rt,$rs */ 662 { 663 IQ2000_INSN_SRAV, "srav", "srav", 32, 664 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 665 }, 666/* srl $rd,$rt,$shamt */ 667 { 668 IQ2000_INSN_SRL, "srl", "srl", 32, 669 { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 670 }, 671/* srlv ${rd-rt},$rs */ 672 { 673 -1, "srlv2", "srlv", 32, 674 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 675 }, 676/* srlv $rd,$rt,$rs */ 677 { 678 IQ2000_INSN_SRLV, "srlv", "srlv", 32, 679 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 680 }, 681/* srmv ${rd-rt},$rs,$shamt */ 682 { 683 -1, "srmv2", "srmv", 32, 684 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 685 }, 686/* srmv $rd,$rt,$rs,$shamt */ 687 { 688 IQ2000_INSN_SRMV, "srmv", "srmv", 32, 689 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 690 }, 691/* sub ${rd-rs},$rt */ 692 { 693 -1, "sub2", "sub", 32, 694 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 695 }, 696/* sub $rd,$rs,$rt */ 697 { 698 IQ2000_INSN_SUB, "sub", "sub", 32, 699 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 700 }, 701/* subu ${rd-rs},$rt */ 702 { 703 -1, "subu2", "subu", 32, 704 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 705 }, 706/* subu $rd,$rs,$rt */ 707 { 708 IQ2000_INSN_SUBU, "subu", "subu", 32, 709 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 710 }, 711/* xor ${rd-rs},$rt */ 712 { 713 -1, "xor2", "xor", 32, 714 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 715 }, 716/* xor $rd,$rs,$rt */ 717 { 718 IQ2000_INSN_XOR, "xor", "xor", 32, 719 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_BASE), 0 } } } } 720 }, 721/* xori ${rt-rs},$lo16 */ 722 { 723 -1, "xori2", "xori", 32, 724 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } } 725 }, 726/* xori $rt,$rs,$lo16 */ 727 { 728 IQ2000_INSN_XORI, "xori", "xori", 32, 729 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 730 }, 731/* bbi $rs($bitnum),$offset */ 732 { 733 IQ2000_INSN_BBI, "bbi", "bbi", 32, 734 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 735 }, 736/* bbin $rs($bitnum),$offset */ 737 { 738 IQ2000_INSN_BBIN, "bbin", "bbin", 32, 739 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 740 }, 741/* bbv $rs,$rt,$offset */ 742 { 743 IQ2000_INSN_BBV, "bbv", "bbv", 32, 744 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 745 }, 746/* bbvn $rs,$rt,$offset */ 747 { 748 IQ2000_INSN_BBVN, "bbvn", "bbvn", 32, 749 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 750 }, 751/* beq $rs,$rt,$offset */ 752 { 753 IQ2000_INSN_BEQ, "beq", "beq", 32, 754 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 755 }, 756/* beql $rs,$rt,$offset */ 757 { 758 IQ2000_INSN_BEQL, "beql", "beql", 32, 759 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 760 }, 761/* bgez $rs,$offset */ 762 { 763 IQ2000_INSN_BGEZ, "bgez", "bgez", 32, 764 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 765 }, 766/* bgezal $rs,$offset */ 767 { 768 IQ2000_INSN_BGEZAL, "bgezal", "bgezal", 32, 769 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 770 }, 771/* bgezall $rs,$offset */ 772 { 773 IQ2000_INSN_BGEZALL, "bgezall", "bgezall", 32, 774 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 775 }, 776/* bgezl $rs,$offset */ 777 { 778 IQ2000_INSN_BGEZL, "bgezl", "bgezl", 32, 779 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 780 }, 781/* bltz $rs,$offset */ 782 { 783 IQ2000_INSN_BLTZ, "bltz", "bltz", 32, 784 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 785 }, 786/* bltzl $rs,$offset */ 787 { 788 IQ2000_INSN_BLTZL, "bltzl", "bltzl", 32, 789 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 790 }, 791/* bltzal $rs,$offset */ 792 { 793 IQ2000_INSN_BLTZAL, "bltzal", "bltzal", 32, 794 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 795 }, 796/* bltzall $rs,$offset */ 797 { 798 IQ2000_INSN_BLTZALL, "bltzall", "bltzall", 32, 799 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 800 }, 801/* bmb0 $rs,$rt,$offset */ 802 { 803 IQ2000_INSN_BMB0, "bmb0", "bmb0", 32, 804 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 805 }, 806/* bmb1 $rs,$rt,$offset */ 807 { 808 IQ2000_INSN_BMB1, "bmb1", "bmb1", 32, 809 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 810 }, 811/* bmb2 $rs,$rt,$offset */ 812 { 813 IQ2000_INSN_BMB2, "bmb2", "bmb2", 32, 814 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 815 }, 816/* bmb3 $rs,$rt,$offset */ 817 { 818 IQ2000_INSN_BMB3, "bmb3", "bmb3", 32, 819 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 820 }, 821/* bne $rs,$rt,$offset */ 822 { 823 IQ2000_INSN_BNE, "bne", "bne", 32, 824 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 825 }, 826/* bnel $rs,$rt,$offset */ 827 { 828 IQ2000_INSN_BNEL, "bnel", "bnel", 32, 829 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 830 }, 831/* jalr $rd,$rs */ 832 { 833 IQ2000_INSN_JALR, "jalr", "jalr", 32, 834 { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 835 }, 836/* jr $rs */ 837 { 838 IQ2000_INSN_JR, "jr", "jr", 32, 839 { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } } 840 }, 841/* lb $rt,$lo16($base) */ 842 { 843 IQ2000_INSN_LB, "lb", "lb", 32, 844 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } 845 }, 846/* lbu $rt,$lo16($base) */ 847 { 848 IQ2000_INSN_LBU, "lbu", "lbu", 32, 849 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } 850 }, 851/* lh $rt,$lo16($base) */ 852 { 853 IQ2000_INSN_LH, "lh", "lh", 32, 854 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } 855 }, 856/* lhu $rt,$lo16($base) */ 857 { 858 IQ2000_INSN_LHU, "lhu", "lhu", 32, 859 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } 860 }, 861/* lui $rt,$hi16 */ 862 { 863 IQ2000_INSN_LUI, "lui", "lui", 32, 864 { 0|A(USES_RT), { { { (1<<MACH_BASE), 0 } } } } 865 }, 866/* lw $rt,$lo16($base) */ 867 { 868 IQ2000_INSN_LW, "lw", "lw", 32, 869 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } } 870 }, 871/* sb $rt,$lo16($base) */ 872 { 873 IQ2000_INSN_SB, "sb", "sb", 32, 874 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 875 }, 876/* sh $rt,$lo16($base) */ 877 { 878 IQ2000_INSN_SH, "sh", "sh", 32, 879 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 880 }, 881/* sw $rt,$lo16($base) */ 882 { 883 IQ2000_INSN_SW, "sw", "sw", 32, 884 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_BASE), 0 } } } } 885 }, 886/* break */ 887 { 888 IQ2000_INSN_BREAK, "break", "break", 32, 889 { 0, { { { (1<<MACH_BASE), 0 } } } } 890 }, 891/* syscall */ 892 { 893 IQ2000_INSN_SYSCALL, "syscall", "syscall", 32, 894 { 0|A(YIELD_INSN), { { { (1<<MACH_BASE), 0 } } } } 895 }, 896/* andoui $rt,$rs,$hi16 */ 897 { 898 IQ2000_INSN_ANDOUI, "andoui", "andoui", 32, 899 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } } 900 }, 901/* andoui ${rt-rs},$hi16 */ 902 { 903 -1, "andoui2", "andoui", 32, 904 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } } 905 }, 906/* orui ${rt-rs},$hi16 */ 907 { 908 -1, "orui2", "orui", 32, 909 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } } 910 }, 911/* orui $rt,$rs,$hi16 */ 912 { 913 IQ2000_INSN_ORUI, "orui", "orui", 32, 914 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ2000), 0 } } } } 915 }, 916/* bgtz $rs,$offset */ 917 { 918 IQ2000_INSN_BGTZ, "bgtz", "bgtz", 32, 919 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 920 }, 921/* bgtzl $rs,$offset */ 922 { 923 IQ2000_INSN_BGTZL, "bgtzl", "bgtzl", 32, 924 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 925 }, 926/* blez $rs,$offset */ 927 { 928 IQ2000_INSN_BLEZ, "blez", "blez", 32, 929 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 930 }, 931/* blezl $rs,$offset */ 932 { 933 IQ2000_INSN_BLEZL, "blezl", "blezl", 32, 934 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 935 }, 936/* mrgb $rd,$rs,$rt,$mask */ 937 { 938 IQ2000_INSN_MRGB, "mrgb", "mrgb", 32, 939 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 940 }, 941/* mrgb ${rd-rs},$rt,$mask */ 942 { 943 -1, "mrgb2", "mrgb", 32, 944 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } } 945 }, 946/* bctxt $rs,$offset */ 947 { 948 IQ2000_INSN_BCTXT, "bctxt", "bctxt", 32, 949 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 950 }, 951/* bc0f $offset */ 952 { 953 IQ2000_INSN_BC0F, "bc0f", "bc0f", 32, 954 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 955 }, 956/* bc0fl $offset */ 957 { 958 IQ2000_INSN_BC0FL, "bc0fl", "bc0fl", 32, 959 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 960 }, 961/* bc3f $offset */ 962 { 963 IQ2000_INSN_BC3F, "bc3f", "bc3f", 32, 964 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 965 }, 966/* bc3fl $offset */ 967 { 968 IQ2000_INSN_BC3FL, "bc3fl", "bc3fl", 32, 969 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 970 }, 971/* bc0t $offset */ 972 { 973 IQ2000_INSN_BC0T, "bc0t", "bc0t", 32, 974 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 975 }, 976/* bc0tl $offset */ 977 { 978 IQ2000_INSN_BC0TL, "bc0tl", "bc0tl", 32, 979 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 980 }, 981/* bc3t $offset */ 982 { 983 IQ2000_INSN_BC3T, "bc3t", "bc3t", 32, 984 { 0|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 985 }, 986/* bc3tl $offset */ 987 { 988 IQ2000_INSN_BC3TL, "bc3tl", "bc3tl", 32, 989 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 990 }, 991/* cfc0 $rt,$rd */ 992 { 993 IQ2000_INSN_CFC0, "cfc0", "cfc0", 32, 994 { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 995 }, 996/* cfc1 $rt,$rd */ 997 { 998 IQ2000_INSN_CFC1, "cfc1", "cfc1", 32, 999 { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1000 }, 1001/* cfc2 $rt,$rd */ 1002 { 1003 IQ2000_INSN_CFC2, "cfc2", "cfc2", 32, 1004 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1005 }, 1006/* cfc3 $rt,$rd */ 1007 { 1008 IQ2000_INSN_CFC3, "cfc3", "cfc3", 32, 1009 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1010 }, 1011/* chkhdr $rd,$rt */ 1012 { 1013 IQ2000_INSN_CHKHDR, "chkhdr", "chkhdr", 32, 1014 { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1015 }, 1016/* ctc0 $rt,$rd */ 1017 { 1018 IQ2000_INSN_CTC0, "ctc0", "ctc0", 32, 1019 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1020 }, 1021/* ctc1 $rt,$rd */ 1022 { 1023 IQ2000_INSN_CTC1, "ctc1", "ctc1", 32, 1024 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1025 }, 1026/* ctc2 $rt,$rd */ 1027 { 1028 IQ2000_INSN_CTC2, "ctc2", "ctc2", 32, 1029 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1030 }, 1031/* ctc3 $rt,$rd */ 1032 { 1033 IQ2000_INSN_CTC3, "ctc3", "ctc3", 32, 1034 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1035 }, 1036/* jcr $rs */ 1037 { 1038 IQ2000_INSN_JCR, "jcr", "jcr", 32, 1039 { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 1040 }, 1041/* luc32 $rt,$rd */ 1042 { 1043 IQ2000_INSN_LUC32, "luc32", "luc32", 32, 1044 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1045 }, 1046/* luc32l $rt,$rd */ 1047 { 1048 IQ2000_INSN_LUC32L, "luc32l", "luc32l", 32, 1049 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1050 }, 1051/* luc64 $rt,$rd */ 1052 { 1053 IQ2000_INSN_LUC64, "luc64", "luc64", 32, 1054 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1055 }, 1056/* luc64l $rt,$rd */ 1057 { 1058 IQ2000_INSN_LUC64L, "luc64l", "luc64l", 32, 1059 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1060 }, 1061/* luk $rt,$rd */ 1062 { 1063 IQ2000_INSN_LUK, "luk", "luk", 32, 1064 { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1065 }, 1066/* lulck $rt */ 1067 { 1068 IQ2000_INSN_LULCK, "lulck", "lulck", 32, 1069 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1070 }, 1071/* lum32 $rt,$rd */ 1072 { 1073 IQ2000_INSN_LUM32, "lum32", "lum32", 32, 1074 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1075 }, 1076/* lum32l $rt,$rd */ 1077 { 1078 IQ2000_INSN_LUM32L, "lum32l", "lum32l", 32, 1079 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1080 }, 1081/* lum64 $rt,$rd */ 1082 { 1083 IQ2000_INSN_LUM64, "lum64", "lum64", 32, 1084 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1085 }, 1086/* lum64l $rt,$rd */ 1087 { 1088 IQ2000_INSN_LUM64L, "lum64l", "lum64l", 32, 1089 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1090 }, 1091/* lur $rt,$rd */ 1092 { 1093 IQ2000_INSN_LUR, "lur", "lur", 32, 1094 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1095 }, 1096/* lurl $rt,$rd */ 1097 { 1098 IQ2000_INSN_LURL, "lurl", "lurl", 32, 1099 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1100 }, 1101/* luulck $rt */ 1102 { 1103 IQ2000_INSN_LUULCK, "luulck", "luulck", 32, 1104 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1105 }, 1106/* mfc0 $rt,$rd */ 1107 { 1108 IQ2000_INSN_MFC0, "mfc0", "mfc0", 32, 1109 { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1110 }, 1111/* mfc1 $rt,$rd */ 1112 { 1113 IQ2000_INSN_MFC1, "mfc1", "mfc1", 32, 1114 { 0|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1115 }, 1116/* mfc2 $rt,$rd */ 1117 { 1118 IQ2000_INSN_MFC2, "mfc2", "mfc2", 32, 1119 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1120 }, 1121/* mfc3 $rt,$rd */ 1122 { 1123 IQ2000_INSN_MFC3, "mfc3", "mfc3", 32, 1124 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { { { (1<<MACH_IQ2000), 0 } } } } 1125 }, 1126/* mtc0 $rt,$rd */ 1127 { 1128 IQ2000_INSN_MTC0, "mtc0", "mtc0", 32, 1129 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1130 }, 1131/* mtc1 $rt,$rd */ 1132 { 1133 IQ2000_INSN_MTC1, "mtc1", "mtc1", 32, 1134 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1135 }, 1136/* mtc2 $rt,$rd */ 1137 { 1138 IQ2000_INSN_MTC2, "mtc2", "mtc2", 32, 1139 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1140 }, 1141/* mtc3 $rt,$rd */ 1142 { 1143 IQ2000_INSN_MTC3, "mtc3", "mtc3", 32, 1144 { 0|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1145 }, 1146/* pkrl $rd,$rt */ 1147 { 1148 IQ2000_INSN_PKRL, "pkrl", "pkrl", 32, 1149 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1150 }, 1151/* pkrlr1 $rt,$_index,$count */ 1152 { 1153 IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32, 1154 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1155 }, 1156/* pkrlr30 $rt,$_index,$count */ 1157 { 1158 IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32, 1159 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1160 }, 1161/* rb $rd,$rt */ 1162 { 1163 IQ2000_INSN_RB, "rb", "rb", 32, 1164 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1165 }, 1166/* rbr1 $rt,$_index,$count */ 1167 { 1168 IQ2000_INSN_RBR1, "rbr1", "rbr1", 32, 1169 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1170 }, 1171/* rbr30 $rt,$_index,$count */ 1172 { 1173 IQ2000_INSN_RBR30, "rbr30", "rbr30", 32, 1174 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1175 }, 1176/* rfe */ 1177 { 1178 IQ2000_INSN_RFE, "rfe", "rfe", 32, 1179 { 0, { { { (1<<MACH_IQ2000), 0 } } } } 1180 }, 1181/* rx $rd,$rt */ 1182 { 1183 IQ2000_INSN_RX, "rx", "rx", 32, 1184 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1185 }, 1186/* rxr1 $rt,$_index,$count */ 1187 { 1188 IQ2000_INSN_RXR1, "rxr1", "rxr1", 32, 1189 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1190 }, 1191/* rxr30 $rt,$_index,$count */ 1192 { 1193 IQ2000_INSN_RXR30, "rxr30", "rxr30", 32, 1194 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1195 }, 1196/* sleep */ 1197 { 1198 IQ2000_INSN_SLEEP, "sleep", "sleep", 32, 1199 { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } } 1200 }, 1201/* srrd $rt */ 1202 { 1203 IQ2000_INSN_SRRD, "srrd", "srrd", 32, 1204 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1205 }, 1206/* srrdl $rt */ 1207 { 1208 IQ2000_INSN_SRRDL, "srrdl", "srrdl", 32, 1209 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1210 }, 1211/* srulck $rt */ 1212 { 1213 IQ2000_INSN_SRULCK, "srulck", "srulck", 32, 1214 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1215 }, 1216/* srwr $rt,$rd */ 1217 { 1218 IQ2000_INSN_SRWR, "srwr", "srwr", 32, 1219 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1220 }, 1221/* srwru $rt,$rd */ 1222 { 1223 IQ2000_INSN_SRWRU, "srwru", "srwru", 32, 1224 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1225 }, 1226/* trapqfl */ 1227 { 1228 IQ2000_INSN_TRAPQFL, "trapqfl", "trapqfl", 32, 1229 { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } } 1230 }, 1231/* trapqne */ 1232 { 1233 IQ2000_INSN_TRAPQNE, "trapqne", "trapqne", 32, 1234 { 0|A(YIELD_INSN), { { { (1<<MACH_IQ2000), 0 } } } } 1235 }, 1236/* traprel $rt */ 1237 { 1238 IQ2000_INSN_TRAPREL, "traprel", "traprel", 32, 1239 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1240 }, 1241/* wb $rd,$rt */ 1242 { 1243 IQ2000_INSN_WB, "wb", "wb", 32, 1244 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1245 }, 1246/* wbu $rd,$rt */ 1247 { 1248 IQ2000_INSN_WBU, "wbu", "wbu", 32, 1249 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1250 }, 1251/* wbr1 $rt,$_index,$count */ 1252 { 1253 IQ2000_INSN_WBR1, "wbr1", "wbr1", 32, 1254 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1255 }, 1256/* wbr1u $rt,$_index,$count */ 1257 { 1258 IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32, 1259 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1260 }, 1261/* wbr30 $rt,$_index,$count */ 1262 { 1263 IQ2000_INSN_WBR30, "wbr30", "wbr30", 32, 1264 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1265 }, 1266/* wbr30u $rt,$_index,$count */ 1267 { 1268 IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32, 1269 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1270 }, 1271/* wx $rd,$rt */ 1272 { 1273 IQ2000_INSN_WX, "wx", "wx", 32, 1274 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1275 }, 1276/* wxu $rd,$rt */ 1277 { 1278 IQ2000_INSN_WXU, "wxu", "wxu", 32, 1279 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ2000), 0 } } } } 1280 }, 1281/* wxr1 $rt,$_index,$count */ 1282 { 1283 IQ2000_INSN_WXR1, "wxr1", "wxr1", 32, 1284 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1285 }, 1286/* wxr1u $rt,$_index,$count */ 1287 { 1288 IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32, 1289 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1290 }, 1291/* wxr30 $rt,$_index,$count */ 1292 { 1293 IQ2000_INSN_WXR30, "wxr30", "wxr30", 32, 1294 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1295 }, 1296/* wxr30u $rt,$_index,$count */ 1297 { 1298 IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32, 1299 { 0|A(YIELD_INSN)|A(USES_RT), { { { (1<<MACH_IQ2000), 0 } } } } 1300 }, 1301/* ldw $rt,$lo16($base) */ 1302 { 1303 IQ2000_INSN_LDW, "ldw", "ldw", 32, 1304 { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } } 1305 }, 1306/* sdw $rt,$lo16($base) */ 1307 { 1308 IQ2000_INSN_SDW, "sdw", "sdw", 32, 1309 { 0|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ2000), 0 } } } } 1310 }, 1311/* j $jmptarg */ 1312 { 1313 IQ2000_INSN_J, "j", "j", 32, 1314 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 1315 }, 1316/* jal $jmptarg */ 1317 { 1318 IQ2000_INSN_JAL, "jal", "jal", 32, 1319 { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 1320 }, 1321/* bmb $rs,$rt,$offset */ 1322 { 1323 IQ2000_INSN_BMB, "bmb", "bmb", 32, 1324 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ2000), 0 } } } } 1325 }, 1326/* andoui $rt,$rs,$hi16 */ 1327 { 1328 IQ2000_INSN_ANDOUI_Q10, "andoui-q10", "andoui", 32, 1329 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1330 }, 1331/* andoui ${rt-rs},$hi16 */ 1332 { 1333 -1, "andoui2-q10", "andoui", 32, 1334 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } } 1335 }, 1336/* orui $rt,$rs,$hi16 */ 1337 { 1338 IQ2000_INSN_ORUI_Q10, "orui-q10", "orui", 32, 1339 { 0|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1340 }, 1341/* orui ${rt-rs},$hi16 */ 1342 { 1343 -1, "orui2-q10", "orui", 32, 1344 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } } 1345 }, 1346/* mrgb $rd,$rs,$rt,$maskq10 */ 1347 { 1348 IQ2000_INSN_MRGBQ10, "mrgbq10", "mrgb", 32, 1349 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1350 }, 1351/* mrgb ${rd-rs},$rt,$maskq10 */ 1352 { 1353 -1, "mrgbq102", "mrgb", 32, 1354 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } } 1355 }, 1356/* j $jmptarg */ 1357 { 1358 IQ2000_INSN_JQ10, "jq10", "j", 32, 1359 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1360 }, 1361/* jal $rt,$jmptarg */ 1362 { 1363 IQ2000_INSN_JALQ10, "jalq10", "jal", 32, 1364 { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1365 }, 1366/* jal $jmptarg */ 1367 { 1368 IQ2000_INSN_JALQ10_2, "jalq10-2", "jal", 32, 1369 { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1370 }, 1371/* bbil $rs($bitnum),$offset */ 1372 { 1373 IQ2000_INSN_BBIL, "bbil", "bbil", 32, 1374 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1375 }, 1376/* bbinl $rs($bitnum),$offset */ 1377 { 1378 IQ2000_INSN_BBINL, "bbinl", "bbinl", 32, 1379 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1380 }, 1381/* bbvl $rs,$rt,$offset */ 1382 { 1383 IQ2000_INSN_BBVL, "bbvl", "bbvl", 32, 1384 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1385 }, 1386/* bbvnl $rs,$rt,$offset */ 1387 { 1388 IQ2000_INSN_BBVNL, "bbvnl", "bbvnl", 32, 1389 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1390 }, 1391/* bgtzal $rs,$offset */ 1392 { 1393 IQ2000_INSN_BGTZAL, "bgtzal", "bgtzal", 32, 1394 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1395 }, 1396/* bgtzall $rs,$offset */ 1397 { 1398 IQ2000_INSN_BGTZALL, "bgtzall", "bgtzall", 32, 1399 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1400 }, 1401/* blezal $rs,$offset */ 1402 { 1403 IQ2000_INSN_BLEZAL, "blezal", "blezal", 32, 1404 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1405 }, 1406/* blezall $rs,$offset */ 1407 { 1408 IQ2000_INSN_BLEZALL, "blezall", "blezall", 32, 1409 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1410 }, 1411/* bgtz $rs,$offset */ 1412 { 1413 IQ2000_INSN_BGTZ_Q10, "bgtz-q10", "bgtz", 32, 1414 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1415 }, 1416/* bgtzl $rs,$offset */ 1417 { 1418 IQ2000_INSN_BGTZL_Q10, "bgtzl-q10", "bgtzl", 32, 1419 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1420 }, 1421/* blez $rs,$offset */ 1422 { 1423 IQ2000_INSN_BLEZ_Q10, "blez-q10", "blez", 32, 1424 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1425 }, 1426/* blezl $rs,$offset */ 1427 { 1428 IQ2000_INSN_BLEZL_Q10, "blezl-q10", "blezl", 32, 1429 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1430 }, 1431/* bmb $rs,$rt,$offset */ 1432 { 1433 IQ2000_INSN_BMB_Q10, "bmb-q10", "bmb", 32, 1434 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1435 }, 1436/* bmbl $rs,$rt,$offset */ 1437 { 1438 IQ2000_INSN_BMBL, "bmbl", "bmbl", 32, 1439 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1440 }, 1441/* bri $rs,$offset */ 1442 { 1443 IQ2000_INSN_BRI, "bri", "bri", 32, 1444 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1445 }, 1446/* brv $rs,$offset */ 1447 { 1448 IQ2000_INSN_BRV, "brv", "brv", 32, 1449 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1450 }, 1451/* bctx $rs,$offset */ 1452 { 1453 IQ2000_INSN_BCTX, "bctx", "bctx", 32, 1454 { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_IQ10), 0 } } } } 1455 }, 1456/* yield */ 1457 { 1458 IQ2000_INSN_YIELD, "yield", "yield", 32, 1459 { 0, { { { (1<<MACH_IQ10), 0 } } } } 1460 }, 1461/* crc32 $rd,$rs,$rt */ 1462 { 1463 IQ2000_INSN_CRC32, "crc32", "crc32", 32, 1464 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1465 }, 1466/* crc32b $rd,$rs,$rt */ 1467 { 1468 IQ2000_INSN_CRC32B, "crc32b", "crc32b", 32, 1469 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1470 }, 1471/* cnt1s $rd,$rs */ 1472 { 1473 IQ2000_INSN_CNT1S, "cnt1s", "cnt1s", 32, 1474 { 0|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1475 }, 1476/* avail $rd */ 1477 { 1478 IQ2000_INSN_AVAIL, "avail", "avail", 32, 1479 { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1480 }, 1481/* free $rd,$rs */ 1482 { 1483 IQ2000_INSN_FREE, "free", "free", 32, 1484 { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1485 }, 1486/* tstod $rd,$rs */ 1487 { 1488 IQ2000_INSN_TSTOD, "tstod", "tstod", 32, 1489 { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1490 }, 1491/* cmphdr $rd */ 1492 { 1493 IQ2000_INSN_CMPHDR, "cmphdr", "cmphdr", 32, 1494 { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1495 }, 1496/* mcid $rd,$rt */ 1497 { 1498 IQ2000_INSN_MCID, "mcid", "mcid", 32, 1499 { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1500 }, 1501/* dba $rd */ 1502 { 1503 IQ2000_INSN_DBA, "dba", "dba", 32, 1504 { 0|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1505 }, 1506/* dbd $rd,$rs,$rt */ 1507 { 1508 IQ2000_INSN_DBD, "dbd", "dbd", 32, 1509 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1510 }, 1511/* dpwt $rd,$rs */ 1512 { 1513 IQ2000_INSN_DPWT, "dpwt", "dpwt", 32, 1514 { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1515 }, 1516/* chkhdr $rd,$rs */ 1517 { 1518 IQ2000_INSN_CHKHDRQ10, "chkhdrq10", "chkhdr", 32, 1519 { 0|A(USES_RD)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1520 }, 1521/* rba $rd,$rs,$rt */ 1522 { 1523 IQ2000_INSN_RBA, "rba", "rba", 32, 1524 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1525 }, 1526/* rbal $rd,$rs,$rt */ 1527 { 1528 IQ2000_INSN_RBAL, "rbal", "rbal", 32, 1529 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1530 }, 1531/* rbar $rd,$rs,$rt */ 1532 { 1533 IQ2000_INSN_RBAR, "rbar", "rbar", 32, 1534 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1535 }, 1536/* wba $rd,$rs,$rt */ 1537 { 1538 IQ2000_INSN_WBA, "wba", "wba", 32, 1539 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1540 }, 1541/* wbau $rd,$rs,$rt */ 1542 { 1543 IQ2000_INSN_WBAU, "wbau", "wbau", 32, 1544 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1545 }, 1546/* wbac $rd,$rs,$rt */ 1547 { 1548 IQ2000_INSN_WBAC, "wbac", "wbac", 32, 1549 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1550 }, 1551/* rbi $rd,$rs,$rt,$bytecount */ 1552 { 1553 IQ2000_INSN_RBI, "rbi", "rbi", 32, 1554 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1555 }, 1556/* rbil $rd,$rs,$rt,$bytecount */ 1557 { 1558 IQ2000_INSN_RBIL, "rbil", "rbil", 32, 1559 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1560 }, 1561/* rbir $rd,$rs,$rt,$bytecount */ 1562 { 1563 IQ2000_INSN_RBIR, "rbir", "rbir", 32, 1564 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1565 }, 1566/* wbi $rd,$rs,$rt,$bytecount */ 1567 { 1568 IQ2000_INSN_WBI, "wbi", "wbi", 32, 1569 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1570 }, 1571/* wbic $rd,$rs,$rt,$bytecount */ 1572 { 1573 IQ2000_INSN_WBIC, "wbic", "wbic", 32, 1574 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1575 }, 1576/* wbiu $rd,$rs,$rt,$bytecount */ 1577 { 1578 IQ2000_INSN_WBIU, "wbiu", "wbiu", 32, 1579 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1580 }, 1581/* pkrli $rd,$rs,$rt,$bytecount */ 1582 { 1583 IQ2000_INSN_PKRLI, "pkrli", "pkrli", 32, 1584 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1585 }, 1586/* pkrlih $rd,$rs,$rt,$bytecount */ 1587 { 1588 IQ2000_INSN_PKRLIH, "pkrlih", "pkrlih", 32, 1589 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1590 }, 1591/* pkrliu $rd,$rs,$rt,$bytecount */ 1592 { 1593 IQ2000_INSN_PKRLIU, "pkrliu", "pkrliu", 32, 1594 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1595 }, 1596/* pkrlic $rd,$rs,$rt,$bytecount */ 1597 { 1598 IQ2000_INSN_PKRLIC, "pkrlic", "pkrlic", 32, 1599 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1600 }, 1601/* pkrla $rd,$rs,$rt */ 1602 { 1603 IQ2000_INSN_PKRLA, "pkrla", "pkrla", 32, 1604 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1605 }, 1606/* pkrlau $rd,$rs,$rt */ 1607 { 1608 IQ2000_INSN_PKRLAU, "pkrlau", "pkrlau", 32, 1609 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1610 }, 1611/* pkrlah $rd,$rs,$rt */ 1612 { 1613 IQ2000_INSN_PKRLAH, "pkrlah", "pkrlah", 32, 1614 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1615 }, 1616/* pkrlac $rd,$rs,$rt */ 1617 { 1618 IQ2000_INSN_PKRLAC, "pkrlac", "pkrlac", 32, 1619 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1620 }, 1621/* lock $rd,$rt */ 1622 { 1623 IQ2000_INSN_LOCK, "lock", "lock", 32, 1624 { 0|A(USES_RT)|A(USES_RD), { { { (1<<MACH_IQ10), 0 } } } } 1625 }, 1626/* unlk $rd,$rt */ 1627 { 1628 IQ2000_INSN_UNLK, "unlk", "unlk", 32, 1629 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1630 }, 1631/* swrd $rd,$rt */ 1632 { 1633 IQ2000_INSN_SWRD, "swrd", "swrd", 32, 1634 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1635 }, 1636/* swrdl $rd,$rt */ 1637 { 1638 IQ2000_INSN_SWRDL, "swrdl", "swrdl", 32, 1639 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1640 }, 1641/* swwr $rd,$rs,$rt */ 1642 { 1643 IQ2000_INSN_SWWR, "swwr", "swwr", 32, 1644 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1645 }, 1646/* swwru $rd,$rs,$rt */ 1647 { 1648 IQ2000_INSN_SWWRU, "swwru", "swwru", 32, 1649 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1650 }, 1651/* dwrd $rd,$rt */ 1652 { 1653 IQ2000_INSN_DWRD, "dwrd", "dwrd", 32, 1654 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1655 }, 1656/* dwrdl $rd,$rt */ 1657 { 1658 IQ2000_INSN_DWRDL, "dwrdl", "dwrdl", 32, 1659 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1660 }, 1661/* cam36 $rd,$rt,${cam-z},${cam-y} */ 1662 { 1663 IQ2000_INSN_CAM36, "cam36", "cam36", 32, 1664 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1665 }, 1666/* cam72 $rd,$rt,${cam-y},${cam-z} */ 1667 { 1668 IQ2000_INSN_CAM72, "cam72", "cam72", 32, 1669 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1670 }, 1671/* cam144 $rd,$rt,${cam-y},${cam-z} */ 1672 { 1673 IQ2000_INSN_CAM144, "cam144", "cam144", 32, 1674 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1675 }, 1676/* cam288 $rd,$rt,${cam-y},${cam-z} */ 1677 { 1678 IQ2000_INSN_CAM288, "cam288", "cam288", 32, 1679 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1680 }, 1681/* cm32and $rd,$rs,$rt */ 1682 { 1683 IQ2000_INSN_CM32AND, "cm32and", "cm32and", 32, 1684 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1685 }, 1686/* cm32andn $rd,$rs,$rt */ 1687 { 1688 IQ2000_INSN_CM32ANDN, "cm32andn", "cm32andn", 32, 1689 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1690 }, 1691/* cm32or $rd,$rs,$rt */ 1692 { 1693 IQ2000_INSN_CM32OR, "cm32or", "cm32or", 32, 1694 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1695 }, 1696/* cm32ra $rd,$rs,$rt */ 1697 { 1698 IQ2000_INSN_CM32RA, "cm32ra", "cm32ra", 32, 1699 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1700 }, 1701/* cm32rd $rd,$rt */ 1702 { 1703 IQ2000_INSN_CM32RD, "cm32rd", "cm32rd", 32, 1704 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1705 }, 1706/* cm32ri $rd,$rt */ 1707 { 1708 IQ2000_INSN_CM32RI, "cm32ri", "cm32ri", 32, 1709 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1710 }, 1711/* cm32rs $rd,$rs,$rt */ 1712 { 1713 IQ2000_INSN_CM32RS, "cm32rs", "cm32rs", 32, 1714 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1715 }, 1716/* cm32sa $rd,$rs,$rt */ 1717 { 1718 IQ2000_INSN_CM32SA, "cm32sa", "cm32sa", 32, 1719 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1720 }, 1721/* cm32sd $rd,$rt */ 1722 { 1723 IQ2000_INSN_CM32SD, "cm32sd", "cm32sd", 32, 1724 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1725 }, 1726/* cm32si $rd,$rt */ 1727 { 1728 IQ2000_INSN_CM32SI, "cm32si", "cm32si", 32, 1729 { 0|A(USES_RD)|A(USES_RT), { { { (1<<MACH_IQ10), 0 } } } } 1730 }, 1731/* cm32ss $rd,$rs,$rt */ 1732 { 1733 IQ2000_INSN_CM32SS, "cm32ss", "cm32ss", 32, 1734 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1735 }, 1736/* cm32xor $rd,$rs,$rt */ 1737 { 1738 IQ2000_INSN_CM32XOR, "cm32xor", "cm32xor", 32, 1739 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1740 }, 1741/* cm64clr $rd,$rt */ 1742 { 1743 IQ2000_INSN_CM64CLR, "cm64clr", "cm64clr", 32, 1744 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1745 }, 1746/* cm64ra $rd,$rs,$rt */ 1747 { 1748 IQ2000_INSN_CM64RA, "cm64ra", "cm64ra", 32, 1749 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1750 }, 1751/* cm64rd $rd,$rt */ 1752 { 1753 IQ2000_INSN_CM64RD, "cm64rd", "cm64rd", 32, 1754 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1755 }, 1756/* cm64ri $rd,$rt */ 1757 { 1758 IQ2000_INSN_CM64RI, "cm64ri", "cm64ri", 32, 1759 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1760 }, 1761/* cm64ria2 $rd,$rs,$rt */ 1762 { 1763 IQ2000_INSN_CM64RIA2, "cm64ria2", "cm64ria2", 32, 1764 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1765 }, 1766/* cm64rs $rd,$rs,$rt */ 1767 { 1768 IQ2000_INSN_CM64RS, "cm64rs", "cm64rs", 32, 1769 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1770 }, 1771/* cm64sa $rd,$rs,$rt */ 1772 { 1773 IQ2000_INSN_CM64SA, "cm64sa", "cm64sa", 32, 1774 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1775 }, 1776/* cm64sd $rd,$rt */ 1777 { 1778 IQ2000_INSN_CM64SD, "cm64sd", "cm64sd", 32, 1779 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1780 }, 1781/* cm64si $rd,$rt */ 1782 { 1783 IQ2000_INSN_CM64SI, "cm64si", "cm64si", 32, 1784 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1785 }, 1786/* cm64sia2 $rd,$rs,$rt */ 1787 { 1788 IQ2000_INSN_CM64SIA2, "cm64sia2", "cm64sia2", 32, 1789 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1790 }, 1791/* cm64ss $rd,$rs,$rt */ 1792 { 1793 IQ2000_INSN_CM64SS, "cm64ss", "cm64ss", 32, 1794 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1795 }, 1796/* cm128ria2 $rd,$rs,$rt */ 1797 { 1798 IQ2000_INSN_CM128RIA2, "cm128ria2", "cm128ria2", 32, 1799 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1800 }, 1801/* cm128ria3 $rd,$rs,$rt,${cm-3z} */ 1802 { 1803 IQ2000_INSN_CM128RIA3, "cm128ria3", "cm128ria3", 32, 1804 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1805 }, 1806/* cm128ria4 $rd,$rs,$rt,${cm-4z} */ 1807 { 1808 IQ2000_INSN_CM128RIA4, "cm128ria4", "cm128ria4", 32, 1809 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1810 }, 1811/* cm128sia2 $rd,$rs,$rt */ 1812 { 1813 IQ2000_INSN_CM128SIA2, "cm128sia2", "cm128sia2", 32, 1814 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1815 }, 1816/* cm128sia3 $rd,$rs,$rt,${cm-3z} */ 1817 { 1818 IQ2000_INSN_CM128SIA3, "cm128sia3", "cm128sia3", 32, 1819 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { { { (1<<MACH_IQ10), 0 } } } } 1820 }, 1821/* cm128sia4 $rd,$rs,$rt,${cm-4z} */ 1822 { 1823 IQ2000_INSN_CM128SIA4, "cm128sia4", "cm128sia4", 32, 1824 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1825 }, 1826/* cm128vsa $rd,$rs,$rt */ 1827 { 1828 IQ2000_INSN_CM128VSA, "cm128vsa", "cm128vsa", 32, 1829 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1830 }, 1831/* cfc $rd,$rt */ 1832 { 1833 IQ2000_INSN_CFC, "cfc", "cfc", 32, 1834 { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { { { (1<<MACH_IQ10), 0 } } } } 1835 }, 1836/* ctc $rs,$rt */ 1837 { 1838 IQ2000_INSN_CTC, "ctc", "ctc", 32, 1839 { 0|A(USES_RS), { { { (1<<MACH_IQ10), 0 } } } } 1840 }, 1841}; 1842 1843#undef OP 1844#undef A 1845 1846/* Initialize anything needed to be done once, before any cpu_open call. */ 1847 1848static void 1849init_tables (void) 1850{ 1851} 1852 1853#ifndef opcodes_error_handler 1854#define opcodes_error_handler(...) \ 1855 fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr) 1856#endif 1857 1858static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *); 1859static void build_hw_table (CGEN_CPU_TABLE *); 1860static void build_ifield_table (CGEN_CPU_TABLE *); 1861static void build_operand_table (CGEN_CPU_TABLE *); 1862static void build_insn_table (CGEN_CPU_TABLE *); 1863static void iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *); 1864 1865/* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name. */ 1866 1867static const CGEN_MACH * 1868lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name) 1869{ 1870 while (table->name) 1871 { 1872 if (strcmp (name, table->bfd_name) == 0) 1873 return table; 1874 ++table; 1875 } 1876 return NULL; 1877} 1878 1879/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ 1880 1881static void 1882build_hw_table (CGEN_CPU_TABLE *cd) 1883{ 1884 int i; 1885 int machs = cd->machs; 1886 const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0]; 1887 /* MAX_HW is only an upper bound on the number of selected entries. 1888 However each entry is indexed by it's enum so there can be holes in 1889 the table. */ 1890 const CGEN_HW_ENTRY **selected = 1891 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1892 1893 cd->hw_table.init_entries = init; 1894 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY); 1895 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *)); 1896 /* ??? For now we just use machs to determine which ones we want. */ 1897 for (i = 0; init[i].name != NULL; ++i) 1898 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH) 1899 & machs) 1900 selected[init[i].type] = &init[i]; 1901 cd->hw_table.entries = selected; 1902 cd->hw_table.num_entries = MAX_HW; 1903} 1904 1905/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ 1906 1907static void 1908build_ifield_table (CGEN_CPU_TABLE *cd) 1909{ 1910 cd->ifld_table = & iq2000_cgen_ifld_table[0]; 1911} 1912 1913/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */ 1914 1915static void 1916build_operand_table (CGEN_CPU_TABLE *cd) 1917{ 1918 int i; 1919 int machs = cd->machs; 1920 const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0]; 1921 /* MAX_OPERANDS is only an upper bound on the number of selected entries. 1922 However each entry is indexed by it's enum so there can be holes in 1923 the table. */ 1924 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected)); 1925 1926 cd->operand_table.init_entries = init; 1927 cd->operand_table.entry_size = sizeof (CGEN_OPERAND); 1928 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *)); 1929 /* ??? For now we just use mach to determine which ones we want. */ 1930 for (i = 0; init[i].name != NULL; ++i) 1931 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH) 1932 & machs) 1933 selected[init[i].type] = &init[i]; 1934 cd->operand_table.entries = selected; 1935 cd->operand_table.num_entries = MAX_OPERANDS; 1936} 1937 1938/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. 1939 ??? This could leave out insns not supported by the specified mach/isa, 1940 but that would cause errors like "foo only supported by bar" to become 1941 "unknown insn", so for now we include all insns and require the app to 1942 do the checking later. 1943 ??? On the other hand, parsing of such insns may require their hardware or 1944 operand elements to be in the table [which they mightn't be]. */ 1945 1946static void 1947build_insn_table (CGEN_CPU_TABLE *cd) 1948{ 1949 int i; 1950 const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0]; 1951 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN)); 1952 1953 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN)); 1954 for (i = 0; i < MAX_INSNS; ++i) 1955 insns[i].base = &ib[i]; 1956 cd->insn_table.init_entries = insns; 1957 cd->insn_table.entry_size = sizeof (CGEN_IBASE); 1958 cd->insn_table.num_init_entries = MAX_INSNS; 1959} 1960 1961/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */ 1962 1963static void 1964iq2000_cgen_rebuild_tables (CGEN_CPU_TABLE *cd) 1965{ 1966 int i; 1967 CGEN_BITSET *isas = cd->isas; 1968 unsigned int machs = cd->machs; 1969 1970 cd->int_insn_p = CGEN_INT_INSN_P; 1971 1972 /* Data derived from the isa spec. */ 1973#define UNSET (CGEN_SIZE_UNKNOWN + 1) 1974 cd->default_insn_bitsize = UNSET; 1975 cd->base_insn_bitsize = UNSET; 1976 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */ 1977 cd->max_insn_bitsize = 0; 1978 for (i = 0; i < MAX_ISAS; ++i) 1979 if (cgen_bitset_contains (isas, i)) 1980 { 1981 const CGEN_ISA *isa = & iq2000_cgen_isa_table[i]; 1982 1983 /* Default insn sizes of all selected isas must be 1984 equal or we set the result to 0, meaning "unknown". */ 1985 if (cd->default_insn_bitsize == UNSET) 1986 cd->default_insn_bitsize = isa->default_insn_bitsize; 1987 else if (isa->default_insn_bitsize == cd->default_insn_bitsize) 1988 ; /* This is ok. */ 1989 else 1990 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN; 1991 1992 /* Base insn sizes of all selected isas must be equal 1993 or we set the result to 0, meaning "unknown". */ 1994 if (cd->base_insn_bitsize == UNSET) 1995 cd->base_insn_bitsize = isa->base_insn_bitsize; 1996 else if (isa->base_insn_bitsize == cd->base_insn_bitsize) 1997 ; /* This is ok. */ 1998 else 1999 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN; 2000 2001 /* Set min,max insn sizes. */ 2002 if (isa->min_insn_bitsize < cd->min_insn_bitsize) 2003 cd->min_insn_bitsize = isa->min_insn_bitsize; 2004 if (isa->max_insn_bitsize > cd->max_insn_bitsize) 2005 cd->max_insn_bitsize = isa->max_insn_bitsize; 2006 } 2007 2008 /* Data derived from the mach spec. */ 2009 for (i = 0; i < MAX_MACHS; ++i) 2010 if (((1 << i) & machs) != 0) 2011 { 2012 const CGEN_MACH *mach = & iq2000_cgen_mach_table[i]; 2013 2014 if (mach->insn_chunk_bitsize != 0) 2015 { 2016 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize) 2017 { 2018 opcodes_error_handler 2019 (/* xgettext:c-format */ 2020 _("internal error: iq2000_cgen_rebuild_tables: " 2021 "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"), 2022 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize); 2023 abort (); 2024 } 2025 2026 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize; 2027 } 2028 } 2029 2030 /* Determine which hw elements are used by MACH. */ 2031 build_hw_table (cd); 2032 2033 /* Build the ifield table. */ 2034 build_ifield_table (cd); 2035 2036 /* Determine which operands are used by MACH/ISA. */ 2037 build_operand_table (cd); 2038 2039 /* Build the instruction table. */ 2040 build_insn_table (cd); 2041} 2042 2043/* Initialize a cpu table and return a descriptor. 2044 It's much like opening a file, and must be the first function called. 2045 The arguments are a set of (type/value) pairs, terminated with 2046 CGEN_CPU_OPEN_END. 2047 2048 Currently supported values: 2049 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr 2050 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr 2051 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name 2052 CGEN_CPU_OPEN_ENDIAN: specify endian choice 2053 CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice 2054 CGEN_CPU_OPEN_END: terminates arguments 2055 2056 ??? Simultaneous multiple isas might not make sense, but it's not (yet) 2057 precluded. */ 2058 2059CGEN_CPU_DESC 2060iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...) 2061{ 2062 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE)); 2063 static int init_p; 2064 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */ 2065 unsigned int machs = 0; /* 0 = "unspecified" */ 2066 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN; 2067 enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN; 2068 va_list ap; 2069 2070 if (! init_p) 2071 { 2072 init_tables (); 2073 init_p = 1; 2074 } 2075 2076 memset (cd, 0, sizeof (*cd)); 2077 2078 va_start (ap, arg_type); 2079 while (arg_type != CGEN_CPU_OPEN_END) 2080 { 2081 switch (arg_type) 2082 { 2083 case CGEN_CPU_OPEN_ISAS : 2084 isas = va_arg (ap, CGEN_BITSET *); 2085 break; 2086 case CGEN_CPU_OPEN_MACHS : 2087 machs = va_arg (ap, unsigned int); 2088 break; 2089 case CGEN_CPU_OPEN_BFDMACH : 2090 { 2091 const char *name = va_arg (ap, const char *); 2092 const CGEN_MACH *mach = 2093 lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name); 2094 2095 if (mach != NULL) 2096 machs |= 1 << mach->num; 2097 break; 2098 } 2099 case CGEN_CPU_OPEN_ENDIAN : 2100 endian = va_arg (ap, enum cgen_endian); 2101 break; 2102 case CGEN_CPU_OPEN_INSN_ENDIAN : 2103 insn_endian = va_arg (ap, enum cgen_endian); 2104 break; 2105 default : 2106 opcodes_error_handler 2107 (/* xgettext:c-format */ 2108 _("internal error: iq2000_cgen_cpu_open: " 2109 "unsupported argument `%d'"), 2110 arg_type); 2111 abort (); /* ??? return NULL? */ 2112 } 2113 arg_type = va_arg (ap, enum cgen_cpu_open_arg); 2114 } 2115 va_end (ap); 2116 2117 /* Mach unspecified means "all". */ 2118 if (machs == 0) 2119 machs = (1 << MAX_MACHS) - 1; 2120 /* Base mach is always selected. */ 2121 machs |= 1; 2122 if (endian == CGEN_ENDIAN_UNKNOWN) 2123 { 2124 /* ??? If target has only one, could have a default. */ 2125 opcodes_error_handler 2126 (/* xgettext:c-format */ 2127 _("internal error: iq2000_cgen_cpu_open: no endianness specified")); 2128 abort (); 2129 } 2130 2131 cd->isas = cgen_bitset_copy (isas); 2132 cd->machs = machs; 2133 cd->endian = endian; 2134 cd->insn_endian 2135 = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian); 2136 2137 /* Table (re)builder. */ 2138 cd->rebuild_tables = iq2000_cgen_rebuild_tables; 2139 iq2000_cgen_rebuild_tables (cd); 2140 2141 /* Default to not allowing signed overflow. */ 2142 cd->signed_overflow_ok_p = 0; 2143 2144 return (CGEN_CPU_DESC) cd; 2145} 2146 2147/* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach. 2148 MACH_NAME is the bfd name of the mach. */ 2149 2150CGEN_CPU_DESC 2151iq2000_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian) 2152{ 2153 return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 2154 CGEN_CPU_OPEN_ENDIAN, endian, 2155 CGEN_CPU_OPEN_END); 2156} 2157 2158/* Close a cpu table. 2159 ??? This can live in a machine independent file, but there's currently 2160 no place to put this file (there's no libcgen). libopcodes is the wrong 2161 place as some simulator ports use this but they don't use libopcodes. */ 2162 2163void 2164iq2000_cgen_cpu_close (CGEN_CPU_DESC cd) 2165{ 2166 unsigned int i; 2167 const CGEN_INSN *insns; 2168 2169 if (cd->macro_insn_table.init_entries) 2170 { 2171 insns = cd->macro_insn_table.init_entries; 2172 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns) 2173 if (CGEN_INSN_RX ((insns))) 2174 regfree (CGEN_INSN_RX (insns)); 2175 } 2176 2177 if (cd->insn_table.init_entries) 2178 { 2179 insns = cd->insn_table.init_entries; 2180 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns) 2181 if (CGEN_INSN_RX (insns)) 2182 regfree (CGEN_INSN_RX (insns)); 2183 } 2184 2185 free ((CGEN_INSN *) cd->macro_insn_table.init_entries); 2186 free ((CGEN_INSN *) cd->insn_table.init_entries); 2187 free ((CGEN_HW_ENTRY *) cd->hw_table.entries); 2188 free ((CGEN_HW_ENTRY *) cd->operand_table.entries); 2189 free (cd); 2190} 2191 2192