i386-dis.c revision 1.3 
1/* Print i386 instructions for GDB, the GNU debugger.
2   Copyright (C) 1988-2015 Free Software Foundation, Inc.
3
4   This file is part of the GNU opcodes library.
5
6   This library is free software; you can redistribute it and/or modify
7   it under the terms of the GNU General Public License as published by
8   the Free Software Foundation; either version 3, or (at your option)
9   any later version.
10
11   It is distributed in the hope that it will be useful, but WITHOUT
12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14   License for more details.
15
16   You should have received a copy of the GNU General Public License
17   along with this program; if not, write to the Free Software
18   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19   MA 02110-1301, USA.  */
20
21
22/* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23   July 1988
24    modified by John Hassey (hassey@dg-rtp.dg.com)
25    x86-64 support added by Jan Hubicka (jh@suse.cz)
26    VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
27
28/* The main tables describing the instructions is essentially a copy
29   of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30   Programmers Manual.  Usually, there is a capital letter, followed
31   by a small letter.  The capital letter tell the addressing mode,
32   and the small letter tells about the operand size.  Refer to
33   the Intel manual for details.  */
34
35#include "sysdep.h"
36#include "dis-asm.h"
37#include "opintl.h"
38#include "opcode/i386.h"
39#include "libiberty.h"
40
41#include <setjmp.h>
42
43static int print_insn (bfd_vma, disassemble_info *);
44static void dofloat (int);
45static void OP_ST (int, int);
46static void OP_STi (int, int);
47static int putop (const char *, int);
48static void oappend (const char *);
49static void append_seg (void);
50static void OP_indirE (int, int);
51static void print_operand_value (char *, int, bfd_vma);
52static void OP_E_register (int, int);
53static void OP_E_memory (int, int);
54static void print_displacement (char *, bfd_vma);
55static void OP_E (int, int);
56static void OP_G (int, int);
57static bfd_vma get64 (void);
58static bfd_signed_vma get32 (void);
59static bfd_signed_vma get32s (void);
60static int get16 (void);
61static void set_op (bfd_vma, int);
62static void OP_Skip_MODRM (int, int);
63static void OP_REG (int, int);
64static void OP_IMREG (int, int);
65static void OP_I (int, int);
66static void OP_I64 (int, int);
67static void OP_sI (int, int);
68static void OP_J (int, int);
69static void OP_SEG (int, int);
70static void OP_DIR (int, int);
71static void OP_OFF (int, int);
72static void OP_OFF64 (int, int);
73static void ptr_reg (int, int);
74static void OP_ESreg (int, int);
75static void OP_DSreg (int, int);
76static void OP_C (int, int);
77static void OP_D (int, int);
78static void OP_T (int, int);
79static void OP_R (int, int);
80static void OP_MMX (int, int);
81static void OP_XMM (int, int);
82static void OP_EM (int, int);
83static void OP_EX (int, int);
84static void OP_EMC (int,int);
85static void OP_MXC (int,int);
86static void OP_MS (int, int);
87static void OP_XS (int, int);
88static void OP_M (int, int);
89static void OP_VEX (int, int);
90static void OP_EX_Vex (int, int);
91static void OP_EX_VexW (int, int);
92static void OP_EX_VexImmW (int, int);
93static void OP_XMM_Vex (int, int);
94static void OP_XMM_VexW (int, int);
95static void OP_Rounding (int, int);
96static void OP_REG_VexI4 (int, int);
97static void PCLMUL_Fixup (int, int);
98static void VEXI4_Fixup (int, int);
99static void VZERO_Fixup (int, int);
100static void VCMP_Fixup (int, int);
101static void VPCMP_Fixup (int, int);
102static void OP_0f07 (int, int);
103static void OP_Monitor (int, int);
104static void OP_Mwait (int, int);
105static void NOP_Fixup1 (int, int);
106static void NOP_Fixup2 (int, int);
107static void OP_3DNowSuffix (int, int);
108static void CMP_Fixup (int, int);
109static void BadOp (void);
110static void REP_Fixup (int, int);
111static void BND_Fixup (int, int);
112static void HLE_Fixup1 (int, int);
113static void HLE_Fixup2 (int, int);
114static void HLE_Fixup3 (int, int);
115static void CMPXCHG8B_Fixup (int, int);
116static void XMM_Fixup (int, int);
117static void CRC32_Fixup (int, int);
118static void FXSAVE_Fixup (int, int);
119static void OP_LWPCB_E (int, int);
120static void OP_LWP_E (int, int);
121static void OP_Vex_2src_1 (int, int);
122static void OP_Vex_2src_2 (int, int);
123
124static void MOVBE_Fixup (int, int);
125
126static void OP_Mask (int, int);
127
128struct dis_private {
129  /* Points to first byte not fetched.  */
130  bfd_byte *max_fetched;
131  bfd_byte the_buffer[MAX_MNEM_SIZE];
132  bfd_vma insn_start;
133  int orig_sizeflag;
134  OPCODES_SIGJMP_BUF bailout;
135};
136
137enum address_mode
138{
139  mode_16bit,
140  mode_32bit,
141  mode_64bit
142};
143
144enum address_mode address_mode;
145
146/* Flags for the prefixes for the current instruction.  See below.  */
147static int prefixes;
148
149/* REX prefix the current instruction.  See below.  */
150static int rex;
151/* Bits of REX we've already used.  */
152static int rex_used;
153/* REX bits in original REX prefix ignored.  */
154static int rex_ignored;
155/* Mark parts used in the REX prefix.  When we are testing for
156   empty prefix (for 8bit register REX extension), just mask it
157   out.  Otherwise test for REX bit is excuse for existence of REX
158   only in case value is nonzero.  */
159#define USED_REX(value)					\
160  {							\
161    if (value)						\
162      {							\
163	if ((rex & value))				\
164	  rex_used |= (value) | REX_OPCODE;		\
165      }							\
166    else						\
167      rex_used |= REX_OPCODE;				\
168  }
169
170/* Flags for prefixes which we somehow handled when printing the
171   current instruction.  */
172static int used_prefixes;
173
174/* Flags stored in PREFIXES.  */
175#define PREFIX_REPZ 1
176#define PREFIX_REPNZ 2
177#define PREFIX_LOCK 4
178#define PREFIX_CS 8
179#define PREFIX_SS 0x10
180#define PREFIX_DS 0x20
181#define PREFIX_ES 0x40
182#define PREFIX_FS 0x80
183#define PREFIX_GS 0x100
184#define PREFIX_DATA 0x200
185#define PREFIX_ADDR 0x400
186#define PREFIX_FWAIT 0x800
187
188/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
189   to ADDR (exclusive) are valid.  Returns 1 for success, longjmps
190   on error.  */
191#define FETCH_DATA(info, addr) \
192  ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
193   ? 1 : fetch_data ((info), (addr)))
194
195static int
196fetch_data (struct disassemble_info *info, bfd_byte *addr)
197{
198  int status;
199  struct dis_private *priv = (struct dis_private *) info->private_data;
200  bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
201
202  if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
203    status = (*info->read_memory_func) (start,
204					priv->max_fetched,
205					addr - priv->max_fetched,
206					info);
207  else
208    status = -1;
209  if (status != 0)
210    {
211      /* If we did manage to read at least one byte, then
212	 print_insn_i386 will do something sensible.  Otherwise, print
213	 an error.  We do that here because this is where we know
214	 STATUS.  */
215      if (priv->max_fetched == priv->the_buffer)
216	(*info->memory_error_func) (status, start, info);
217      OPCODES_SIGLONGJMP (priv->bailout, 1);
218    }
219  else
220    priv->max_fetched = addr;
221  return 1;
222}
223
224#define XX { NULL, 0 }
225#define Bad_Opcode NULL, { { NULL, 0 } }
226
227#define Eb { OP_E, b_mode }
228#define Ebnd { OP_E, bnd_mode }
229#define EbS { OP_E, b_swap_mode }
230#define Ev { OP_E, v_mode }
231#define Ev_bnd { OP_E, v_bnd_mode }
232#define EvS { OP_E, v_swap_mode }
233#define Ed { OP_E, d_mode }
234#define Edq { OP_E, dq_mode }
235#define Edqw { OP_E, dqw_mode }
236#define EdqwS { OP_E, dqw_swap_mode }
237#define Edqb { OP_E, dqb_mode }
238#define Edb { OP_E, db_mode }
239#define Edw { OP_E, dw_mode }
240#define Edqd { OP_E, dqd_mode }
241#define Eq { OP_E, q_mode }
242#define indirEv { OP_indirE, stack_v_mode }
243#define indirEp { OP_indirE, f_mode }
244#define stackEv { OP_E, stack_v_mode }
245#define Em { OP_E, m_mode }
246#define Ew { OP_E, w_mode }
247#define M { OP_M, 0 }		/* lea, lgdt, etc. */
248#define Ma { OP_M, a_mode }
249#define Mb { OP_M, b_mode }
250#define Md { OP_M, d_mode }
251#define Mo { OP_M, o_mode }
252#define Mp { OP_M, f_mode }		/* 32 or 48 bit memory operand for LDS, LES etc */
253#define Mq { OP_M, q_mode }
254#define Mx { OP_M, x_mode }
255#define Mxmm { OP_M, xmm_mode }
256#define Gb { OP_G, b_mode }
257#define Gbnd { OP_G, bnd_mode }
258#define Gv { OP_G, v_mode }
259#define Gd { OP_G, d_mode }
260#define Gdq { OP_G, dq_mode }
261#define Gm { OP_G, m_mode }
262#define Gw { OP_G, w_mode }
263#define Rd { OP_R, d_mode }
264#define Rdq { OP_R, dq_mode }
265#define Rm { OP_R, m_mode }
266#define Ib { OP_I, b_mode }
267#define sIb { OP_sI, b_mode }	/* sign extened byte */
268#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
269#define Iv { OP_I, v_mode }
270#define sIv { OP_sI, v_mode }
271#define Iq { OP_I, q_mode }
272#define Iv64 { OP_I64, v_mode }
273#define Iw { OP_I, w_mode }
274#define I1 { OP_I, const_1_mode }
275#define Jb { OP_J, b_mode }
276#define Jv { OP_J, v_mode }
277#define Cm { OP_C, m_mode }
278#define Dm { OP_D, m_mode }
279#define Td { OP_T, d_mode }
280#define Skip_MODRM { OP_Skip_MODRM, 0 }
281
282#define RMeAX { OP_REG, eAX_reg }
283#define RMeBX { OP_REG, eBX_reg }
284#define RMeCX { OP_REG, eCX_reg }
285#define RMeDX { OP_REG, eDX_reg }
286#define RMeSP { OP_REG, eSP_reg }
287#define RMeBP { OP_REG, eBP_reg }
288#define RMeSI { OP_REG, eSI_reg }
289#define RMeDI { OP_REG, eDI_reg }
290#define RMrAX { OP_REG, rAX_reg }
291#define RMrBX { OP_REG, rBX_reg }
292#define RMrCX { OP_REG, rCX_reg }
293#define RMrDX { OP_REG, rDX_reg }
294#define RMrSP { OP_REG, rSP_reg }
295#define RMrBP { OP_REG, rBP_reg }
296#define RMrSI { OP_REG, rSI_reg }
297#define RMrDI { OP_REG, rDI_reg }
298#define RMAL { OP_REG, al_reg }
299#define RMCL { OP_REG, cl_reg }
300#define RMDL { OP_REG, dl_reg }
301#define RMBL { OP_REG, bl_reg }
302#define RMAH { OP_REG, ah_reg }
303#define RMCH { OP_REG, ch_reg }
304#define RMDH { OP_REG, dh_reg }
305#define RMBH { OP_REG, bh_reg }
306#define RMAX { OP_REG, ax_reg }
307#define RMDX { OP_REG, dx_reg }
308
309#define eAX { OP_IMREG, eAX_reg }
310#define eBX { OP_IMREG, eBX_reg }
311#define eCX { OP_IMREG, eCX_reg }
312#define eDX { OP_IMREG, eDX_reg }
313#define eSP { OP_IMREG, eSP_reg }
314#define eBP { OP_IMREG, eBP_reg }
315#define eSI { OP_IMREG, eSI_reg }
316#define eDI { OP_IMREG, eDI_reg }
317#define AL { OP_IMREG, al_reg }
318#define CL { OP_IMREG, cl_reg }
319#define DL { OP_IMREG, dl_reg }
320#define BL { OP_IMREG, bl_reg }
321#define AH { OP_IMREG, ah_reg }
322#define CH { OP_IMREG, ch_reg }
323#define DH { OP_IMREG, dh_reg }
324#define BH { OP_IMREG, bh_reg }
325#define AX { OP_IMREG, ax_reg }
326#define DX { OP_IMREG, dx_reg }
327#define zAX { OP_IMREG, z_mode_ax_reg }
328#define indirDX { OP_IMREG, indir_dx_reg }
329
330#define Sw { OP_SEG, w_mode }
331#define Sv { OP_SEG, v_mode }
332#define Ap { OP_DIR, 0 }
333#define Ob { OP_OFF64, b_mode }
334#define Ov { OP_OFF64, v_mode }
335#define Xb { OP_DSreg, eSI_reg }
336#define Xv { OP_DSreg, eSI_reg }
337#define Xz { OP_DSreg, eSI_reg }
338#define Yb { OP_ESreg, eDI_reg }
339#define Yv { OP_ESreg, eDI_reg }
340#define DSBX { OP_DSreg, eBX_reg }
341
342#define es { OP_REG, es_reg }
343#define ss { OP_REG, ss_reg }
344#define cs { OP_REG, cs_reg }
345#define ds { OP_REG, ds_reg }
346#define fs { OP_REG, fs_reg }
347#define gs { OP_REG, gs_reg }
348
349#define MX { OP_MMX, 0 }
350#define XM { OP_XMM, 0 }
351#define XMScalar { OP_XMM, scalar_mode }
352#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
353#define XMM { OP_XMM, xmm_mode }
354#define XMxmmq { OP_XMM, xmmq_mode }
355#define EM { OP_EM, v_mode }
356#define EMS { OP_EM, v_swap_mode }
357#define EMd { OP_EM, d_mode }
358#define EMx { OP_EM, x_mode }
359#define EXw { OP_EX, w_mode }
360#define EXd { OP_EX, d_mode }
361#define EXdScalar { OP_EX, d_scalar_mode }
362#define EXdS { OP_EX, d_swap_mode }
363#define EXdScalarS { OP_EX, d_scalar_swap_mode }
364#define EXq { OP_EX, q_mode }
365#define EXqScalar { OP_EX, q_scalar_mode }
366#define EXqScalarS { OP_EX, q_scalar_swap_mode }
367#define EXqS { OP_EX, q_swap_mode }
368#define EXx { OP_EX, x_mode }
369#define EXxS { OP_EX, x_swap_mode }
370#define EXxmm { OP_EX, xmm_mode }
371#define EXymm { OP_EX, ymm_mode }
372#define EXxmmq { OP_EX, xmmq_mode }
373#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
374#define EXxmm_mb { OP_EX, xmm_mb_mode }
375#define EXxmm_mw { OP_EX, xmm_mw_mode }
376#define EXxmm_md { OP_EX, xmm_md_mode }
377#define EXxmm_mq { OP_EX, xmm_mq_mode }
378#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
379#define EXxmmdw { OP_EX, xmmdw_mode }
380#define EXxmmqd { OP_EX, xmmqd_mode }
381#define EXymmq { OP_EX, ymmq_mode }
382#define EXVexWdq { OP_EX, vex_w_dq_mode }
383#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
384#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
385#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
386#define MS { OP_MS, v_mode }
387#define XS { OP_XS, v_mode }
388#define EMCq { OP_EMC, q_mode }
389#define MXC { OP_MXC, 0 }
390#define OPSUF { OP_3DNowSuffix, 0 }
391#define CMP { CMP_Fixup, 0 }
392#define XMM0 { XMM_Fixup, 0 }
393#define FXSAVE { FXSAVE_Fixup, 0 }
394#define Vex_2src_1 { OP_Vex_2src_1, 0 }
395#define Vex_2src_2 { OP_Vex_2src_2, 0 }
396
397#define Vex { OP_VEX, vex_mode }
398#define VexScalar { OP_VEX, vex_scalar_mode }
399#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
400#define Vex128 { OP_VEX, vex128_mode }
401#define Vex256 { OP_VEX, vex256_mode }
402#define VexGdq { OP_VEX, dq_mode }
403#define VexI4 { VEXI4_Fixup, 0}
404#define EXdVex { OP_EX_Vex, d_mode }
405#define EXdVexS { OP_EX_Vex, d_swap_mode }
406#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
407#define EXqVex { OP_EX_Vex, q_mode }
408#define EXqVexS { OP_EX_Vex, q_swap_mode }
409#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
410#define EXVexW { OP_EX_VexW, x_mode }
411#define EXdVexW { OP_EX_VexW, d_mode }
412#define EXqVexW { OP_EX_VexW, q_mode }
413#define EXVexImmW { OP_EX_VexImmW, x_mode }
414#define XMVex { OP_XMM_Vex, 0 }
415#define XMVexScalar { OP_XMM_Vex, scalar_mode }
416#define XMVexW { OP_XMM_VexW, 0 }
417#define XMVexI4 { OP_REG_VexI4, x_mode }
418#define PCLMUL { PCLMUL_Fixup, 0 }
419#define VZERO { VZERO_Fixup, 0 }
420#define VCMP { VCMP_Fixup, 0 }
421#define VPCMP { VPCMP_Fixup, 0 }
422
423#define EXxEVexR { OP_Rounding, evex_rounding_mode }
424#define EXxEVexS { OP_Rounding, evex_sae_mode }
425
426#define XMask { OP_Mask, mask_mode }
427#define MaskG { OP_G, mask_mode }
428#define MaskE { OP_E, mask_mode }
429#define MaskBDE { OP_E, mask_bd_mode }
430#define MaskR { OP_R, mask_mode }
431#define MaskVex { OP_VEX, mask_mode }
432
433#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
434#define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
435#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
436#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
437
438/* Used handle "rep" prefix for string instructions.  */
439#define Xbr { REP_Fixup, eSI_reg }
440#define Xvr { REP_Fixup, eSI_reg }
441#define Ybr { REP_Fixup, eDI_reg }
442#define Yvr { REP_Fixup, eDI_reg }
443#define Yzr { REP_Fixup, eDI_reg }
444#define indirDXr { REP_Fixup, indir_dx_reg }
445#define ALr { REP_Fixup, al_reg }
446#define eAXr { REP_Fixup, eAX_reg }
447
448/* Used handle HLE prefix for lockable instructions.  */
449#define Ebh1 { HLE_Fixup1, b_mode }
450#define Evh1 { HLE_Fixup1, v_mode }
451#define Ebh2 { HLE_Fixup2, b_mode }
452#define Evh2 { HLE_Fixup2, v_mode }
453#define Ebh3 { HLE_Fixup3, b_mode }
454#define Evh3 { HLE_Fixup3, v_mode }
455
456#define BND { BND_Fixup, 0 }
457
458#define cond_jump_flag { NULL, cond_jump_mode }
459#define loop_jcxz_flag { NULL, loop_jcxz_mode }
460
461/* bits in sizeflag */
462#define SUFFIX_ALWAYS 4
463#define AFLAG 2
464#define DFLAG 1
465
466enum
467{
468  /* byte operand */
469  b_mode = 1,
470  /* byte operand with operand swapped */
471  b_swap_mode,
472  /* byte operand, sign extend like 'T' suffix */
473  b_T_mode,
474  /* operand size depends on prefixes */
475  v_mode,
476  /* operand size depends on prefixes with operand swapped */
477  v_swap_mode,
478  /* word operand */
479  w_mode,
480  /* double word operand  */
481  d_mode,
482  /* double word operand with operand swapped */
483  d_swap_mode,
484  /* quad word operand */
485  q_mode,
486  /* quad word operand with operand swapped */
487  q_swap_mode,
488  /* ten-byte operand */
489  t_mode,
490  /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
491     broadcast enabled.  */
492  x_mode,
493  /* Similar to x_mode, but with different EVEX mem shifts.  */
494  evex_x_gscat_mode,
495  /* Similar to x_mode, but with disabled broadcast.  */
496  evex_x_nobcst_mode,
497  /* Similar to x_mode, but with operands swapped and disabled broadcast
498     in EVEX.  */
499  x_swap_mode,
500  /* 16-byte XMM operand */
501  xmm_mode,
502  /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
503     memory operand (depending on vector length).  Broadcast isn't
504     allowed.  */
505  xmmq_mode,
506  /* Same as xmmq_mode, but broadcast is allowed.  */
507  evex_half_bcst_xmmq_mode,
508  /* XMM register or byte memory operand */
509  xmm_mb_mode,
510  /* XMM register or word memory operand */
511  xmm_mw_mode,
512  /* XMM register or double word memory operand */
513  xmm_md_mode,
514  /* XMM register or quad word memory operand */
515  xmm_mq_mode,
516  /* XMM register or double/quad word memory operand, depending on
517     VEX.W.  */
518  xmm_mdq_mode,
519  /* 16-byte XMM, word, double word or quad word operand.  */
520  xmmdw_mode,
521  /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
522  xmmqd_mode,
523  /* 32-byte YMM operand */
524  ymm_mode,
525  /* quad word, ymmword or zmmword memory operand.  */
526  ymmq_mode,
527  /* 32-byte YMM or 16-byte word operand */
528  ymmxmm_mode,
529  /* d_mode in 32bit, q_mode in 64bit mode.  */
530  m_mode,
531  /* pair of v_mode operands */
532  a_mode,
533  cond_jump_mode,
534  loop_jcxz_mode,
535  v_bnd_mode,
536  /* operand size depends on REX prefixes.  */
537  dq_mode,
538  /* registers like dq_mode, memory like w_mode.  */
539  dqw_mode,
540  dqw_swap_mode,
541  bnd_mode,
542  /* 4- or 6-byte pointer operand */
543  f_mode,
544  const_1_mode,
545  /* v_mode for stack-related opcodes.  */
546  stack_v_mode,
547  /* non-quad operand size depends on prefixes */
548  z_mode,
549  /* 16-byte operand */
550  o_mode,
551  /* registers like dq_mode, memory like b_mode.  */
552  dqb_mode,
553  /* registers like d_mode, memory like b_mode.  */
554  db_mode,
555  /* registers like d_mode, memory like w_mode.  */
556  dw_mode,
557  /* registers like dq_mode, memory like d_mode.  */
558  dqd_mode,
559  /* normal vex mode */
560  vex_mode,
561  /* 128bit vex mode */
562  vex128_mode,
563  /* 256bit vex mode */
564  vex256_mode,
565  /* operand size depends on the VEX.W bit.  */
566  vex_w_dq_mode,
567
568  /* Similar to vex_w_dq_mode, with VSIB dword indices.  */
569  vex_vsib_d_w_dq_mode,
570  /* Similar to vex_vsib_d_w_dq_mode, with smaller memory.  */
571  vex_vsib_d_w_d_mode,
572  /* Similar to vex_w_dq_mode, with VSIB qword indices.  */
573  vex_vsib_q_w_dq_mode,
574  /* Similar to vex_vsib_q_w_dq_mode, with smaller memory.  */
575  vex_vsib_q_w_d_mode,
576
577  /* scalar, ignore vector length.  */
578  scalar_mode,
579  /* like d_mode, ignore vector length.  */
580  d_scalar_mode,
581  /* like d_swap_mode, ignore vector length.  */
582  d_scalar_swap_mode,
583  /* like q_mode, ignore vector length.  */
584  q_scalar_mode,
585  /* like q_swap_mode, ignore vector length.  */
586  q_scalar_swap_mode,
587  /* like vex_mode, ignore vector length.  */
588  vex_scalar_mode,
589  /* like vex_w_dq_mode, ignore vector length.  */
590  vex_scalar_w_dq_mode,
591
592  /* Static rounding.  */
593  evex_rounding_mode,
594  /* Supress all exceptions.  */
595  evex_sae_mode,
596
597  /* Mask register operand.  */
598  mask_mode,
599  /* Mask register operand.  */
600  mask_bd_mode,
601
602  es_reg,
603  cs_reg,
604  ss_reg,
605  ds_reg,
606  fs_reg,
607  gs_reg,
608
609  eAX_reg,
610  eCX_reg,
611  eDX_reg,
612  eBX_reg,
613  eSP_reg,
614  eBP_reg,
615  eSI_reg,
616  eDI_reg,
617
618  al_reg,
619  cl_reg,
620  dl_reg,
621  bl_reg,
622  ah_reg,
623  ch_reg,
624  dh_reg,
625  bh_reg,
626
627  ax_reg,
628  cx_reg,
629  dx_reg,
630  bx_reg,
631  sp_reg,
632  bp_reg,
633  si_reg,
634  di_reg,
635
636  rAX_reg,
637  rCX_reg,
638  rDX_reg,
639  rBX_reg,
640  rSP_reg,
641  rBP_reg,
642  rSI_reg,
643  rDI_reg,
644
645  z_mode_ax_reg,
646  indir_dx_reg
647};
648
649enum
650{
651  FLOATCODE = 1,
652  USE_REG_TABLE,
653  USE_MOD_TABLE,
654  USE_RM_TABLE,
655  USE_PREFIX_TABLE,
656  USE_X86_64_TABLE,
657  USE_3BYTE_TABLE,
658  USE_XOP_8F_TABLE,
659  USE_VEX_C4_TABLE,
660  USE_VEX_C5_TABLE,
661  USE_VEX_LEN_TABLE,
662  USE_VEX_W_TABLE,
663  USE_EVEX_TABLE
664};
665
666#define FLOAT			NULL, { { NULL, FLOATCODE } }
667
668#define DIS386(T, I)		NULL, { { NULL, (T)}, { NULL,  (I) } }
669#define REG_TABLE(I)		DIS386 (USE_REG_TABLE, (I))
670#define MOD_TABLE(I)		DIS386 (USE_MOD_TABLE, (I))
671#define RM_TABLE(I)		DIS386 (USE_RM_TABLE, (I))
672#define PREFIX_TABLE(I)		DIS386 (USE_PREFIX_TABLE, (I))
673#define X86_64_TABLE(I)		DIS386 (USE_X86_64_TABLE, (I))
674#define THREE_BYTE_TABLE(I)	DIS386 (USE_3BYTE_TABLE, (I))
675#define XOP_8F_TABLE(I)		DIS386 (USE_XOP_8F_TABLE, (I))
676#define VEX_C4_TABLE(I)		DIS386 (USE_VEX_C4_TABLE, (I))
677#define VEX_C5_TABLE(I)		DIS386 (USE_VEX_C5_TABLE, (I))
678#define VEX_LEN_TABLE(I)	DIS386 (USE_VEX_LEN_TABLE, (I))
679#define VEX_W_TABLE(I)		DIS386 (USE_VEX_W_TABLE, (I))
680#define EVEX_TABLE(I)		DIS386 (USE_EVEX_TABLE, (I))
681
682enum
683{
684  REG_80 = 0,
685  REG_81,
686  REG_82,
687  REG_8F,
688  REG_C0,
689  REG_C1,
690  REG_C6,
691  REG_C7,
692  REG_D0,
693  REG_D1,
694  REG_D2,
695  REG_D3,
696  REG_F6,
697  REG_F7,
698  REG_FE,
699  REG_FF,
700  REG_0F00,
701  REG_0F01,
702  REG_0F0D,
703  REG_0F18,
704  REG_0F71,
705  REG_0F72,
706  REG_0F73,
707  REG_0FA6,
708  REG_0FA7,
709  REG_0FAE,
710  REG_0FBA,
711  REG_0FC7,
712  REG_VEX_0F71,
713  REG_VEX_0F72,
714  REG_VEX_0F73,
715  REG_VEX_0FAE,
716  REG_VEX_0F38F3,
717  REG_XOP_LWPCB,
718  REG_XOP_LWP,
719  REG_XOP_TBM_01,
720  REG_XOP_TBM_02,
721
722  REG_EVEX_0F71,
723  REG_EVEX_0F72,
724  REG_EVEX_0F73,
725  REG_EVEX_0F38C6,
726  REG_EVEX_0F38C7
727};
728
729enum
730{
731  MOD_8D = 0,
732  MOD_C6_REG_7,
733  MOD_C7_REG_7,
734  MOD_FF_REG_3,
735  MOD_FF_REG_5,
736  MOD_0F01_REG_0,
737  MOD_0F01_REG_1,
738  MOD_0F01_REG_2,
739  MOD_0F01_REG_3,
740  MOD_0F01_REG_7,
741  MOD_0F12_PREFIX_0,
742  MOD_0F13,
743  MOD_0F16_PREFIX_0,
744  MOD_0F17,
745  MOD_0F18_REG_0,
746  MOD_0F18_REG_1,
747  MOD_0F18_REG_2,
748  MOD_0F18_REG_3,
749  MOD_0F18_REG_4,
750  MOD_0F18_REG_5,
751  MOD_0F18_REG_6,
752  MOD_0F18_REG_7,
753  MOD_0F1A_PREFIX_0,
754  MOD_0F1B_PREFIX_0,
755  MOD_0F1B_PREFIX_1,
756  MOD_0F24,
757  MOD_0F26,
758  MOD_0F2B_PREFIX_0,
759  MOD_0F2B_PREFIX_1,
760  MOD_0F2B_PREFIX_2,
761  MOD_0F2B_PREFIX_3,
762  MOD_0F51,
763  MOD_0F71_REG_2,
764  MOD_0F71_REG_4,
765  MOD_0F71_REG_6,
766  MOD_0F72_REG_2,
767  MOD_0F72_REG_4,
768  MOD_0F72_REG_6,
769  MOD_0F73_REG_2,
770  MOD_0F73_REG_3,
771  MOD_0F73_REG_6,
772  MOD_0F73_REG_7,
773  MOD_0FAE_REG_0,
774  MOD_0FAE_REG_1,
775  MOD_0FAE_REG_2,
776  MOD_0FAE_REG_3,
777  MOD_0FAE_REG_4,
778  MOD_0FAE_REG_5,
779  MOD_0FAE_REG_6,
780  MOD_0FAE_REG_7,
781  MOD_0FB2,
782  MOD_0FB4,
783  MOD_0FB5,
784  MOD_0FC7_REG_3,
785  MOD_0FC7_REG_4,
786  MOD_0FC7_REG_5,
787  MOD_0FC7_REG_6,
788  MOD_0FC7_REG_7,
789  MOD_0FD7,
790  MOD_0FE7_PREFIX_2,
791  MOD_0FF0_PREFIX_3,
792  MOD_0F382A_PREFIX_2,
793  MOD_62_32BIT,
794  MOD_C4_32BIT,
795  MOD_C5_32BIT,
796  MOD_VEX_0F12_PREFIX_0,
797  MOD_VEX_0F13,
798  MOD_VEX_0F16_PREFIX_0,
799  MOD_VEX_0F17,
800  MOD_VEX_0F2B,
801  MOD_VEX_0F50,
802  MOD_VEX_0F71_REG_2,
803  MOD_VEX_0F71_REG_4,
804  MOD_VEX_0F71_REG_6,
805  MOD_VEX_0F72_REG_2,
806  MOD_VEX_0F72_REG_4,
807  MOD_VEX_0F72_REG_6,
808  MOD_VEX_0F73_REG_2,
809  MOD_VEX_0F73_REG_3,
810  MOD_VEX_0F73_REG_6,
811  MOD_VEX_0F73_REG_7,
812  MOD_VEX_0FAE_REG_2,
813  MOD_VEX_0FAE_REG_3,
814  MOD_VEX_0FD7_PREFIX_2,
815  MOD_VEX_0FE7_PREFIX_2,
816  MOD_VEX_0FF0_PREFIX_3,
817  MOD_VEX_0F381A_PREFIX_2,
818  MOD_VEX_0F382A_PREFIX_2,
819  MOD_VEX_0F382C_PREFIX_2,
820  MOD_VEX_0F382D_PREFIX_2,
821  MOD_VEX_0F382E_PREFIX_2,
822  MOD_VEX_0F382F_PREFIX_2,
823  MOD_VEX_0F385A_PREFIX_2,
824  MOD_VEX_0F388C_PREFIX_2,
825  MOD_VEX_0F388E_PREFIX_2,
826
827  MOD_EVEX_0F10_PREFIX_1,
828  MOD_EVEX_0F10_PREFIX_3,
829  MOD_EVEX_0F11_PREFIX_1,
830  MOD_EVEX_0F11_PREFIX_3,
831  MOD_EVEX_0F12_PREFIX_0,
832  MOD_EVEX_0F16_PREFIX_0,
833  MOD_EVEX_0F38C6_REG_1,
834  MOD_EVEX_0F38C6_REG_2,
835  MOD_EVEX_0F38C6_REG_5,
836  MOD_EVEX_0F38C6_REG_6,
837  MOD_EVEX_0F38C7_REG_1,
838  MOD_EVEX_0F38C7_REG_2,
839  MOD_EVEX_0F38C7_REG_5,
840  MOD_EVEX_0F38C7_REG_6
841};
842
843enum
844{
845  RM_C6_REG_7 = 0,
846  RM_C7_REG_7,
847  RM_0F01_REG_0,
848  RM_0F01_REG_1,
849  RM_0F01_REG_2,
850  RM_0F01_REG_3,
851  RM_0F01_REG_7,
852  RM_0FAE_REG_5,
853  RM_0FAE_REG_6,
854  RM_0FAE_REG_7
855};
856
857enum
858{
859  PREFIX_90 = 0,
860  PREFIX_0F10,
861  PREFIX_0F11,
862  PREFIX_0F12,
863  PREFIX_0F16,
864  PREFIX_0F1A,
865  PREFIX_0F1B,
866  PREFIX_0F2A,
867  PREFIX_0F2B,
868  PREFIX_0F2C,
869  PREFIX_0F2D,
870  PREFIX_0F2E,
871  PREFIX_0F2F,
872  PREFIX_0F51,
873  PREFIX_0F52,
874  PREFIX_0F53,
875  PREFIX_0F58,
876  PREFIX_0F59,
877  PREFIX_0F5A,
878  PREFIX_0F5B,
879  PREFIX_0F5C,
880  PREFIX_0F5D,
881  PREFIX_0F5E,
882  PREFIX_0F5F,
883  PREFIX_0F60,
884  PREFIX_0F61,
885  PREFIX_0F62,
886  PREFIX_0F6C,
887  PREFIX_0F6D,
888  PREFIX_0F6F,
889  PREFIX_0F70,
890  PREFIX_0F73_REG_3,
891  PREFIX_0F73_REG_7,
892  PREFIX_0F78,
893  PREFIX_0F79,
894  PREFIX_0F7C,
895  PREFIX_0F7D,
896  PREFIX_0F7E,
897  PREFIX_0F7F,
898  PREFIX_0FAE_REG_0,
899  PREFIX_0FAE_REG_1,
900  PREFIX_0FAE_REG_2,
901  PREFIX_0FAE_REG_3,
902  PREFIX_0FAE_REG_6,
903  PREFIX_0FAE_REG_7,
904  PREFIX_RM_0_0FAE_REG_7,
905  PREFIX_0FB8,
906  PREFIX_0FBC,
907  PREFIX_0FBD,
908  PREFIX_0FC2,
909  PREFIX_0FC3,
910  PREFIX_0FC7_REG_6,
911  PREFIX_0FD0,
912  PREFIX_0FD6,
913  PREFIX_0FE6,
914  PREFIX_0FE7,
915  PREFIX_0FF0,
916  PREFIX_0FF7,
917  PREFIX_0F3810,
918  PREFIX_0F3814,
919  PREFIX_0F3815,
920  PREFIX_0F3817,
921  PREFIX_0F3820,
922  PREFIX_0F3821,
923  PREFIX_0F3822,
924  PREFIX_0F3823,
925  PREFIX_0F3824,
926  PREFIX_0F3825,
927  PREFIX_0F3828,
928  PREFIX_0F3829,
929  PREFIX_0F382A,
930  PREFIX_0F382B,
931  PREFIX_0F3830,
932  PREFIX_0F3831,
933  PREFIX_0F3832,
934  PREFIX_0F3833,
935  PREFIX_0F3834,
936  PREFIX_0F3835,
937  PREFIX_0F3837,
938  PREFIX_0F3838,
939  PREFIX_0F3839,
940  PREFIX_0F383A,
941  PREFIX_0F383B,
942  PREFIX_0F383C,
943  PREFIX_0F383D,
944  PREFIX_0F383E,
945  PREFIX_0F383F,
946  PREFIX_0F3840,
947  PREFIX_0F3841,
948  PREFIX_0F3880,
949  PREFIX_0F3881,
950  PREFIX_0F3882,
951  PREFIX_0F38C8,
952  PREFIX_0F38C9,
953  PREFIX_0F38CA,
954  PREFIX_0F38CB,
955  PREFIX_0F38CC,
956  PREFIX_0F38CD,
957  PREFIX_0F38DB,
958  PREFIX_0F38DC,
959  PREFIX_0F38DD,
960  PREFIX_0F38DE,
961  PREFIX_0F38DF,
962  PREFIX_0F38F0,
963  PREFIX_0F38F1,
964  PREFIX_0F38F6,
965  PREFIX_0F3A08,
966  PREFIX_0F3A09,
967  PREFIX_0F3A0A,
968  PREFIX_0F3A0B,
969  PREFIX_0F3A0C,
970  PREFIX_0F3A0D,
971  PREFIX_0F3A0E,
972  PREFIX_0F3A14,
973  PREFIX_0F3A15,
974  PREFIX_0F3A16,
975  PREFIX_0F3A17,
976  PREFIX_0F3A20,
977  PREFIX_0F3A21,
978  PREFIX_0F3A22,
979  PREFIX_0F3A40,
980  PREFIX_0F3A41,
981  PREFIX_0F3A42,
982  PREFIX_0F3A44,
983  PREFIX_0F3A60,
984  PREFIX_0F3A61,
985  PREFIX_0F3A62,
986  PREFIX_0F3A63,
987  PREFIX_0F3ACC,
988  PREFIX_0F3ADF,
989  PREFIX_VEX_0F10,
990  PREFIX_VEX_0F11,
991  PREFIX_VEX_0F12,
992  PREFIX_VEX_0F16,
993  PREFIX_VEX_0F2A,
994  PREFIX_VEX_0F2C,
995  PREFIX_VEX_0F2D,
996  PREFIX_VEX_0F2E,
997  PREFIX_VEX_0F2F,
998  PREFIX_VEX_0F41,
999  PREFIX_VEX_0F42,
1000  PREFIX_VEX_0F44,
1001  PREFIX_VEX_0F45,
1002  PREFIX_VEX_0F46,
1003  PREFIX_VEX_0F47,
1004  PREFIX_VEX_0F4A,
1005  PREFIX_VEX_0F4B,
1006  PREFIX_VEX_0F51,
1007  PREFIX_VEX_0F52,
1008  PREFIX_VEX_0F53,
1009  PREFIX_VEX_0F58,
1010  PREFIX_VEX_0F59,
1011  PREFIX_VEX_0F5A,
1012  PREFIX_VEX_0F5B,
1013  PREFIX_VEX_0F5C,
1014  PREFIX_VEX_0F5D,
1015  PREFIX_VEX_0F5E,
1016  PREFIX_VEX_0F5F,
1017  PREFIX_VEX_0F60,
1018  PREFIX_VEX_0F61,
1019  PREFIX_VEX_0F62,
1020  PREFIX_VEX_0F63,
1021  PREFIX_VEX_0F64,
1022  PREFIX_VEX_0F65,
1023  PREFIX_VEX_0F66,
1024  PREFIX_VEX_0F67,
1025  PREFIX_VEX_0F68,
1026  PREFIX_VEX_0F69,
1027  PREFIX_VEX_0F6A,
1028  PREFIX_VEX_0F6B,
1029  PREFIX_VEX_0F6C,
1030  PREFIX_VEX_0F6D,
1031  PREFIX_VEX_0F6E,
1032  PREFIX_VEX_0F6F,
1033  PREFIX_VEX_0F70,
1034  PREFIX_VEX_0F71_REG_2,
1035  PREFIX_VEX_0F71_REG_4,
1036  PREFIX_VEX_0F71_REG_6,
1037  PREFIX_VEX_0F72_REG_2,
1038  PREFIX_VEX_0F72_REG_4,
1039  PREFIX_VEX_0F72_REG_6,
1040  PREFIX_VEX_0F73_REG_2,
1041  PREFIX_VEX_0F73_REG_3,
1042  PREFIX_VEX_0F73_REG_6,
1043  PREFIX_VEX_0F73_REG_7,
1044  PREFIX_VEX_0F74,
1045  PREFIX_VEX_0F75,
1046  PREFIX_VEX_0F76,
1047  PREFIX_VEX_0F77,
1048  PREFIX_VEX_0F7C,
1049  PREFIX_VEX_0F7D,
1050  PREFIX_VEX_0F7E,
1051  PREFIX_VEX_0F7F,
1052  PREFIX_VEX_0F90,
1053  PREFIX_VEX_0F91,
1054  PREFIX_VEX_0F92,
1055  PREFIX_VEX_0F93,
1056  PREFIX_VEX_0F98,
1057  PREFIX_VEX_0F99,
1058  PREFIX_VEX_0FC2,
1059  PREFIX_VEX_0FC4,
1060  PREFIX_VEX_0FC5,
1061  PREFIX_VEX_0FD0,
1062  PREFIX_VEX_0FD1,
1063  PREFIX_VEX_0FD2,
1064  PREFIX_VEX_0FD3,
1065  PREFIX_VEX_0FD4,
1066  PREFIX_VEX_0FD5,
1067  PREFIX_VEX_0FD6,
1068  PREFIX_VEX_0FD7,
1069  PREFIX_VEX_0FD8,
1070  PREFIX_VEX_0FD9,
1071  PREFIX_VEX_0FDA,
1072  PREFIX_VEX_0FDB,
1073  PREFIX_VEX_0FDC,
1074  PREFIX_VEX_0FDD,
1075  PREFIX_VEX_0FDE,
1076  PREFIX_VEX_0FDF,
1077  PREFIX_VEX_0FE0,
1078  PREFIX_VEX_0FE1,
1079  PREFIX_VEX_0FE2,
1080  PREFIX_VEX_0FE3,
1081  PREFIX_VEX_0FE4,
1082  PREFIX_VEX_0FE5,
1083  PREFIX_VEX_0FE6,
1084  PREFIX_VEX_0FE7,
1085  PREFIX_VEX_0FE8,
1086  PREFIX_VEX_0FE9,
1087  PREFIX_VEX_0FEA,
1088  PREFIX_VEX_0FEB,
1089  PREFIX_VEX_0FEC,
1090  PREFIX_VEX_0FED,
1091  PREFIX_VEX_0FEE,
1092  PREFIX_VEX_0FEF,
1093  PREFIX_VEX_0FF0,
1094  PREFIX_VEX_0FF1,
1095  PREFIX_VEX_0FF2,
1096  PREFIX_VEX_0FF3,
1097  PREFIX_VEX_0FF4,
1098  PREFIX_VEX_0FF5,
1099  PREFIX_VEX_0FF6,
1100  PREFIX_VEX_0FF7,
1101  PREFIX_VEX_0FF8,
1102  PREFIX_VEX_0FF9,
1103  PREFIX_VEX_0FFA,
1104  PREFIX_VEX_0FFB,
1105  PREFIX_VEX_0FFC,
1106  PREFIX_VEX_0FFD,
1107  PREFIX_VEX_0FFE,
1108  PREFIX_VEX_0F3800,
1109  PREFIX_VEX_0F3801,
1110  PREFIX_VEX_0F3802,
1111  PREFIX_VEX_0F3803,
1112  PREFIX_VEX_0F3804,
1113  PREFIX_VEX_0F3805,
1114  PREFIX_VEX_0F3806,
1115  PREFIX_VEX_0F3807,
1116  PREFIX_VEX_0F3808,
1117  PREFIX_VEX_0F3809,
1118  PREFIX_VEX_0F380A,
1119  PREFIX_VEX_0F380B,
1120  PREFIX_VEX_0F380C,
1121  PREFIX_VEX_0F380D,
1122  PREFIX_VEX_0F380E,
1123  PREFIX_VEX_0F380F,
1124  PREFIX_VEX_0F3813,
1125  PREFIX_VEX_0F3816,
1126  PREFIX_VEX_0F3817,
1127  PREFIX_VEX_0F3818,
1128  PREFIX_VEX_0F3819,
1129  PREFIX_VEX_0F381A,
1130  PREFIX_VEX_0F381C,
1131  PREFIX_VEX_0F381D,
1132  PREFIX_VEX_0F381E,
1133  PREFIX_VEX_0F3820,
1134  PREFIX_VEX_0F3821,
1135  PREFIX_VEX_0F3822,
1136  PREFIX_VEX_0F3823,
1137  PREFIX_VEX_0F3824,
1138  PREFIX_VEX_0F3825,
1139  PREFIX_VEX_0F3828,
1140  PREFIX_VEX_0F3829,
1141  PREFIX_VEX_0F382A,
1142  PREFIX_VEX_0F382B,
1143  PREFIX_VEX_0F382C,
1144  PREFIX_VEX_0F382D,
1145  PREFIX_VEX_0F382E,
1146  PREFIX_VEX_0F382F,
1147  PREFIX_VEX_0F3830,
1148  PREFIX_VEX_0F3831,
1149  PREFIX_VEX_0F3832,
1150  PREFIX_VEX_0F3833,
1151  PREFIX_VEX_0F3834,
1152  PREFIX_VEX_0F3835,
1153  PREFIX_VEX_0F3836,
1154  PREFIX_VEX_0F3837,
1155  PREFIX_VEX_0F3838,
1156  PREFIX_VEX_0F3839,
1157  PREFIX_VEX_0F383A,
1158  PREFIX_VEX_0F383B,
1159  PREFIX_VEX_0F383C,
1160  PREFIX_VEX_0F383D,
1161  PREFIX_VEX_0F383E,
1162  PREFIX_VEX_0F383F,
1163  PREFIX_VEX_0F3840,
1164  PREFIX_VEX_0F3841,
1165  PREFIX_VEX_0F3845,
1166  PREFIX_VEX_0F3846,
1167  PREFIX_VEX_0F3847,
1168  PREFIX_VEX_0F3858,
1169  PREFIX_VEX_0F3859,
1170  PREFIX_VEX_0F385A,
1171  PREFIX_VEX_0F3878,
1172  PREFIX_VEX_0F3879,
1173  PREFIX_VEX_0F388C,
1174  PREFIX_VEX_0F388E,
1175  PREFIX_VEX_0F3890,
1176  PREFIX_VEX_0F3891,
1177  PREFIX_VEX_0F3892,
1178  PREFIX_VEX_0F3893,
1179  PREFIX_VEX_0F3896,
1180  PREFIX_VEX_0F3897,
1181  PREFIX_VEX_0F3898,
1182  PREFIX_VEX_0F3899,
1183  PREFIX_VEX_0F389A,
1184  PREFIX_VEX_0F389B,
1185  PREFIX_VEX_0F389C,
1186  PREFIX_VEX_0F389D,
1187  PREFIX_VEX_0F389E,
1188  PREFIX_VEX_0F389F,
1189  PREFIX_VEX_0F38A6,
1190  PREFIX_VEX_0F38A7,
1191  PREFIX_VEX_0F38A8,
1192  PREFIX_VEX_0F38A9,
1193  PREFIX_VEX_0F38AA,
1194  PREFIX_VEX_0F38AB,
1195  PREFIX_VEX_0F38AC,
1196  PREFIX_VEX_0F38AD,
1197  PREFIX_VEX_0F38AE,
1198  PREFIX_VEX_0F38AF,
1199  PREFIX_VEX_0F38B6,
1200  PREFIX_VEX_0F38B7,
1201  PREFIX_VEX_0F38B8,
1202  PREFIX_VEX_0F38B9,
1203  PREFIX_VEX_0F38BA,
1204  PREFIX_VEX_0F38BB,
1205  PREFIX_VEX_0F38BC,
1206  PREFIX_VEX_0F38BD,
1207  PREFIX_VEX_0F38BE,
1208  PREFIX_VEX_0F38BF,
1209  PREFIX_VEX_0F38DB,
1210  PREFIX_VEX_0F38DC,
1211  PREFIX_VEX_0F38DD,
1212  PREFIX_VEX_0F38DE,
1213  PREFIX_VEX_0F38DF,
1214  PREFIX_VEX_0F38F2,
1215  PREFIX_VEX_0F38F3_REG_1,
1216  PREFIX_VEX_0F38F3_REG_2,
1217  PREFIX_VEX_0F38F3_REG_3,
1218  PREFIX_VEX_0F38F5,
1219  PREFIX_VEX_0F38F6,
1220  PREFIX_VEX_0F38F7,
1221  PREFIX_VEX_0F3A00,
1222  PREFIX_VEX_0F3A01,
1223  PREFIX_VEX_0F3A02,
1224  PREFIX_VEX_0F3A04,
1225  PREFIX_VEX_0F3A05,
1226  PREFIX_VEX_0F3A06,
1227  PREFIX_VEX_0F3A08,
1228  PREFIX_VEX_0F3A09,
1229  PREFIX_VEX_0F3A0A,
1230  PREFIX_VEX_0F3A0B,
1231  PREFIX_VEX_0F3A0C,
1232  PREFIX_VEX_0F3A0D,
1233  PREFIX_VEX_0F3A0E,
1234  PREFIX_VEX_0F3A0F,
1235  PREFIX_VEX_0F3A14,
1236  PREFIX_VEX_0F3A15,
1237  PREFIX_VEX_0F3A16,
1238  PREFIX_VEX_0F3A17,
1239  PREFIX_VEX_0F3A18,
1240  PREFIX_VEX_0F3A19,
1241  PREFIX_VEX_0F3A1D,
1242  PREFIX_VEX_0F3A20,
1243  PREFIX_VEX_0F3A21,
1244  PREFIX_VEX_0F3A22,
1245  PREFIX_VEX_0F3A30,
1246  PREFIX_VEX_0F3A31,
1247  PREFIX_VEX_0F3A32,
1248  PREFIX_VEX_0F3A33,
1249  PREFIX_VEX_0F3A38,
1250  PREFIX_VEX_0F3A39,
1251  PREFIX_VEX_0F3A40,
1252  PREFIX_VEX_0F3A41,
1253  PREFIX_VEX_0F3A42,
1254  PREFIX_VEX_0F3A44,
1255  PREFIX_VEX_0F3A46,
1256  PREFIX_VEX_0F3A48,
1257  PREFIX_VEX_0F3A49,
1258  PREFIX_VEX_0F3A4A,
1259  PREFIX_VEX_0F3A4B,
1260  PREFIX_VEX_0F3A4C,
1261  PREFIX_VEX_0F3A5C,
1262  PREFIX_VEX_0F3A5D,
1263  PREFIX_VEX_0F3A5E,
1264  PREFIX_VEX_0F3A5F,
1265  PREFIX_VEX_0F3A60,
1266  PREFIX_VEX_0F3A61,
1267  PREFIX_VEX_0F3A62,
1268  PREFIX_VEX_0F3A63,
1269  PREFIX_VEX_0F3A68,
1270  PREFIX_VEX_0F3A69,
1271  PREFIX_VEX_0F3A6A,
1272  PREFIX_VEX_0F3A6B,
1273  PREFIX_VEX_0F3A6C,
1274  PREFIX_VEX_0F3A6D,
1275  PREFIX_VEX_0F3A6E,
1276  PREFIX_VEX_0F3A6F,
1277  PREFIX_VEX_0F3A78,
1278  PREFIX_VEX_0F3A79,
1279  PREFIX_VEX_0F3A7A,
1280  PREFIX_VEX_0F3A7B,
1281  PREFIX_VEX_0F3A7C,
1282  PREFIX_VEX_0F3A7D,
1283  PREFIX_VEX_0F3A7E,
1284  PREFIX_VEX_0F3A7F,
1285  PREFIX_VEX_0F3ADF,
1286  PREFIX_VEX_0F3AF0,
1287
1288  PREFIX_EVEX_0F10,
1289  PREFIX_EVEX_0F11,
1290  PREFIX_EVEX_0F12,
1291  PREFIX_EVEX_0F13,
1292  PREFIX_EVEX_0F14,
1293  PREFIX_EVEX_0F15,
1294  PREFIX_EVEX_0F16,
1295  PREFIX_EVEX_0F17,
1296  PREFIX_EVEX_0F28,
1297  PREFIX_EVEX_0F29,
1298  PREFIX_EVEX_0F2A,
1299  PREFIX_EVEX_0F2B,
1300  PREFIX_EVEX_0F2C,
1301  PREFIX_EVEX_0F2D,
1302  PREFIX_EVEX_0F2E,
1303  PREFIX_EVEX_0F2F,
1304  PREFIX_EVEX_0F51,
1305  PREFIX_EVEX_0F54,
1306  PREFIX_EVEX_0F55,
1307  PREFIX_EVEX_0F56,
1308  PREFIX_EVEX_0F57,
1309  PREFIX_EVEX_0F58,
1310  PREFIX_EVEX_0F59,
1311  PREFIX_EVEX_0F5A,
1312  PREFIX_EVEX_0F5B,
1313  PREFIX_EVEX_0F5C,
1314  PREFIX_EVEX_0F5D,
1315  PREFIX_EVEX_0F5E,
1316  PREFIX_EVEX_0F5F,
1317  PREFIX_EVEX_0F60,
1318  PREFIX_EVEX_0F61,
1319  PREFIX_EVEX_0F62,
1320  PREFIX_EVEX_0F63,
1321  PREFIX_EVEX_0F64,
1322  PREFIX_EVEX_0F65,
1323  PREFIX_EVEX_0F66,
1324  PREFIX_EVEX_0F67,
1325  PREFIX_EVEX_0F68,
1326  PREFIX_EVEX_0F69,
1327  PREFIX_EVEX_0F6A,
1328  PREFIX_EVEX_0F6B,
1329  PREFIX_EVEX_0F6C,
1330  PREFIX_EVEX_0F6D,
1331  PREFIX_EVEX_0F6E,
1332  PREFIX_EVEX_0F6F,
1333  PREFIX_EVEX_0F70,
1334  PREFIX_EVEX_0F71_REG_2,
1335  PREFIX_EVEX_0F71_REG_4,
1336  PREFIX_EVEX_0F71_REG_6,
1337  PREFIX_EVEX_0F72_REG_0,
1338  PREFIX_EVEX_0F72_REG_1,
1339  PREFIX_EVEX_0F72_REG_2,
1340  PREFIX_EVEX_0F72_REG_4,
1341  PREFIX_EVEX_0F72_REG_6,
1342  PREFIX_EVEX_0F73_REG_2,
1343  PREFIX_EVEX_0F73_REG_3,
1344  PREFIX_EVEX_0F73_REG_6,
1345  PREFIX_EVEX_0F73_REG_7,
1346  PREFIX_EVEX_0F74,
1347  PREFIX_EVEX_0F75,
1348  PREFIX_EVEX_0F76,
1349  PREFIX_EVEX_0F78,
1350  PREFIX_EVEX_0F79,
1351  PREFIX_EVEX_0F7A,
1352  PREFIX_EVEX_0F7B,
1353  PREFIX_EVEX_0F7E,
1354  PREFIX_EVEX_0F7F,
1355  PREFIX_EVEX_0FC2,
1356  PREFIX_EVEX_0FC4,
1357  PREFIX_EVEX_0FC5,
1358  PREFIX_EVEX_0FC6,
1359  PREFIX_EVEX_0FD1,
1360  PREFIX_EVEX_0FD2,
1361  PREFIX_EVEX_0FD3,
1362  PREFIX_EVEX_0FD4,
1363  PREFIX_EVEX_0FD5,
1364  PREFIX_EVEX_0FD6,
1365  PREFIX_EVEX_0FD8,
1366  PREFIX_EVEX_0FD9,
1367  PREFIX_EVEX_0FDA,
1368  PREFIX_EVEX_0FDB,
1369  PREFIX_EVEX_0FDC,
1370  PREFIX_EVEX_0FDD,
1371  PREFIX_EVEX_0FDE,
1372  PREFIX_EVEX_0FDF,
1373  PREFIX_EVEX_0FE0,
1374  PREFIX_EVEX_0FE1,
1375  PREFIX_EVEX_0FE2,
1376  PREFIX_EVEX_0FE3,
1377  PREFIX_EVEX_0FE4,
1378  PREFIX_EVEX_0FE5,
1379  PREFIX_EVEX_0FE6,
1380  PREFIX_EVEX_0FE7,
1381  PREFIX_EVEX_0FE8,
1382  PREFIX_EVEX_0FE9,
1383  PREFIX_EVEX_0FEA,
1384  PREFIX_EVEX_0FEB,
1385  PREFIX_EVEX_0FEC,
1386  PREFIX_EVEX_0FED,
1387  PREFIX_EVEX_0FEE,
1388  PREFIX_EVEX_0FEF,
1389  PREFIX_EVEX_0FF1,
1390  PREFIX_EVEX_0FF2,
1391  PREFIX_EVEX_0FF3,
1392  PREFIX_EVEX_0FF4,
1393  PREFIX_EVEX_0FF5,
1394  PREFIX_EVEX_0FF6,
1395  PREFIX_EVEX_0FF8,
1396  PREFIX_EVEX_0FF9,
1397  PREFIX_EVEX_0FFA,
1398  PREFIX_EVEX_0FFB,
1399  PREFIX_EVEX_0FFC,
1400  PREFIX_EVEX_0FFD,
1401  PREFIX_EVEX_0FFE,
1402  PREFIX_EVEX_0F3800,
1403  PREFIX_EVEX_0F3804,
1404  PREFIX_EVEX_0F380B,
1405  PREFIX_EVEX_0F380C,
1406  PREFIX_EVEX_0F380D,
1407  PREFIX_EVEX_0F3810,
1408  PREFIX_EVEX_0F3811,
1409  PREFIX_EVEX_0F3812,
1410  PREFIX_EVEX_0F3813,
1411  PREFIX_EVEX_0F3814,
1412  PREFIX_EVEX_0F3815,
1413  PREFIX_EVEX_0F3816,
1414  PREFIX_EVEX_0F3818,
1415  PREFIX_EVEX_0F3819,
1416  PREFIX_EVEX_0F381A,
1417  PREFIX_EVEX_0F381B,
1418  PREFIX_EVEX_0F381C,
1419  PREFIX_EVEX_0F381D,
1420  PREFIX_EVEX_0F381E,
1421  PREFIX_EVEX_0F381F,
1422  PREFIX_EVEX_0F3820,
1423  PREFIX_EVEX_0F3821,
1424  PREFIX_EVEX_0F3822,
1425  PREFIX_EVEX_0F3823,
1426  PREFIX_EVEX_0F3824,
1427  PREFIX_EVEX_0F3825,
1428  PREFIX_EVEX_0F3826,
1429  PREFIX_EVEX_0F3827,
1430  PREFIX_EVEX_0F3828,
1431  PREFIX_EVEX_0F3829,
1432  PREFIX_EVEX_0F382A,
1433  PREFIX_EVEX_0F382B,
1434  PREFIX_EVEX_0F382C,
1435  PREFIX_EVEX_0F382D,
1436  PREFIX_EVEX_0F3830,
1437  PREFIX_EVEX_0F3831,
1438  PREFIX_EVEX_0F3832,
1439  PREFIX_EVEX_0F3833,
1440  PREFIX_EVEX_0F3834,
1441  PREFIX_EVEX_0F3835,
1442  PREFIX_EVEX_0F3836,
1443  PREFIX_EVEX_0F3837,
1444  PREFIX_EVEX_0F3838,
1445  PREFIX_EVEX_0F3839,
1446  PREFIX_EVEX_0F383A,
1447  PREFIX_EVEX_0F383B,
1448  PREFIX_EVEX_0F383C,
1449  PREFIX_EVEX_0F383D,
1450  PREFIX_EVEX_0F383E,
1451  PREFIX_EVEX_0F383F,
1452  PREFIX_EVEX_0F3840,
1453  PREFIX_EVEX_0F3842,
1454  PREFIX_EVEX_0F3843,
1455  PREFIX_EVEX_0F3844,
1456  PREFIX_EVEX_0F3845,
1457  PREFIX_EVEX_0F3846,
1458  PREFIX_EVEX_0F3847,
1459  PREFIX_EVEX_0F384C,
1460  PREFIX_EVEX_0F384D,
1461  PREFIX_EVEX_0F384E,
1462  PREFIX_EVEX_0F384F,
1463  PREFIX_EVEX_0F3858,
1464  PREFIX_EVEX_0F3859,
1465  PREFIX_EVEX_0F385A,
1466  PREFIX_EVEX_0F385B,
1467  PREFIX_EVEX_0F3864,
1468  PREFIX_EVEX_0F3865,
1469  PREFIX_EVEX_0F3866,
1470  PREFIX_EVEX_0F3875,
1471  PREFIX_EVEX_0F3876,
1472  PREFIX_EVEX_0F3877,
1473  PREFIX_EVEX_0F3878,
1474  PREFIX_EVEX_0F3879,
1475  PREFIX_EVEX_0F387A,
1476  PREFIX_EVEX_0F387B,
1477  PREFIX_EVEX_0F387C,
1478  PREFIX_EVEX_0F387D,
1479  PREFIX_EVEX_0F387E,
1480  PREFIX_EVEX_0F387F,
1481  PREFIX_EVEX_0F3883,
1482  PREFIX_EVEX_0F3888,
1483  PREFIX_EVEX_0F3889,
1484  PREFIX_EVEX_0F388A,
1485  PREFIX_EVEX_0F388B,
1486  PREFIX_EVEX_0F388D,
1487  PREFIX_EVEX_0F3890,
1488  PREFIX_EVEX_0F3891,
1489  PREFIX_EVEX_0F3892,
1490  PREFIX_EVEX_0F3893,
1491  PREFIX_EVEX_0F3896,
1492  PREFIX_EVEX_0F3897,
1493  PREFIX_EVEX_0F3898,
1494  PREFIX_EVEX_0F3899,
1495  PREFIX_EVEX_0F389A,
1496  PREFIX_EVEX_0F389B,
1497  PREFIX_EVEX_0F389C,
1498  PREFIX_EVEX_0F389D,
1499  PREFIX_EVEX_0F389E,
1500  PREFIX_EVEX_0F389F,
1501  PREFIX_EVEX_0F38A0,
1502  PREFIX_EVEX_0F38A1,
1503  PREFIX_EVEX_0F38A2,
1504  PREFIX_EVEX_0F38A3,
1505  PREFIX_EVEX_0F38A6,
1506  PREFIX_EVEX_0F38A7,
1507  PREFIX_EVEX_0F38A8,
1508  PREFIX_EVEX_0F38A9,
1509  PREFIX_EVEX_0F38AA,
1510  PREFIX_EVEX_0F38AB,
1511  PREFIX_EVEX_0F38AC,
1512  PREFIX_EVEX_0F38AD,
1513  PREFIX_EVEX_0F38AE,
1514  PREFIX_EVEX_0F38AF,
1515  PREFIX_EVEX_0F38B4,
1516  PREFIX_EVEX_0F38B5,
1517  PREFIX_EVEX_0F38B6,
1518  PREFIX_EVEX_0F38B7,
1519  PREFIX_EVEX_0F38B8,
1520  PREFIX_EVEX_0F38B9,
1521  PREFIX_EVEX_0F38BA,
1522  PREFIX_EVEX_0F38BB,
1523  PREFIX_EVEX_0F38BC,
1524  PREFIX_EVEX_0F38BD,
1525  PREFIX_EVEX_0F38BE,
1526  PREFIX_EVEX_0F38BF,
1527  PREFIX_EVEX_0F38C4,
1528  PREFIX_EVEX_0F38C6_REG_1,
1529  PREFIX_EVEX_0F38C6_REG_2,
1530  PREFIX_EVEX_0F38C6_REG_5,
1531  PREFIX_EVEX_0F38C6_REG_6,
1532  PREFIX_EVEX_0F38C7_REG_1,
1533  PREFIX_EVEX_0F38C7_REG_2,
1534  PREFIX_EVEX_0F38C7_REG_5,
1535  PREFIX_EVEX_0F38C7_REG_6,
1536  PREFIX_EVEX_0F38C8,
1537  PREFIX_EVEX_0F38CA,
1538  PREFIX_EVEX_0F38CB,
1539  PREFIX_EVEX_0F38CC,
1540  PREFIX_EVEX_0F38CD,
1541
1542  PREFIX_EVEX_0F3A00,
1543  PREFIX_EVEX_0F3A01,
1544  PREFIX_EVEX_0F3A03,
1545  PREFIX_EVEX_0F3A04,
1546  PREFIX_EVEX_0F3A05,
1547  PREFIX_EVEX_0F3A08,
1548  PREFIX_EVEX_0F3A09,
1549  PREFIX_EVEX_0F3A0A,
1550  PREFIX_EVEX_0F3A0B,
1551  PREFIX_EVEX_0F3A0F,
1552  PREFIX_EVEX_0F3A14,
1553  PREFIX_EVEX_0F3A15,
1554  PREFIX_EVEX_0F3A16,
1555  PREFIX_EVEX_0F3A17,
1556  PREFIX_EVEX_0F3A18,
1557  PREFIX_EVEX_0F3A19,
1558  PREFIX_EVEX_0F3A1A,
1559  PREFIX_EVEX_0F3A1B,
1560  PREFIX_EVEX_0F3A1D,
1561  PREFIX_EVEX_0F3A1E,
1562  PREFIX_EVEX_0F3A1F,
1563  PREFIX_EVEX_0F3A20,
1564  PREFIX_EVEX_0F3A21,
1565  PREFIX_EVEX_0F3A22,
1566  PREFIX_EVEX_0F3A23,
1567  PREFIX_EVEX_0F3A25,
1568  PREFIX_EVEX_0F3A26,
1569  PREFIX_EVEX_0F3A27,
1570  PREFIX_EVEX_0F3A38,
1571  PREFIX_EVEX_0F3A39,
1572  PREFIX_EVEX_0F3A3A,
1573  PREFIX_EVEX_0F3A3B,
1574  PREFIX_EVEX_0F3A3E,
1575  PREFIX_EVEX_0F3A3F,
1576  PREFIX_EVEX_0F3A42,
1577  PREFIX_EVEX_0F3A43,
1578  PREFIX_EVEX_0F3A50,
1579  PREFIX_EVEX_0F3A51,
1580  PREFIX_EVEX_0F3A54,
1581  PREFIX_EVEX_0F3A55,
1582  PREFIX_EVEX_0F3A56,
1583  PREFIX_EVEX_0F3A57,
1584  PREFIX_EVEX_0F3A66,
1585  PREFIX_EVEX_0F3A67
1586};
1587
1588enum
1589{
1590  X86_64_06 = 0,
1591  X86_64_07,
1592  X86_64_0D,
1593  X86_64_16,
1594  X86_64_17,
1595  X86_64_1E,
1596  X86_64_1F,
1597  X86_64_27,
1598  X86_64_2F,
1599  X86_64_37,
1600  X86_64_3F,
1601  X86_64_60,
1602  X86_64_61,
1603  X86_64_62,
1604  X86_64_63,
1605  X86_64_6D,
1606  X86_64_6F,
1607  X86_64_9A,
1608  X86_64_C4,
1609  X86_64_C5,
1610  X86_64_CE,
1611  X86_64_D4,
1612  X86_64_D5,
1613  X86_64_EA,
1614  X86_64_0F01_REG_0,
1615  X86_64_0F01_REG_1,
1616  X86_64_0F01_REG_2,
1617  X86_64_0F01_REG_3
1618};
1619
1620enum
1621{
1622  THREE_BYTE_0F38 = 0,
1623  THREE_BYTE_0F3A,
1624  THREE_BYTE_0F7A
1625};
1626
1627enum
1628{
1629  XOP_08 = 0,
1630  XOP_09,
1631  XOP_0A
1632};
1633
1634enum
1635{
1636  VEX_0F = 0,
1637  VEX_0F38,
1638  VEX_0F3A
1639};
1640
1641enum
1642{
1643  EVEX_0F = 0,
1644  EVEX_0F38,
1645  EVEX_0F3A
1646};
1647
1648enum
1649{
1650  VEX_LEN_0F10_P_1 = 0,
1651  VEX_LEN_0F10_P_3,
1652  VEX_LEN_0F11_P_1,
1653  VEX_LEN_0F11_P_3,
1654  VEX_LEN_0F12_P_0_M_0,
1655  VEX_LEN_0F12_P_0_M_1,
1656  VEX_LEN_0F12_P_2,
1657  VEX_LEN_0F13_M_0,
1658  VEX_LEN_0F16_P_0_M_0,
1659  VEX_LEN_0F16_P_0_M_1,
1660  VEX_LEN_0F16_P_2,
1661  VEX_LEN_0F17_M_0,
1662  VEX_LEN_0F2A_P_1,
1663  VEX_LEN_0F2A_P_3,
1664  VEX_LEN_0F2C_P_1,
1665  VEX_LEN_0F2C_P_3,
1666  VEX_LEN_0F2D_P_1,
1667  VEX_LEN_0F2D_P_3,
1668  VEX_LEN_0F2E_P_0,
1669  VEX_LEN_0F2E_P_2,
1670  VEX_LEN_0F2F_P_0,
1671  VEX_LEN_0F2F_P_2,
1672  VEX_LEN_0F41_P_0,
1673  VEX_LEN_0F41_P_2,
1674  VEX_LEN_0F42_P_0,
1675  VEX_LEN_0F42_P_2,
1676  VEX_LEN_0F44_P_0,
1677  VEX_LEN_0F44_P_2,
1678  VEX_LEN_0F45_P_0,
1679  VEX_LEN_0F45_P_2,
1680  VEX_LEN_0F46_P_0,
1681  VEX_LEN_0F46_P_2,
1682  VEX_LEN_0F47_P_0,
1683  VEX_LEN_0F47_P_2,
1684  VEX_LEN_0F4A_P_0,
1685  VEX_LEN_0F4A_P_2,
1686  VEX_LEN_0F4B_P_0,
1687  VEX_LEN_0F4B_P_2,
1688  VEX_LEN_0F51_P_1,
1689  VEX_LEN_0F51_P_3,
1690  VEX_LEN_0F52_P_1,
1691  VEX_LEN_0F53_P_1,
1692  VEX_LEN_0F58_P_1,
1693  VEX_LEN_0F58_P_3,
1694  VEX_LEN_0F59_P_1,
1695  VEX_LEN_0F59_P_3,
1696  VEX_LEN_0F5A_P_1,
1697  VEX_LEN_0F5A_P_3,
1698  VEX_LEN_0F5C_P_1,
1699  VEX_LEN_0F5C_P_3,
1700  VEX_LEN_0F5D_P_1,
1701  VEX_LEN_0F5D_P_3,
1702  VEX_LEN_0F5E_P_1,
1703  VEX_LEN_0F5E_P_3,
1704  VEX_LEN_0F5F_P_1,
1705  VEX_LEN_0F5F_P_3,
1706  VEX_LEN_0F6E_P_2,
1707  VEX_LEN_0F7E_P_1,
1708  VEX_LEN_0F7E_P_2,
1709  VEX_LEN_0F90_P_0,
1710  VEX_LEN_0F90_P_2,
1711  VEX_LEN_0F91_P_0,
1712  VEX_LEN_0F91_P_2,
1713  VEX_LEN_0F92_P_0,
1714  VEX_LEN_0F92_P_2,
1715  VEX_LEN_0F92_P_3,
1716  VEX_LEN_0F93_P_0,
1717  VEX_LEN_0F93_P_2,
1718  VEX_LEN_0F93_P_3,
1719  VEX_LEN_0F98_P_0,
1720  VEX_LEN_0F98_P_2,
1721  VEX_LEN_0F99_P_0,
1722  VEX_LEN_0F99_P_2,
1723  VEX_LEN_0FAE_R_2_M_0,
1724  VEX_LEN_0FAE_R_3_M_0,
1725  VEX_LEN_0FC2_P_1,
1726  VEX_LEN_0FC2_P_3,
1727  VEX_LEN_0FC4_P_2,
1728  VEX_LEN_0FC5_P_2,
1729  VEX_LEN_0FD6_P_2,
1730  VEX_LEN_0FF7_P_2,
1731  VEX_LEN_0F3816_P_2,
1732  VEX_LEN_0F3819_P_2,
1733  VEX_LEN_0F381A_P_2_M_0,
1734  VEX_LEN_0F3836_P_2,
1735  VEX_LEN_0F3841_P_2,
1736  VEX_LEN_0F385A_P_2_M_0,
1737  VEX_LEN_0F38DB_P_2,
1738  VEX_LEN_0F38DC_P_2,
1739  VEX_LEN_0F38DD_P_2,
1740  VEX_LEN_0F38DE_P_2,
1741  VEX_LEN_0F38DF_P_2,
1742  VEX_LEN_0F38F2_P_0,
1743  VEX_LEN_0F38F3_R_1_P_0,
1744  VEX_LEN_0F38F3_R_2_P_0,
1745  VEX_LEN_0F38F3_R_3_P_0,
1746  VEX_LEN_0F38F5_P_0,
1747  VEX_LEN_0F38F5_P_1,
1748  VEX_LEN_0F38F5_P_3,
1749  VEX_LEN_0F38F6_P_3,
1750  VEX_LEN_0F38F7_P_0,
1751  VEX_LEN_0F38F7_P_1,
1752  VEX_LEN_0F38F7_P_2,
1753  VEX_LEN_0F38F7_P_3,
1754  VEX_LEN_0F3A00_P_2,
1755  VEX_LEN_0F3A01_P_2,
1756  VEX_LEN_0F3A06_P_2,
1757  VEX_LEN_0F3A0A_P_2,
1758  VEX_LEN_0F3A0B_P_2,
1759  VEX_LEN_0F3A14_P_2,
1760  VEX_LEN_0F3A15_P_2,
1761  VEX_LEN_0F3A16_P_2,
1762  VEX_LEN_0F3A17_P_2,
1763  VEX_LEN_0F3A18_P_2,
1764  VEX_LEN_0F3A19_P_2,
1765  VEX_LEN_0F3A20_P_2,
1766  VEX_LEN_0F3A21_P_2,
1767  VEX_LEN_0F3A22_P_2,
1768  VEX_LEN_0F3A30_P_2,
1769  VEX_LEN_0F3A31_P_2,
1770  VEX_LEN_0F3A32_P_2,
1771  VEX_LEN_0F3A33_P_2,
1772  VEX_LEN_0F3A38_P_2,
1773  VEX_LEN_0F3A39_P_2,
1774  VEX_LEN_0F3A41_P_2,
1775  VEX_LEN_0F3A44_P_2,
1776  VEX_LEN_0F3A46_P_2,
1777  VEX_LEN_0F3A60_P_2,
1778  VEX_LEN_0F3A61_P_2,
1779  VEX_LEN_0F3A62_P_2,
1780  VEX_LEN_0F3A63_P_2,
1781  VEX_LEN_0F3A6A_P_2,
1782  VEX_LEN_0F3A6B_P_2,
1783  VEX_LEN_0F3A6E_P_2,
1784  VEX_LEN_0F3A6F_P_2,
1785  VEX_LEN_0F3A7A_P_2,
1786  VEX_LEN_0F3A7B_P_2,
1787  VEX_LEN_0F3A7E_P_2,
1788  VEX_LEN_0F3A7F_P_2,
1789  VEX_LEN_0F3ADF_P_2,
1790  VEX_LEN_0F3AF0_P_3,
1791  VEX_LEN_0FXOP_08_CC,
1792  VEX_LEN_0FXOP_08_CD,
1793  VEX_LEN_0FXOP_08_CE,
1794  VEX_LEN_0FXOP_08_CF,
1795  VEX_LEN_0FXOP_08_EC,
1796  VEX_LEN_0FXOP_08_ED,
1797  VEX_LEN_0FXOP_08_EE,
1798  VEX_LEN_0FXOP_08_EF,
1799  VEX_LEN_0FXOP_09_80,
1800  VEX_LEN_0FXOP_09_81
1801};
1802
1803enum
1804{
1805  VEX_W_0F10_P_0 = 0,
1806  VEX_W_0F10_P_1,
1807  VEX_W_0F10_P_2,
1808  VEX_W_0F10_P_3,
1809  VEX_W_0F11_P_0,
1810  VEX_W_0F11_P_1,
1811  VEX_W_0F11_P_2,
1812  VEX_W_0F11_P_3,
1813  VEX_W_0F12_P_0_M_0,
1814  VEX_W_0F12_P_0_M_1,
1815  VEX_W_0F12_P_1,
1816  VEX_W_0F12_P_2,
1817  VEX_W_0F12_P_3,
1818  VEX_W_0F13_M_0,
1819  VEX_W_0F14,
1820  VEX_W_0F15,
1821  VEX_W_0F16_P_0_M_0,
1822  VEX_W_0F16_P_0_M_1,
1823  VEX_W_0F16_P_1,
1824  VEX_W_0F16_P_2,
1825  VEX_W_0F17_M_0,
1826  VEX_W_0F28,
1827  VEX_W_0F29,
1828  VEX_W_0F2B_M_0,
1829  VEX_W_0F2E_P_0,
1830  VEX_W_0F2E_P_2,
1831  VEX_W_0F2F_P_0,
1832  VEX_W_0F2F_P_2,
1833  VEX_W_0F41_P_0_LEN_1,
1834  VEX_W_0F41_P_2_LEN_1,
1835  VEX_W_0F42_P_0_LEN_1,
1836  VEX_W_0F42_P_2_LEN_1,
1837  VEX_W_0F44_P_0_LEN_0,
1838  VEX_W_0F44_P_2_LEN_0,
1839  VEX_W_0F45_P_0_LEN_1,
1840  VEX_W_0F45_P_2_LEN_1,
1841  VEX_W_0F46_P_0_LEN_1,
1842  VEX_W_0F46_P_2_LEN_1,
1843  VEX_W_0F47_P_0_LEN_1,
1844  VEX_W_0F47_P_2_LEN_1,
1845  VEX_W_0F4A_P_0_LEN_1,
1846  VEX_W_0F4A_P_2_LEN_1,
1847  VEX_W_0F4B_P_0_LEN_1,
1848  VEX_W_0F4B_P_2_LEN_1,
1849  VEX_W_0F50_M_0,
1850  VEX_W_0F51_P_0,
1851  VEX_W_0F51_P_1,
1852  VEX_W_0F51_P_2,
1853  VEX_W_0F51_P_3,
1854  VEX_W_0F52_P_0,
1855  VEX_W_0F52_P_1,
1856  VEX_W_0F53_P_0,
1857  VEX_W_0F53_P_1,
1858  VEX_W_0F58_P_0,
1859  VEX_W_0F58_P_1,
1860  VEX_W_0F58_P_2,
1861  VEX_W_0F58_P_3,
1862  VEX_W_0F59_P_0,
1863  VEX_W_0F59_P_1,
1864  VEX_W_0F59_P_2,
1865  VEX_W_0F59_P_3,
1866  VEX_W_0F5A_P_0,
1867  VEX_W_0F5A_P_1,
1868  VEX_W_0F5A_P_3,
1869  VEX_W_0F5B_P_0,
1870  VEX_W_0F5B_P_1,
1871  VEX_W_0F5B_P_2,
1872  VEX_W_0F5C_P_0,
1873  VEX_W_0F5C_P_1,
1874  VEX_W_0F5C_P_2,
1875  VEX_W_0F5C_P_3,
1876  VEX_W_0F5D_P_0,
1877  VEX_W_0F5D_P_1,
1878  VEX_W_0F5D_P_2,
1879  VEX_W_0F5D_P_3,
1880  VEX_W_0F5E_P_0,
1881  VEX_W_0F5E_P_1,
1882  VEX_W_0F5E_P_2,
1883  VEX_W_0F5E_P_3,
1884  VEX_W_0F5F_P_0,
1885  VEX_W_0F5F_P_1,
1886  VEX_W_0F5F_P_2,
1887  VEX_W_0F5F_P_3,
1888  VEX_W_0F60_P_2,
1889  VEX_W_0F61_P_2,
1890  VEX_W_0F62_P_2,
1891  VEX_W_0F63_P_2,
1892  VEX_W_0F64_P_2,
1893  VEX_W_0F65_P_2,
1894  VEX_W_0F66_P_2,
1895  VEX_W_0F67_P_2,
1896  VEX_W_0F68_P_2,
1897  VEX_W_0F69_P_2,
1898  VEX_W_0F6A_P_2,
1899  VEX_W_0F6B_P_2,
1900  VEX_W_0F6C_P_2,
1901  VEX_W_0F6D_P_2,
1902  VEX_W_0F6F_P_1,
1903  VEX_W_0F6F_P_2,
1904  VEX_W_0F70_P_1,
1905  VEX_W_0F70_P_2,
1906  VEX_W_0F70_P_3,
1907  VEX_W_0F71_R_2_P_2,
1908  VEX_W_0F71_R_4_P_2,
1909  VEX_W_0F71_R_6_P_2,
1910  VEX_W_0F72_R_2_P_2,
1911  VEX_W_0F72_R_4_P_2,
1912  VEX_W_0F72_R_6_P_2,
1913  VEX_W_0F73_R_2_P_2,
1914  VEX_W_0F73_R_3_P_2,
1915  VEX_W_0F73_R_6_P_2,
1916  VEX_W_0F73_R_7_P_2,
1917  VEX_W_0F74_P_2,
1918  VEX_W_0F75_P_2,
1919  VEX_W_0F76_P_2,
1920  VEX_W_0F77_P_0,
1921  VEX_W_0F7C_P_2,
1922  VEX_W_0F7C_P_3,
1923  VEX_W_0F7D_P_2,
1924  VEX_W_0F7D_P_3,
1925  VEX_W_0F7E_P_1,
1926  VEX_W_0F7F_P_1,
1927  VEX_W_0F7F_P_2,
1928  VEX_W_0F90_P_0_LEN_0,
1929  VEX_W_0F90_P_2_LEN_0,
1930  VEX_W_0F91_P_0_LEN_0,
1931  VEX_W_0F91_P_2_LEN_0,
1932  VEX_W_0F92_P_0_LEN_0,
1933  VEX_W_0F92_P_2_LEN_0,
1934  VEX_W_0F92_P_3_LEN_0,
1935  VEX_W_0F93_P_0_LEN_0,
1936  VEX_W_0F93_P_2_LEN_0,
1937  VEX_W_0F93_P_3_LEN_0,
1938  VEX_W_0F98_P_0_LEN_0,
1939  VEX_W_0F98_P_2_LEN_0,
1940  VEX_W_0F99_P_0_LEN_0,
1941  VEX_W_0F99_P_2_LEN_0,
1942  VEX_W_0FAE_R_2_M_0,
1943  VEX_W_0FAE_R_3_M_0,
1944  VEX_W_0FC2_P_0,
1945  VEX_W_0FC2_P_1,
1946  VEX_W_0FC2_P_2,
1947  VEX_W_0FC2_P_3,
1948  VEX_W_0FC4_P_2,
1949  VEX_W_0FC5_P_2,
1950  VEX_W_0FD0_P_2,
1951  VEX_W_0FD0_P_3,
1952  VEX_W_0FD1_P_2,
1953  VEX_W_0FD2_P_2,
1954  VEX_W_0FD3_P_2,
1955  VEX_W_0FD4_P_2,
1956  VEX_W_0FD5_P_2,
1957  VEX_W_0FD6_P_2,
1958  VEX_W_0FD7_P_2_M_1,
1959  VEX_W_0FD8_P_2,
1960  VEX_W_0FD9_P_2,
1961  VEX_W_0FDA_P_2,
1962  VEX_W_0FDB_P_2,
1963  VEX_W_0FDC_P_2,
1964  VEX_W_0FDD_P_2,
1965  VEX_W_0FDE_P_2,
1966  VEX_W_0FDF_P_2,
1967  VEX_W_0FE0_P_2,
1968  VEX_W_0FE1_P_2,
1969  VEX_W_0FE2_P_2,
1970  VEX_W_0FE3_P_2,
1971  VEX_W_0FE4_P_2,
1972  VEX_W_0FE5_P_2,
1973  VEX_W_0FE6_P_1,
1974  VEX_W_0FE6_P_2,
1975  VEX_W_0FE6_P_3,
1976  VEX_W_0FE7_P_2_M_0,
1977  VEX_W_0FE8_P_2,
1978  VEX_W_0FE9_P_2,
1979  VEX_W_0FEA_P_2,
1980  VEX_W_0FEB_P_2,
1981  VEX_W_0FEC_P_2,
1982  VEX_W_0FED_P_2,
1983  VEX_W_0FEE_P_2,
1984  VEX_W_0FEF_P_2,
1985  VEX_W_0FF0_P_3_M_0,
1986  VEX_W_0FF1_P_2,
1987  VEX_W_0FF2_P_2,
1988  VEX_W_0FF3_P_2,
1989  VEX_W_0FF4_P_2,
1990  VEX_W_0FF5_P_2,
1991  VEX_W_0FF6_P_2,
1992  VEX_W_0FF7_P_2,
1993  VEX_W_0FF8_P_2,
1994  VEX_W_0FF9_P_2,
1995  VEX_W_0FFA_P_2,
1996  VEX_W_0FFB_P_2,
1997  VEX_W_0FFC_P_2,
1998  VEX_W_0FFD_P_2,
1999  VEX_W_0FFE_P_2,
2000  VEX_W_0F3800_P_2,
2001  VEX_W_0F3801_P_2,
2002  VEX_W_0F3802_P_2,
2003  VEX_W_0F3803_P_2,
2004  VEX_W_0F3804_P_2,
2005  VEX_W_0F3805_P_2,
2006  VEX_W_0F3806_P_2,
2007  VEX_W_0F3807_P_2,
2008  VEX_W_0F3808_P_2,
2009  VEX_W_0F3809_P_2,
2010  VEX_W_0F380A_P_2,
2011  VEX_W_0F380B_P_2,
2012  VEX_W_0F380C_P_2,
2013  VEX_W_0F380D_P_2,
2014  VEX_W_0F380E_P_2,
2015  VEX_W_0F380F_P_2,
2016  VEX_W_0F3816_P_2,
2017  VEX_W_0F3817_P_2,
2018  VEX_W_0F3818_P_2,
2019  VEX_W_0F3819_P_2,
2020  VEX_W_0F381A_P_2_M_0,
2021  VEX_W_0F381C_P_2,
2022  VEX_W_0F381D_P_2,
2023  VEX_W_0F381E_P_2,
2024  VEX_W_0F3820_P_2,
2025  VEX_W_0F3821_P_2,
2026  VEX_W_0F3822_P_2,
2027  VEX_W_0F3823_P_2,
2028  VEX_W_0F3824_P_2,
2029  VEX_W_0F3825_P_2,
2030  VEX_W_0F3828_P_2,
2031  VEX_W_0F3829_P_2,
2032  VEX_W_0F382A_P_2_M_0,
2033  VEX_W_0F382B_P_2,
2034  VEX_W_0F382C_P_2_M_0,
2035  VEX_W_0F382D_P_2_M_0,
2036  VEX_W_0F382E_P_2_M_0,
2037  VEX_W_0F382F_P_2_M_0,
2038  VEX_W_0F3830_P_2,
2039  VEX_W_0F3831_P_2,
2040  VEX_W_0F3832_P_2,
2041  VEX_W_0F3833_P_2,
2042  VEX_W_0F3834_P_2,
2043  VEX_W_0F3835_P_2,
2044  VEX_W_0F3836_P_2,
2045  VEX_W_0F3837_P_2,
2046  VEX_W_0F3838_P_2,
2047  VEX_W_0F3839_P_2,
2048  VEX_W_0F383A_P_2,
2049  VEX_W_0F383B_P_2,
2050  VEX_W_0F383C_P_2,
2051  VEX_W_0F383D_P_2,
2052  VEX_W_0F383E_P_2,
2053  VEX_W_0F383F_P_2,
2054  VEX_W_0F3840_P_2,
2055  VEX_W_0F3841_P_2,
2056  VEX_W_0F3846_P_2,
2057  VEX_W_0F3858_P_2,
2058  VEX_W_0F3859_P_2,
2059  VEX_W_0F385A_P_2_M_0,
2060  VEX_W_0F3878_P_2,
2061  VEX_W_0F3879_P_2,
2062  VEX_W_0F38DB_P_2,
2063  VEX_W_0F38DC_P_2,
2064  VEX_W_0F38DD_P_2,
2065  VEX_W_0F38DE_P_2,
2066  VEX_W_0F38DF_P_2,
2067  VEX_W_0F3A00_P_2,
2068  VEX_W_0F3A01_P_2,
2069  VEX_W_0F3A02_P_2,
2070  VEX_W_0F3A04_P_2,
2071  VEX_W_0F3A05_P_2,
2072  VEX_W_0F3A06_P_2,
2073  VEX_W_0F3A08_P_2,
2074  VEX_W_0F3A09_P_2,
2075  VEX_W_0F3A0A_P_2,
2076  VEX_W_0F3A0B_P_2,
2077  VEX_W_0F3A0C_P_2,
2078  VEX_W_0F3A0D_P_2,
2079  VEX_W_0F3A0E_P_2,
2080  VEX_W_0F3A0F_P_2,
2081  VEX_W_0F3A14_P_2,
2082  VEX_W_0F3A15_P_2,
2083  VEX_W_0F3A18_P_2,
2084  VEX_W_0F3A19_P_2,
2085  VEX_W_0F3A20_P_2,
2086  VEX_W_0F3A21_P_2,
2087  VEX_W_0F3A30_P_2_LEN_0,
2088  VEX_W_0F3A31_P_2_LEN_0,
2089  VEX_W_0F3A32_P_2_LEN_0,
2090  VEX_W_0F3A33_P_2_LEN_0,
2091  VEX_W_0F3A38_P_2,
2092  VEX_W_0F3A39_P_2,
2093  VEX_W_0F3A40_P_2,
2094  VEX_W_0F3A41_P_2,
2095  VEX_W_0F3A42_P_2,
2096  VEX_W_0F3A44_P_2,
2097  VEX_W_0F3A46_P_2,
2098  VEX_W_0F3A48_P_2,
2099  VEX_W_0F3A49_P_2,
2100  VEX_W_0F3A4A_P_2,
2101  VEX_W_0F3A4B_P_2,
2102  VEX_W_0F3A4C_P_2,
2103  VEX_W_0F3A60_P_2,
2104  VEX_W_0F3A61_P_2,
2105  VEX_W_0F3A62_P_2,
2106  VEX_W_0F3A63_P_2,
2107  VEX_W_0F3ADF_P_2,
2108
2109  EVEX_W_0F10_P_0,
2110  EVEX_W_0F10_P_1_M_0,
2111  EVEX_W_0F10_P_1_M_1,
2112  EVEX_W_0F10_P_2,
2113  EVEX_W_0F10_P_3_M_0,
2114  EVEX_W_0F10_P_3_M_1,
2115  EVEX_W_0F11_P_0,
2116  EVEX_W_0F11_P_1_M_0,
2117  EVEX_W_0F11_P_1_M_1,
2118  EVEX_W_0F11_P_2,
2119  EVEX_W_0F11_P_3_M_0,
2120  EVEX_W_0F11_P_3_M_1,
2121  EVEX_W_0F12_P_0_M_0,
2122  EVEX_W_0F12_P_0_M_1,
2123  EVEX_W_0F12_P_1,
2124  EVEX_W_0F12_P_2,
2125  EVEX_W_0F12_P_3,
2126  EVEX_W_0F13_P_0,
2127  EVEX_W_0F13_P_2,
2128  EVEX_W_0F14_P_0,
2129  EVEX_W_0F14_P_2,
2130  EVEX_W_0F15_P_0,
2131  EVEX_W_0F15_P_2,
2132  EVEX_W_0F16_P_0_M_0,
2133  EVEX_W_0F16_P_0_M_1,
2134  EVEX_W_0F16_P_1,
2135  EVEX_W_0F16_P_2,
2136  EVEX_W_0F17_P_0,
2137  EVEX_W_0F17_P_2,
2138  EVEX_W_0F28_P_0,
2139  EVEX_W_0F28_P_2,
2140  EVEX_W_0F29_P_0,
2141  EVEX_W_0F29_P_2,
2142  EVEX_W_0F2A_P_1,
2143  EVEX_W_0F2A_P_3,
2144  EVEX_W_0F2B_P_0,
2145  EVEX_W_0F2B_P_2,
2146  EVEX_W_0F2E_P_0,
2147  EVEX_W_0F2E_P_2,
2148  EVEX_W_0F2F_P_0,
2149  EVEX_W_0F2F_P_2,
2150  EVEX_W_0F51_P_0,
2151  EVEX_W_0F51_P_1,
2152  EVEX_W_0F51_P_2,
2153  EVEX_W_0F51_P_3,
2154  EVEX_W_0F54_P_0,
2155  EVEX_W_0F54_P_2,
2156  EVEX_W_0F55_P_0,
2157  EVEX_W_0F55_P_2,
2158  EVEX_W_0F56_P_0,
2159  EVEX_W_0F56_P_2,
2160  EVEX_W_0F57_P_0,
2161  EVEX_W_0F57_P_2,
2162  EVEX_W_0F58_P_0,
2163  EVEX_W_0F58_P_1,
2164  EVEX_W_0F58_P_2,
2165  EVEX_W_0F58_P_3,
2166  EVEX_W_0F59_P_0,
2167  EVEX_W_0F59_P_1,
2168  EVEX_W_0F59_P_2,
2169  EVEX_W_0F59_P_3,
2170  EVEX_W_0F5A_P_0,
2171  EVEX_W_0F5A_P_1,
2172  EVEX_W_0F5A_P_2,
2173  EVEX_W_0F5A_P_3,
2174  EVEX_W_0F5B_P_0,
2175  EVEX_W_0F5B_P_1,
2176  EVEX_W_0F5B_P_2,
2177  EVEX_W_0F5C_P_0,
2178  EVEX_W_0F5C_P_1,
2179  EVEX_W_0F5C_P_2,
2180  EVEX_W_0F5C_P_3,
2181  EVEX_W_0F5D_P_0,
2182  EVEX_W_0F5D_P_1,
2183  EVEX_W_0F5D_P_2,
2184  EVEX_W_0F5D_P_3,
2185  EVEX_W_0F5E_P_0,
2186  EVEX_W_0F5E_P_1,
2187  EVEX_W_0F5E_P_2,
2188  EVEX_W_0F5E_P_3,
2189  EVEX_W_0F5F_P_0,
2190  EVEX_W_0F5F_P_1,
2191  EVEX_W_0F5F_P_2,
2192  EVEX_W_0F5F_P_3,
2193  EVEX_W_0F62_P_2,
2194  EVEX_W_0F66_P_2,
2195  EVEX_W_0F6A_P_2,
2196  EVEX_W_0F6B_P_2,
2197  EVEX_W_0F6C_P_2,
2198  EVEX_W_0F6D_P_2,
2199  EVEX_W_0F6E_P_2,
2200  EVEX_W_0F6F_P_1,
2201  EVEX_W_0F6F_P_2,
2202  EVEX_W_0F6F_P_3,
2203  EVEX_W_0F70_P_2,
2204  EVEX_W_0F72_R_2_P_2,
2205  EVEX_W_0F72_R_6_P_2,
2206  EVEX_W_0F73_R_2_P_2,
2207  EVEX_W_0F73_R_6_P_2,
2208  EVEX_W_0F76_P_2,
2209  EVEX_W_0F78_P_0,
2210  EVEX_W_0F78_P_2,
2211  EVEX_W_0F79_P_0,
2212  EVEX_W_0F79_P_2,
2213  EVEX_W_0F7A_P_1,
2214  EVEX_W_0F7A_P_2,
2215  EVEX_W_0F7A_P_3,
2216  EVEX_W_0F7B_P_1,
2217  EVEX_W_0F7B_P_2,
2218  EVEX_W_0F7B_P_3,
2219  EVEX_W_0F7E_P_1,
2220  EVEX_W_0F7E_P_2,
2221  EVEX_W_0F7F_P_1,
2222  EVEX_W_0F7F_P_2,
2223  EVEX_W_0F7F_P_3,
2224  EVEX_W_0FC2_P_0,
2225  EVEX_W_0FC2_P_1,
2226  EVEX_W_0FC2_P_2,
2227  EVEX_W_0FC2_P_3,
2228  EVEX_W_0FC6_P_0,
2229  EVEX_W_0FC6_P_2,
2230  EVEX_W_0FD2_P_2,
2231  EVEX_W_0FD3_P_2,
2232  EVEX_W_0FD4_P_2,
2233  EVEX_W_0FD6_P_2,
2234  EVEX_W_0FE6_P_1,
2235  EVEX_W_0FE6_P_2,
2236  EVEX_W_0FE6_P_3,
2237  EVEX_W_0FE7_P_2,
2238  EVEX_W_0FF2_P_2,
2239  EVEX_W_0FF3_P_2,
2240  EVEX_W_0FF4_P_2,
2241  EVEX_W_0FFA_P_2,
2242  EVEX_W_0FFB_P_2,
2243  EVEX_W_0FFE_P_2,
2244  EVEX_W_0F380C_P_2,
2245  EVEX_W_0F380D_P_2,
2246  EVEX_W_0F3810_P_1,
2247  EVEX_W_0F3810_P_2,
2248  EVEX_W_0F3811_P_1,
2249  EVEX_W_0F3811_P_2,
2250  EVEX_W_0F3812_P_1,
2251  EVEX_W_0F3812_P_2,
2252  EVEX_W_0F3813_P_1,
2253  EVEX_W_0F3813_P_2,
2254  EVEX_W_0F3814_P_1,
2255  EVEX_W_0F3815_P_1,
2256  EVEX_W_0F3818_P_2,
2257  EVEX_W_0F3819_P_2,
2258  EVEX_W_0F381A_P_2,
2259  EVEX_W_0F381B_P_2,
2260  EVEX_W_0F381E_P_2,
2261  EVEX_W_0F381F_P_2,
2262  EVEX_W_0F3820_P_1,
2263  EVEX_W_0F3821_P_1,
2264  EVEX_W_0F3822_P_1,
2265  EVEX_W_0F3823_P_1,
2266  EVEX_W_0F3824_P_1,
2267  EVEX_W_0F3825_P_1,
2268  EVEX_W_0F3825_P_2,
2269  EVEX_W_0F3826_P_1,
2270  EVEX_W_0F3826_P_2,
2271  EVEX_W_0F3828_P_1,
2272  EVEX_W_0F3828_P_2,
2273  EVEX_W_0F3829_P_1,
2274  EVEX_W_0F3829_P_2,
2275  EVEX_W_0F382A_P_1,
2276  EVEX_W_0F382A_P_2,
2277  EVEX_W_0F382B_P_2,
2278  EVEX_W_0F3830_P_1,
2279  EVEX_W_0F3831_P_1,
2280  EVEX_W_0F3832_P_1,
2281  EVEX_W_0F3833_P_1,
2282  EVEX_W_0F3834_P_1,
2283  EVEX_W_0F3835_P_1,
2284  EVEX_W_0F3835_P_2,
2285  EVEX_W_0F3837_P_2,
2286  EVEX_W_0F3838_P_1,
2287  EVEX_W_0F3839_P_1,
2288  EVEX_W_0F383A_P_1,
2289  EVEX_W_0F3840_P_2,
2290  EVEX_W_0F3858_P_2,
2291  EVEX_W_0F3859_P_2,
2292  EVEX_W_0F385A_P_2,
2293  EVEX_W_0F385B_P_2,
2294  EVEX_W_0F3866_P_2,
2295  EVEX_W_0F3875_P_2,
2296  EVEX_W_0F3878_P_2,
2297  EVEX_W_0F3879_P_2,
2298  EVEX_W_0F387A_P_2,
2299  EVEX_W_0F387B_P_2,
2300  EVEX_W_0F387D_P_2,
2301  EVEX_W_0F3883_P_2,
2302  EVEX_W_0F388D_P_2,
2303  EVEX_W_0F3891_P_2,
2304  EVEX_W_0F3893_P_2,
2305  EVEX_W_0F38A1_P_2,
2306  EVEX_W_0F38A3_P_2,
2307  EVEX_W_0F38C7_R_1_P_2,
2308  EVEX_W_0F38C7_R_2_P_2,
2309  EVEX_W_0F38C7_R_5_P_2,
2310  EVEX_W_0F38C7_R_6_P_2,
2311
2312  EVEX_W_0F3A00_P_2,
2313  EVEX_W_0F3A01_P_2,
2314  EVEX_W_0F3A04_P_2,
2315  EVEX_W_0F3A05_P_2,
2316  EVEX_W_0F3A08_P_2,
2317  EVEX_W_0F3A09_P_2,
2318  EVEX_W_0F3A0A_P_2,
2319  EVEX_W_0F3A0B_P_2,
2320  EVEX_W_0F3A16_P_2,
2321  EVEX_W_0F3A18_P_2,
2322  EVEX_W_0F3A19_P_2,
2323  EVEX_W_0F3A1A_P_2,
2324  EVEX_W_0F3A1B_P_2,
2325  EVEX_W_0F3A1D_P_2,
2326  EVEX_W_0F3A21_P_2,
2327  EVEX_W_0F3A22_P_2,
2328  EVEX_W_0F3A23_P_2,
2329  EVEX_W_0F3A38_P_2,
2330  EVEX_W_0F3A39_P_2,
2331  EVEX_W_0F3A3A_P_2,
2332  EVEX_W_0F3A3B_P_2,
2333  EVEX_W_0F3A3E_P_2,
2334  EVEX_W_0F3A3F_P_2,
2335  EVEX_W_0F3A42_P_2,
2336  EVEX_W_0F3A43_P_2,
2337  EVEX_W_0F3A50_P_2,
2338  EVEX_W_0F3A51_P_2,
2339  EVEX_W_0F3A56_P_2,
2340  EVEX_W_0F3A57_P_2,
2341  EVEX_W_0F3A66_P_2,
2342  EVEX_W_0F3A67_P_2
2343};
2344
2345typedef void (*op_rtn) (int bytemode, int sizeflag);
2346
2347struct dis386 {
2348  const char *name;
2349  struct
2350    {
2351      op_rtn rtn;
2352      int bytemode;
2353    } op[MAX_OPERANDS];
2354};
2355
2356/* Upper case letters in the instruction names here are macros.
2357   'A' => print 'b' if no register operands or suffix_always is true
2358   'B' => print 'b' if suffix_always is true
2359   'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2360	  size prefix
2361   'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2362	  suffix_always is true
2363   'E' => print 'e' if 32-bit form of jcxz
2364   'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2365   'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2366   'H' => print ",pt" or ",pn" branch hint
2367   'I' => honor following macro letter even in Intel mode (implemented only
2368	  for some of the macro letters)
2369   'J' => print 'l'
2370   'K' => print 'd' or 'q' if rex prefix is present.
2371   'L' => print 'l' if suffix_always is true
2372   'M' => print 'r' if intel_mnemonic is false.
2373   'N' => print 'n' if instruction has no wait "prefix"
2374   'O' => print 'd' or 'o' (or 'q' in Intel mode)
2375   'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2376	  or suffix_always is true.  print 'q' if rex prefix is present.
2377   'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2378	  is true
2379   'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2380   'S' => print 'w', 'l' or 'q' if suffix_always is true
2381   'T' => print 'q' in 64bit mode and behave as 'P' otherwise
2382   'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
2383   'V' => print 'q' in 64bit mode and behave as 'S' otherwise
2384   'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2385   'X' => print 's', 'd' depending on data16 prefix (for XMM)
2386   'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2387	  suffix_always is true.
2388   'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2389   '!' => change condition from true to false or from false to true.
2390   '%' => add 1 upper case letter to the macro.
2391
2392   2 upper case letter macros:
2393   "XY" => print 'x' or 'y' if no register operands or suffix_always
2394	   is true.
2395   "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2396   "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2397	   or suffix_always is true
2398   "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2399   "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2400   "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2401   "LW" => print 'd', 'q' depending on the VEX.W bit
2402   "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2403	   an operand size prefix, or suffix_always is true.  print
2404	   'q' if rex prefix is present.
2405
2406   Many of the above letters print nothing in Intel mode.  See "putop"
2407   for the details.
2408
2409   Braces '{' and '}', and vertical bars '|', indicate alternative
2410   mnemonic strings for AT&T and Intel.  */
2411
2412static const struct dis386 dis386[] = {
2413  /* 00 */
2414  { "addB",		{ Ebh1, Gb } },
2415  { "addS",		{ Evh1, Gv } },
2416  { "addB",		{ Gb, EbS } },
2417  { "addS",		{ Gv, EvS } },
2418  { "addB",		{ AL, Ib } },
2419  { "addS",		{ eAX, Iv } },
2420  { X86_64_TABLE (X86_64_06) },
2421  { X86_64_TABLE (X86_64_07) },
2422  /* 08 */
2423  { "orB",		{ Ebh1, Gb } },
2424  { "orS",		{ Evh1, Gv } },
2425  { "orB",		{ Gb, EbS } },
2426  { "orS",		{ Gv, EvS } },
2427  { "orB",		{ AL, Ib } },
2428  { "orS",		{ eAX, Iv } },
2429  { X86_64_TABLE (X86_64_0D) },
2430  { Bad_Opcode },	/* 0x0f extended opcode escape */
2431  /* 10 */
2432  { "adcB",		{ Ebh1, Gb } },
2433  { "adcS",		{ Evh1, Gv } },
2434  { "adcB",		{ Gb, EbS } },
2435  { "adcS",		{ Gv, EvS } },
2436  { "adcB",		{ AL, Ib } },
2437  { "adcS",		{ eAX, Iv } },
2438  { X86_64_TABLE (X86_64_16) },
2439  { X86_64_TABLE (X86_64_17) },
2440  /* 18 */
2441  { "sbbB",		{ Ebh1, Gb } },
2442  { "sbbS",		{ Evh1, Gv } },
2443  { "sbbB",		{ Gb, EbS } },
2444  { "sbbS",		{ Gv, EvS } },
2445  { "sbbB",		{ AL, Ib } },
2446  { "sbbS",		{ eAX, Iv } },
2447  { X86_64_TABLE (X86_64_1E) },
2448  { X86_64_TABLE (X86_64_1F) },
2449  /* 20 */
2450  { "andB",		{ Ebh1, Gb } },
2451  { "andS",		{ Evh1, Gv } },
2452  { "andB",		{ Gb, EbS } },
2453  { "andS",		{ Gv, EvS } },
2454  { "andB",		{ AL, Ib } },
2455  { "andS",		{ eAX, Iv } },
2456  { Bad_Opcode },	/* SEG ES prefix */
2457  { X86_64_TABLE (X86_64_27) },
2458  /* 28 */
2459  { "subB",		{ Ebh1, Gb } },
2460  { "subS",		{ Evh1, Gv } },
2461  { "subB",		{ Gb, EbS } },
2462  { "subS",		{ Gv, EvS } },
2463  { "subB",		{ AL, Ib } },
2464  { "subS",		{ eAX, Iv } },
2465  { Bad_Opcode },	/* SEG CS prefix */
2466  { X86_64_TABLE (X86_64_2F) },
2467  /* 30 */
2468  { "xorB",		{ Ebh1, Gb } },
2469  { "xorS",		{ Evh1, Gv } },
2470  { "xorB",		{ Gb, EbS } },
2471  { "xorS",		{ Gv, EvS } },
2472  { "xorB",		{ AL, Ib } },
2473  { "xorS",		{ eAX, Iv } },
2474  { Bad_Opcode },	/* SEG SS prefix */
2475  { X86_64_TABLE (X86_64_37) },
2476  /* 38 */
2477  { "cmpB",		{ Eb, Gb } },
2478  { "cmpS",		{ Ev, Gv } },
2479  { "cmpB",		{ Gb, EbS } },
2480  { "cmpS",		{ Gv, EvS } },
2481  { "cmpB",		{ AL, Ib } },
2482  { "cmpS",		{ eAX, Iv } },
2483  { Bad_Opcode },	/* SEG DS prefix */
2484  { X86_64_TABLE (X86_64_3F) },
2485  /* 40 */
2486  { "inc{S|}",		{ RMeAX } },
2487  { "inc{S|}",		{ RMeCX } },
2488  { "inc{S|}",		{ RMeDX } },
2489  { "inc{S|}",		{ RMeBX } },
2490  { "inc{S|}",		{ RMeSP } },
2491  { "inc{S|}",		{ RMeBP } },
2492  { "inc{S|}",		{ RMeSI } },
2493  { "inc{S|}",		{ RMeDI } },
2494  /* 48 */
2495  { "dec{S|}",		{ RMeAX } },
2496  { "dec{S|}",		{ RMeCX } },
2497  { "dec{S|}",		{ RMeDX } },
2498  { "dec{S|}",		{ RMeBX } },
2499  { "dec{S|}",		{ RMeSP } },
2500  { "dec{S|}",		{ RMeBP } },
2501  { "dec{S|}",		{ RMeSI } },
2502  { "dec{S|}",		{ RMeDI } },
2503  /* 50 */
2504  { "pushV",		{ RMrAX } },
2505  { "pushV",		{ RMrCX } },
2506  { "pushV",		{ RMrDX } },
2507  { "pushV",		{ RMrBX } },
2508  { "pushV",		{ RMrSP } },
2509  { "pushV",		{ RMrBP } },
2510  { "pushV",		{ RMrSI } },
2511  { "pushV",		{ RMrDI } },
2512  /* 58 */
2513  { "popV",		{ RMrAX } },
2514  { "popV",		{ RMrCX } },
2515  { "popV",		{ RMrDX } },
2516  { "popV",		{ RMrBX } },
2517  { "popV",		{ RMrSP } },
2518  { "popV",		{ RMrBP } },
2519  { "popV",		{ RMrSI } },
2520  { "popV",		{ RMrDI } },
2521  /* 60 */
2522  { X86_64_TABLE (X86_64_60) },
2523  { X86_64_TABLE (X86_64_61) },
2524  { X86_64_TABLE (X86_64_62) },
2525  { X86_64_TABLE (X86_64_63) },
2526  { Bad_Opcode },	/* seg fs */
2527  { Bad_Opcode },	/* seg gs */
2528  { Bad_Opcode },	/* op size prefix */
2529  { Bad_Opcode },	/* adr size prefix */
2530  /* 68 */
2531  { "pushT",		{ sIv } },
2532  { "imulS",		{ Gv, Ev, Iv } },
2533  { "pushT",		{ sIbT } },
2534  { "imulS",		{ Gv, Ev, sIb } },
2535  { "ins{b|}",		{ Ybr, indirDX } },
2536  { X86_64_TABLE (X86_64_6D) },
2537  { "outs{b|}",		{ indirDXr, Xb } },
2538  { X86_64_TABLE (X86_64_6F) },
2539  /* 70 */
2540  { "joH",		{ Jb, BND, cond_jump_flag } },
2541  { "jnoH",		{ Jb, BND, cond_jump_flag } },
2542  { "jbH",		{ Jb, BND, cond_jump_flag } },
2543  { "jaeH",		{ Jb, BND, cond_jump_flag } },
2544  { "jeH",		{ Jb, BND, cond_jump_flag } },
2545  { "jneH",		{ Jb, BND, cond_jump_flag } },
2546  { "jbeH",		{ Jb, BND, cond_jump_flag } },
2547  { "jaH",		{ Jb, BND, cond_jump_flag } },
2548  /* 78 */
2549  { "jsH",		{ Jb, BND, cond_jump_flag } },
2550  { "jnsH",		{ Jb, BND, cond_jump_flag } },
2551  { "jpH",		{ Jb, BND, cond_jump_flag } },
2552  { "jnpH",		{ Jb, BND, cond_jump_flag } },
2553  { "jlH",		{ Jb, BND, cond_jump_flag } },
2554  { "jgeH",		{ Jb, BND, cond_jump_flag } },
2555  { "jleH",		{ Jb, BND, cond_jump_flag } },
2556  { "jgH",		{ Jb, BND, cond_jump_flag } },
2557  /* 80 */
2558  { REG_TABLE (REG_80) },
2559  { REG_TABLE (REG_81) },
2560  { Bad_Opcode },
2561  { REG_TABLE (REG_82) },
2562  { "testB",		{ Eb, Gb } },
2563  { "testS",		{ Ev, Gv } },
2564  { "xchgB",		{ Ebh2, Gb } },
2565  { "xchgS",		{ Evh2, Gv } },
2566  /* 88 */
2567  { "movB",		{ Ebh3, Gb } },
2568  { "movS",		{ Evh3, Gv } },
2569  { "movB",		{ Gb, EbS } },
2570  { "movS",		{ Gv, EvS } },
2571  { "movD",		{ Sv, Sw } },
2572  { MOD_TABLE (MOD_8D) },
2573  { "movD",		{ Sw, Sv } },
2574  { REG_TABLE (REG_8F) },
2575  /* 90 */
2576  { PREFIX_TABLE (PREFIX_90) },
2577  { "xchgS",		{ RMeCX, eAX } },
2578  { "xchgS",		{ RMeDX, eAX } },
2579  { "xchgS",		{ RMeBX, eAX } },
2580  { "xchgS",		{ RMeSP, eAX } },
2581  { "xchgS",		{ RMeBP, eAX } },
2582  { "xchgS",		{ RMeSI, eAX } },
2583  { "xchgS",		{ RMeDI, eAX } },
2584  /* 98 */
2585  { "cW{t|}R",		{ XX } },
2586  { "cR{t|}O",		{ XX } },
2587  { X86_64_TABLE (X86_64_9A) },
2588  { Bad_Opcode },	/* fwait */
2589  { "pushfT",		{ XX } },
2590  { "popfT",		{ XX } },
2591  { "sahf",		{ XX } },
2592  { "lahf",		{ XX } },
2593  /* a0 */
2594  { "mov%LB",		{ AL, Ob } },
2595  { "mov%LS",		{ eAX, Ov } },
2596  { "mov%LB",		{ Ob, AL } },
2597  { "mov%LS",		{ Ov, eAX } },
2598  { "movs{b|}",		{ Ybr, Xb } },
2599  { "movs{R|}",		{ Yvr, Xv } },
2600  { "cmps{b|}",		{ Xb, Yb } },
2601  { "cmps{R|}",		{ Xv, Yv } },
2602  /* a8 */
2603  { "testB",		{ AL, Ib } },
2604  { "testS",		{ eAX, Iv } },
2605  { "stosB",		{ Ybr, AL } },
2606  { "stosS",		{ Yvr, eAX } },
2607  { "lodsB",		{ ALr, Xb } },
2608  { "lodsS",		{ eAXr, Xv } },
2609  { "scasB",		{ AL, Yb } },
2610  { "scasS",		{ eAX, Yv } },
2611  /* b0 */
2612  { "movB",		{ RMAL, Ib } },
2613  { "movB",		{ RMCL, Ib } },
2614  { "movB",		{ RMDL, Ib } },
2615  { "movB",		{ RMBL, Ib } },
2616  { "movB",		{ RMAH, Ib } },
2617  { "movB",		{ RMCH, Ib } },
2618  { "movB",		{ RMDH, Ib } },
2619  { "movB",		{ RMBH, Ib } },
2620  /* b8 */
2621  { "mov%LV",		{ RMeAX, Iv64 } },
2622  { "mov%LV",		{ RMeCX, Iv64 } },
2623  { "mov%LV",		{ RMeDX, Iv64 } },
2624  { "mov%LV",		{ RMeBX, Iv64 } },
2625  { "mov%LV",		{ RMeSP, Iv64 } },
2626  { "mov%LV",		{ RMeBP, Iv64 } },
2627  { "mov%LV",		{ RMeSI, Iv64 } },
2628  { "mov%LV",		{ RMeDI, Iv64 } },
2629  /* c0 */
2630  { REG_TABLE (REG_C0) },
2631  { REG_TABLE (REG_C1) },
2632  { "retT",		{ Iw, BND } },
2633  { "retT",		{ BND } },
2634  { X86_64_TABLE (X86_64_C4) },
2635  { X86_64_TABLE (X86_64_C5) },
2636  { REG_TABLE (REG_C6) },
2637  { REG_TABLE (REG_C7) },
2638  /* c8 */
2639  { "enterT",		{ Iw, Ib } },
2640  { "leaveT",		{ XX } },
2641  { "Jret{|f}P",	{ Iw } },
2642  { "Jret{|f}P",	{ XX } },
2643  { "int3",		{ XX } },
2644  { "int",		{ Ib } },
2645  { X86_64_TABLE (X86_64_CE) },
2646  { "iret%LP",		{ XX } },
2647  /* d0 */
2648  { REG_TABLE (REG_D0) },
2649  { REG_TABLE (REG_D1) },
2650  { REG_TABLE (REG_D2) },
2651  { REG_TABLE (REG_D3) },
2652  { X86_64_TABLE (X86_64_D4) },
2653  { X86_64_TABLE (X86_64_D5) },
2654  { Bad_Opcode },
2655  { "xlat",		{ DSBX } },
2656  /* d8 */
2657  { FLOAT },
2658  { FLOAT },
2659  { FLOAT },
2660  { FLOAT },
2661  { FLOAT },
2662  { FLOAT },
2663  { FLOAT },
2664  { FLOAT },
2665  /* e0 */
2666  { "loopneFH",		{ Jb, XX, loop_jcxz_flag } },
2667  { "loopeFH",		{ Jb, XX, loop_jcxz_flag } },
2668  { "loopFH",		{ Jb, XX, loop_jcxz_flag } },
2669  { "jEcxzH",		{ Jb, XX, loop_jcxz_flag } },
2670  { "inB",		{ AL, Ib } },
2671  { "inG",		{ zAX, Ib } },
2672  { "outB",		{ Ib, AL } },
2673  { "outG",		{ Ib, zAX } },
2674  /* e8 */
2675  { "callT",		{ Jv, BND } },
2676  { "jmpT",		{ Jv, BND } },
2677  { X86_64_TABLE (X86_64_EA) },
2678  { "jmp",		{ Jb, BND } },
2679  { "inB",		{ AL, indirDX } },
2680  { "inG",		{ zAX, indirDX } },
2681  { "outB",		{ indirDX, AL } },
2682  { "outG",		{ indirDX, zAX } },
2683  /* f0 */
2684  { Bad_Opcode },	/* lock prefix */
2685  { "icebp",		{ XX } },
2686  { Bad_Opcode },	/* repne */
2687  { Bad_Opcode },	/* repz */
2688  { "hlt",		{ XX } },
2689  { "cmc",		{ XX } },
2690  { REG_TABLE (REG_F6) },
2691  { REG_TABLE (REG_F7) },
2692  /* f8 */
2693  { "clc",		{ XX } },
2694  { "stc",		{ XX } },
2695  { "cli",		{ XX } },
2696  { "sti",		{ XX } },
2697  { "cld",		{ XX } },
2698  { "std",		{ XX } },
2699  { REG_TABLE (REG_FE) },
2700  { REG_TABLE (REG_FF) },
2701};
2702
2703static const struct dis386 dis386_twobyte[] = {
2704  /* 00 */
2705  { REG_TABLE (REG_0F00 ) },
2706  { REG_TABLE (REG_0F01 ) },
2707  { "larS",		{ Gv, Ew } },
2708  { "lslS",		{ Gv, Ew } },
2709  { Bad_Opcode },
2710  { "syscall",		{ XX } },
2711  { "clts",		{ XX } },
2712  { "sysret%LP",		{ XX } },
2713  /* 08 */
2714  { "invd",		{ XX } },
2715  { "wbinvd",		{ XX } },
2716  { Bad_Opcode },
2717  { "ud2",		{ XX } },
2718  { Bad_Opcode },
2719  { REG_TABLE (REG_0F0D) },
2720  { "femms",		{ XX } },
2721  { "",			{ MX, EM, OPSUF } }, /* See OP_3DNowSuffix.  */
2722  /* 10 */
2723  { PREFIX_TABLE (PREFIX_0F10) },
2724  { PREFIX_TABLE (PREFIX_0F11) },
2725  { PREFIX_TABLE (PREFIX_0F12) },
2726  { MOD_TABLE (MOD_0F13) },
2727  { "unpcklpX",		{ XM, EXx } },
2728  { "unpckhpX",		{ XM, EXx } },
2729  { PREFIX_TABLE (PREFIX_0F16) },
2730  { MOD_TABLE (MOD_0F17) },
2731  /* 18 */
2732  { REG_TABLE (REG_0F18) },
2733  { "nopQ",		{ Ev } },
2734  { PREFIX_TABLE (PREFIX_0F1A) },
2735  { PREFIX_TABLE (PREFIX_0F1B) },
2736  { "nopQ",		{ Ev } },
2737  { "nopQ",		{ Ev } },
2738  { "nopQ",		{ Ev } },
2739  { "nopQ",		{ Ev } },
2740  /* 20 */
2741  { "movZ",		{ Rm, Cm } },
2742  { "movZ",		{ Rm, Dm } },
2743  { "movZ",		{ Cm, Rm } },
2744  { "movZ",		{ Dm, Rm } },
2745  { MOD_TABLE (MOD_0F24) },
2746  { Bad_Opcode },
2747  { MOD_TABLE (MOD_0F26) },
2748  { Bad_Opcode },
2749  /* 28 */
2750  { "movapX",		{ XM, EXx } },
2751  { "movapX",		{ EXxS, XM } },
2752  { PREFIX_TABLE (PREFIX_0F2A) },
2753  { PREFIX_TABLE (PREFIX_0F2B) },
2754  { PREFIX_TABLE (PREFIX_0F2C) },
2755  { PREFIX_TABLE (PREFIX_0F2D) },
2756  { PREFIX_TABLE (PREFIX_0F2E) },
2757  { PREFIX_TABLE (PREFIX_0F2F) },
2758  /* 30 */
2759  { "wrmsr",		{ XX } },
2760  { "rdtsc",		{ XX } },
2761  { "rdmsr",		{ XX } },
2762  { "rdpmc",		{ XX } },
2763  { "sysenter",		{ XX } },
2764  { "sysexit",		{ XX } },
2765  { Bad_Opcode },
2766  { "getsec",		{ XX } },
2767  /* 38 */
2768  { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2769  { Bad_Opcode },
2770  { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2771  { Bad_Opcode },
2772  { Bad_Opcode },
2773  { Bad_Opcode },
2774  { Bad_Opcode },
2775  { Bad_Opcode },
2776  /* 40 */
2777  { "cmovoS",		{ Gv, Ev } },
2778  { "cmovnoS",		{ Gv, Ev } },
2779  { "cmovbS",		{ Gv, Ev } },
2780  { "cmovaeS",		{ Gv, Ev } },
2781  { "cmoveS",		{ Gv, Ev } },
2782  { "cmovneS",		{ Gv, Ev } },
2783  { "cmovbeS",		{ Gv, Ev } },
2784  { "cmovaS",		{ Gv, Ev } },
2785  /* 48 */
2786  { "cmovsS",		{ Gv, Ev } },
2787  { "cmovnsS",		{ Gv, Ev } },
2788  { "cmovpS",		{ Gv, Ev } },
2789  { "cmovnpS",		{ Gv, Ev } },
2790  { "cmovlS",		{ Gv, Ev } },
2791  { "cmovgeS",		{ Gv, Ev } },
2792  { "cmovleS",		{ Gv, Ev } },
2793  { "cmovgS",		{ Gv, Ev } },
2794  /* 50 */
2795  { MOD_TABLE (MOD_0F51) },
2796  { PREFIX_TABLE (PREFIX_0F51) },
2797  { PREFIX_TABLE (PREFIX_0F52) },
2798  { PREFIX_TABLE (PREFIX_0F53) },
2799  { "andpX",		{ XM, EXx } },
2800  { "andnpX",		{ XM, EXx } },
2801  { "orpX",		{ XM, EXx } },
2802  { "xorpX",		{ XM, EXx } },
2803  /* 58 */
2804  { PREFIX_TABLE (PREFIX_0F58) },
2805  { PREFIX_TABLE (PREFIX_0F59) },
2806  { PREFIX_TABLE (PREFIX_0F5A) },
2807  { PREFIX_TABLE (PREFIX_0F5B) },
2808  { PREFIX_TABLE (PREFIX_0F5C) },
2809  { PREFIX_TABLE (PREFIX_0F5D) },
2810  { PREFIX_TABLE (PREFIX_0F5E) },
2811  { PREFIX_TABLE (PREFIX_0F5F) },
2812  /* 60 */
2813  { PREFIX_TABLE (PREFIX_0F60) },
2814  { PREFIX_TABLE (PREFIX_0F61) },
2815  { PREFIX_TABLE (PREFIX_0F62) },
2816  { "packsswb",		{ MX, EM } },
2817  { "pcmpgtb",		{ MX, EM } },
2818  { "pcmpgtw",		{ MX, EM } },
2819  { "pcmpgtd",		{ MX, EM } },
2820  { "packuswb",		{ MX, EM } },
2821  /* 68 */
2822  { "punpckhbw",	{ MX, EM } },
2823  { "punpckhwd",	{ MX, EM } },
2824  { "punpckhdq",	{ MX, EM } },
2825  { "packssdw",		{ MX, EM } },
2826  { PREFIX_TABLE (PREFIX_0F6C) },
2827  { PREFIX_TABLE (PREFIX_0F6D) },
2828  { "movK",		{ MX, Edq } },
2829  { PREFIX_TABLE (PREFIX_0F6F) },
2830  /* 70 */
2831  { PREFIX_TABLE (PREFIX_0F70) },
2832  { REG_TABLE (REG_0F71) },
2833  { REG_TABLE (REG_0F72) },
2834  { REG_TABLE (REG_0F73) },
2835  { "pcmpeqb",		{ MX, EM } },
2836  { "pcmpeqw",		{ MX, EM } },
2837  { "pcmpeqd",		{ MX, EM } },
2838  { "emms",		{ XX } },
2839  /* 78 */
2840  { PREFIX_TABLE (PREFIX_0F78) },
2841  { PREFIX_TABLE (PREFIX_0F79) },
2842  { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2843  { Bad_Opcode },
2844  { PREFIX_TABLE (PREFIX_0F7C) },
2845  { PREFIX_TABLE (PREFIX_0F7D) },
2846  { PREFIX_TABLE (PREFIX_0F7E) },
2847  { PREFIX_TABLE (PREFIX_0F7F) },
2848  /* 80 */
2849  { "joH",		{ Jv, BND, cond_jump_flag } },
2850  { "jnoH",		{ Jv, BND, cond_jump_flag } },
2851  { "jbH",		{ Jv, BND, cond_jump_flag } },
2852  { "jaeH",		{ Jv, BND, cond_jump_flag } },
2853  { "jeH",		{ Jv, BND, cond_jump_flag } },
2854  { "jneH",		{ Jv, BND, cond_jump_flag } },
2855  { "jbeH",		{ Jv, BND, cond_jump_flag } },
2856  { "jaH",		{ Jv, BND, cond_jump_flag } },
2857  /* 88 */
2858  { "jsH",		{ Jv, BND, cond_jump_flag } },
2859  { "jnsH",		{ Jv, BND, cond_jump_flag } },
2860  { "jpH",		{ Jv, BND, cond_jump_flag } },
2861  { "jnpH",		{ Jv, BND, cond_jump_flag } },
2862  { "jlH",		{ Jv, BND, cond_jump_flag } },
2863  { "jgeH",		{ Jv, BND, cond_jump_flag } },
2864  { "jleH",		{ Jv, BND, cond_jump_flag } },
2865  { "jgH",		{ Jv, BND, cond_jump_flag } },
2866  /* 90 */
2867  { "seto",		{ Eb } },
2868  { "setno",		{ Eb } },
2869  { "setb",		{ Eb } },
2870  { "setae",		{ Eb } },
2871  { "sete",		{ Eb } },
2872  { "setne",		{ Eb } },
2873  { "setbe",		{ Eb } },
2874  { "seta",		{ Eb } },
2875  /* 98 */
2876  { "sets",		{ Eb } },
2877  { "setns",		{ Eb } },
2878  { "setp",		{ Eb } },
2879  { "setnp",		{ Eb } },
2880  { "setl",		{ Eb } },
2881  { "setge",		{ Eb } },
2882  { "setle",		{ Eb } },
2883  { "setg",		{ Eb } },
2884  /* a0 */
2885  { "pushT",		{ fs } },
2886  { "popT",		{ fs } },
2887  { "cpuid",		{ XX } },
2888  { "btS",		{ Ev, Gv } },
2889  { "shldS",		{ Ev, Gv, Ib } },
2890  { "shldS",		{ Ev, Gv, CL } },
2891  { REG_TABLE (REG_0FA6) },
2892  { REG_TABLE (REG_0FA7) },
2893  /* a8 */
2894  { "pushT",		{ gs } },
2895  { "popT",		{ gs } },
2896  { "rsm",		{ XX } },
2897  { "btsS",		{ Evh1, Gv } },
2898  { "shrdS",		{ Ev, Gv, Ib } },
2899  { "shrdS",		{ Ev, Gv, CL } },
2900  { REG_TABLE (REG_0FAE) },
2901  { "imulS",		{ Gv, Ev } },
2902  /* b0 */
2903  { "cmpxchgB",		{ Ebh1, Gb } },
2904  { "cmpxchgS",		{ Evh1, Gv } },
2905  { MOD_TABLE (MOD_0FB2) },
2906  { "btrS",		{ Evh1, Gv } },
2907  { MOD_TABLE (MOD_0FB4) },
2908  { MOD_TABLE (MOD_0FB5) },
2909  { "movz{bR|x}",	{ Gv, Eb } },
2910  { "movz{wR|x}",	{ Gv, Ew } }, /* yes, there really is movzww ! */
2911  /* b8 */
2912  { PREFIX_TABLE (PREFIX_0FB8) },
2913  { "ud1",		{ XX } },
2914  { REG_TABLE (REG_0FBA) },
2915  { "btcS",		{ Evh1, Gv } },
2916  { PREFIX_TABLE (PREFIX_0FBC) },
2917  { PREFIX_TABLE (PREFIX_0FBD) },
2918  { "movs{bR|x}",	{ Gv, Eb } },
2919  { "movs{wR|x}",	{ Gv, Ew } }, /* yes, there really is movsww ! */
2920  /* c0 */
2921  { "xaddB",		{ Ebh1, Gb } },
2922  { "xaddS",		{ Evh1, Gv } },
2923  { PREFIX_TABLE (PREFIX_0FC2) },
2924  { PREFIX_TABLE (PREFIX_0FC3) },
2925  { "pinsrw",		{ MX, Edqw, Ib } },
2926  { "pextrw",		{ Gdq, MS, Ib } },
2927  { "shufpX",		{ XM, EXx, Ib } },
2928  { REG_TABLE (REG_0FC7) },
2929  /* c8 */
2930  { "bswap",		{ RMeAX } },
2931  { "bswap",		{ RMeCX } },
2932  { "bswap",		{ RMeDX } },
2933  { "bswap",		{ RMeBX } },
2934  { "bswap",		{ RMeSP } },
2935  { "bswap",		{ RMeBP } },
2936  { "bswap",		{ RMeSI } },
2937  { "bswap",		{ RMeDI } },
2938  /* d0 */
2939  { PREFIX_TABLE (PREFIX_0FD0) },
2940  { "psrlw",		{ MX, EM } },
2941  { "psrld",		{ MX, EM } },
2942  { "psrlq",		{ MX, EM } },
2943  { "paddq",		{ MX, EM } },
2944  { "pmullw",		{ MX, EM } },
2945  { PREFIX_TABLE (PREFIX_0FD6) },
2946  { MOD_TABLE (MOD_0FD7) },
2947  /* d8 */
2948  { "psubusb",		{ MX, EM } },
2949  { "psubusw",		{ MX, EM } },
2950  { "pminub",		{ MX, EM } },
2951  { "pand",		{ MX, EM } },
2952  { "paddusb",		{ MX, EM } },
2953  { "paddusw",		{ MX, EM } },
2954  { "pmaxub",		{ MX, EM } },
2955  { "pandn",		{ MX, EM } },
2956  /* e0 */
2957  { "pavgb",		{ MX, EM } },
2958  { "psraw",		{ MX, EM } },
2959  { "psrad",		{ MX, EM } },
2960  { "pavgw",		{ MX, EM } },
2961  { "pmulhuw",		{ MX, EM } },
2962  { "pmulhw",		{ MX, EM } },
2963  { PREFIX_TABLE (PREFIX_0FE6) },
2964  { PREFIX_TABLE (PREFIX_0FE7) },
2965  /* e8 */
2966  { "psubsb",		{ MX, EM } },
2967  { "psubsw",		{ MX, EM } },
2968  { "pminsw",		{ MX, EM } },
2969  { "por",		{ MX, EM } },
2970  { "paddsb",		{ MX, EM } },
2971  { "paddsw",		{ MX, EM } },
2972  { "pmaxsw",		{ MX, EM } },
2973  { "pxor",		{ MX, EM } },
2974  /* f0 */
2975  { PREFIX_TABLE (PREFIX_0FF0) },
2976  { "psllw",		{ MX, EM } },
2977  { "pslld",		{ MX, EM } },
2978  { "psllq",		{ MX, EM } },
2979  { "pmuludq",		{ MX, EM } },
2980  { "pmaddwd",		{ MX, EM } },
2981  { "psadbw",		{ MX, EM } },
2982  { PREFIX_TABLE (PREFIX_0FF7) },
2983  /* f8 */
2984  { "psubb",		{ MX, EM } },
2985  { "psubw",		{ MX, EM } },
2986  { "psubd",		{ MX, EM } },
2987  { "psubq",		{ MX, EM } },
2988  { "paddb",		{ MX, EM } },
2989  { "paddw",		{ MX, EM } },
2990  { "paddd",		{ MX, EM } },
2991  { Bad_Opcode },
2992};
2993
2994static const unsigned char onebyte_has_modrm[256] = {
2995  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2996  /*       -------------------------------        */
2997  /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2998  /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2999  /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3000  /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3001  /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3002  /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3003  /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3004  /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3005  /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3006  /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3007  /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3008  /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3009  /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3010  /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3011  /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3012  /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
3013  /*       -------------------------------        */
3014  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3015};
3016
3017static const unsigned char twobyte_has_modrm[256] = {
3018  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3019  /*       -------------------------------        */
3020  /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3021  /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3022  /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3023  /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3024  /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3025  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3026  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3027  /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3028  /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3029  /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3030  /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3031  /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3032  /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3033  /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3034  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3035  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3036  /*       -------------------------------        */
3037  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3038};
3039
3040static const unsigned char twobyte_has_mandatory_prefix[256] = {
3041  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3042  /*       -------------------------------        */
3043  /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */
3044  /* 10 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* 1f */
3045  /* 20 */ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,0,0, /* 2f */
3046  /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3047  /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */
3048  /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3049  /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3050  /* 70 */ 1,0,0,0,1,1,1,1,0,0,1,1,1,1,1,1, /* 7f */
3051  /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3052  /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */
3053  /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */
3054  /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */
3055  /* c0 */ 0,0,1,1,1,1,1,0,0,0,0,0,0,0,0,0, /* cf */
3056  /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3057  /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3058  /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0  /* ff */
3059  /*       -------------------------------        */
3060  /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
3061};
3062
3063static char obuf[100];
3064static char *obufp;
3065static char *mnemonicendp;
3066static char scratchbuf[100];
3067static unsigned char *start_codep;
3068static unsigned char *insn_codep;
3069static unsigned char *codep;
3070static unsigned char *end_codep;
3071static int last_lock_prefix;
3072static int last_repz_prefix;
3073static int last_repnz_prefix;
3074static int last_data_prefix;
3075static int last_addr_prefix;
3076static int last_rex_prefix;
3077static int last_seg_prefix;
3078static int fwait_prefix;
3079/* The PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is mandatory.  */
3080static int mandatory_prefix;
3081/* The active segment register prefix.  */
3082static int active_seg_prefix;
3083#define MAX_CODE_LENGTH 15
3084/* We can up to 14 prefixes since the maximum instruction length is
3085   15bytes.  */
3086static int all_prefixes[MAX_CODE_LENGTH - 1];
3087static disassemble_info *the_info;
3088static struct
3089  {
3090    int mod;
3091    int reg;
3092    int rm;
3093  }
3094modrm;
3095static unsigned char need_modrm;
3096static struct
3097  {
3098    int scale;
3099    int index;
3100    int base;
3101  }
3102sib;
3103static struct
3104  {
3105    int register_specifier;
3106    int length;
3107    int prefix;
3108    int w;
3109    int evex;
3110    int r;
3111    int v;
3112    int mask_register_specifier;
3113    int zeroing;
3114    int ll;
3115    int b;
3116  }
3117vex;
3118static unsigned char need_vex;
3119static unsigned char need_vex_reg;
3120static unsigned char vex_w_done;
3121
3122struct op
3123  {
3124    const char *name;
3125    unsigned int len;
3126  };
3127
3128/* If we are accessing mod/rm/reg without need_modrm set, then the
3129   values are stale.  Hitting this abort likely indicates that you
3130   need to update onebyte_has_modrm or twobyte_has_modrm.  */
3131#define MODRM_CHECK  if (!need_modrm) abort ()
3132
3133static const char **names64;
3134static const char **names32;
3135static const char **names16;
3136static const char **names8;
3137static const char **names8rex;
3138static const char **names_seg;
3139static const char *index64;
3140static const char *index32;
3141static const char **index16;
3142static const char **names_bnd;
3143
3144static const char *intel_names64[] = {
3145  "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3146  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3147};
3148static const char *intel_names32[] = {
3149  "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3150  "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3151};
3152static const char *intel_names16[] = {
3153  "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3154  "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3155};
3156static const char *intel_names8[] = {
3157  "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3158};
3159static const char *intel_names8rex[] = {
3160  "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3161  "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3162};
3163static const char *intel_names_seg[] = {
3164  "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3165};
3166static const char *intel_index64 = "riz";
3167static const char *intel_index32 = "eiz";
3168static const char *intel_index16[] = {
3169  "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3170};
3171
3172static const char *att_names64[] = {
3173  "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3174  "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3175};
3176static const char *att_names32[] = {
3177  "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3178  "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3179};
3180static const char *att_names16[] = {
3181  "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3182  "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3183};
3184static const char *att_names8[] = {
3185  "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3186};
3187static const char *att_names8rex[] = {
3188  "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3189  "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3190};
3191static const char *att_names_seg[] = {
3192  "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3193};
3194static const char *att_index64 = "%riz";
3195static const char *att_index32 = "%eiz";
3196static const char *att_index16[] = {
3197  "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3198};
3199
3200static const char **names_mm;
3201static const char *intel_names_mm[] = {
3202  "mm0", "mm1", "mm2", "mm3",
3203  "mm4", "mm5", "mm6", "mm7"
3204};
3205static const char *att_names_mm[] = {
3206  "%mm0", "%mm1", "%mm2", "%mm3",
3207  "%mm4", "%mm5", "%mm6", "%mm7"
3208};
3209
3210static const char *intel_names_bnd[] = {
3211  "bnd0", "bnd1", "bnd2", "bnd3"
3212};
3213
3214static const char *att_names_bnd[] = {
3215  "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3216};
3217
3218static const char **names_xmm;
3219static const char *intel_names_xmm[] = {
3220  "xmm0", "xmm1", "xmm2", "xmm3",
3221  "xmm4", "xmm5", "xmm6", "xmm7",
3222  "xmm8", "xmm9", "xmm10", "xmm11",
3223  "xmm12", "xmm13", "xmm14", "xmm15",
3224  "xmm16", "xmm17", "xmm18", "xmm19",
3225  "xmm20", "xmm21", "xmm22", "xmm23",
3226  "xmm24", "xmm25", "xmm26", "xmm27",
3227  "xmm28", "xmm29", "xmm30", "xmm31"
3228};
3229static const char *att_names_xmm[] = {
3230  "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3231  "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3232  "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3233  "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3234  "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3235  "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3236  "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3237  "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3238};
3239
3240static const char **names_ymm;
3241static const char *intel_names_ymm[] = {
3242  "ymm0", "ymm1", "ymm2", "ymm3",
3243  "ymm4", "ymm5", "ymm6", "ymm7",
3244  "ymm8", "ymm9", "ymm10", "ymm11",
3245  "ymm12", "ymm13", "ymm14", "ymm15",
3246  "ymm16", "ymm17", "ymm18", "ymm19",
3247  "ymm20", "ymm21", "ymm22", "ymm23",
3248  "ymm24", "ymm25", "ymm26", "ymm27",
3249  "ymm28", "ymm29", "ymm30", "ymm31"
3250};
3251static const char *att_names_ymm[] = {
3252  "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3253  "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3254  "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3255  "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3256  "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3257  "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3258  "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3259  "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3260};
3261
3262static const char **names_zmm;
3263static const char *intel_names_zmm[] = {
3264  "zmm0", "zmm1", "zmm2", "zmm3",
3265  "zmm4", "zmm5", "zmm6", "zmm7",
3266  "zmm8", "zmm9", "zmm10", "zmm11",
3267  "zmm12", "zmm13", "zmm14", "zmm15",
3268  "zmm16", "zmm17", "zmm18", "zmm19",
3269  "zmm20", "zmm21", "zmm22", "zmm23",
3270  "zmm24", "zmm25", "zmm26", "zmm27",
3271  "zmm28", "zmm29", "zmm30", "zmm31"
3272};
3273static const char *att_names_zmm[] = {
3274  "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3275  "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3276  "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3277  "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3278  "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3279  "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3280  "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3281  "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3282};
3283
3284static const char **names_mask;
3285static const char *intel_names_mask[] = {
3286  "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3287};
3288static const char *att_names_mask[] = {
3289  "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3290};
3291
3292static const char *names_rounding[] =
3293{
3294  "{rn-sae}",
3295  "{rd-sae}",
3296  "{ru-sae}",
3297  "{rz-sae}"
3298};
3299
3300static const struct dis386 reg_table[][8] = {
3301  /* REG_80 */
3302  {
3303    { "addA",	{ Ebh1, Ib } },
3304    { "orA",	{ Ebh1, Ib } },
3305    { "adcA",	{ Ebh1, Ib } },
3306    { "sbbA",	{ Ebh1, Ib } },
3307    { "andA",	{ Ebh1, Ib } },
3308    { "subA",	{ Ebh1, Ib } },
3309    { "xorA",	{ Ebh1, Ib } },
3310    { "cmpA",	{ Eb, Ib } },
3311  },
3312  /* REG_81 */
3313  {
3314    { "addQ",	{ Evh1, Iv } },
3315    { "orQ",	{ Evh1, Iv } },
3316    { "adcQ",	{ Evh1, Iv } },
3317    { "sbbQ",	{ Evh1, Iv } },
3318    { "andQ",	{ Evh1, Iv } },
3319    { "subQ",	{ Evh1, Iv } },
3320    { "xorQ",	{ Evh1, Iv } },
3321    { "cmpQ",	{ Ev, Iv } },
3322  },
3323  /* REG_82 */
3324  {
3325    { "addQ",	{ Evh1, sIb } },
3326    { "orQ",	{ Evh1, sIb } },
3327    { "adcQ",	{ Evh1, sIb } },
3328    { "sbbQ",	{ Evh1, sIb } },
3329    { "andQ",	{ Evh1, sIb } },
3330    { "subQ",	{ Evh1, sIb } },
3331    { "xorQ",	{ Evh1, sIb } },
3332    { "cmpQ",	{ Ev, sIb } },
3333  },
3334  /* REG_8F */
3335  {
3336    { "popU",	{ stackEv } },
3337    { XOP_8F_TABLE (XOP_09) },
3338    { Bad_Opcode },
3339    { Bad_Opcode },
3340    { Bad_Opcode },
3341    { XOP_8F_TABLE (XOP_09) },
3342  },
3343  /* REG_C0 */
3344  {
3345    { "rolA",	{ Eb, Ib } },
3346    { "rorA",	{ Eb, Ib } },
3347    { "rclA",	{ Eb, Ib } },
3348    { "rcrA",	{ Eb, Ib } },
3349    { "shlA",	{ Eb, Ib } },
3350    { "shrA",	{ Eb, Ib } },
3351    { Bad_Opcode },
3352    { "sarA",	{ Eb, Ib } },
3353  },
3354  /* REG_C1 */
3355  {
3356    { "rolQ",	{ Ev, Ib } },
3357    { "rorQ",	{ Ev, Ib } },
3358    { "rclQ",	{ Ev, Ib } },
3359    { "rcrQ",	{ Ev, Ib } },
3360    { "shlQ",	{ Ev, Ib } },
3361    { "shrQ",	{ Ev, Ib } },
3362    { Bad_Opcode },
3363    { "sarQ",	{ Ev, Ib } },
3364  },
3365  /* REG_C6 */
3366  {
3367    { "movA",	{ Ebh3, Ib } },
3368    { Bad_Opcode },
3369    { Bad_Opcode },
3370    { Bad_Opcode },
3371    { Bad_Opcode },
3372    { Bad_Opcode },
3373    { Bad_Opcode },
3374    { MOD_TABLE (MOD_C6_REG_7) },
3375  },
3376  /* REG_C7 */
3377  {
3378    { "movQ",	{ Evh3, Iv } },
3379    { Bad_Opcode },
3380    { Bad_Opcode },
3381    { Bad_Opcode },
3382    { Bad_Opcode },
3383    { Bad_Opcode },
3384    { Bad_Opcode },
3385    { MOD_TABLE (MOD_C7_REG_7) },
3386  },
3387  /* REG_D0 */
3388  {
3389    { "rolA",	{ Eb, I1 } },
3390    { "rorA",	{ Eb, I1 } },
3391    { "rclA",	{ Eb, I1 } },
3392    { "rcrA",	{ Eb, I1 } },
3393    { "shlA",	{ Eb, I1 } },
3394    { "shrA",	{ Eb, I1 } },
3395    { Bad_Opcode },
3396    { "sarA",	{ Eb, I1 } },
3397  },
3398  /* REG_D1 */
3399  {
3400    { "rolQ",	{ Ev, I1 } },
3401    { "rorQ",	{ Ev, I1 } },
3402    { "rclQ",	{ Ev, I1 } },
3403    { "rcrQ",	{ Ev, I1 } },
3404    { "shlQ",	{ Ev, I1 } },
3405    { "shrQ",	{ Ev, I1 } },
3406    { Bad_Opcode },
3407    { "sarQ",	{ Ev, I1 } },
3408  },
3409  /* REG_D2 */
3410  {
3411    { "rolA",	{ Eb, CL } },
3412    { "rorA",	{ Eb, CL } },
3413    { "rclA",	{ Eb, CL } },
3414    { "rcrA",	{ Eb, CL } },
3415    { "shlA",	{ Eb, CL } },
3416    { "shrA",	{ Eb, CL } },
3417    { Bad_Opcode },
3418    { "sarA",	{ Eb, CL } },
3419  },
3420  /* REG_D3 */
3421  {
3422    { "rolQ",	{ Ev, CL } },
3423    { "rorQ",	{ Ev, CL } },
3424    { "rclQ",	{ Ev, CL } },
3425    { "rcrQ",	{ Ev, CL } },
3426    { "shlQ",	{ Ev, CL } },
3427    { "shrQ",	{ Ev, CL } },
3428    { Bad_Opcode },
3429    { "sarQ",	{ Ev, CL } },
3430  },
3431  /* REG_F6 */
3432  {
3433    { "testA",	{ Eb, Ib } },
3434    { Bad_Opcode },
3435    { "notA",	{ Ebh1 } },
3436    { "negA",	{ Ebh1 } },
3437    { "mulA",	{ Eb } },	/* Don't print the implicit %al register,  */
3438    { "imulA",	{ Eb } },	/* to distinguish these opcodes from other */
3439    { "divA",	{ Eb } },	/* mul/imul opcodes.  Do the same for div  */
3440    { "idivA",	{ Eb } },	/* and idiv for consistency.		   */
3441  },
3442  /* REG_F7 */
3443  {
3444    { "testQ",	{ Ev, Iv } },
3445    { Bad_Opcode },
3446    { "notQ",	{ Evh1 } },
3447    { "negQ",	{ Evh1 } },
3448    { "mulQ",	{ Ev } },	/* Don't print the implicit register.  */
3449    { "imulQ",	{ Ev } },
3450    { "divQ",	{ Ev } },
3451    { "idivQ",	{ Ev } },
3452  },
3453  /* REG_FE */
3454  {
3455    { "incA",	{ Ebh1 } },
3456    { "decA",	{ Ebh1 } },
3457  },
3458  /* REG_FF */
3459  {
3460    { "incQ",	{ Evh1 } },
3461    { "decQ",	{ Evh1 } },
3462    { "call{T|}", { indirEv, BND } },
3463    { MOD_TABLE (MOD_FF_REG_3) },
3464    { "jmp{T|}", { indirEv, BND } },
3465    { MOD_TABLE (MOD_FF_REG_5) },
3466    { "pushU",	{ stackEv } },
3467    { Bad_Opcode },
3468  },
3469  /* REG_0F00 */
3470  {
3471    { "sldtD",	{ Sv } },
3472    { "strD",	{ Sv } },
3473    { "lldt",	{ Ew } },
3474    { "ltr",	{ Ew } },
3475    { "verr",	{ Ew } },
3476    { "verw",	{ Ew } },
3477    { Bad_Opcode },
3478    { Bad_Opcode },
3479  },
3480  /* REG_0F01 */
3481  {
3482    { MOD_TABLE (MOD_0F01_REG_0) },
3483    { MOD_TABLE (MOD_0F01_REG_1) },
3484    { MOD_TABLE (MOD_0F01_REG_2) },
3485    { MOD_TABLE (MOD_0F01_REG_3) },
3486    { "smswD",	{ Sv } },
3487    { Bad_Opcode },
3488    { "lmsw",	{ Ew } },
3489    { MOD_TABLE (MOD_0F01_REG_7) },
3490  },
3491  /* REG_0F0D */
3492  {
3493    { "prefetch",	{ Mb } },
3494    { "prefetchw",	{ Mb } },
3495    { "prefetchwt1",	{ Mb } },
3496    { "prefetch",	{ Mb } },
3497    { "prefetch",	{ Mb } },
3498    { "prefetch",	{ Mb } },
3499    { "prefetch",	{ Mb } },
3500    { "prefetch",	{ Mb } },
3501  },
3502  /* REG_0F18 */
3503  {
3504    { MOD_TABLE (MOD_0F18_REG_0) },
3505    { MOD_TABLE (MOD_0F18_REG_1) },
3506    { MOD_TABLE (MOD_0F18_REG_2) },
3507    { MOD_TABLE (MOD_0F18_REG_3) },
3508    { MOD_TABLE (MOD_0F18_REG_4) },
3509    { MOD_TABLE (MOD_0F18_REG_5) },
3510    { MOD_TABLE (MOD_0F18_REG_6) },
3511    { MOD_TABLE (MOD_0F18_REG_7) },
3512  },
3513  /* REG_0F71 */
3514  {
3515    { Bad_Opcode },
3516    { Bad_Opcode },
3517    { MOD_TABLE (MOD_0F71_REG_2) },
3518    { Bad_Opcode },
3519    { MOD_TABLE (MOD_0F71_REG_4) },
3520    { Bad_Opcode },
3521    { MOD_TABLE (MOD_0F71_REG_6) },
3522  },
3523  /* REG_0F72 */
3524  {
3525    { Bad_Opcode },
3526    { Bad_Opcode },
3527    { MOD_TABLE (MOD_0F72_REG_2) },
3528    { Bad_Opcode },
3529    { MOD_TABLE (MOD_0F72_REG_4) },
3530    { Bad_Opcode },
3531    { MOD_TABLE (MOD_0F72_REG_6) },
3532  },
3533  /* REG_0F73 */
3534  {
3535    { Bad_Opcode },
3536    { Bad_Opcode },
3537    { MOD_TABLE (MOD_0F73_REG_2) },
3538    { MOD_TABLE (MOD_0F73_REG_3) },
3539    { Bad_Opcode },
3540    { Bad_Opcode },
3541    { MOD_TABLE (MOD_0F73_REG_6) },
3542    { MOD_TABLE (MOD_0F73_REG_7) },
3543  },
3544  /* REG_0FA6 */
3545  {
3546    { "montmul",	{ { OP_0f07, 0 } } },
3547    { "xsha1",		{ { OP_0f07, 0 } } },
3548    { "xsha256",	{ { OP_0f07, 0 } } },
3549  },
3550  /* REG_0FA7 */
3551  {
3552    { "xstore-rng",	{ { OP_0f07, 0 } } },
3553    { "xcrypt-ecb",	{ { OP_0f07, 0 } } },
3554    { "xcrypt-cbc",	{ { OP_0f07, 0 } } },
3555    { "xcrypt-ctr",	{ { OP_0f07, 0 } } },
3556    { "xcrypt-cfb",	{ { OP_0f07, 0 } } },
3557    { "xcrypt-ofb",	{ { OP_0f07, 0 } } },
3558  },
3559  /* REG_0FAE */
3560  {
3561    { MOD_TABLE (MOD_0FAE_REG_0) },
3562    { MOD_TABLE (MOD_0FAE_REG_1) },
3563    { MOD_TABLE (MOD_0FAE_REG_2) },
3564    { MOD_TABLE (MOD_0FAE_REG_3) },
3565    { MOD_TABLE (MOD_0FAE_REG_4) },
3566    { MOD_TABLE (MOD_0FAE_REG_5) },
3567    { MOD_TABLE (MOD_0FAE_REG_6) },
3568    { MOD_TABLE (MOD_0FAE_REG_7) },
3569  },
3570  /* REG_0FBA */
3571  {
3572    { Bad_Opcode },
3573    { Bad_Opcode },
3574    { Bad_Opcode },
3575    { Bad_Opcode },
3576    { "btQ",	{ Ev, Ib } },
3577    { "btsQ",	{ Evh1, Ib } },
3578    { "btrQ",	{ Evh1, Ib } },
3579    { "btcQ",	{ Evh1, Ib } },
3580  },
3581  /* REG_0FC7 */
3582  {
3583    { Bad_Opcode },
3584    { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
3585    { Bad_Opcode },
3586    { MOD_TABLE (MOD_0FC7_REG_3) },
3587    { MOD_TABLE (MOD_0FC7_REG_4) },
3588    { MOD_TABLE (MOD_0FC7_REG_5) },
3589    { MOD_TABLE (MOD_0FC7_REG_6) },
3590    { MOD_TABLE (MOD_0FC7_REG_7) },
3591  },
3592  /* REG_VEX_0F71 */
3593  {
3594    { Bad_Opcode },
3595    { Bad_Opcode },
3596    { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3597    { Bad_Opcode },
3598    { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3599    { Bad_Opcode },
3600    { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3601  },
3602  /* REG_VEX_0F72 */
3603  {
3604    { Bad_Opcode },
3605    { Bad_Opcode },
3606    { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3607    { Bad_Opcode },
3608    { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3609    { Bad_Opcode },
3610    { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3611  },
3612  /* REG_VEX_0F73 */
3613  {
3614    { Bad_Opcode },
3615    { Bad_Opcode },
3616    { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3617    { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3618    { Bad_Opcode },
3619    { Bad_Opcode },
3620    { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3621    { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3622  },
3623  /* REG_VEX_0FAE */
3624  {
3625    { Bad_Opcode },
3626    { Bad_Opcode },
3627    { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3628    { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3629  },
3630  /* REG_VEX_0F38F3 */
3631  {
3632    { Bad_Opcode },
3633    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3634    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3635    { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3636  },
3637  /* REG_XOP_LWPCB */
3638  {
3639    { "llwpcb", { { OP_LWPCB_E, 0 } } },
3640    { "slwpcb",	{ { OP_LWPCB_E, 0 } } },
3641  },
3642  /* REG_XOP_LWP */
3643  {
3644    { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
3645    { "lwpval",	{ { OP_LWP_E, 0 }, Ed, Iq } },
3646  },
3647  /* REG_XOP_TBM_01 */
3648  {
3649    { Bad_Opcode },
3650    { "blcfill",	{ { OP_LWP_E, 0 }, Ev } },
3651    { "blsfill",	{ { OP_LWP_E, 0 }, Ev } },
3652    { "blcs",	{ { OP_LWP_E, 0 }, Ev } },
3653    { "tzmsk",	{ { OP_LWP_E, 0 }, Ev } },
3654    { "blcic",	{ { OP_LWP_E, 0 }, Ev } },
3655    { "blsic",	{ { OP_LWP_E, 0 }, Ev } },
3656    { "t1mskc",	{ { OP_LWP_E, 0 }, Ev } },
3657  },
3658  /* REG_XOP_TBM_02 */
3659  {
3660    { Bad_Opcode },
3661    { "blcmsk",	{ { OP_LWP_E, 0 }, Ev } },
3662    { Bad_Opcode },
3663    { Bad_Opcode },
3664    { Bad_Opcode },
3665    { Bad_Opcode },
3666    { "blci",	{ { OP_LWP_E, 0 }, Ev } },
3667  },
3668#define NEED_REG_TABLE
3669#include "i386-dis-evex.h"
3670#undef NEED_REG_TABLE
3671};
3672
3673static const struct dis386 prefix_table[][4] = {
3674  /* PREFIX_90 */
3675  {
3676    { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3677    { "pause", { XX } },
3678    { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
3679  },
3680
3681  /* PREFIX_0F10 */
3682  {
3683    { "movups",	{ XM, EXx } },
3684    { "movss",	{ XM, EXd } },
3685    { "movupd",	{ XM, EXx } },
3686    { "movsd",	{ XM, EXq } },
3687  },
3688
3689  /* PREFIX_0F11 */
3690  {
3691    { "movups",	{ EXxS, XM } },
3692    { "movss",	{ EXdS, XM } },
3693    { "movupd",	{ EXxS, XM } },
3694    { "movsd",	{ EXqS, XM } },
3695  },
3696
3697  /* PREFIX_0F12 */
3698  {
3699    { MOD_TABLE (MOD_0F12_PREFIX_0) },
3700    { "movsldup", { XM, EXx } },
3701    { "movlpd",	{ XM, EXq } },
3702    { "movddup", { XM, EXq } },
3703  },
3704
3705  /* PREFIX_0F16 */
3706  {
3707    { MOD_TABLE (MOD_0F16_PREFIX_0) },
3708    { "movshdup", { XM, EXx } },
3709    { "movhpd",	{ XM, EXq } },
3710  },
3711
3712  /* PREFIX_0F1A */
3713  {
3714    { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3715    { "bndcl",  { Gbnd, Ev_bnd } },
3716    { "bndmov", { Gbnd, Ebnd } },
3717    { "bndcu",  { Gbnd, Ev_bnd } },
3718  },
3719
3720  /* PREFIX_0F1B */
3721  {
3722    { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3723    { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3724    { "bndmov", { Ebnd, Gbnd } },
3725    { "bndcn",  { Gbnd, Ev_bnd } },
3726  },
3727
3728  /* PREFIX_0F2A */
3729  {
3730    { "cvtpi2ps", { XM, EMCq } },
3731    { "cvtsi2ss%LQ", { XM, Ev } },
3732    { "cvtpi2pd", { XM, EMCq } },
3733    { "cvtsi2sd%LQ", { XM, Ev } },
3734  },
3735
3736  /* PREFIX_0F2B */
3737  {
3738    { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3739    { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3740    { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3741    { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3742  },
3743
3744  /* PREFIX_0F2C */
3745  {
3746    { "cvttps2pi", { MXC, EXq } },
3747    { "cvttss2siY", { Gv, EXd } },
3748    { "cvttpd2pi", { MXC, EXx } },
3749    { "cvttsd2siY", { Gv, EXq } },
3750  },
3751
3752  /* PREFIX_0F2D */
3753  {
3754    { "cvtps2pi", { MXC, EXq } },
3755    { "cvtss2siY", { Gv, EXd } },
3756    { "cvtpd2pi", { MXC, EXx } },
3757    { "cvtsd2siY", { Gv, EXq } },
3758  },
3759
3760  /* PREFIX_0F2E */
3761  {
3762    { "ucomiss",{ XM, EXd } },
3763    { Bad_Opcode },
3764    { "ucomisd",{ XM, EXq } },
3765  },
3766
3767  /* PREFIX_0F2F */
3768  {
3769    { "comiss",	{ XM, EXd } },
3770    { Bad_Opcode },
3771    { "comisd",	{ XM, EXq } },
3772  },
3773
3774  /* PREFIX_0F51 */
3775  {
3776    { "sqrtps", { XM, EXx } },
3777    { "sqrtss", { XM, EXd } },
3778    { "sqrtpd", { XM, EXx } },
3779    { "sqrtsd",	{ XM, EXq } },
3780  },
3781
3782  /* PREFIX_0F52 */
3783  {
3784    { "rsqrtps",{ XM, EXx } },
3785    { "rsqrtss",{ XM, EXd } },
3786  },
3787
3788  /* PREFIX_0F53 */
3789  {
3790    { "rcpps",	{ XM, EXx } },
3791    { "rcpss",	{ XM, EXd } },
3792  },
3793
3794  /* PREFIX_0F58 */
3795  {
3796    { "addps", { XM, EXx } },
3797    { "addss", { XM, EXd } },
3798    { "addpd", { XM, EXx } },
3799    { "addsd", { XM, EXq } },
3800  },
3801
3802  /* PREFIX_0F59 */
3803  {
3804    { "mulps",	{ XM, EXx } },
3805    { "mulss",	{ XM, EXd } },
3806    { "mulpd",	{ XM, EXx } },
3807    { "mulsd",	{ XM, EXq } },
3808  },
3809
3810  /* PREFIX_0F5A */
3811  {
3812    { "cvtps2pd", { XM, EXq } },
3813    { "cvtss2sd", { XM, EXd } },
3814    { "cvtpd2ps", { XM, EXx } },
3815    { "cvtsd2ss", { XM, EXq } },
3816  },
3817
3818  /* PREFIX_0F5B */
3819  {
3820    { "cvtdq2ps", { XM, EXx } },
3821    { "cvttps2dq", { XM, EXx } },
3822    { "cvtps2dq", { XM, EXx } },
3823  },
3824
3825  /* PREFIX_0F5C */
3826  {
3827    { "subps",	{ XM, EXx } },
3828    { "subss",	{ XM, EXd } },
3829    { "subpd",	{ XM, EXx } },
3830    { "subsd",	{ XM, EXq } },
3831  },
3832
3833  /* PREFIX_0F5D */
3834  {
3835    { "minps",	{ XM, EXx } },
3836    { "minss",	{ XM, EXd } },
3837    { "minpd",	{ XM, EXx } },
3838    { "minsd",	{ XM, EXq } },
3839  },
3840
3841  /* PREFIX_0F5E */
3842  {
3843    { "divps",	{ XM, EXx } },
3844    { "divss",	{ XM, EXd } },
3845    { "divpd",	{ XM, EXx } },
3846    { "divsd",	{ XM, EXq } },
3847  },
3848
3849  /* PREFIX_0F5F */
3850  {
3851    { "maxps",	{ XM, EXx } },
3852    { "maxss",	{ XM, EXd } },
3853    { "maxpd",	{ XM, EXx } },
3854    { "maxsd",	{ XM, EXq } },
3855  },
3856
3857  /* PREFIX_0F60 */
3858  {
3859    { "punpcklbw",{ MX, EMd } },
3860    { Bad_Opcode },
3861    { "punpcklbw",{ MX, EMx } },
3862  },
3863
3864  /* PREFIX_0F61 */
3865  {
3866    { "punpcklwd",{ MX, EMd } },
3867    { Bad_Opcode },
3868    { "punpcklwd",{ MX, EMx } },
3869  },
3870
3871  /* PREFIX_0F62 */
3872  {
3873    { "punpckldq",{ MX, EMd } },
3874    { Bad_Opcode },
3875    { "punpckldq",{ MX, EMx } },
3876  },
3877
3878  /* PREFIX_0F6C */
3879  {
3880    { Bad_Opcode },
3881    { Bad_Opcode },
3882    { "punpcklqdq", { XM, EXx } },
3883  },
3884
3885  /* PREFIX_0F6D */
3886  {
3887    { Bad_Opcode },
3888    { Bad_Opcode },
3889    { "punpckhqdq", { XM, EXx } },
3890  },
3891
3892  /* PREFIX_0F6F */
3893  {
3894    { "movq",	{ MX, EM } },
3895    { "movdqu",	{ XM, EXx } },
3896    { "movdqa",	{ XM, EXx } },
3897  },
3898
3899  /* PREFIX_0F70 */
3900  {
3901    { "pshufw",	{ MX, EM, Ib } },
3902    { "pshufhw",{ XM, EXx, Ib } },
3903    { "pshufd",	{ XM, EXx, Ib } },
3904    { "pshuflw",{ XM, EXx, Ib } },
3905  },
3906
3907  /* PREFIX_0F73_REG_3 */
3908  {
3909    { Bad_Opcode },
3910    { Bad_Opcode },
3911    { "psrldq",	{ XS, Ib } },
3912  },
3913
3914  /* PREFIX_0F73_REG_7 */
3915  {
3916    { Bad_Opcode },
3917    { Bad_Opcode },
3918    { "pslldq",	{ XS, Ib } },
3919  },
3920
3921  /* PREFIX_0F78 */
3922  {
3923    {"vmread",	{ Em, Gm } },
3924    { Bad_Opcode },
3925    {"extrq",	{ XS, Ib, Ib } },
3926    {"insertq",	{ XM, XS, Ib, Ib } },
3927  },
3928
3929  /* PREFIX_0F79 */
3930  {
3931    {"vmwrite",	{ Gm, Em } },
3932    { Bad_Opcode },
3933    {"extrq",	{ XM, XS } },
3934    {"insertq",	{ XM, XS } },
3935  },
3936
3937  /* PREFIX_0F7C */
3938  {
3939    { Bad_Opcode },
3940    { Bad_Opcode },
3941    { "haddpd",	{ XM, EXx } },
3942    { "haddps",	{ XM, EXx } },
3943  },
3944
3945  /* PREFIX_0F7D */
3946  {
3947    { Bad_Opcode },
3948    { Bad_Opcode },
3949    { "hsubpd",	{ XM, EXx } },
3950    { "hsubps",	{ XM, EXx } },
3951  },
3952
3953  /* PREFIX_0F7E */
3954  {
3955    { "movK",	{ Edq, MX } },
3956    { "movq",	{ XM, EXq } },
3957    { "movK",	{ Edq, XM } },
3958  },
3959
3960  /* PREFIX_0F7F */
3961  {
3962    { "movq",	{ EMS, MX } },
3963    { "movdqu",	{ EXxS, XM } },
3964    { "movdqa",	{ EXxS, XM } },
3965  },
3966
3967  /* PREFIX_0FAE_REG_0 */
3968  {
3969    { Bad_Opcode },
3970    { "rdfsbase", { Ev } },
3971  },
3972
3973  /* PREFIX_0FAE_REG_1 */
3974  {
3975    { Bad_Opcode },
3976    { "rdgsbase", { Ev } },
3977  },
3978
3979  /* PREFIX_0FAE_REG_2 */
3980  {
3981    { Bad_Opcode },
3982    { "wrfsbase", { Ev } },
3983  },
3984
3985  /* PREFIX_0FAE_REG_3 */
3986  {
3987    { Bad_Opcode },
3988    { "wrgsbase", { Ev } },
3989  },
3990
3991  /* PREFIX_0FAE_REG_6 */
3992  {
3993    { "xsaveopt",      { FXSAVE } },
3994    { Bad_Opcode },
3995    { "clwb",	{ Mb } },
3996  },
3997
3998  /* PREFIX_0FAE_REG_7 */
3999  {
4000    { "clflush",	{ Mb } },
4001    { Bad_Opcode },
4002    { "clflushopt",	{ Mb } },
4003  },
4004
4005  /* PREFIX_RM_0_0FAE_REG_7 */
4006  {
4007    { "sfence",		{ Skip_MODRM } },
4008    { Bad_Opcode },
4009    { "pcommit",		{ Skip_MODRM } },
4010  },
4011
4012  /* PREFIX_0FB8 */
4013  {
4014    { Bad_Opcode },
4015    { "popcntS", { Gv, Ev } },
4016  },
4017
4018  /* PREFIX_0FBC */
4019  {
4020    { "bsfS",	{ Gv, Ev } },
4021    { "tzcntS",	{ Gv, Ev } },
4022    { "bsfS",	{ Gv, Ev } },
4023  },
4024
4025  /* PREFIX_0FBD */
4026  {
4027    { "bsrS",	{ Gv, Ev } },
4028    { "lzcntS",	{ Gv, Ev } },
4029    { "bsrS",	{ Gv, Ev } },
4030  },
4031
4032  /* PREFIX_0FC2 */
4033  {
4034    { "cmpps",	{ XM, EXx, CMP } },
4035    { "cmpss",	{ XM, EXd, CMP } },
4036    { "cmppd",	{ XM, EXx, CMP } },
4037    { "cmpsd",	{ XM, EXq, CMP } },
4038  },
4039
4040  /* PREFIX_0FC3 */
4041  {
4042    { "movntiS", { Ma, Gv } },
4043  },
4044
4045  /* PREFIX_0FC7_REG_6 */
4046  {
4047    { "vmptrld",{ Mq } },
4048    { "vmxon",	{ Mq } },
4049    { "vmclear",{ Mq } },
4050  },
4051
4052  /* PREFIX_0FD0 */
4053  {
4054    { Bad_Opcode },
4055    { Bad_Opcode },
4056    { "addsubpd", { XM, EXx } },
4057    { "addsubps", { XM, EXx } },
4058  },
4059
4060  /* PREFIX_0FD6 */
4061  {
4062    { Bad_Opcode },
4063    { "movq2dq",{ XM, MS } },
4064    { "movq",	{ EXqS, XM } },
4065    { "movdq2q",{ MX, XS } },
4066  },
4067
4068  /* PREFIX_0FE6 */
4069  {
4070    { Bad_Opcode },
4071    { "cvtdq2pd", { XM, EXq } },
4072    { "cvttpd2dq", { XM, EXx } },
4073    { "cvtpd2dq", { XM, EXx } },
4074  },
4075
4076  /* PREFIX_0FE7 */
4077  {
4078    { "movntq",	{ Mq, MX } },
4079    { Bad_Opcode },
4080    { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4081  },
4082
4083  /* PREFIX_0FF0 */
4084  {
4085    { Bad_Opcode },
4086    { Bad_Opcode },
4087    { Bad_Opcode },
4088    { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4089  },
4090
4091  /* PREFIX_0FF7 */
4092  {
4093    { "maskmovq", { MX, MS } },
4094    { Bad_Opcode },
4095    { "maskmovdqu", { XM, XS } },
4096  },
4097
4098  /* PREFIX_0F3810 */
4099  {
4100    { Bad_Opcode },
4101    { Bad_Opcode },
4102    { "pblendvb", { XM, EXx, XMM0 } },
4103  },
4104
4105  /* PREFIX_0F3814 */
4106  {
4107    { Bad_Opcode },
4108    { Bad_Opcode },
4109    { "blendvps", { XM, EXx, XMM0 } },
4110  },
4111
4112  /* PREFIX_0F3815 */
4113  {
4114    { Bad_Opcode },
4115    { Bad_Opcode },
4116    { "blendvpd", { XM, EXx, XMM0 } },
4117  },
4118
4119  /* PREFIX_0F3817 */
4120  {
4121    { Bad_Opcode },
4122    { Bad_Opcode },
4123    { "ptest",  { XM, EXx } },
4124  },
4125
4126  /* PREFIX_0F3820 */
4127  {
4128    { Bad_Opcode },
4129    { Bad_Opcode },
4130    { "pmovsxbw", { XM, EXq } },
4131  },
4132
4133  /* PREFIX_0F3821 */
4134  {
4135    { Bad_Opcode },
4136    { Bad_Opcode },
4137    { "pmovsxbd", { XM, EXd } },
4138  },
4139
4140  /* PREFIX_0F3822 */
4141  {
4142    { Bad_Opcode },
4143    { Bad_Opcode },
4144    { "pmovsxbq", { XM, EXw } },
4145  },
4146
4147  /* PREFIX_0F3823 */
4148  {
4149    { Bad_Opcode },
4150    { Bad_Opcode },
4151    { "pmovsxwd", { XM, EXq } },
4152  },
4153
4154  /* PREFIX_0F3824 */
4155  {
4156    { Bad_Opcode },
4157    { Bad_Opcode },
4158    { "pmovsxwq", { XM, EXd } },
4159  },
4160
4161  /* PREFIX_0F3825 */
4162  {
4163    { Bad_Opcode },
4164    { Bad_Opcode },
4165    { "pmovsxdq", { XM, EXq } },
4166  },
4167
4168  /* PREFIX_0F3828 */
4169  {
4170    { Bad_Opcode },
4171    { Bad_Opcode },
4172    { "pmuldq", { XM, EXx } },
4173  },
4174
4175  /* PREFIX_0F3829 */
4176  {
4177    { Bad_Opcode },
4178    { Bad_Opcode },
4179    { "pcmpeqq", { XM, EXx } },
4180  },
4181
4182  /* PREFIX_0F382A */
4183  {
4184    { Bad_Opcode },
4185    { Bad_Opcode },
4186    { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4187  },
4188
4189  /* PREFIX_0F382B */
4190  {
4191    { Bad_Opcode },
4192    { Bad_Opcode },
4193    { "packusdw", { XM, EXx } },
4194  },
4195
4196  /* PREFIX_0F3830 */
4197  {
4198    { Bad_Opcode },
4199    { Bad_Opcode },
4200    { "pmovzxbw", { XM, EXq } },
4201  },
4202
4203  /* PREFIX_0F3831 */
4204  {
4205    { Bad_Opcode },
4206    { Bad_Opcode },
4207    { "pmovzxbd", { XM, EXd } },
4208  },
4209
4210  /* PREFIX_0F3832 */
4211  {
4212    { Bad_Opcode },
4213    { Bad_Opcode },
4214    { "pmovzxbq", { XM, EXw } },
4215  },
4216
4217  /* PREFIX_0F3833 */
4218  {
4219    { Bad_Opcode },
4220    { Bad_Opcode },
4221    { "pmovzxwd", { XM, EXq } },
4222  },
4223
4224  /* PREFIX_0F3834 */
4225  {
4226    { Bad_Opcode },
4227    { Bad_Opcode },
4228    { "pmovzxwq", { XM, EXd } },
4229  },
4230
4231  /* PREFIX_0F3835 */
4232  {
4233    { Bad_Opcode },
4234    { Bad_Opcode },
4235    { "pmovzxdq", { XM, EXq } },
4236  },
4237
4238  /* PREFIX_0F3837 */
4239  {
4240    { Bad_Opcode },
4241    { Bad_Opcode },
4242    { "pcmpgtq", { XM, EXx } },
4243  },
4244
4245  /* PREFIX_0F3838 */
4246  {
4247    { Bad_Opcode },
4248    { Bad_Opcode },
4249    { "pminsb",	{ XM, EXx } },
4250  },
4251
4252  /* PREFIX_0F3839 */
4253  {
4254    { Bad_Opcode },
4255    { Bad_Opcode },
4256    { "pminsd",	{ XM, EXx } },
4257  },
4258
4259  /* PREFIX_0F383A */
4260  {
4261    { Bad_Opcode },
4262    { Bad_Opcode },
4263    { "pminuw",	{ XM, EXx } },
4264  },
4265
4266  /* PREFIX_0F383B */
4267  {
4268    { Bad_Opcode },
4269    { Bad_Opcode },
4270    { "pminud",	{ XM, EXx } },
4271  },
4272
4273  /* PREFIX_0F383C */
4274  {
4275    { Bad_Opcode },
4276    { Bad_Opcode },
4277    { "pmaxsb",	{ XM, EXx } },
4278  },
4279
4280  /* PREFIX_0F383D */
4281  {
4282    { Bad_Opcode },
4283    { Bad_Opcode },
4284    { "pmaxsd",	{ XM, EXx } },
4285  },
4286
4287  /* PREFIX_0F383E */
4288  {
4289    { Bad_Opcode },
4290    { Bad_Opcode },
4291    { "pmaxuw", { XM, EXx } },
4292  },
4293
4294  /* PREFIX_0F383F */
4295  {
4296    { Bad_Opcode },
4297    { Bad_Opcode },
4298    { "pmaxud", { XM, EXx } },
4299  },
4300
4301  /* PREFIX_0F3840 */
4302  {
4303    { Bad_Opcode },
4304    { Bad_Opcode },
4305    { "pmulld", { XM, EXx } },
4306  },
4307
4308  /* PREFIX_0F3841 */
4309  {
4310    { Bad_Opcode },
4311    { Bad_Opcode },
4312    { "phminposuw", { XM, EXx } },
4313  },
4314
4315  /* PREFIX_0F3880 */
4316  {
4317    { Bad_Opcode },
4318    { Bad_Opcode },
4319    { "invept",	{ Gm, Mo } },
4320  },
4321
4322  /* PREFIX_0F3881 */
4323  {
4324    { Bad_Opcode },
4325    { Bad_Opcode },
4326    { "invvpid", { Gm, Mo } },
4327  },
4328
4329  /* PREFIX_0F3882 */
4330  {
4331    { Bad_Opcode },
4332    { Bad_Opcode },
4333    { "invpcid", { Gm, M } },
4334  },
4335
4336  /* PREFIX_0F38C8 */
4337  {
4338    { "sha1nexte", { XM, EXxmm } },
4339  },
4340
4341  /* PREFIX_0F38C9 */
4342  {
4343    { "sha1msg1", { XM, EXxmm } },
4344  },
4345
4346  /* PREFIX_0F38CA */
4347  {
4348    { "sha1msg2", { XM, EXxmm } },
4349  },
4350
4351  /* PREFIX_0F38CB */
4352  {
4353    { "sha256rnds2", { XM, EXxmm, XMM0 } },
4354  },
4355
4356  /* PREFIX_0F38CC */
4357  {
4358    { "sha256msg1", { XM, EXxmm } },
4359  },
4360
4361  /* PREFIX_0F38CD */
4362  {
4363    { "sha256msg2", { XM, EXxmm } },
4364  },
4365
4366  /* PREFIX_0F38DB */
4367  {
4368    { Bad_Opcode },
4369    { Bad_Opcode },
4370    { "aesimc", { XM, EXx } },
4371  },
4372
4373  /* PREFIX_0F38DC */
4374  {
4375    { Bad_Opcode },
4376    { Bad_Opcode },
4377    { "aesenc", { XM, EXx } },
4378  },
4379
4380  /* PREFIX_0F38DD */
4381  {
4382    { Bad_Opcode },
4383    { Bad_Opcode },
4384    { "aesenclast", { XM, EXx } },
4385  },
4386
4387  /* PREFIX_0F38DE */
4388  {
4389    { Bad_Opcode },
4390    { Bad_Opcode },
4391    { "aesdec", { XM, EXx } },
4392  },
4393
4394  /* PREFIX_0F38DF */
4395  {
4396    { Bad_Opcode },
4397    { Bad_Opcode },
4398    { "aesdeclast", { XM, EXx } },
4399  },
4400
4401  /* PREFIX_0F38F0 */
4402  {
4403    { "movbeS",	{ Gv, { MOVBE_Fixup, v_mode } } },
4404    { Bad_Opcode },
4405    { "movbeS",	{ Gv, { MOVBE_Fixup, v_mode } } },
4406    { "crc32",	{ Gdq, { CRC32_Fixup, b_mode } } },
4407  },
4408
4409  /* PREFIX_0F38F1 */
4410  {
4411    { "movbeS",	{ { MOVBE_Fixup, v_mode }, Gv } },
4412    { Bad_Opcode },
4413    { "movbeS",	{ { MOVBE_Fixup, v_mode }, Gv } },
4414    { "crc32",	{ Gdq, { CRC32_Fixup, v_mode } } },
4415  },
4416
4417  /* PREFIX_0F38F6 */
4418  {
4419    { Bad_Opcode },
4420    { "adoxS",	{ Gdq, Edq} },
4421    { "adcxS",	{ Gdq, Edq} },
4422    { Bad_Opcode },
4423  },
4424
4425  /* PREFIX_0F3A08 */
4426  {
4427    { Bad_Opcode },
4428    { Bad_Opcode },
4429    { "roundps", { XM, EXx, Ib } },
4430  },
4431
4432  /* PREFIX_0F3A09 */
4433  {
4434    { Bad_Opcode },
4435    { Bad_Opcode },
4436    { "roundpd", { XM, EXx, Ib } },
4437  },
4438
4439  /* PREFIX_0F3A0A */
4440  {
4441    { Bad_Opcode },
4442    { Bad_Opcode },
4443    { "roundss", { XM, EXd, Ib } },
4444  },
4445
4446  /* PREFIX_0F3A0B */
4447  {
4448    { Bad_Opcode },
4449    { Bad_Opcode },
4450    { "roundsd", { XM, EXq, Ib } },
4451  },
4452
4453  /* PREFIX_0F3A0C */
4454  {
4455    { Bad_Opcode },
4456    { Bad_Opcode },
4457    { "blendps", { XM, EXx, Ib } },
4458  },
4459
4460  /* PREFIX_0F3A0D */
4461  {
4462    { Bad_Opcode },
4463    { Bad_Opcode },
4464    { "blendpd", { XM, EXx, Ib } },
4465  },
4466
4467  /* PREFIX_0F3A0E */
4468  {
4469    { Bad_Opcode },
4470    { Bad_Opcode },
4471    { "pblendw", { XM, EXx, Ib } },
4472  },
4473
4474  /* PREFIX_0F3A14 */
4475  {
4476    { Bad_Opcode },
4477    { Bad_Opcode },
4478    { "pextrb",	{ Edqb, XM, Ib } },
4479  },
4480
4481  /* PREFIX_0F3A15 */
4482  {
4483    { Bad_Opcode },
4484    { Bad_Opcode },
4485    { "pextrw",	{ Edqw, XM, Ib } },
4486  },
4487
4488  /* PREFIX_0F3A16 */
4489  {
4490    { Bad_Opcode },
4491    { Bad_Opcode },
4492    { "pextrK",	{ Edq, XM, Ib } },
4493  },
4494
4495  /* PREFIX_0F3A17 */
4496  {
4497    { Bad_Opcode },
4498    { Bad_Opcode },
4499    { "extractps", { Edqd, XM, Ib } },
4500  },
4501
4502  /* PREFIX_0F3A20 */
4503  {
4504    { Bad_Opcode },
4505    { Bad_Opcode },
4506    { "pinsrb",	{ XM, Edqb, Ib } },
4507  },
4508
4509  /* PREFIX_0F3A21 */
4510  {
4511    { Bad_Opcode },
4512    { Bad_Opcode },
4513    { "insertps", { XM, EXd, Ib } },
4514  },
4515
4516  /* PREFIX_0F3A22 */
4517  {
4518    { Bad_Opcode },
4519    { Bad_Opcode },
4520    { "pinsrK",	{ XM, Edq, Ib } },
4521  },
4522
4523  /* PREFIX_0F3A40 */
4524  {
4525    { Bad_Opcode },
4526    { Bad_Opcode },
4527    { "dpps",	{ XM, EXx, Ib } },
4528  },
4529
4530  /* PREFIX_0F3A41 */
4531  {
4532    { Bad_Opcode },
4533    { Bad_Opcode },
4534    { "dppd",	{ XM, EXx, Ib } },
4535  },
4536
4537  /* PREFIX_0F3A42 */
4538  {
4539    { Bad_Opcode },
4540    { Bad_Opcode },
4541    { "mpsadbw", { XM, EXx, Ib } },
4542  },
4543
4544  /* PREFIX_0F3A44 */
4545  {
4546    { Bad_Opcode },
4547    { Bad_Opcode },
4548    { "pclmulqdq", { XM, EXx, PCLMUL } },
4549  },
4550
4551  /* PREFIX_0F3A60 */
4552  {
4553    { Bad_Opcode },
4554    { Bad_Opcode },
4555    { "pcmpestrm", { XM, EXx, Ib } },
4556  },
4557
4558  /* PREFIX_0F3A61 */
4559  {
4560    { Bad_Opcode },
4561    { Bad_Opcode },
4562    { "pcmpestri", { XM, EXx, Ib } },
4563  },
4564
4565  /* PREFIX_0F3A62 */
4566  {
4567    { Bad_Opcode },
4568    { Bad_Opcode },
4569    { "pcmpistrm", { XM, EXx, Ib } },
4570  },
4571
4572  /* PREFIX_0F3A63 */
4573  {
4574    { Bad_Opcode },
4575    { Bad_Opcode },
4576    { "pcmpistri", { XM, EXx, Ib } },
4577  },
4578
4579  /* PREFIX_0F3ACC */
4580  {
4581    { "sha1rnds4", { XM, EXxmm, Ib } },
4582  },
4583
4584  /* PREFIX_0F3ADF */
4585  {
4586    { Bad_Opcode },
4587    { Bad_Opcode },
4588    { "aeskeygenassist", { XM, EXx, Ib } },
4589  },
4590
4591  /* PREFIX_VEX_0F10 */
4592  {
4593    { VEX_W_TABLE (VEX_W_0F10_P_0) },
4594    { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4595    { VEX_W_TABLE (VEX_W_0F10_P_2) },
4596    { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4597  },
4598
4599  /* PREFIX_VEX_0F11 */
4600  {
4601    { VEX_W_TABLE (VEX_W_0F11_P_0) },
4602    { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4603    { VEX_W_TABLE (VEX_W_0F11_P_2) },
4604    { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4605  },
4606
4607  /* PREFIX_VEX_0F12 */
4608  {
4609    { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4610    { VEX_W_TABLE (VEX_W_0F12_P_1) },
4611    { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4612    { VEX_W_TABLE (VEX_W_0F12_P_3) },
4613  },
4614
4615  /* PREFIX_VEX_0F16 */
4616  {
4617    { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4618    { VEX_W_TABLE (VEX_W_0F16_P_1) },
4619    { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4620  },
4621
4622  /* PREFIX_VEX_0F2A */
4623  {
4624    { Bad_Opcode },
4625    { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4626    { Bad_Opcode },
4627    { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4628  },
4629
4630  /* PREFIX_VEX_0F2C */
4631  {
4632    { Bad_Opcode },
4633    { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4634    { Bad_Opcode },
4635    { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4636  },
4637
4638  /* PREFIX_VEX_0F2D */
4639  {
4640    { Bad_Opcode },
4641    { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4642    { Bad_Opcode },
4643    { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4644  },
4645
4646  /* PREFIX_VEX_0F2E */
4647  {
4648    { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4649    { Bad_Opcode },
4650    { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4651  },
4652
4653  /* PREFIX_VEX_0F2F */
4654  {
4655    { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4656    { Bad_Opcode },
4657    { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4658  },
4659
4660  /* PREFIX_VEX_0F41 */
4661  {
4662    { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4663    { Bad_Opcode },
4664    { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4665  },
4666
4667  /* PREFIX_VEX_0F42 */
4668  {
4669    { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4670    { Bad_Opcode },
4671    { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4672  },
4673
4674  /* PREFIX_VEX_0F44 */
4675  {
4676    { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4677    { Bad_Opcode },
4678    { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4679  },
4680
4681  /* PREFIX_VEX_0F45 */
4682  {
4683    { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4684    { Bad_Opcode },
4685    { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4686  },
4687
4688  /* PREFIX_VEX_0F46 */
4689  {
4690    { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4691    { Bad_Opcode },
4692    { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4693  },
4694
4695  /* PREFIX_VEX_0F47 */
4696  {
4697    { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4698    { Bad_Opcode },
4699    { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4700  },
4701
4702  /* PREFIX_VEX_0F4A */
4703  {
4704    { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4705    { Bad_Opcode },
4706    { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4707  },
4708
4709  /* PREFIX_VEX_0F4B */
4710  {
4711    { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4712    { Bad_Opcode },
4713    { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4714  },
4715
4716  /* PREFIX_VEX_0F51 */
4717  {
4718    { VEX_W_TABLE (VEX_W_0F51_P_0) },
4719    { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4720    { VEX_W_TABLE (VEX_W_0F51_P_2) },
4721    { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4722  },
4723
4724  /* PREFIX_VEX_0F52 */
4725  {
4726    { VEX_W_TABLE (VEX_W_0F52_P_0) },
4727    { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4728  },
4729
4730  /* PREFIX_VEX_0F53 */
4731  {
4732    { VEX_W_TABLE (VEX_W_0F53_P_0) },
4733    { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4734  },
4735
4736  /* PREFIX_VEX_0F58 */
4737  {
4738    { VEX_W_TABLE (VEX_W_0F58_P_0) },
4739    { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4740    { VEX_W_TABLE (VEX_W_0F58_P_2) },
4741    { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4742  },
4743
4744  /* PREFIX_VEX_0F59 */
4745  {
4746    { VEX_W_TABLE (VEX_W_0F59_P_0) },
4747    { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4748    { VEX_W_TABLE (VEX_W_0F59_P_2) },
4749    { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4750  },
4751
4752  /* PREFIX_VEX_0F5A */
4753  {
4754    { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4755    { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4756    { "vcvtpd2ps%XY", { XMM, EXx } },
4757    { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4758  },
4759
4760  /* PREFIX_VEX_0F5B */
4761  {
4762    { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4763    { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4764    { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4765  },
4766
4767  /* PREFIX_VEX_0F5C */
4768  {
4769    { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4770    { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4771    { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4772    { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4773  },
4774
4775  /* PREFIX_VEX_0F5D */
4776  {
4777    { VEX_W_TABLE (VEX_W_0F5D_P_0) },
4778    { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
4779    { VEX_W_TABLE (VEX_W_0F5D_P_2) },
4780    { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
4781  },
4782
4783  /* PREFIX_VEX_0F5E */
4784  {
4785    { VEX_W_TABLE (VEX_W_0F5E_P_0) },
4786    { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
4787    { VEX_W_TABLE (VEX_W_0F5E_P_2) },
4788    { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
4789  },
4790
4791  /* PREFIX_VEX_0F5F */
4792  {
4793    { VEX_W_TABLE (VEX_W_0F5F_P_0) },
4794    { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
4795    { VEX_W_TABLE (VEX_W_0F5F_P_2) },
4796    { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
4797  },
4798
4799  /* PREFIX_VEX_0F60 */
4800  {
4801    { Bad_Opcode },
4802    { Bad_Opcode },
4803    { VEX_W_TABLE (VEX_W_0F60_P_2) },
4804  },
4805
4806  /* PREFIX_VEX_0F61 */
4807  {
4808    { Bad_Opcode },
4809    { Bad_Opcode },
4810    { VEX_W_TABLE (VEX_W_0F61_P_2) },
4811  },
4812
4813  /* PREFIX_VEX_0F62 */
4814  {
4815    { Bad_Opcode },
4816    { Bad_Opcode },
4817    { VEX_W_TABLE (VEX_W_0F62_P_2) },
4818  },
4819
4820  /* PREFIX_VEX_0F63 */
4821  {
4822    { Bad_Opcode },
4823    { Bad_Opcode },
4824    { VEX_W_TABLE (VEX_W_0F63_P_2) },
4825  },
4826
4827  /* PREFIX_VEX_0F64 */
4828  {
4829    { Bad_Opcode },
4830    { Bad_Opcode },
4831    { VEX_W_TABLE (VEX_W_0F64_P_2) },
4832  },
4833
4834  /* PREFIX_VEX_0F65 */
4835  {
4836    { Bad_Opcode },
4837    { Bad_Opcode },
4838    { VEX_W_TABLE (VEX_W_0F65_P_2) },
4839  },
4840
4841  /* PREFIX_VEX_0F66 */
4842  {
4843    { Bad_Opcode },
4844    { Bad_Opcode },
4845    { VEX_W_TABLE (VEX_W_0F66_P_2) },
4846  },
4847
4848  /* PREFIX_VEX_0F67 */
4849  {
4850    { Bad_Opcode },
4851    { Bad_Opcode },
4852    { VEX_W_TABLE (VEX_W_0F67_P_2) },
4853  },
4854
4855  /* PREFIX_VEX_0F68 */
4856  {
4857    { Bad_Opcode },
4858    { Bad_Opcode },
4859    { VEX_W_TABLE (VEX_W_0F68_P_2) },
4860  },
4861
4862  /* PREFIX_VEX_0F69 */
4863  {
4864    { Bad_Opcode },
4865    { Bad_Opcode },
4866    { VEX_W_TABLE (VEX_W_0F69_P_2) },
4867  },
4868
4869  /* PREFIX_VEX_0F6A */
4870  {
4871    { Bad_Opcode },
4872    { Bad_Opcode },
4873    { VEX_W_TABLE (VEX_W_0F6A_P_2) },
4874  },
4875
4876  /* PREFIX_VEX_0F6B */
4877  {
4878    { Bad_Opcode },
4879    { Bad_Opcode },
4880    { VEX_W_TABLE (VEX_W_0F6B_P_2) },
4881  },
4882
4883  /* PREFIX_VEX_0F6C */
4884  {
4885    { Bad_Opcode },
4886    { Bad_Opcode },
4887    { VEX_W_TABLE (VEX_W_0F6C_P_2) },
4888  },
4889
4890  /* PREFIX_VEX_0F6D */
4891  {
4892    { Bad_Opcode },
4893    { Bad_Opcode },
4894    { VEX_W_TABLE (VEX_W_0F6D_P_2) },
4895  },
4896
4897  /* PREFIX_VEX_0F6E */
4898  {
4899    { Bad_Opcode },
4900    { Bad_Opcode },
4901    { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4902  },
4903
4904  /* PREFIX_VEX_0F6F */
4905  {
4906    { Bad_Opcode },
4907    { VEX_W_TABLE (VEX_W_0F6F_P_1) },
4908    { VEX_W_TABLE (VEX_W_0F6F_P_2) },
4909  },
4910
4911  /* PREFIX_VEX_0F70 */
4912  {
4913    { Bad_Opcode },
4914    { VEX_W_TABLE (VEX_W_0F70_P_1) },
4915    { VEX_W_TABLE (VEX_W_0F70_P_2) },
4916    { VEX_W_TABLE (VEX_W_0F70_P_3) },
4917  },
4918
4919  /* PREFIX_VEX_0F71_REG_2 */
4920  {
4921    { Bad_Opcode },
4922    { Bad_Opcode },
4923    { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
4924  },
4925
4926  /* PREFIX_VEX_0F71_REG_4 */
4927  {
4928    { Bad_Opcode },
4929    { Bad_Opcode },
4930    { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
4931  },
4932
4933  /* PREFIX_VEX_0F71_REG_6 */
4934  {
4935    { Bad_Opcode },
4936    { Bad_Opcode },
4937    { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
4938  },
4939
4940  /* PREFIX_VEX_0F72_REG_2 */
4941  {
4942    { Bad_Opcode },
4943    { Bad_Opcode },
4944    { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
4945  },
4946
4947  /* PREFIX_VEX_0F72_REG_4 */
4948  {
4949    { Bad_Opcode },
4950    { Bad_Opcode },
4951    { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
4952  },
4953
4954  /* PREFIX_VEX_0F72_REG_6 */
4955  {
4956    { Bad_Opcode },
4957    { Bad_Opcode },
4958    { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
4959  },
4960
4961  /* PREFIX_VEX_0F73_REG_2 */
4962  {
4963    { Bad_Opcode },
4964    { Bad_Opcode },
4965    { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
4966  },
4967
4968  /* PREFIX_VEX_0F73_REG_3 */
4969  {
4970    { Bad_Opcode },
4971    { Bad_Opcode },
4972    { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
4973  },
4974
4975  /* PREFIX_VEX_0F73_REG_6 */
4976  {
4977    { Bad_Opcode },
4978    { Bad_Opcode },
4979    { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4980  },
4981
4982  /* PREFIX_VEX_0F73_REG_7 */
4983  {
4984    { Bad_Opcode },
4985    { Bad_Opcode },
4986    { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4987  },
4988
4989  /* PREFIX_VEX_0F74 */
4990  {
4991    { Bad_Opcode },
4992    { Bad_Opcode },
4993    { VEX_W_TABLE (VEX_W_0F74_P_2) },
4994  },
4995
4996  /* PREFIX_VEX_0F75 */
4997  {
4998    { Bad_Opcode },
4999    { Bad_Opcode },
5000    { VEX_W_TABLE (VEX_W_0F75_P_2) },
5001  },
5002
5003  /* PREFIX_VEX_0F76 */
5004  {
5005    { Bad_Opcode },
5006    { Bad_Opcode },
5007    { VEX_W_TABLE (VEX_W_0F76_P_2) },
5008  },
5009
5010  /* PREFIX_VEX_0F77 */
5011  {
5012    { VEX_W_TABLE (VEX_W_0F77_P_0) },
5013  },
5014
5015  /* PREFIX_VEX_0F7C */
5016  {
5017    { Bad_Opcode },
5018    { Bad_Opcode },
5019    { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5020    { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5021  },
5022
5023  /* PREFIX_VEX_0F7D */
5024  {
5025    { Bad_Opcode },
5026    { Bad_Opcode },
5027    { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5028    { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5029  },
5030
5031  /* PREFIX_VEX_0F7E */
5032  {
5033    { Bad_Opcode },
5034    { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5035    { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5036  },
5037
5038  /* PREFIX_VEX_0F7F */
5039  {
5040    { Bad_Opcode },
5041    { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5042    { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5043  },
5044
5045  /* PREFIX_VEX_0F90 */
5046  {
5047    { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5048    { Bad_Opcode },
5049    { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5050  },
5051
5052  /* PREFIX_VEX_0F91 */
5053  {
5054    { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5055    { Bad_Opcode },
5056    { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5057  },
5058
5059  /* PREFIX_VEX_0F92 */
5060  {
5061    { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5062    { Bad_Opcode },
5063    { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5064    { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5065  },
5066
5067  /* PREFIX_VEX_0F93 */
5068  {
5069    { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5070    { Bad_Opcode },
5071    { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5072    { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5073  },
5074
5075  /* PREFIX_VEX_0F98 */
5076  {
5077    { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5078    { Bad_Opcode },
5079    { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5080  },
5081
5082  /* PREFIX_VEX_0F99 */
5083  {
5084    { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5085    { Bad_Opcode },
5086    { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5087  },
5088
5089  /* PREFIX_VEX_0FC2 */
5090  {
5091    { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5092    { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5093    { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5094    { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5095  },
5096
5097  /* PREFIX_VEX_0FC4 */
5098  {
5099    { Bad_Opcode },
5100    { Bad_Opcode },
5101    { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5102  },
5103
5104  /* PREFIX_VEX_0FC5 */
5105  {
5106    { Bad_Opcode },
5107    { Bad_Opcode },
5108    { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5109  },
5110
5111  /* PREFIX_VEX_0FD0 */
5112  {
5113    { Bad_Opcode },
5114    { Bad_Opcode },
5115    { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5116    { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5117  },
5118
5119  /* PREFIX_VEX_0FD1 */
5120  {
5121    { Bad_Opcode },
5122    { Bad_Opcode },
5123    { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5124  },
5125
5126  /* PREFIX_VEX_0FD2 */
5127  {
5128    { Bad_Opcode },
5129    { Bad_Opcode },
5130    { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5131  },
5132
5133  /* PREFIX_VEX_0FD3 */
5134  {
5135    { Bad_Opcode },
5136    { Bad_Opcode },
5137    { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5138  },
5139
5140  /* PREFIX_VEX_0FD4 */
5141  {
5142    { Bad_Opcode },
5143    { Bad_Opcode },
5144    { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5145  },
5146
5147  /* PREFIX_VEX_0FD5 */
5148  {
5149    { Bad_Opcode },
5150    { Bad_Opcode },
5151    { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5152  },
5153
5154  /* PREFIX_VEX_0FD6 */
5155  {
5156    { Bad_Opcode },
5157    { Bad_Opcode },
5158    { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5159  },
5160
5161  /* PREFIX_VEX_0FD7 */
5162  {
5163    { Bad_Opcode },
5164    { Bad_Opcode },
5165    { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5166  },
5167
5168  /* PREFIX_VEX_0FD8 */
5169  {
5170    { Bad_Opcode },
5171    { Bad_Opcode },
5172    { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5173  },
5174
5175  /* PREFIX_VEX_0FD9 */
5176  {
5177    { Bad_Opcode },
5178    { Bad_Opcode },
5179    { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5180  },
5181
5182  /* PREFIX_VEX_0FDA */
5183  {
5184    { Bad_Opcode },
5185    { Bad_Opcode },
5186    { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5187  },
5188
5189  /* PREFIX_VEX_0FDB */
5190  {
5191    { Bad_Opcode },
5192    { Bad_Opcode },
5193    { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5194  },
5195
5196  /* PREFIX_VEX_0FDC */
5197  {
5198    { Bad_Opcode },
5199    { Bad_Opcode },
5200    { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5201  },
5202
5203  /* PREFIX_VEX_0FDD */
5204  {
5205    { Bad_Opcode },
5206    { Bad_Opcode },
5207    { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5208  },
5209
5210  /* PREFIX_VEX_0FDE */
5211  {
5212    { Bad_Opcode },
5213    { Bad_Opcode },
5214    { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5215  },
5216
5217  /* PREFIX_VEX_0FDF */
5218  {
5219    { Bad_Opcode },
5220    { Bad_Opcode },
5221    { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5222  },
5223
5224  /* PREFIX_VEX_0FE0 */
5225  {
5226    { Bad_Opcode },
5227    { Bad_Opcode },
5228    { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5229  },
5230
5231  /* PREFIX_VEX_0FE1 */
5232  {
5233    { Bad_Opcode },
5234    { Bad_Opcode },
5235    { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5236  },
5237
5238  /* PREFIX_VEX_0FE2 */
5239  {
5240    { Bad_Opcode },
5241    { Bad_Opcode },
5242    { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5243  },
5244
5245  /* PREFIX_VEX_0FE3 */
5246  {
5247    { Bad_Opcode },
5248    { Bad_Opcode },
5249    { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5250  },
5251
5252  /* PREFIX_VEX_0FE4 */
5253  {
5254    { Bad_Opcode },
5255    { Bad_Opcode },
5256    { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5257  },
5258
5259  /* PREFIX_VEX_0FE5 */
5260  {
5261    { Bad_Opcode },
5262    { Bad_Opcode },
5263    { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5264  },
5265
5266  /* PREFIX_VEX_0FE6 */
5267  {
5268    { Bad_Opcode },
5269    { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5270    { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5271    { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5272  },
5273
5274  /* PREFIX_VEX_0FE7 */
5275  {
5276    { Bad_Opcode },
5277    { Bad_Opcode },
5278    { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5279  },
5280
5281  /* PREFIX_VEX_0FE8 */
5282  {
5283    { Bad_Opcode },
5284    { Bad_Opcode },
5285    { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5286  },
5287
5288  /* PREFIX_VEX_0FE9 */
5289  {
5290    { Bad_Opcode },
5291    { Bad_Opcode },
5292    { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5293  },
5294
5295  /* PREFIX_VEX_0FEA */
5296  {
5297    { Bad_Opcode },
5298    { Bad_Opcode },
5299    { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5300  },
5301
5302  /* PREFIX_VEX_0FEB */
5303  {
5304    { Bad_Opcode },
5305    { Bad_Opcode },
5306    { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5307  },
5308
5309  /* PREFIX_VEX_0FEC */
5310  {
5311    { Bad_Opcode },
5312    { Bad_Opcode },
5313    { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5314  },
5315
5316  /* PREFIX_VEX_0FED */
5317  {
5318    { Bad_Opcode },
5319    { Bad_Opcode },
5320    { VEX_W_TABLE (VEX_W_0FED_P_2) },
5321  },
5322
5323  /* PREFIX_VEX_0FEE */
5324  {
5325    { Bad_Opcode },
5326    { Bad_Opcode },
5327    { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5328  },
5329
5330  /* PREFIX_VEX_0FEF */
5331  {
5332    { Bad_Opcode },
5333    { Bad_Opcode },
5334    { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5335  },
5336
5337  /* PREFIX_VEX_0FF0 */
5338  {
5339    { Bad_Opcode },
5340    { Bad_Opcode },
5341    { Bad_Opcode },
5342    { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5343  },
5344
5345  /* PREFIX_VEX_0FF1 */
5346  {
5347    { Bad_Opcode },
5348    { Bad_Opcode },
5349    { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5350  },
5351
5352  /* PREFIX_VEX_0FF2 */
5353  {
5354    { Bad_Opcode },
5355    { Bad_Opcode },
5356    { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5357  },
5358
5359  /* PREFIX_VEX_0FF3 */
5360  {
5361    { Bad_Opcode },
5362    { Bad_Opcode },
5363    { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5364  },
5365
5366  /* PREFIX_VEX_0FF4 */
5367  {
5368    { Bad_Opcode },
5369    { Bad_Opcode },
5370    { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5371  },
5372
5373  /* PREFIX_VEX_0FF5 */
5374  {
5375    { Bad_Opcode },
5376    { Bad_Opcode },
5377    { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5378  },
5379
5380  /* PREFIX_VEX_0FF6 */
5381  {
5382    { Bad_Opcode },
5383    { Bad_Opcode },
5384    { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5385  },
5386
5387  /* PREFIX_VEX_0FF7 */
5388  {
5389    { Bad_Opcode },
5390    { Bad_Opcode },
5391    { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5392  },
5393
5394  /* PREFIX_VEX_0FF8 */
5395  {
5396    { Bad_Opcode },
5397    { Bad_Opcode },
5398    { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5399  },
5400
5401  /* PREFIX_VEX_0FF9 */
5402  {
5403    { Bad_Opcode },
5404    { Bad_Opcode },
5405    { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5406  },
5407
5408  /* PREFIX_VEX_0FFA */
5409  {
5410    { Bad_Opcode },
5411    { Bad_Opcode },
5412    { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5413  },
5414
5415  /* PREFIX_VEX_0FFB */
5416  {
5417    { Bad_Opcode },
5418    { Bad_Opcode },
5419    { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5420  },
5421
5422  /* PREFIX_VEX_0FFC */
5423  {
5424    { Bad_Opcode },
5425    { Bad_Opcode },
5426    { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5427  },
5428
5429  /* PREFIX_VEX_0FFD */
5430  {
5431    { Bad_Opcode },
5432    { Bad_Opcode },
5433    { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5434  },
5435
5436  /* PREFIX_VEX_0FFE */
5437  {
5438    { Bad_Opcode },
5439    { Bad_Opcode },
5440    { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5441  },
5442
5443  /* PREFIX_VEX_0F3800 */
5444  {
5445    { Bad_Opcode },
5446    { Bad_Opcode },
5447    { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5448  },
5449
5450  /* PREFIX_VEX_0F3801 */
5451  {
5452    { Bad_Opcode },
5453    { Bad_Opcode },
5454    { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5455  },
5456
5457  /* PREFIX_VEX_0F3802 */
5458  {
5459    { Bad_Opcode },
5460    { Bad_Opcode },
5461    { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5462  },
5463
5464  /* PREFIX_VEX_0F3803 */
5465  {
5466    { Bad_Opcode },
5467    { Bad_Opcode },
5468    { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5469  },
5470
5471  /* PREFIX_VEX_0F3804 */
5472  {
5473    { Bad_Opcode },
5474    { Bad_Opcode },
5475    { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5476  },
5477
5478  /* PREFIX_VEX_0F3805 */
5479  {
5480    { Bad_Opcode },
5481    { Bad_Opcode },
5482    { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5483  },
5484
5485  /* PREFIX_VEX_0F3806 */
5486  {
5487    { Bad_Opcode },
5488    { Bad_Opcode },
5489    { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5490  },
5491
5492  /* PREFIX_VEX_0F3807 */
5493  {
5494    { Bad_Opcode },
5495    { Bad_Opcode },
5496    { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5497  },
5498
5499  /* PREFIX_VEX_0F3808 */
5500  {
5501    { Bad_Opcode },
5502    { Bad_Opcode },
5503    { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5504  },
5505
5506  /* PREFIX_VEX_0F3809 */
5507  {
5508    { Bad_Opcode },
5509    { Bad_Opcode },
5510    { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5511  },
5512
5513  /* PREFIX_VEX_0F380A */
5514  {
5515    { Bad_Opcode },
5516    { Bad_Opcode },
5517    { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5518  },
5519
5520  /* PREFIX_VEX_0F380B */
5521  {
5522    { Bad_Opcode },
5523    { Bad_Opcode },
5524    { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5525  },
5526
5527  /* PREFIX_VEX_0F380C */
5528  {
5529    { Bad_Opcode },
5530    { Bad_Opcode },
5531    { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5532  },
5533
5534  /* PREFIX_VEX_0F380D */
5535  {
5536    { Bad_Opcode },
5537    { Bad_Opcode },
5538    { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5539  },
5540
5541  /* PREFIX_VEX_0F380E */
5542  {
5543    { Bad_Opcode },
5544    { Bad_Opcode },
5545    { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5546  },
5547
5548  /* PREFIX_VEX_0F380F */
5549  {
5550    { Bad_Opcode },
5551    { Bad_Opcode },
5552    { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5553  },
5554
5555  /* PREFIX_VEX_0F3813 */
5556  {
5557    { Bad_Opcode },
5558    { Bad_Opcode },
5559    { "vcvtph2ps", { XM, EXxmmq } },
5560  },
5561
5562  /* PREFIX_VEX_0F3816 */
5563  {
5564    { Bad_Opcode },
5565    { Bad_Opcode },
5566    { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5567  },
5568
5569  /* PREFIX_VEX_0F3817 */
5570  {
5571    { Bad_Opcode },
5572    { Bad_Opcode },
5573    { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5574  },
5575
5576  /* PREFIX_VEX_0F3818 */
5577  {
5578    { Bad_Opcode },
5579    { Bad_Opcode },
5580    { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5581  },
5582
5583  /* PREFIX_VEX_0F3819 */
5584  {
5585    { Bad_Opcode },
5586    { Bad_Opcode },
5587    { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5588  },
5589
5590  /* PREFIX_VEX_0F381A */
5591  {
5592    { Bad_Opcode },
5593    { Bad_Opcode },
5594    { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5595  },
5596
5597  /* PREFIX_VEX_0F381C */
5598  {
5599    { Bad_Opcode },
5600    { Bad_Opcode },
5601    { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5602  },
5603
5604  /* PREFIX_VEX_0F381D */
5605  {
5606    { Bad_Opcode },
5607    { Bad_Opcode },
5608    { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5609  },
5610
5611  /* PREFIX_VEX_0F381E */
5612  {
5613    { Bad_Opcode },
5614    { Bad_Opcode },
5615    { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5616  },
5617
5618  /* PREFIX_VEX_0F3820 */
5619  {
5620    { Bad_Opcode },
5621    { Bad_Opcode },
5622    { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5623  },
5624
5625  /* PREFIX_VEX_0F3821 */
5626  {
5627    { Bad_Opcode },
5628    { Bad_Opcode },
5629    { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5630  },
5631
5632  /* PREFIX_VEX_0F3822 */
5633  {
5634    { Bad_Opcode },
5635    { Bad_Opcode },
5636    { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5637  },
5638
5639  /* PREFIX_VEX_0F3823 */
5640  {
5641    { Bad_Opcode },
5642    { Bad_Opcode },
5643    { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5644  },
5645
5646  /* PREFIX_VEX_0F3824 */
5647  {
5648    { Bad_Opcode },
5649    { Bad_Opcode },
5650    { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5651  },
5652
5653  /* PREFIX_VEX_0F3825 */
5654  {
5655    { Bad_Opcode },
5656    { Bad_Opcode },
5657    { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5658  },
5659
5660  /* PREFIX_VEX_0F3828 */
5661  {
5662    { Bad_Opcode },
5663    { Bad_Opcode },
5664    { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5665  },
5666
5667  /* PREFIX_VEX_0F3829 */
5668  {
5669    { Bad_Opcode },
5670    { Bad_Opcode },
5671    { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5672  },
5673
5674  /* PREFIX_VEX_0F382A */
5675  {
5676    { Bad_Opcode },
5677    { Bad_Opcode },
5678    { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5679  },
5680
5681  /* PREFIX_VEX_0F382B */
5682  {
5683    { Bad_Opcode },
5684    { Bad_Opcode },
5685    { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5686  },
5687
5688  /* PREFIX_VEX_0F382C */
5689  {
5690    { Bad_Opcode },
5691    { Bad_Opcode },
5692     { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5693  },
5694
5695  /* PREFIX_VEX_0F382D */
5696  {
5697    { Bad_Opcode },
5698    { Bad_Opcode },
5699     { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5700  },
5701
5702  /* PREFIX_VEX_0F382E */
5703  {
5704    { Bad_Opcode },
5705    { Bad_Opcode },
5706     { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5707  },
5708
5709  /* PREFIX_VEX_0F382F */
5710  {
5711    { Bad_Opcode },
5712    { Bad_Opcode },
5713     { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5714  },
5715
5716  /* PREFIX_VEX_0F3830 */
5717  {
5718    { Bad_Opcode },
5719    { Bad_Opcode },
5720    { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5721  },
5722
5723  /* PREFIX_VEX_0F3831 */
5724  {
5725    { Bad_Opcode },
5726    { Bad_Opcode },
5727    { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5728  },
5729
5730  /* PREFIX_VEX_0F3832 */
5731  {
5732    { Bad_Opcode },
5733    { Bad_Opcode },
5734    { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5735  },
5736
5737  /* PREFIX_VEX_0F3833 */
5738  {
5739    { Bad_Opcode },
5740    { Bad_Opcode },
5741    { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5742  },
5743
5744  /* PREFIX_VEX_0F3834 */
5745  {
5746    { Bad_Opcode },
5747    { Bad_Opcode },
5748    { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5749  },
5750
5751  /* PREFIX_VEX_0F3835 */
5752  {
5753    { Bad_Opcode },
5754    { Bad_Opcode },
5755    { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5756  },
5757
5758  /* PREFIX_VEX_0F3836 */
5759  {
5760    { Bad_Opcode },
5761    { Bad_Opcode },
5762    { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5763  },
5764
5765  /* PREFIX_VEX_0F3837 */
5766  {
5767    { Bad_Opcode },
5768    { Bad_Opcode },
5769    { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5770  },
5771
5772  /* PREFIX_VEX_0F3838 */
5773  {
5774    { Bad_Opcode },
5775    { Bad_Opcode },
5776    { VEX_W_TABLE (VEX_W_0F3838_P_2) },
5777  },
5778
5779  /* PREFIX_VEX_0F3839 */
5780  {
5781    { Bad_Opcode },
5782    { Bad_Opcode },
5783    { VEX_W_TABLE (VEX_W_0F3839_P_2) },
5784  },
5785
5786  /* PREFIX_VEX_0F383A */
5787  {
5788    { Bad_Opcode },
5789    { Bad_Opcode },
5790    { VEX_W_TABLE (VEX_W_0F383A_P_2) },
5791  },
5792
5793  /* PREFIX_VEX_0F383B */
5794  {
5795    { Bad_Opcode },
5796    { Bad_Opcode },
5797    { VEX_W_TABLE (VEX_W_0F383B_P_2) },
5798  },
5799
5800  /* PREFIX_VEX_0F383C */
5801  {
5802    { Bad_Opcode },
5803    { Bad_Opcode },
5804    { VEX_W_TABLE (VEX_W_0F383C_P_2) },
5805  },
5806
5807  /* PREFIX_VEX_0F383D */
5808  {
5809    { Bad_Opcode },
5810    { Bad_Opcode },
5811    { VEX_W_TABLE (VEX_W_0F383D_P_2) },
5812  },
5813
5814  /* PREFIX_VEX_0F383E */
5815  {
5816    { Bad_Opcode },
5817    { Bad_Opcode },
5818    { VEX_W_TABLE (VEX_W_0F383E_P_2) },
5819  },
5820
5821  /* PREFIX_VEX_0F383F */
5822  {
5823    { Bad_Opcode },
5824    { Bad_Opcode },
5825    { VEX_W_TABLE (VEX_W_0F383F_P_2) },
5826  },
5827
5828  /* PREFIX_VEX_0F3840 */
5829  {
5830    { Bad_Opcode },
5831    { Bad_Opcode },
5832    { VEX_W_TABLE (VEX_W_0F3840_P_2) },
5833  },
5834
5835  /* PREFIX_VEX_0F3841 */
5836  {
5837    { Bad_Opcode },
5838    { Bad_Opcode },
5839    { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5840  },
5841
5842  /* PREFIX_VEX_0F3845 */
5843  {
5844    { Bad_Opcode },
5845    { Bad_Opcode },
5846    { "vpsrlv%LW", { XM, Vex, EXx } },
5847  },
5848
5849  /* PREFIX_VEX_0F3846 */
5850  {
5851    { Bad_Opcode },
5852    { Bad_Opcode },
5853    { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5854  },
5855
5856  /* PREFIX_VEX_0F3847 */
5857  {
5858    { Bad_Opcode },
5859    { Bad_Opcode },
5860    { "vpsllv%LW", { XM, Vex, EXx } },
5861  },
5862
5863  /* PREFIX_VEX_0F3858 */
5864  {
5865    { Bad_Opcode },
5866    { Bad_Opcode },
5867    { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5868  },
5869
5870  /* PREFIX_VEX_0F3859 */
5871  {
5872    { Bad_Opcode },
5873    { Bad_Opcode },
5874    { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5875  },
5876
5877  /* PREFIX_VEX_0F385A */
5878  {
5879    { Bad_Opcode },
5880    { Bad_Opcode },
5881    { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5882  },
5883
5884  /* PREFIX_VEX_0F3878 */
5885  {
5886    { Bad_Opcode },
5887    { Bad_Opcode },
5888    { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5889  },
5890
5891  /* PREFIX_VEX_0F3879 */
5892  {
5893    { Bad_Opcode },
5894    { Bad_Opcode },
5895    { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5896  },
5897
5898  /* PREFIX_VEX_0F388C */
5899  {
5900    { Bad_Opcode },
5901    { Bad_Opcode },
5902    { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5903  },
5904
5905  /* PREFIX_VEX_0F388E */
5906  {
5907    { Bad_Opcode },
5908    { Bad_Opcode },
5909    { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5910  },
5911
5912  /* PREFIX_VEX_0F3890 */
5913  {
5914    { Bad_Opcode },
5915    { Bad_Opcode },
5916    { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
5917  },
5918
5919  /* PREFIX_VEX_0F3891 */
5920  {
5921    { Bad_Opcode },
5922    { Bad_Opcode },
5923    { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5924  },
5925
5926  /* PREFIX_VEX_0F3892 */
5927  {
5928    { Bad_Opcode },
5929    { Bad_Opcode },
5930    { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
5931  },
5932
5933  /* PREFIX_VEX_0F3893 */
5934  {
5935    { Bad_Opcode },
5936    { Bad_Opcode },
5937    { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
5938  },
5939
5940  /* PREFIX_VEX_0F3896 */
5941  {
5942    { Bad_Opcode },
5943    { Bad_Opcode },
5944    { "vfmaddsub132p%XW", { XM, Vex, EXx } },
5945  },
5946
5947  /* PREFIX_VEX_0F3897 */
5948  {
5949    { Bad_Opcode },
5950    { Bad_Opcode },
5951    { "vfmsubadd132p%XW", { XM, Vex, EXx } },
5952  },
5953
5954  /* PREFIX_VEX_0F3898 */
5955  {
5956    { Bad_Opcode },
5957    { Bad_Opcode },
5958    { "vfmadd132p%XW", { XM, Vex, EXx } },
5959  },
5960
5961  /* PREFIX_VEX_0F3899 */
5962  {
5963    { Bad_Opcode },
5964    { Bad_Opcode },
5965    { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5966  },
5967
5968  /* PREFIX_VEX_0F389A */
5969  {
5970    { Bad_Opcode },
5971    { Bad_Opcode },
5972    { "vfmsub132p%XW", { XM, Vex, EXx } },
5973  },
5974
5975  /* PREFIX_VEX_0F389B */
5976  {
5977    { Bad_Opcode },
5978    { Bad_Opcode },
5979    { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5980  },
5981
5982  /* PREFIX_VEX_0F389C */
5983  {
5984    { Bad_Opcode },
5985    { Bad_Opcode },
5986    { "vfnmadd132p%XW", { XM, Vex, EXx } },
5987  },
5988
5989  /* PREFIX_VEX_0F389D */
5990  {
5991    { Bad_Opcode },
5992    { Bad_Opcode },
5993    { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5994  },
5995
5996  /* PREFIX_VEX_0F389E */
5997  {
5998    { Bad_Opcode },
5999    { Bad_Opcode },
6000    { "vfnmsub132p%XW", { XM, Vex, EXx } },
6001  },
6002
6003  /* PREFIX_VEX_0F389F */
6004  {
6005    { Bad_Opcode },
6006    { Bad_Opcode },
6007    { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6008  },
6009
6010  /* PREFIX_VEX_0F38A6 */
6011  {
6012    { Bad_Opcode },
6013    { Bad_Opcode },
6014    { "vfmaddsub213p%XW", { XM, Vex, EXx } },
6015    { Bad_Opcode },
6016  },
6017
6018  /* PREFIX_VEX_0F38A7 */
6019  {
6020    { Bad_Opcode },
6021    { Bad_Opcode },
6022    { "vfmsubadd213p%XW", { XM, Vex, EXx } },
6023  },
6024
6025  /* PREFIX_VEX_0F38A8 */
6026  {
6027    { Bad_Opcode },
6028    { Bad_Opcode },
6029    { "vfmadd213p%XW", { XM, Vex, EXx } },
6030  },
6031
6032  /* PREFIX_VEX_0F38A9 */
6033  {
6034    { Bad_Opcode },
6035    { Bad_Opcode },
6036    { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6037  },
6038
6039  /* PREFIX_VEX_0F38AA */
6040  {
6041    { Bad_Opcode },
6042    { Bad_Opcode },
6043    { "vfmsub213p%XW", { XM, Vex, EXx } },
6044  },
6045
6046  /* PREFIX_VEX_0F38AB */
6047  {
6048    { Bad_Opcode },
6049    { Bad_Opcode },
6050    { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6051  },
6052
6053  /* PREFIX_VEX_0F38AC */
6054  {
6055    { Bad_Opcode },
6056    { Bad_Opcode },
6057    { "vfnmadd213p%XW", { XM, Vex, EXx } },
6058  },
6059
6060  /* PREFIX_VEX_0F38AD */
6061  {
6062    { Bad_Opcode },
6063    { Bad_Opcode },
6064    { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6065  },
6066
6067  /* PREFIX_VEX_0F38AE */
6068  {
6069    { Bad_Opcode },
6070    { Bad_Opcode },
6071    { "vfnmsub213p%XW", { XM, Vex, EXx } },
6072  },
6073
6074  /* PREFIX_VEX_0F38AF */
6075  {
6076    { Bad_Opcode },
6077    { Bad_Opcode },
6078    { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6079  },
6080
6081  /* PREFIX_VEX_0F38B6 */
6082  {
6083    { Bad_Opcode },
6084    { Bad_Opcode },
6085    { "vfmaddsub231p%XW", { XM, Vex, EXx } },
6086  },
6087
6088  /* PREFIX_VEX_0F38B7 */
6089  {
6090    { Bad_Opcode },
6091    { Bad_Opcode },
6092    { "vfmsubadd231p%XW", { XM, Vex, EXx } },
6093  },
6094
6095  /* PREFIX_VEX_0F38B8 */
6096  {
6097    { Bad_Opcode },
6098    { Bad_Opcode },
6099    { "vfmadd231p%XW", { XM, Vex, EXx } },
6100  },
6101
6102  /* PREFIX_VEX_0F38B9 */
6103  {
6104    { Bad_Opcode },
6105    { Bad_Opcode },
6106    { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6107  },
6108
6109  /* PREFIX_VEX_0F38BA */
6110  {
6111    { Bad_Opcode },
6112    { Bad_Opcode },
6113    { "vfmsub231p%XW", { XM, Vex, EXx } },
6114  },
6115
6116  /* PREFIX_VEX_0F38BB */
6117  {
6118    { Bad_Opcode },
6119    { Bad_Opcode },
6120    { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6121  },
6122
6123  /* PREFIX_VEX_0F38BC */
6124  {
6125    { Bad_Opcode },
6126    { Bad_Opcode },
6127    { "vfnmadd231p%XW", { XM, Vex, EXx } },
6128  },
6129
6130  /* PREFIX_VEX_0F38BD */
6131  {
6132    { Bad_Opcode },
6133    { Bad_Opcode },
6134    { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6135  },
6136
6137  /* PREFIX_VEX_0F38BE */
6138  {
6139    { Bad_Opcode },
6140    { Bad_Opcode },
6141    { "vfnmsub231p%XW", { XM, Vex, EXx } },
6142  },
6143
6144  /* PREFIX_VEX_0F38BF */
6145  {
6146    { Bad_Opcode },
6147    { Bad_Opcode },
6148    { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
6149  },
6150
6151  /* PREFIX_VEX_0F38DB */
6152  {
6153    { Bad_Opcode },
6154    { Bad_Opcode },
6155    { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6156  },
6157
6158  /* PREFIX_VEX_0F38DC */
6159  {
6160    { Bad_Opcode },
6161    { Bad_Opcode },
6162    { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
6163  },
6164
6165  /* PREFIX_VEX_0F38DD */
6166  {
6167    { Bad_Opcode },
6168    { Bad_Opcode },
6169    { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
6170  },
6171
6172  /* PREFIX_VEX_0F38DE */
6173  {
6174    { Bad_Opcode },
6175    { Bad_Opcode },
6176    { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
6177  },
6178
6179  /* PREFIX_VEX_0F38DF */
6180  {
6181    { Bad_Opcode },
6182    { Bad_Opcode },
6183    { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
6184  },
6185
6186  /* PREFIX_VEX_0F38F2 */
6187  {
6188    { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6189  },
6190
6191  /* PREFIX_VEX_0F38F3_REG_1 */
6192  {
6193    { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6194  },
6195
6196  /* PREFIX_VEX_0F38F3_REG_2 */
6197  {
6198    { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6199  },
6200
6201  /* PREFIX_VEX_0F38F3_REG_3 */
6202  {
6203    { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6204  },
6205
6206  /* PREFIX_VEX_0F38F5 */
6207  {
6208    { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6209    { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6210    { Bad_Opcode },
6211    { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6212  },
6213
6214  /* PREFIX_VEX_0F38F6 */
6215  {
6216    { Bad_Opcode },
6217    { Bad_Opcode },
6218    { Bad_Opcode },
6219    { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6220  },
6221
6222  /* PREFIX_VEX_0F38F7 */
6223  {
6224    { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6225    { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6226    { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6227    { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6228  },
6229
6230  /* PREFIX_VEX_0F3A00 */
6231  {
6232    { Bad_Opcode },
6233    { Bad_Opcode },
6234    { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6235  },
6236
6237  /* PREFIX_VEX_0F3A01 */
6238  {
6239    { Bad_Opcode },
6240    { Bad_Opcode },
6241    { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6242  },
6243
6244  /* PREFIX_VEX_0F3A02 */
6245  {
6246    { Bad_Opcode },
6247    { Bad_Opcode },
6248    { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6249  },
6250
6251  /* PREFIX_VEX_0F3A04 */
6252  {
6253    { Bad_Opcode },
6254    { Bad_Opcode },
6255    { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6256  },
6257
6258  /* PREFIX_VEX_0F3A05 */
6259  {
6260    { Bad_Opcode },
6261    { Bad_Opcode },
6262    { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6263  },
6264
6265  /* PREFIX_VEX_0F3A06 */
6266  {
6267    { Bad_Opcode },
6268    { Bad_Opcode },
6269    { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6270  },
6271
6272  /* PREFIX_VEX_0F3A08 */
6273  {
6274    { Bad_Opcode },
6275    { Bad_Opcode },
6276    { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6277  },
6278
6279  /* PREFIX_VEX_0F3A09 */
6280  {
6281    { Bad_Opcode },
6282    { Bad_Opcode },
6283    { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6284  },
6285
6286  /* PREFIX_VEX_0F3A0A */
6287  {
6288    { Bad_Opcode },
6289    { Bad_Opcode },
6290    { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6291  },
6292
6293  /* PREFIX_VEX_0F3A0B */
6294  {
6295    { Bad_Opcode },
6296    { Bad_Opcode },
6297    { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6298  },
6299
6300  /* PREFIX_VEX_0F3A0C */
6301  {
6302    { Bad_Opcode },
6303    { Bad_Opcode },
6304    { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6305  },
6306
6307  /* PREFIX_VEX_0F3A0D */
6308  {
6309    { Bad_Opcode },
6310    { Bad_Opcode },
6311    { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6312  },
6313
6314  /* PREFIX_VEX_0F3A0E */
6315  {
6316    { Bad_Opcode },
6317    { Bad_Opcode },
6318    { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6319  },
6320
6321  /* PREFIX_VEX_0F3A0F */
6322  {
6323    { Bad_Opcode },
6324    { Bad_Opcode },
6325    { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6326  },
6327
6328  /* PREFIX_VEX_0F3A14 */
6329  {
6330    { Bad_Opcode },
6331    { Bad_Opcode },
6332    { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6333  },
6334
6335  /* PREFIX_VEX_0F3A15 */
6336  {
6337    { Bad_Opcode },
6338    { Bad_Opcode },
6339    { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6340  },
6341
6342  /* PREFIX_VEX_0F3A16 */
6343  {
6344    { Bad_Opcode },
6345    { Bad_Opcode },
6346    { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6347  },
6348
6349  /* PREFIX_VEX_0F3A17 */
6350  {
6351    { Bad_Opcode },
6352    { Bad_Opcode },
6353    { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6354  },
6355
6356  /* PREFIX_VEX_0F3A18 */
6357  {
6358    { Bad_Opcode },
6359    { Bad_Opcode },
6360    { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6361  },
6362
6363  /* PREFIX_VEX_0F3A19 */
6364  {
6365    { Bad_Opcode },
6366    { Bad_Opcode },
6367    { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6368  },
6369
6370  /* PREFIX_VEX_0F3A1D */
6371  {
6372    { Bad_Opcode },
6373    { Bad_Opcode },
6374    { "vcvtps2ph", { EXxmmq, XM, Ib } },
6375  },
6376
6377  /* PREFIX_VEX_0F3A20 */
6378  {
6379    { Bad_Opcode },
6380    { Bad_Opcode },
6381    { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6382  },
6383
6384  /* PREFIX_VEX_0F3A21 */
6385  {
6386    { Bad_Opcode },
6387    { Bad_Opcode },
6388    { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6389  },
6390
6391  /* PREFIX_VEX_0F3A22 */
6392  {
6393    { Bad_Opcode },
6394    { Bad_Opcode },
6395    { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6396  },
6397
6398  /* PREFIX_VEX_0F3A30 */
6399  {
6400    { Bad_Opcode },
6401    { Bad_Opcode },
6402    { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6403  },
6404
6405  /* PREFIX_VEX_0F3A31 */
6406  {
6407    { Bad_Opcode },
6408    { Bad_Opcode },
6409    { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6410  },
6411
6412  /* PREFIX_VEX_0F3A32 */
6413  {
6414    { Bad_Opcode },
6415    { Bad_Opcode },
6416    { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6417  },
6418
6419  /* PREFIX_VEX_0F3A33 */
6420  {
6421    { Bad_Opcode },
6422    { Bad_Opcode },
6423    { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6424  },
6425
6426  /* PREFIX_VEX_0F3A38 */
6427  {
6428    { Bad_Opcode },
6429    { Bad_Opcode },
6430    { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6431  },
6432
6433  /* PREFIX_VEX_0F3A39 */
6434  {
6435    { Bad_Opcode },
6436    { Bad_Opcode },
6437    { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6438  },
6439
6440  /* PREFIX_VEX_0F3A40 */
6441  {
6442    { Bad_Opcode },
6443    { Bad_Opcode },
6444    { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6445  },
6446
6447  /* PREFIX_VEX_0F3A41 */
6448  {
6449    { Bad_Opcode },
6450    { Bad_Opcode },
6451    { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6452  },
6453
6454  /* PREFIX_VEX_0F3A42 */
6455  {
6456    { Bad_Opcode },
6457    { Bad_Opcode },
6458    { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6459  },
6460
6461  /* PREFIX_VEX_0F3A44 */
6462  {
6463    { Bad_Opcode },
6464    { Bad_Opcode },
6465    { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
6466  },
6467
6468  /* PREFIX_VEX_0F3A46 */
6469  {
6470    { Bad_Opcode },
6471    { Bad_Opcode },
6472    { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6473  },
6474
6475  /* PREFIX_VEX_0F3A48 */
6476  {
6477    { Bad_Opcode },
6478    { Bad_Opcode },
6479    { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6480  },
6481
6482  /* PREFIX_VEX_0F3A49 */
6483  {
6484    { Bad_Opcode },
6485    { Bad_Opcode },
6486    { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6487  },
6488
6489  /* PREFIX_VEX_0F3A4A */
6490  {
6491    { Bad_Opcode },
6492    { Bad_Opcode },
6493    { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6494  },
6495
6496  /* PREFIX_VEX_0F3A4B */
6497  {
6498    { Bad_Opcode },
6499    { Bad_Opcode },
6500    { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6501  },
6502
6503  /* PREFIX_VEX_0F3A4C */
6504  {
6505    { Bad_Opcode },
6506    { Bad_Opcode },
6507    { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6508  },
6509
6510  /* PREFIX_VEX_0F3A5C */
6511  {
6512    { Bad_Opcode },
6513    { Bad_Opcode },
6514    { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6515  },
6516
6517  /* PREFIX_VEX_0F3A5D */
6518  {
6519    { Bad_Opcode },
6520    { Bad_Opcode },
6521    { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6522  },
6523
6524  /* PREFIX_VEX_0F3A5E */
6525  {
6526    { Bad_Opcode },
6527    { Bad_Opcode },
6528    { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6529  },
6530
6531  /* PREFIX_VEX_0F3A5F */
6532  {
6533    { Bad_Opcode },
6534    { Bad_Opcode },
6535    { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6536  },
6537
6538  /* PREFIX_VEX_0F3A60 */
6539  {
6540    { Bad_Opcode },
6541    { Bad_Opcode },
6542    { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6543    { Bad_Opcode },
6544  },
6545
6546  /* PREFIX_VEX_0F3A61 */
6547  {
6548    { Bad_Opcode },
6549    { Bad_Opcode },
6550    { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6551  },
6552
6553  /* PREFIX_VEX_0F3A62 */
6554  {
6555    { Bad_Opcode },
6556    { Bad_Opcode },
6557    { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6558  },
6559
6560  /* PREFIX_VEX_0F3A63 */
6561  {
6562    { Bad_Opcode },
6563    { Bad_Opcode },
6564    { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6565  },
6566
6567  /* PREFIX_VEX_0F3A68 */
6568  {
6569    { Bad_Opcode },
6570    { Bad_Opcode },
6571    { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6572  },
6573
6574  /* PREFIX_VEX_0F3A69 */
6575  {
6576    { Bad_Opcode },
6577    { Bad_Opcode },
6578    { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6579  },
6580
6581  /* PREFIX_VEX_0F3A6A */
6582  {
6583    { Bad_Opcode },
6584    { Bad_Opcode },
6585    { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6586  },
6587
6588  /* PREFIX_VEX_0F3A6B */
6589  {
6590    { Bad_Opcode },
6591    { Bad_Opcode },
6592    { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6593  },
6594
6595  /* PREFIX_VEX_0F3A6C */
6596  {
6597    { Bad_Opcode },
6598    { Bad_Opcode },
6599    { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6600  },
6601
6602  /* PREFIX_VEX_0F3A6D */
6603  {
6604    { Bad_Opcode },
6605    { Bad_Opcode },
6606    { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6607  },
6608
6609  /* PREFIX_VEX_0F3A6E */
6610  {
6611    { Bad_Opcode },
6612    { Bad_Opcode },
6613    { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6614  },
6615
6616  /* PREFIX_VEX_0F3A6F */
6617  {
6618    { Bad_Opcode },
6619    { Bad_Opcode },
6620    { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6621  },
6622
6623  /* PREFIX_VEX_0F3A78 */
6624  {
6625    { Bad_Opcode },
6626    { Bad_Opcode },
6627    { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6628  },
6629
6630  /* PREFIX_VEX_0F3A79 */
6631  {
6632    { Bad_Opcode },
6633    { Bad_Opcode },
6634    { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6635  },
6636
6637  /* PREFIX_VEX_0F3A7A */
6638  {
6639    { Bad_Opcode },
6640    { Bad_Opcode },
6641    { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6642  },
6643
6644  /* PREFIX_VEX_0F3A7B */
6645  {
6646    { Bad_Opcode },
6647    { Bad_Opcode },
6648    { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6649  },
6650
6651  /* PREFIX_VEX_0F3A7C */
6652  {
6653    { Bad_Opcode },
6654    { Bad_Opcode },
6655    { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6656    { Bad_Opcode },
6657  },
6658
6659  /* PREFIX_VEX_0F3A7D */
6660  {
6661    { Bad_Opcode },
6662    { Bad_Opcode },
6663    { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6664  },
6665
6666  /* PREFIX_VEX_0F3A7E */
6667  {
6668    { Bad_Opcode },
6669    { Bad_Opcode },
6670    { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6671  },
6672
6673  /* PREFIX_VEX_0F3A7F */
6674  {
6675    { Bad_Opcode },
6676    { Bad_Opcode },
6677    { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6678  },
6679
6680  /* PREFIX_VEX_0F3ADF */
6681  {
6682    { Bad_Opcode },
6683    { Bad_Opcode },
6684    { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6685  },
6686
6687  /* PREFIX_VEX_0F3AF0 */
6688  {
6689    { Bad_Opcode },
6690    { Bad_Opcode },
6691    { Bad_Opcode },
6692    { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6693  },
6694
6695#define NEED_PREFIX_TABLE
6696#include "i386-dis-evex.h"
6697#undef NEED_PREFIX_TABLE
6698};
6699
6700static const struct dis386 x86_64_table[][2] = {
6701  /* X86_64_06 */
6702  {
6703    { "pushP", { es } },
6704  },
6705
6706  /* X86_64_07 */
6707  {
6708    { "popP", { es } },
6709  },
6710
6711  /* X86_64_0D */
6712  {
6713    { "pushP", { cs } },
6714  },
6715
6716  /* X86_64_16 */
6717  {
6718    { "pushP", { ss } },
6719  },
6720
6721  /* X86_64_17 */
6722  {
6723    { "popP", { ss } },
6724  },
6725
6726  /* X86_64_1E */
6727  {
6728    { "pushP", { ds } },
6729  },
6730
6731  /* X86_64_1F */
6732  {
6733    { "popP", { ds } },
6734  },
6735
6736  /* X86_64_27 */
6737  {
6738    { "daa", { XX } },
6739  },
6740
6741  /* X86_64_2F */
6742  {
6743    { "das", { XX } },
6744  },
6745
6746  /* X86_64_37 */
6747  {
6748    { "aaa", { XX } },
6749  },
6750
6751  /* X86_64_3F */
6752  {
6753    { "aas", { XX } },
6754  },
6755
6756  /* X86_64_60 */
6757  {
6758    { "pushaP", { XX } },
6759  },
6760
6761  /* X86_64_61 */
6762  {
6763    { "popaP", { XX } },
6764  },
6765
6766  /* X86_64_62 */
6767  {
6768    { MOD_TABLE (MOD_62_32BIT) },
6769    { EVEX_TABLE (EVEX_0F) },
6770  },
6771
6772  /* X86_64_63 */
6773  {
6774    { "arpl", { Ew, Gw } },
6775    { "movs{lq|xd}", { Gv, Ed } },
6776  },
6777
6778  /* X86_64_6D */
6779  {
6780    { "ins{R|}", { Yzr, indirDX } },
6781    { "ins{G|}", { Yzr, indirDX } },
6782  },
6783
6784  /* X86_64_6F */
6785  {
6786    { "outs{R|}", { indirDXr, Xz } },
6787    { "outs{G|}", { indirDXr, Xz } },
6788  },
6789
6790  /* X86_64_9A */
6791  {
6792    { "Jcall{T|}", { Ap } },
6793  },
6794
6795  /* X86_64_C4 */
6796  {
6797    { MOD_TABLE (MOD_C4_32BIT) },
6798    { VEX_C4_TABLE (VEX_0F) },
6799  },
6800
6801  /* X86_64_C5 */
6802  {
6803    { MOD_TABLE (MOD_C5_32BIT) },
6804    { VEX_C5_TABLE (VEX_0F) },
6805  },
6806
6807  /* X86_64_CE */
6808  {
6809    { "into", { XX } },
6810  },
6811
6812  /* X86_64_D4 */
6813  {
6814    { "aam", { Ib } },
6815  },
6816
6817  /* X86_64_D5 */
6818  {
6819    { "aad", { Ib } },
6820  },
6821
6822  /* X86_64_EA */
6823  {
6824    { "Jjmp{T|}", { Ap } },
6825  },
6826
6827  /* X86_64_0F01_REG_0 */
6828  {
6829    { "sgdt{Q|IQ}", { M } },
6830    { "sgdt", { M } },
6831  },
6832
6833  /* X86_64_0F01_REG_1 */
6834  {
6835    { "sidt{Q|IQ}", { M } },
6836    { "sidt", { M } },
6837  },
6838
6839  /* X86_64_0F01_REG_2 */
6840  {
6841    { "lgdt{Q|Q}", { M } },
6842    { "lgdt", { M } },
6843  },
6844
6845  /* X86_64_0F01_REG_3 */
6846  {
6847    { "lidt{Q|Q}", { M } },
6848    { "lidt", { M } },
6849  },
6850};
6851
6852static const struct dis386 three_byte_table[][256] = {
6853
6854  /* THREE_BYTE_0F38 */
6855  {
6856    /* 00 */
6857    { "pshufb",		{ MX, EM } },
6858    { "phaddw",		{ MX, EM } },
6859    { "phaddd",		{ MX, EM } },
6860    { "phaddsw",	{ MX, EM } },
6861    { "pmaddubsw",	{ MX, EM } },
6862    { "phsubw",		{ MX, EM } },
6863    { "phsubd",		{ MX, EM } },
6864    { "phsubsw",	{ MX, EM } },
6865    /* 08 */
6866    { "psignb",		{ MX, EM } },
6867    { "psignw",		{ MX, EM } },
6868    { "psignd",		{ MX, EM } },
6869    { "pmulhrsw",	{ MX, EM } },
6870    { Bad_Opcode },
6871    { Bad_Opcode },
6872    { Bad_Opcode },
6873    { Bad_Opcode },
6874    /* 10 */
6875    { PREFIX_TABLE (PREFIX_0F3810) },
6876    { Bad_Opcode },
6877    { Bad_Opcode },
6878    { Bad_Opcode },
6879    { PREFIX_TABLE (PREFIX_0F3814) },
6880    { PREFIX_TABLE (PREFIX_0F3815) },
6881    { Bad_Opcode },
6882    { PREFIX_TABLE (PREFIX_0F3817) },
6883    /* 18 */
6884    { Bad_Opcode },
6885    { Bad_Opcode },
6886    { Bad_Opcode },
6887    { Bad_Opcode },
6888    { "pabsb",		{ MX, EM } },
6889    { "pabsw",		{ MX, EM } },
6890    { "pabsd",		{ MX, EM } },
6891    { Bad_Opcode },
6892    /* 20 */
6893    { PREFIX_TABLE (PREFIX_0F3820) },
6894    { PREFIX_TABLE (PREFIX_0F3821) },
6895    { PREFIX_TABLE (PREFIX_0F3822) },
6896    { PREFIX_TABLE (PREFIX_0F3823) },
6897    { PREFIX_TABLE (PREFIX_0F3824) },
6898    { PREFIX_TABLE (PREFIX_0F3825) },
6899    { Bad_Opcode },
6900    { Bad_Opcode },
6901    /* 28 */
6902    { PREFIX_TABLE (PREFIX_0F3828) },
6903    { PREFIX_TABLE (PREFIX_0F3829) },
6904    { PREFIX_TABLE (PREFIX_0F382A) },
6905    { PREFIX_TABLE (PREFIX_0F382B) },
6906    { Bad_Opcode },
6907    { Bad_Opcode },
6908    { Bad_Opcode },
6909    { Bad_Opcode },
6910    /* 30 */
6911    { PREFIX_TABLE (PREFIX_0F3830) },
6912    { PREFIX_TABLE (PREFIX_0F3831) },
6913    { PREFIX_TABLE (PREFIX_0F3832) },
6914    { PREFIX_TABLE (PREFIX_0F3833) },
6915    { PREFIX_TABLE (PREFIX_0F3834) },
6916    { PREFIX_TABLE (PREFIX_0F3835) },
6917    { Bad_Opcode },
6918    { PREFIX_TABLE (PREFIX_0F3837) },
6919    /* 38 */
6920    { PREFIX_TABLE (PREFIX_0F3838) },
6921    { PREFIX_TABLE (PREFIX_0F3839) },
6922    { PREFIX_TABLE (PREFIX_0F383A) },
6923    { PREFIX_TABLE (PREFIX_0F383B) },
6924    { PREFIX_TABLE (PREFIX_0F383C) },
6925    { PREFIX_TABLE (PREFIX_0F383D) },
6926    { PREFIX_TABLE (PREFIX_0F383E) },
6927    { PREFIX_TABLE (PREFIX_0F383F) },
6928    /* 40 */
6929    { PREFIX_TABLE (PREFIX_0F3840) },
6930    { PREFIX_TABLE (PREFIX_0F3841) },
6931    { Bad_Opcode },
6932    { Bad_Opcode },
6933    { Bad_Opcode },
6934    { Bad_Opcode },
6935    { Bad_Opcode },
6936    { Bad_Opcode },
6937    /* 48 */
6938    { Bad_Opcode },
6939    { Bad_Opcode },
6940    { Bad_Opcode },
6941    { Bad_Opcode },
6942    { Bad_Opcode },
6943    { Bad_Opcode },
6944    { Bad_Opcode },
6945    { Bad_Opcode },
6946    /* 50 */
6947    { Bad_Opcode },
6948    { Bad_Opcode },
6949    { Bad_Opcode },
6950    { Bad_Opcode },
6951    { Bad_Opcode },
6952    { Bad_Opcode },
6953    { Bad_Opcode },
6954    { Bad_Opcode },
6955    /* 58 */
6956    { Bad_Opcode },
6957    { Bad_Opcode },
6958    { Bad_Opcode },
6959    { Bad_Opcode },
6960    { Bad_Opcode },
6961    { Bad_Opcode },
6962    { Bad_Opcode },
6963    { Bad_Opcode },
6964    /* 60 */
6965    { Bad_Opcode },
6966    { Bad_Opcode },
6967    { Bad_Opcode },
6968    { Bad_Opcode },
6969    { Bad_Opcode },
6970    { Bad_Opcode },
6971    { Bad_Opcode },
6972    { Bad_Opcode },
6973    /* 68 */
6974    { Bad_Opcode },
6975    { Bad_Opcode },
6976    { Bad_Opcode },
6977    { Bad_Opcode },
6978    { Bad_Opcode },
6979    { Bad_Opcode },
6980    { Bad_Opcode },
6981    { Bad_Opcode },
6982    /* 70 */
6983    { Bad_Opcode },
6984    { Bad_Opcode },
6985    { Bad_Opcode },
6986    { Bad_Opcode },
6987    { Bad_Opcode },
6988    { Bad_Opcode },
6989    { Bad_Opcode },
6990    { Bad_Opcode },
6991    /* 78 */
6992    { Bad_Opcode },
6993    { Bad_Opcode },
6994    { Bad_Opcode },
6995    { Bad_Opcode },
6996    { Bad_Opcode },
6997    { Bad_Opcode },
6998    { Bad_Opcode },
6999    { Bad_Opcode },
7000    /* 80 */
7001    { PREFIX_TABLE (PREFIX_0F3880) },
7002    { PREFIX_TABLE (PREFIX_0F3881) },
7003    { PREFIX_TABLE (PREFIX_0F3882) },
7004    { Bad_Opcode },
7005    { Bad_Opcode },
7006    { Bad_Opcode },
7007    { Bad_Opcode },
7008    { Bad_Opcode },
7009    /* 88 */
7010    { Bad_Opcode },
7011    { Bad_Opcode },
7012    { Bad_Opcode },
7013    { Bad_Opcode },
7014    { Bad_Opcode },
7015    { Bad_Opcode },
7016    { Bad_Opcode },
7017    { Bad_Opcode },
7018    /* 90 */
7019    { Bad_Opcode },
7020    { Bad_Opcode },
7021    { Bad_Opcode },
7022    { Bad_Opcode },
7023    { Bad_Opcode },
7024    { Bad_Opcode },
7025    { Bad_Opcode },
7026    { Bad_Opcode },
7027    /* 98 */
7028    { Bad_Opcode },
7029    { Bad_Opcode },
7030    { Bad_Opcode },
7031    { Bad_Opcode },
7032    { Bad_Opcode },
7033    { Bad_Opcode },
7034    { Bad_Opcode },
7035    { Bad_Opcode },
7036    /* a0 */
7037    { Bad_Opcode },
7038    { Bad_Opcode },
7039    { Bad_Opcode },
7040    { Bad_Opcode },
7041    { Bad_Opcode },
7042    { Bad_Opcode },
7043    { Bad_Opcode },
7044    { Bad_Opcode },
7045    /* a8 */
7046    { Bad_Opcode },
7047    { Bad_Opcode },
7048    { Bad_Opcode },
7049    { Bad_Opcode },
7050    { Bad_Opcode },
7051    { Bad_Opcode },
7052    { Bad_Opcode },
7053    { Bad_Opcode },
7054    /* b0 */
7055    { Bad_Opcode },
7056    { Bad_Opcode },
7057    { Bad_Opcode },
7058    { Bad_Opcode },
7059    { Bad_Opcode },
7060    { Bad_Opcode },
7061    { Bad_Opcode },
7062    { Bad_Opcode },
7063    /* b8 */
7064    { Bad_Opcode },
7065    { Bad_Opcode },
7066    { Bad_Opcode },
7067    { Bad_Opcode },
7068    { Bad_Opcode },
7069    { Bad_Opcode },
7070    { Bad_Opcode },
7071    { Bad_Opcode },
7072    /* c0 */
7073    { Bad_Opcode },
7074    { Bad_Opcode },
7075    { Bad_Opcode },
7076    { Bad_Opcode },
7077    { Bad_Opcode },
7078    { Bad_Opcode },
7079    { Bad_Opcode },
7080    { Bad_Opcode },
7081    /* c8 */
7082    { PREFIX_TABLE (PREFIX_0F38C8) },
7083    { PREFIX_TABLE (PREFIX_0F38C9) },
7084    { PREFIX_TABLE (PREFIX_0F38CA) },
7085    { PREFIX_TABLE (PREFIX_0F38CB) },
7086    { PREFIX_TABLE (PREFIX_0F38CC) },
7087    { PREFIX_TABLE (PREFIX_0F38CD) },
7088    { Bad_Opcode },
7089    { Bad_Opcode },
7090    /* d0 */
7091    { Bad_Opcode },
7092    { Bad_Opcode },
7093    { Bad_Opcode },
7094    { Bad_Opcode },
7095    { Bad_Opcode },
7096    { Bad_Opcode },
7097    { Bad_Opcode },
7098    { Bad_Opcode },
7099    /* d8 */
7100    { Bad_Opcode },
7101    { Bad_Opcode },
7102    { Bad_Opcode },
7103    { PREFIX_TABLE (PREFIX_0F38DB) },
7104    { PREFIX_TABLE (PREFIX_0F38DC) },
7105    { PREFIX_TABLE (PREFIX_0F38DD) },
7106    { PREFIX_TABLE (PREFIX_0F38DE) },
7107    { PREFIX_TABLE (PREFIX_0F38DF) },
7108    /* e0 */
7109    { Bad_Opcode },
7110    { Bad_Opcode },
7111    { Bad_Opcode },
7112    { Bad_Opcode },
7113    { Bad_Opcode },
7114    { Bad_Opcode },
7115    { Bad_Opcode },
7116    { Bad_Opcode },
7117    /* e8 */
7118    { Bad_Opcode },
7119    { Bad_Opcode },
7120    { Bad_Opcode },
7121    { Bad_Opcode },
7122    { Bad_Opcode },
7123    { Bad_Opcode },
7124    { Bad_Opcode },
7125    { Bad_Opcode },
7126    /* f0 */
7127    { PREFIX_TABLE (PREFIX_0F38F0) },
7128    { PREFIX_TABLE (PREFIX_0F38F1) },
7129    { Bad_Opcode },
7130    { Bad_Opcode },
7131    { Bad_Opcode },
7132    { Bad_Opcode },
7133    { PREFIX_TABLE (PREFIX_0F38F6) },
7134    { Bad_Opcode },
7135    /* f8 */
7136    { Bad_Opcode },
7137    { Bad_Opcode },
7138    { Bad_Opcode },
7139    { Bad_Opcode },
7140    { Bad_Opcode },
7141    { Bad_Opcode },
7142    { Bad_Opcode },
7143    { Bad_Opcode },
7144  },
7145  /* THREE_BYTE_0F3A */
7146  {
7147    /* 00 */
7148    { Bad_Opcode },
7149    { Bad_Opcode },
7150    { Bad_Opcode },
7151    { Bad_Opcode },
7152    { Bad_Opcode },
7153    { Bad_Opcode },
7154    { Bad_Opcode },
7155    { Bad_Opcode },
7156    /* 08 */
7157    { PREFIX_TABLE (PREFIX_0F3A08) },
7158    { PREFIX_TABLE (PREFIX_0F3A09) },
7159    { PREFIX_TABLE (PREFIX_0F3A0A) },
7160    { PREFIX_TABLE (PREFIX_0F3A0B) },
7161    { PREFIX_TABLE (PREFIX_0F3A0C) },
7162    { PREFIX_TABLE (PREFIX_0F3A0D) },
7163    { PREFIX_TABLE (PREFIX_0F3A0E) },
7164    { "palignr",	{ MX, EM, Ib } },
7165    /* 10 */
7166    { Bad_Opcode },
7167    { Bad_Opcode },
7168    { Bad_Opcode },
7169    { Bad_Opcode },
7170    { PREFIX_TABLE (PREFIX_0F3A14) },
7171    { PREFIX_TABLE (PREFIX_0F3A15) },
7172    { PREFIX_TABLE (PREFIX_0F3A16) },
7173    { PREFIX_TABLE (PREFIX_0F3A17) },
7174    /* 18 */
7175    { Bad_Opcode },
7176    { Bad_Opcode },
7177    { Bad_Opcode },
7178    { Bad_Opcode },
7179    { Bad_Opcode },
7180    { Bad_Opcode },
7181    { Bad_Opcode },
7182    { Bad_Opcode },
7183    /* 20 */
7184    { PREFIX_TABLE (PREFIX_0F3A20) },
7185    { PREFIX_TABLE (PREFIX_0F3A21) },
7186    { PREFIX_TABLE (PREFIX_0F3A22) },
7187    { Bad_Opcode },
7188    { Bad_Opcode },
7189    { Bad_Opcode },
7190    { Bad_Opcode },
7191    { Bad_Opcode },
7192    /* 28 */
7193    { Bad_Opcode },
7194    { Bad_Opcode },
7195    { Bad_Opcode },
7196    { Bad_Opcode },
7197    { Bad_Opcode },
7198    { Bad_Opcode },
7199    { Bad_Opcode },
7200    { Bad_Opcode },
7201    /* 30 */
7202    { Bad_Opcode },
7203    { Bad_Opcode },
7204    { Bad_Opcode },
7205    { Bad_Opcode },
7206    { Bad_Opcode },
7207    { Bad_Opcode },
7208    { Bad_Opcode },
7209    { Bad_Opcode },
7210    /* 38 */
7211    { Bad_Opcode },
7212    { Bad_Opcode },
7213    { Bad_Opcode },
7214    { Bad_Opcode },
7215    { Bad_Opcode },
7216    { Bad_Opcode },
7217    { Bad_Opcode },
7218    { Bad_Opcode },
7219    /* 40 */
7220    { PREFIX_TABLE (PREFIX_0F3A40) },
7221    { PREFIX_TABLE (PREFIX_0F3A41) },
7222    { PREFIX_TABLE (PREFIX_0F3A42) },
7223    { Bad_Opcode },
7224    { PREFIX_TABLE (PREFIX_0F3A44) },
7225    { Bad_Opcode },
7226    { Bad_Opcode },
7227    { Bad_Opcode },
7228    /* 48 */
7229    { Bad_Opcode },
7230    { Bad_Opcode },
7231    { Bad_Opcode },
7232    { Bad_Opcode },
7233    { Bad_Opcode },
7234    { Bad_Opcode },
7235    { Bad_Opcode },
7236    { Bad_Opcode },
7237    /* 50 */
7238    { Bad_Opcode },
7239    { Bad_Opcode },
7240    { Bad_Opcode },
7241    { Bad_Opcode },
7242    { Bad_Opcode },
7243    { Bad_Opcode },
7244    { Bad_Opcode },
7245    { Bad_Opcode },
7246    /* 58 */
7247    { Bad_Opcode },
7248    { Bad_Opcode },
7249    { Bad_Opcode },
7250    { Bad_Opcode },
7251    { Bad_Opcode },
7252    { Bad_Opcode },
7253    { Bad_Opcode },
7254    { Bad_Opcode },
7255    /* 60 */
7256    { PREFIX_TABLE (PREFIX_0F3A60) },
7257    { PREFIX_TABLE (PREFIX_0F3A61) },
7258    { PREFIX_TABLE (PREFIX_0F3A62) },
7259    { PREFIX_TABLE (PREFIX_0F3A63) },
7260    { Bad_Opcode },
7261    { Bad_Opcode },
7262    { Bad_Opcode },
7263    { Bad_Opcode },
7264    /* 68 */
7265    { Bad_Opcode },
7266    { Bad_Opcode },
7267    { Bad_Opcode },
7268    { Bad_Opcode },
7269    { Bad_Opcode },
7270    { Bad_Opcode },
7271    { Bad_Opcode },
7272    { Bad_Opcode },
7273    /* 70 */
7274    { Bad_Opcode },
7275    { Bad_Opcode },
7276    { Bad_Opcode },
7277    { Bad_Opcode },
7278    { Bad_Opcode },
7279    { Bad_Opcode },
7280    { Bad_Opcode },
7281    { Bad_Opcode },
7282    /* 78 */
7283    { Bad_Opcode },
7284    { Bad_Opcode },
7285    { Bad_Opcode },
7286    { Bad_Opcode },
7287    { Bad_Opcode },
7288    { Bad_Opcode },
7289    { Bad_Opcode },
7290    { Bad_Opcode },
7291    /* 80 */
7292    { Bad_Opcode },
7293    { Bad_Opcode },
7294    { Bad_Opcode },
7295    { Bad_Opcode },
7296    { Bad_Opcode },
7297    { Bad_Opcode },
7298    { Bad_Opcode },
7299    { Bad_Opcode },
7300    /* 88 */
7301    { Bad_Opcode },
7302    { Bad_Opcode },
7303    { Bad_Opcode },
7304    { Bad_Opcode },
7305    { Bad_Opcode },
7306    { Bad_Opcode },
7307    { Bad_Opcode },
7308    { Bad_Opcode },
7309    /* 90 */
7310    { Bad_Opcode },
7311    { Bad_Opcode },
7312    { Bad_Opcode },
7313    { Bad_Opcode },
7314    { Bad_Opcode },
7315    { Bad_Opcode },
7316    { Bad_Opcode },
7317    { Bad_Opcode },
7318    /* 98 */
7319    { Bad_Opcode },
7320    { Bad_Opcode },
7321    { Bad_Opcode },
7322    { Bad_Opcode },
7323    { Bad_Opcode },
7324    { Bad_Opcode },
7325    { Bad_Opcode },
7326    { Bad_Opcode },
7327    /* a0 */
7328    { Bad_Opcode },
7329    { Bad_Opcode },
7330    { Bad_Opcode },
7331    { Bad_Opcode },
7332    { Bad_Opcode },
7333    { Bad_Opcode },
7334    { Bad_Opcode },
7335    { Bad_Opcode },
7336    /* a8 */
7337    { Bad_Opcode },
7338    { Bad_Opcode },
7339    { Bad_Opcode },
7340    { Bad_Opcode },
7341    { Bad_Opcode },
7342    { Bad_Opcode },
7343    { Bad_Opcode },
7344    { Bad_Opcode },
7345    /* b0 */
7346    { Bad_Opcode },
7347    { Bad_Opcode },
7348    { Bad_Opcode },
7349    { Bad_Opcode },
7350    { Bad_Opcode },
7351    { Bad_Opcode },
7352    { Bad_Opcode },
7353    { Bad_Opcode },
7354    /* b8 */
7355    { Bad_Opcode },
7356    { Bad_Opcode },
7357    { Bad_Opcode },
7358    { Bad_Opcode },
7359    { Bad_Opcode },
7360    { Bad_Opcode },
7361    { Bad_Opcode },
7362    { Bad_Opcode },
7363    /* c0 */
7364    { Bad_Opcode },
7365    { Bad_Opcode },
7366    { Bad_Opcode },
7367    { Bad_Opcode },
7368    { Bad_Opcode },
7369    { Bad_Opcode },
7370    { Bad_Opcode },
7371    { Bad_Opcode },
7372    /* c8 */
7373    { Bad_Opcode },
7374    { Bad_Opcode },
7375    { Bad_Opcode },
7376    { Bad_Opcode },
7377    { PREFIX_TABLE (PREFIX_0F3ACC) },
7378    { Bad_Opcode },
7379    { Bad_Opcode },
7380    { Bad_Opcode },
7381    /* d0 */
7382    { Bad_Opcode },
7383    { Bad_Opcode },
7384    { Bad_Opcode },
7385    { Bad_Opcode },
7386    { Bad_Opcode },
7387    { Bad_Opcode },
7388    { Bad_Opcode },
7389    { Bad_Opcode },
7390    /* d8 */
7391    { Bad_Opcode },
7392    { Bad_Opcode },
7393    { Bad_Opcode },
7394    { Bad_Opcode },
7395    { Bad_Opcode },
7396    { Bad_Opcode },
7397    { Bad_Opcode },
7398    { PREFIX_TABLE (PREFIX_0F3ADF) },
7399    /* e0 */
7400    { Bad_Opcode },
7401    { Bad_Opcode },
7402    { Bad_Opcode },
7403    { Bad_Opcode },
7404    { Bad_Opcode },
7405    { Bad_Opcode },
7406    { Bad_Opcode },
7407    { Bad_Opcode },
7408    /* e8 */
7409    { Bad_Opcode },
7410    { Bad_Opcode },
7411    { Bad_Opcode },
7412    { Bad_Opcode },
7413    { Bad_Opcode },
7414    { Bad_Opcode },
7415    { Bad_Opcode },
7416    { Bad_Opcode },
7417    /* f0 */
7418    { Bad_Opcode },
7419    { Bad_Opcode },
7420    { Bad_Opcode },
7421    { Bad_Opcode },
7422    { Bad_Opcode },
7423    { Bad_Opcode },
7424    { Bad_Opcode },
7425    { Bad_Opcode },
7426    /* f8 */
7427    { Bad_Opcode },
7428    { Bad_Opcode },
7429    { Bad_Opcode },
7430    { Bad_Opcode },
7431    { Bad_Opcode },
7432    { Bad_Opcode },
7433    { Bad_Opcode },
7434    { Bad_Opcode },
7435  },
7436
7437  /* THREE_BYTE_0F7A */
7438  {
7439    /* 00 */
7440    { Bad_Opcode },
7441    { Bad_Opcode },
7442    { Bad_Opcode },
7443    { Bad_Opcode },
7444    { Bad_Opcode },
7445    { Bad_Opcode },
7446    { Bad_Opcode },
7447    { Bad_Opcode },
7448    /* 08 */
7449    { Bad_Opcode },
7450    { Bad_Opcode },
7451    { Bad_Opcode },
7452    { Bad_Opcode },
7453    { Bad_Opcode },
7454    { Bad_Opcode },
7455    { Bad_Opcode },
7456    { Bad_Opcode },
7457    /* 10 */
7458    { Bad_Opcode },
7459    { Bad_Opcode },
7460    { Bad_Opcode },
7461    { Bad_Opcode },
7462    { Bad_Opcode },
7463    { Bad_Opcode },
7464    { Bad_Opcode },
7465    { Bad_Opcode },
7466    /* 18 */
7467    { Bad_Opcode },
7468    { Bad_Opcode },
7469    { Bad_Opcode },
7470    { Bad_Opcode },
7471    { Bad_Opcode },
7472    { Bad_Opcode },
7473    { Bad_Opcode },
7474    { Bad_Opcode },
7475    /* 20 */
7476    { "ptest",		{ XX } },
7477    { Bad_Opcode },
7478    { Bad_Opcode },
7479    { Bad_Opcode },
7480    { Bad_Opcode },
7481    { Bad_Opcode },
7482    { Bad_Opcode },
7483    { Bad_Opcode },
7484    /* 28 */
7485    { Bad_Opcode },
7486    { Bad_Opcode },
7487    { Bad_Opcode },
7488    { Bad_Opcode },
7489    { Bad_Opcode },
7490    { Bad_Opcode },
7491    { Bad_Opcode },
7492    { Bad_Opcode },
7493    /* 30 */
7494    { Bad_Opcode },
7495    { Bad_Opcode },
7496    { Bad_Opcode },
7497    { Bad_Opcode },
7498    { Bad_Opcode },
7499    { Bad_Opcode },
7500    { Bad_Opcode },
7501    { Bad_Opcode },
7502    /* 38 */
7503    { Bad_Opcode },
7504    { Bad_Opcode },
7505    { Bad_Opcode },
7506    { Bad_Opcode },
7507    { Bad_Opcode },
7508    { Bad_Opcode },
7509    { Bad_Opcode },
7510    { Bad_Opcode },
7511    /* 40 */
7512    { Bad_Opcode },
7513    { "phaddbw",	{ XM, EXq } },
7514    { "phaddbd",	{ XM, EXq } },
7515    { "phaddbq",	{ XM, EXq } },
7516    { Bad_Opcode },
7517    { Bad_Opcode },
7518    { "phaddwd",	{ XM, EXq } },
7519    { "phaddwq",	{ XM, EXq } },
7520    /* 48 */
7521    { Bad_Opcode },
7522    { Bad_Opcode },
7523    { Bad_Opcode },
7524    { "phadddq",	{ XM, EXq } },
7525    { Bad_Opcode },
7526    { Bad_Opcode },
7527    { Bad_Opcode },
7528    { Bad_Opcode },
7529    /* 50 */
7530    { Bad_Opcode },
7531    { "phaddubw",	{ XM, EXq } },
7532    { "phaddubd",	{ XM, EXq } },
7533    { "phaddubq",	{ XM, EXq } },
7534    { Bad_Opcode },
7535    { Bad_Opcode },
7536    { "phadduwd",	{ XM, EXq } },
7537    { "phadduwq",	{ XM, EXq } },
7538    /* 58 */
7539    { Bad_Opcode },
7540    { Bad_Opcode },
7541    { Bad_Opcode },
7542    { "phaddudq",	{ XM, EXq } },
7543    { Bad_Opcode },
7544    { Bad_Opcode },
7545    { Bad_Opcode },
7546    { Bad_Opcode },
7547    /* 60 */
7548    { Bad_Opcode },
7549    { "phsubbw",	{ XM, EXq } },
7550    { "phsubbd",	{ XM, EXq } },
7551    { "phsubbq",	{ XM, EXq } },
7552    { Bad_Opcode },
7553    { Bad_Opcode },
7554    { Bad_Opcode },
7555    { Bad_Opcode },
7556    /* 68 */
7557    { Bad_Opcode },
7558    { Bad_Opcode },
7559    { Bad_Opcode },
7560    { Bad_Opcode },
7561    { Bad_Opcode },
7562    { Bad_Opcode },
7563    { Bad_Opcode },
7564    { Bad_Opcode },
7565    /* 70 */
7566    { Bad_Opcode },
7567    { Bad_Opcode },
7568    { Bad_Opcode },
7569    { Bad_Opcode },
7570    { Bad_Opcode },
7571    { Bad_Opcode },
7572    { Bad_Opcode },
7573    { Bad_Opcode },
7574    /* 78 */
7575    { Bad_Opcode },
7576    { Bad_Opcode },
7577    { Bad_Opcode },
7578    { Bad_Opcode },
7579    { Bad_Opcode },
7580    { Bad_Opcode },
7581    { Bad_Opcode },
7582    { Bad_Opcode },
7583    /* 80 */
7584    { Bad_Opcode },
7585    { Bad_Opcode },
7586    { Bad_Opcode },
7587    { Bad_Opcode },
7588    { Bad_Opcode },
7589    { Bad_Opcode },
7590    { Bad_Opcode },
7591    { Bad_Opcode },
7592    /* 88 */
7593    { Bad_Opcode },
7594    { Bad_Opcode },
7595    { Bad_Opcode },
7596    { Bad_Opcode },
7597    { Bad_Opcode },
7598    { Bad_Opcode },
7599    { Bad_Opcode },
7600    { Bad_Opcode },
7601    /* 90 */
7602    { Bad_Opcode },
7603    { Bad_Opcode },
7604    { Bad_Opcode },
7605    { Bad_Opcode },
7606    { Bad_Opcode },
7607    { Bad_Opcode },
7608    { Bad_Opcode },
7609    { Bad_Opcode },
7610    /* 98 */
7611    { Bad_Opcode },
7612    { Bad_Opcode },
7613    { Bad_Opcode },
7614    { Bad_Opcode },
7615    { Bad_Opcode },
7616    { Bad_Opcode },
7617    { Bad_Opcode },
7618    { Bad_Opcode },
7619    /* a0 */
7620    { Bad_Opcode },
7621    { Bad_Opcode },
7622    { Bad_Opcode },
7623    { Bad_Opcode },
7624    { Bad_Opcode },
7625    { Bad_Opcode },
7626    { Bad_Opcode },
7627    { Bad_Opcode },
7628    /* a8 */
7629    { Bad_Opcode },
7630    { Bad_Opcode },
7631    { Bad_Opcode },
7632    { Bad_Opcode },
7633    { Bad_Opcode },
7634    { Bad_Opcode },
7635    { Bad_Opcode },
7636    { Bad_Opcode },
7637    /* b0 */
7638    { Bad_Opcode },
7639    { Bad_Opcode },
7640    { Bad_Opcode },
7641    { Bad_Opcode },
7642    { Bad_Opcode },
7643    { Bad_Opcode },
7644    { Bad_Opcode },
7645    { Bad_Opcode },
7646    /* b8 */
7647    { Bad_Opcode },
7648    { Bad_Opcode },
7649    { Bad_Opcode },
7650    { Bad_Opcode },
7651    { Bad_Opcode },
7652    { Bad_Opcode },
7653    { Bad_Opcode },
7654    { Bad_Opcode },
7655    /* c0 */
7656    { Bad_Opcode },
7657    { Bad_Opcode },
7658    { Bad_Opcode },
7659    { Bad_Opcode },
7660    { Bad_Opcode },
7661    { Bad_Opcode },
7662    { Bad_Opcode },
7663    { Bad_Opcode },
7664    /* c8 */
7665    { Bad_Opcode },
7666    { Bad_Opcode },
7667    { Bad_Opcode },
7668    { Bad_Opcode },
7669    { Bad_Opcode },
7670    { Bad_Opcode },
7671    { Bad_Opcode },
7672    { Bad_Opcode },
7673    /* d0 */
7674    { Bad_Opcode },
7675    { Bad_Opcode },
7676    { Bad_Opcode },
7677    { Bad_Opcode },
7678    { Bad_Opcode },
7679    { Bad_Opcode },
7680    { Bad_Opcode },
7681    { Bad_Opcode },
7682    /* d8 */
7683    { Bad_Opcode },
7684    { Bad_Opcode },
7685    { Bad_Opcode },
7686    { Bad_Opcode },
7687    { Bad_Opcode },
7688    { Bad_Opcode },
7689    { Bad_Opcode },
7690    { Bad_Opcode },
7691    /* e0 */
7692    { Bad_Opcode },
7693    { Bad_Opcode },
7694    { Bad_Opcode },
7695    { Bad_Opcode },
7696    { Bad_Opcode },
7697    { Bad_Opcode },
7698    { Bad_Opcode },
7699    { Bad_Opcode },
7700    /* e8 */
7701    { Bad_Opcode },
7702    { Bad_Opcode },
7703    { Bad_Opcode },
7704    { Bad_Opcode },
7705    { Bad_Opcode },
7706    { Bad_Opcode },
7707    { Bad_Opcode },
7708    { Bad_Opcode },
7709    /* f0 */
7710    { Bad_Opcode },
7711    { Bad_Opcode },
7712    { Bad_Opcode },
7713    { Bad_Opcode },
7714    { Bad_Opcode },
7715    { Bad_Opcode },
7716    { Bad_Opcode },
7717    { Bad_Opcode },
7718    /* f8 */
7719    { Bad_Opcode },
7720    { Bad_Opcode },
7721    { Bad_Opcode },
7722    { Bad_Opcode },
7723    { Bad_Opcode },
7724    { Bad_Opcode },
7725    { Bad_Opcode },
7726    { Bad_Opcode },
7727  },
7728};
7729
7730static const struct dis386 xop_table[][256] = {
7731  /* XOP_08 */
7732  {
7733    /* 00 */
7734    { Bad_Opcode },
7735    { Bad_Opcode },
7736    { Bad_Opcode },
7737    { Bad_Opcode },
7738    { Bad_Opcode },
7739    { Bad_Opcode },
7740    { Bad_Opcode },
7741    { Bad_Opcode },
7742    /* 08 */
7743    { Bad_Opcode },
7744    { Bad_Opcode },
7745    { Bad_Opcode },
7746    { Bad_Opcode },
7747    { Bad_Opcode },
7748    { Bad_Opcode },
7749    { Bad_Opcode },
7750    { Bad_Opcode },
7751    /* 10 */
7752    { Bad_Opcode },
7753    { Bad_Opcode },
7754    { Bad_Opcode },
7755    { Bad_Opcode },
7756    { Bad_Opcode },
7757    { Bad_Opcode },
7758    { Bad_Opcode },
7759    { Bad_Opcode },
7760    /* 18 */
7761    { Bad_Opcode },
7762    { Bad_Opcode },
7763    { Bad_Opcode },
7764    { Bad_Opcode },
7765    { Bad_Opcode },
7766    { Bad_Opcode },
7767    { Bad_Opcode },
7768    { Bad_Opcode },
7769    /* 20 */
7770    { Bad_Opcode },
7771    { Bad_Opcode },
7772    { Bad_Opcode },
7773    { Bad_Opcode },
7774    { Bad_Opcode },
7775    { Bad_Opcode },
7776    { Bad_Opcode },
7777    { Bad_Opcode },
7778    /* 28 */
7779    { Bad_Opcode },
7780    { Bad_Opcode },
7781    { Bad_Opcode },
7782    { Bad_Opcode },
7783    { Bad_Opcode },
7784    { Bad_Opcode },
7785    { Bad_Opcode },
7786    { Bad_Opcode },
7787    /* 30 */
7788    { Bad_Opcode },
7789    { Bad_Opcode },
7790    { Bad_Opcode },
7791    { Bad_Opcode },
7792    { Bad_Opcode },
7793    { Bad_Opcode },
7794    { Bad_Opcode },
7795    { Bad_Opcode },
7796    /* 38 */
7797    { Bad_Opcode },
7798    { Bad_Opcode },
7799    { Bad_Opcode },
7800    { Bad_Opcode },
7801    { Bad_Opcode },
7802    { Bad_Opcode },
7803    { Bad_Opcode },
7804    { Bad_Opcode },
7805    /* 40 */
7806    { Bad_Opcode },
7807    { Bad_Opcode },
7808    { Bad_Opcode },
7809    { Bad_Opcode },
7810    { Bad_Opcode },
7811    { Bad_Opcode },
7812    { Bad_Opcode },
7813    { Bad_Opcode },
7814    /* 48 */
7815    { Bad_Opcode },
7816    { Bad_Opcode },
7817    { Bad_Opcode },
7818    { Bad_Opcode },
7819    { Bad_Opcode },
7820    { Bad_Opcode },
7821    { Bad_Opcode },
7822    { Bad_Opcode },
7823    /* 50 */
7824    { Bad_Opcode },
7825    { Bad_Opcode },
7826    { Bad_Opcode },
7827    { Bad_Opcode },
7828    { Bad_Opcode },
7829    { Bad_Opcode },
7830    { Bad_Opcode },
7831    { Bad_Opcode },
7832    /* 58 */
7833    { Bad_Opcode },
7834    { Bad_Opcode },
7835    { Bad_Opcode },
7836    { Bad_Opcode },
7837    { Bad_Opcode },
7838    { Bad_Opcode },
7839    { Bad_Opcode },
7840    { Bad_Opcode },
7841    /* 60 */
7842    { Bad_Opcode },
7843    { Bad_Opcode },
7844    { Bad_Opcode },
7845    { Bad_Opcode },
7846    { Bad_Opcode },
7847    { Bad_Opcode },
7848    { Bad_Opcode },
7849    { Bad_Opcode },
7850    /* 68 */
7851    { Bad_Opcode },
7852    { Bad_Opcode },
7853    { Bad_Opcode },
7854    { Bad_Opcode },
7855    { Bad_Opcode },
7856    { Bad_Opcode },
7857    { Bad_Opcode },
7858    { Bad_Opcode },
7859    /* 70 */
7860    { Bad_Opcode },
7861    { Bad_Opcode },
7862    { Bad_Opcode },
7863    { Bad_Opcode },
7864    { Bad_Opcode },
7865    { Bad_Opcode },
7866    { Bad_Opcode },
7867    { Bad_Opcode },
7868    /* 78 */
7869    { Bad_Opcode },
7870    { Bad_Opcode },
7871    { Bad_Opcode },
7872    { Bad_Opcode },
7873    { Bad_Opcode },
7874    { Bad_Opcode },
7875    { Bad_Opcode },
7876    { Bad_Opcode },
7877    /* 80 */
7878    { Bad_Opcode },
7879    { Bad_Opcode },
7880    { Bad_Opcode },
7881    { Bad_Opcode },
7882    { Bad_Opcode },
7883    { "vpmacssww", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7884    { "vpmacsswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7885    { "vpmacssdql", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7886    /* 88 */
7887    { Bad_Opcode },
7888    { Bad_Opcode },
7889    { Bad_Opcode },
7890    { Bad_Opcode },
7891    { Bad_Opcode },
7892    { Bad_Opcode },
7893    { "vpmacssdd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7894    { "vpmacssdqh", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7895    /* 90 */
7896    { Bad_Opcode },
7897    { Bad_Opcode },
7898    { Bad_Opcode },
7899    { Bad_Opcode },
7900    { Bad_Opcode },
7901    { "vpmacsww", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7902    { "vpmacswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7903    { "vpmacsdql", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7904    /* 98 */
7905    { Bad_Opcode },
7906    { Bad_Opcode },
7907    { Bad_Opcode },
7908    { Bad_Opcode },
7909    { Bad_Opcode },
7910    { Bad_Opcode },
7911    { "vpmacsdd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7912    { "vpmacsdqh", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7913    /* a0 */
7914    { Bad_Opcode },
7915    { Bad_Opcode },
7916    { "vpcmov", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7917    { "vpperm", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7918    { Bad_Opcode },
7919    { Bad_Opcode },
7920    { "vpmadcsswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7921    { Bad_Opcode },
7922    /* a8 */
7923    { Bad_Opcode },
7924    { Bad_Opcode },
7925    { Bad_Opcode },
7926    { Bad_Opcode },
7927    { Bad_Opcode },
7928    { Bad_Opcode },
7929    { Bad_Opcode },
7930    { Bad_Opcode },
7931    /* b0 */
7932    { Bad_Opcode },
7933    { Bad_Opcode },
7934    { Bad_Opcode },
7935    { Bad_Opcode },
7936    { Bad_Opcode },
7937    { Bad_Opcode },
7938    { "vpmadcswd", 	{ XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
7939    { Bad_Opcode },
7940    /* b8 */
7941    { Bad_Opcode },
7942    { Bad_Opcode },
7943    { Bad_Opcode },
7944    { Bad_Opcode },
7945    { Bad_Opcode },
7946    { Bad_Opcode },
7947    { Bad_Opcode },
7948    { Bad_Opcode },
7949    /* c0 */
7950    { "vprotb", 	{ XM, Vex_2src_1, Ib } },
7951    { "vprotw", 	{ XM, Vex_2src_1, Ib } },
7952    { "vprotd", 	{ XM, Vex_2src_1, Ib } },
7953    { "vprotq", 	{ XM, Vex_2src_1, Ib } },
7954    { Bad_Opcode },
7955    { Bad_Opcode },
7956    { Bad_Opcode },
7957    { Bad_Opcode },
7958    /* c8 */
7959    { Bad_Opcode },
7960    { Bad_Opcode },
7961    { Bad_Opcode },
7962    { Bad_Opcode },
7963    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7964    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7965    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7966    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7967    /* d0 */
7968    { Bad_Opcode },
7969    { Bad_Opcode },
7970    { Bad_Opcode },
7971    { Bad_Opcode },
7972    { Bad_Opcode },
7973    { Bad_Opcode },
7974    { Bad_Opcode },
7975    { Bad_Opcode },
7976    /* d8 */
7977    { Bad_Opcode },
7978    { Bad_Opcode },
7979    { Bad_Opcode },
7980    { Bad_Opcode },
7981    { Bad_Opcode },
7982    { Bad_Opcode },
7983    { Bad_Opcode },
7984    { Bad_Opcode },
7985    /* e0 */
7986    { Bad_Opcode },
7987    { Bad_Opcode },
7988    { Bad_Opcode },
7989    { Bad_Opcode },
7990    { Bad_Opcode },
7991    { Bad_Opcode },
7992    { Bad_Opcode },
7993    { Bad_Opcode },
7994    /* e8 */
7995    { Bad_Opcode },
7996    { Bad_Opcode },
7997    { Bad_Opcode },
7998    { Bad_Opcode },
7999    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8000    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8001    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8002    { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8003    /* f0 */
8004    { Bad_Opcode },
8005    { Bad_Opcode },
8006    { Bad_Opcode },
8007    { Bad_Opcode },
8008    { Bad_Opcode },
8009    { Bad_Opcode },
8010    { Bad_Opcode },
8011    { Bad_Opcode },
8012    /* f8 */
8013    { Bad_Opcode },
8014    { Bad_Opcode },
8015    { Bad_Opcode },
8016    { Bad_Opcode },
8017    { Bad_Opcode },
8018    { Bad_Opcode },
8019    { Bad_Opcode },
8020    { Bad_Opcode },
8021  },
8022  /* XOP_09 */
8023  {
8024    /* 00 */
8025    { Bad_Opcode },
8026    { REG_TABLE (REG_XOP_TBM_01) },
8027    { REG_TABLE (REG_XOP_TBM_02) },
8028    { Bad_Opcode },
8029    { Bad_Opcode },
8030    { Bad_Opcode },
8031    { Bad_Opcode },
8032    { Bad_Opcode },
8033    /* 08 */
8034    { Bad_Opcode },
8035    { Bad_Opcode },
8036    { Bad_Opcode },
8037    { Bad_Opcode },
8038    { Bad_Opcode },
8039    { Bad_Opcode },
8040    { Bad_Opcode },
8041    { Bad_Opcode },
8042    /* 10 */
8043    { Bad_Opcode },
8044    { Bad_Opcode },
8045    { REG_TABLE (REG_XOP_LWPCB) },
8046    { Bad_Opcode },
8047    { Bad_Opcode },
8048    { Bad_Opcode },
8049    { Bad_Opcode },
8050    { Bad_Opcode },
8051    /* 18 */
8052    { Bad_Opcode },
8053    { Bad_Opcode },
8054    { Bad_Opcode },
8055    { Bad_Opcode },
8056    { Bad_Opcode },
8057    { Bad_Opcode },
8058    { Bad_Opcode },
8059    { Bad_Opcode },
8060    /* 20 */
8061    { Bad_Opcode },
8062    { Bad_Opcode },
8063    { Bad_Opcode },
8064    { Bad_Opcode },
8065    { Bad_Opcode },
8066    { Bad_Opcode },
8067    { Bad_Opcode },
8068    { Bad_Opcode },
8069    /* 28 */
8070    { Bad_Opcode },
8071    { Bad_Opcode },
8072    { Bad_Opcode },
8073    { Bad_Opcode },
8074    { Bad_Opcode },
8075    { Bad_Opcode },
8076    { Bad_Opcode },
8077    { Bad_Opcode },
8078    /* 30 */
8079    { Bad_Opcode },
8080    { Bad_Opcode },
8081    { Bad_Opcode },
8082    { Bad_Opcode },
8083    { Bad_Opcode },
8084    { Bad_Opcode },
8085    { Bad_Opcode },
8086    { Bad_Opcode },
8087    /* 38 */
8088    { Bad_Opcode },
8089    { Bad_Opcode },
8090    { Bad_Opcode },
8091    { Bad_Opcode },
8092    { Bad_Opcode },
8093    { Bad_Opcode },
8094    { Bad_Opcode },
8095    { Bad_Opcode },
8096    /* 40 */
8097    { Bad_Opcode },
8098    { Bad_Opcode },
8099    { Bad_Opcode },
8100    { Bad_Opcode },
8101    { Bad_Opcode },
8102    { Bad_Opcode },
8103    { Bad_Opcode },
8104    { Bad_Opcode },
8105    /* 48 */
8106    { Bad_Opcode },
8107    { Bad_Opcode },
8108    { Bad_Opcode },
8109    { Bad_Opcode },
8110    { Bad_Opcode },
8111    { Bad_Opcode },
8112    { Bad_Opcode },
8113    { Bad_Opcode },
8114    /* 50 */
8115    { Bad_Opcode },
8116    { Bad_Opcode },
8117    { Bad_Opcode },
8118    { Bad_Opcode },
8119    { Bad_Opcode },
8120    { Bad_Opcode },
8121    { Bad_Opcode },
8122    { Bad_Opcode },
8123    /* 58 */
8124    { Bad_Opcode },
8125    { Bad_Opcode },
8126    { Bad_Opcode },
8127    { Bad_Opcode },
8128    { Bad_Opcode },
8129    { Bad_Opcode },
8130    { Bad_Opcode },
8131    { Bad_Opcode },
8132    /* 60 */
8133    { Bad_Opcode },
8134    { Bad_Opcode },
8135    { Bad_Opcode },
8136    { Bad_Opcode },
8137    { Bad_Opcode },
8138    { Bad_Opcode },
8139    { Bad_Opcode },
8140    { Bad_Opcode },
8141    /* 68 */
8142    { Bad_Opcode },
8143    { Bad_Opcode },
8144    { Bad_Opcode },
8145    { Bad_Opcode },
8146    { Bad_Opcode },
8147    { Bad_Opcode },
8148    { Bad_Opcode },
8149    { Bad_Opcode },
8150    /* 70 */
8151    { Bad_Opcode },
8152    { Bad_Opcode },
8153    { Bad_Opcode },
8154    { Bad_Opcode },
8155    { Bad_Opcode },
8156    { Bad_Opcode },
8157    { Bad_Opcode },
8158    { Bad_Opcode },
8159    /* 78 */
8160    { Bad_Opcode },
8161    { Bad_Opcode },
8162    { Bad_Opcode },
8163    { Bad_Opcode },
8164    { Bad_Opcode },
8165    { Bad_Opcode },
8166    { Bad_Opcode },
8167    { Bad_Opcode },
8168    /* 80 */
8169    { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8170    { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8171    { "vfrczss", 	{ XM, EXd } },
8172    { "vfrczsd", 	{ XM, EXq } },
8173    { Bad_Opcode },
8174    { Bad_Opcode },
8175    { Bad_Opcode },
8176    { Bad_Opcode },
8177    /* 88 */
8178    { Bad_Opcode },
8179    { Bad_Opcode },
8180    { Bad_Opcode },
8181    { Bad_Opcode },
8182    { Bad_Opcode },
8183    { Bad_Opcode },
8184    { Bad_Opcode },
8185    { Bad_Opcode },
8186    /* 90 */
8187    { "vprotb",		{ XM, Vex_2src_1, Vex_2src_2 } },
8188    { "vprotw",		{ XM, Vex_2src_1, Vex_2src_2 } },
8189    { "vprotd",		{ XM, Vex_2src_1, Vex_2src_2 } },
8190    { "vprotq",		{ XM, Vex_2src_1, Vex_2src_2 } },
8191    { "vpshlb",		{ XM, Vex_2src_1, Vex_2src_2 } },
8192    { "vpshlw",		{ XM, Vex_2src_1, Vex_2src_2 } },
8193    { "vpshld",		{ XM, Vex_2src_1, Vex_2src_2 } },
8194    { "vpshlq",		{ XM, Vex_2src_1, Vex_2src_2 } },
8195    /* 98 */
8196    { "vpshab",		{ XM, Vex_2src_1, Vex_2src_2 } },
8197    { "vpshaw",		{ XM, Vex_2src_1, Vex_2src_2 } },
8198    { "vpshad",		{ XM, Vex_2src_1, Vex_2src_2 } },
8199    { "vpshaq",		{ XM, Vex_2src_1, Vex_2src_2 } },
8200    { Bad_Opcode },
8201    { Bad_Opcode },
8202    { Bad_Opcode },
8203    { Bad_Opcode },
8204    /* a0 */
8205    { Bad_Opcode },
8206    { Bad_Opcode },
8207    { Bad_Opcode },
8208    { Bad_Opcode },
8209    { Bad_Opcode },
8210    { Bad_Opcode },
8211    { Bad_Opcode },
8212    { Bad_Opcode },
8213    /* a8 */
8214    { Bad_Opcode },
8215    { Bad_Opcode },
8216    { Bad_Opcode },
8217    { Bad_Opcode },
8218    { Bad_Opcode },
8219    { Bad_Opcode },
8220    { Bad_Opcode },
8221    { Bad_Opcode },
8222    /* b0 */
8223    { Bad_Opcode },
8224    { Bad_Opcode },
8225    { Bad_Opcode },
8226    { Bad_Opcode },
8227    { Bad_Opcode },
8228    { Bad_Opcode },
8229    { Bad_Opcode },
8230    { Bad_Opcode },
8231    /* b8 */
8232    { Bad_Opcode },
8233    { Bad_Opcode },
8234    { Bad_Opcode },
8235    { Bad_Opcode },
8236    { Bad_Opcode },
8237    { Bad_Opcode },
8238    { Bad_Opcode },
8239    { Bad_Opcode },
8240    /* c0 */
8241    { Bad_Opcode },
8242    { "vphaddbw",	{ XM, EXxmm } },
8243    { "vphaddbd",	{ XM, EXxmm } },
8244    { "vphaddbq",	{ XM, EXxmm } },
8245    { Bad_Opcode },
8246    { Bad_Opcode },
8247    { "vphaddwd",	{ XM, EXxmm } },
8248    { "vphaddwq",	{ XM, EXxmm } },
8249    /* c8 */
8250    { Bad_Opcode },
8251    { Bad_Opcode },
8252    { Bad_Opcode },
8253    { "vphadddq",	{ XM, EXxmm } },
8254    { Bad_Opcode },
8255    { Bad_Opcode },
8256    { Bad_Opcode },
8257    { Bad_Opcode },
8258    /* d0 */
8259    { Bad_Opcode },
8260    { "vphaddubw",	{ XM, EXxmm } },
8261    { "vphaddubd",	{ XM, EXxmm } },
8262    { "vphaddubq",	{ XM, EXxmm } },
8263    { Bad_Opcode },
8264    { Bad_Opcode },
8265    { "vphadduwd",	{ XM, EXxmm } },
8266    { "vphadduwq",	{ XM, EXxmm } },
8267    /* d8 */
8268    { Bad_Opcode },
8269    { Bad_Opcode },
8270    { Bad_Opcode },
8271    { "vphaddudq",	{ XM, EXxmm } },
8272    { Bad_Opcode },
8273    { Bad_Opcode },
8274    { Bad_Opcode },
8275    { Bad_Opcode },
8276    /* e0 */
8277    { Bad_Opcode },
8278    { "vphsubbw",	{ XM, EXxmm } },
8279    { "vphsubwd",	{ XM, EXxmm } },
8280    { "vphsubdq",	{ XM, EXxmm } },
8281    { Bad_Opcode },
8282    { Bad_Opcode },
8283    { Bad_Opcode },
8284    { Bad_Opcode },
8285    /* e8 */
8286    { Bad_Opcode },
8287    { Bad_Opcode },
8288    { Bad_Opcode },
8289    { Bad_Opcode },
8290    { Bad_Opcode },
8291    { Bad_Opcode },
8292    { Bad_Opcode },
8293    { Bad_Opcode },
8294    /* f0 */
8295    { Bad_Opcode },
8296    { Bad_Opcode },
8297    { Bad_Opcode },
8298    { Bad_Opcode },
8299    { Bad_Opcode },
8300    { Bad_Opcode },
8301    { Bad_Opcode },
8302    { Bad_Opcode },
8303    /* f8 */
8304    { Bad_Opcode },
8305    { Bad_Opcode },
8306    { Bad_Opcode },
8307    { Bad_Opcode },
8308    { Bad_Opcode },
8309    { Bad_Opcode },
8310    { Bad_Opcode },
8311    { Bad_Opcode },
8312  },
8313  /* XOP_0A */
8314  {
8315    /* 00 */
8316    { Bad_Opcode },
8317    { Bad_Opcode },
8318    { Bad_Opcode },
8319    { Bad_Opcode },
8320    { Bad_Opcode },
8321    { Bad_Opcode },
8322    { Bad_Opcode },
8323    { Bad_Opcode },
8324    /* 08 */
8325    { Bad_Opcode },
8326    { Bad_Opcode },
8327    { Bad_Opcode },
8328    { Bad_Opcode },
8329    { Bad_Opcode },
8330    { Bad_Opcode },
8331    { Bad_Opcode },
8332    { Bad_Opcode },
8333    /* 10 */
8334    { "bextr",	{ Gv, Ev, Iq } },
8335    { Bad_Opcode },
8336    { REG_TABLE (REG_XOP_LWP) },
8337    { Bad_Opcode },
8338    { Bad_Opcode },
8339    { Bad_Opcode },
8340    { Bad_Opcode },
8341    { Bad_Opcode },
8342    /* 18 */
8343    { Bad_Opcode },
8344    { Bad_Opcode },
8345    { Bad_Opcode },
8346    { Bad_Opcode },
8347    { Bad_Opcode },
8348    { Bad_Opcode },
8349    { Bad_Opcode },
8350    { Bad_Opcode },
8351    /* 20 */
8352    { Bad_Opcode },
8353    { Bad_Opcode },
8354    { Bad_Opcode },
8355    { Bad_Opcode },
8356    { Bad_Opcode },
8357    { Bad_Opcode },
8358    { Bad_Opcode },
8359    { Bad_Opcode },
8360    /* 28 */
8361    { Bad_Opcode },
8362    { Bad_Opcode },
8363    { Bad_Opcode },
8364    { Bad_Opcode },
8365    { Bad_Opcode },
8366    { Bad_Opcode },
8367    { Bad_Opcode },
8368    { Bad_Opcode },
8369    /* 30 */
8370    { Bad_Opcode },
8371    { Bad_Opcode },
8372    { Bad_Opcode },
8373    { Bad_Opcode },
8374    { Bad_Opcode },
8375    { Bad_Opcode },
8376    { Bad_Opcode },
8377    { Bad_Opcode },
8378    /* 38 */
8379    { Bad_Opcode },
8380    { Bad_Opcode },
8381    { Bad_Opcode },
8382    { Bad_Opcode },
8383    { Bad_Opcode },
8384    { Bad_Opcode },
8385    { Bad_Opcode },
8386    { Bad_Opcode },
8387    /* 40 */
8388    { Bad_Opcode },
8389    { Bad_Opcode },
8390    { Bad_Opcode },
8391    { Bad_Opcode },
8392    { Bad_Opcode },
8393    { Bad_Opcode },
8394    { Bad_Opcode },
8395    { Bad_Opcode },
8396    /* 48 */
8397    { Bad_Opcode },
8398    { Bad_Opcode },
8399    { Bad_Opcode },
8400    { Bad_Opcode },
8401    { Bad_Opcode },
8402    { Bad_Opcode },
8403    { Bad_Opcode },
8404    { Bad_Opcode },
8405    /* 50 */
8406    { Bad_Opcode },
8407    { Bad_Opcode },
8408    { Bad_Opcode },
8409    { Bad_Opcode },
8410    { Bad_Opcode },
8411    { Bad_Opcode },
8412    { Bad_Opcode },
8413    { Bad_Opcode },
8414    /* 58 */
8415    { Bad_Opcode },
8416    { Bad_Opcode },
8417    { Bad_Opcode },
8418    { Bad_Opcode },
8419    { Bad_Opcode },
8420    { Bad_Opcode },
8421    { Bad_Opcode },
8422    { Bad_Opcode },
8423    /* 60 */
8424    { Bad_Opcode },
8425    { Bad_Opcode },
8426    { Bad_Opcode },
8427    { Bad_Opcode },
8428    { Bad_Opcode },
8429    { Bad_Opcode },
8430    { Bad_Opcode },
8431    { Bad_Opcode },
8432    /* 68 */
8433    { Bad_Opcode },
8434    { Bad_Opcode },
8435    { Bad_Opcode },
8436    { Bad_Opcode },
8437    { Bad_Opcode },
8438    { Bad_Opcode },
8439    { Bad_Opcode },
8440    { Bad_Opcode },
8441    /* 70 */
8442    { Bad_Opcode },
8443    { Bad_Opcode },
8444    { Bad_Opcode },
8445    { Bad_Opcode },
8446    { Bad_Opcode },
8447    { Bad_Opcode },
8448    { Bad_Opcode },
8449    { Bad_Opcode },
8450    /* 78 */
8451    { Bad_Opcode },
8452    { Bad_Opcode },
8453    { Bad_Opcode },
8454    { Bad_Opcode },
8455    { Bad_Opcode },
8456    { Bad_Opcode },
8457    { Bad_Opcode },
8458    { Bad_Opcode },
8459    /* 80 */
8460    { Bad_Opcode },
8461    { Bad_Opcode },
8462    { Bad_Opcode },
8463    { Bad_Opcode },
8464    { Bad_Opcode },
8465    { Bad_Opcode },
8466    { Bad_Opcode },
8467    { Bad_Opcode },
8468    /* 88 */
8469    { Bad_Opcode },
8470    { Bad_Opcode },
8471    { Bad_Opcode },
8472    { Bad_Opcode },
8473    { Bad_Opcode },
8474    { Bad_Opcode },
8475    { Bad_Opcode },
8476    { Bad_Opcode },
8477    /* 90 */
8478    { Bad_Opcode },
8479    { Bad_Opcode },
8480    { Bad_Opcode },
8481    { Bad_Opcode },
8482    { Bad_Opcode },
8483    { Bad_Opcode },
8484    { Bad_Opcode },
8485    { Bad_Opcode },
8486    /* 98 */
8487    { Bad_Opcode },
8488    { Bad_Opcode },
8489    { Bad_Opcode },
8490    { Bad_Opcode },
8491    { Bad_Opcode },
8492    { Bad_Opcode },
8493    { Bad_Opcode },
8494    { Bad_Opcode },
8495    /* a0 */
8496    { Bad_Opcode },
8497    { Bad_Opcode },
8498    { Bad_Opcode },
8499    { Bad_Opcode },
8500    { Bad_Opcode },
8501    { Bad_Opcode },
8502    { Bad_Opcode },
8503    { Bad_Opcode },
8504    /* a8 */
8505    { Bad_Opcode },
8506    { Bad_Opcode },
8507    { Bad_Opcode },
8508    { Bad_Opcode },
8509    { Bad_Opcode },
8510    { Bad_Opcode },
8511    { Bad_Opcode },
8512    { Bad_Opcode },
8513    /* b0 */
8514    { Bad_Opcode },
8515    { Bad_Opcode },
8516    { Bad_Opcode },
8517    { Bad_Opcode },
8518    { Bad_Opcode },
8519    { Bad_Opcode },
8520    { Bad_Opcode },
8521    { Bad_Opcode },
8522    /* b8 */
8523    { Bad_Opcode },
8524    { Bad_Opcode },
8525    { Bad_Opcode },
8526    { Bad_Opcode },
8527    { Bad_Opcode },
8528    { Bad_Opcode },
8529    { Bad_Opcode },
8530    { Bad_Opcode },
8531    /* c0 */
8532    { Bad_Opcode },
8533    { Bad_Opcode },
8534    { Bad_Opcode },
8535    { Bad_Opcode },
8536    { Bad_Opcode },
8537    { Bad_Opcode },
8538    { Bad_Opcode },
8539    { Bad_Opcode },
8540    /* c8 */
8541    { Bad_Opcode },
8542    { Bad_Opcode },
8543    { Bad_Opcode },
8544    { Bad_Opcode },
8545    { Bad_Opcode },
8546    { Bad_Opcode },
8547    { Bad_Opcode },
8548    { Bad_Opcode },
8549    /* d0 */
8550    { Bad_Opcode },
8551    { Bad_Opcode },
8552    { Bad_Opcode },
8553    { Bad_Opcode },
8554    { Bad_Opcode },
8555    { Bad_Opcode },
8556    { Bad_Opcode },
8557    { Bad_Opcode },
8558    /* d8 */
8559    { Bad_Opcode },
8560    { Bad_Opcode },
8561    { Bad_Opcode },
8562    { Bad_Opcode },
8563    { Bad_Opcode },
8564    { Bad_Opcode },
8565    { Bad_Opcode },
8566    { Bad_Opcode },
8567    /* e0 */
8568    { Bad_Opcode },
8569    { Bad_Opcode },
8570    { Bad_Opcode },
8571    { Bad_Opcode },
8572    { Bad_Opcode },
8573    { Bad_Opcode },
8574    { Bad_Opcode },
8575    { Bad_Opcode },
8576    /* e8 */
8577    { Bad_Opcode },
8578    { Bad_Opcode },
8579    { Bad_Opcode },
8580    { Bad_Opcode },
8581    { Bad_Opcode },
8582    { Bad_Opcode },
8583    { Bad_Opcode },
8584    { Bad_Opcode },
8585    /* f0 */
8586    { Bad_Opcode },
8587    { Bad_Opcode },
8588    { Bad_Opcode },
8589    { Bad_Opcode },
8590    { Bad_Opcode },
8591    { Bad_Opcode },
8592    { Bad_Opcode },
8593    { Bad_Opcode },
8594    /* f8 */
8595    { Bad_Opcode },
8596    { Bad_Opcode },
8597    { Bad_Opcode },
8598    { Bad_Opcode },
8599    { Bad_Opcode },
8600    { Bad_Opcode },
8601    { Bad_Opcode },
8602    { Bad_Opcode },
8603  },
8604};
8605
8606static const struct dis386 vex_table[][256] = {
8607  /* VEX_0F */
8608  {
8609    /* 00 */
8610    { Bad_Opcode },
8611    { Bad_Opcode },
8612    { Bad_Opcode },
8613    { Bad_Opcode },
8614    { Bad_Opcode },
8615    { Bad_Opcode },
8616    { Bad_Opcode },
8617    { Bad_Opcode },
8618    /* 08 */
8619    { Bad_Opcode },
8620    { Bad_Opcode },
8621    { Bad_Opcode },
8622    { Bad_Opcode },
8623    { Bad_Opcode },
8624    { Bad_Opcode },
8625    { Bad_Opcode },
8626    { Bad_Opcode },
8627    /* 10 */
8628    { PREFIX_TABLE (PREFIX_VEX_0F10) },
8629    { PREFIX_TABLE (PREFIX_VEX_0F11) },
8630    { PREFIX_TABLE (PREFIX_VEX_0F12) },
8631    { MOD_TABLE (MOD_VEX_0F13) },
8632    { VEX_W_TABLE (VEX_W_0F14) },
8633    { VEX_W_TABLE (VEX_W_0F15) },
8634    { PREFIX_TABLE (PREFIX_VEX_0F16) },
8635    { MOD_TABLE (MOD_VEX_0F17) },
8636    /* 18 */
8637    { Bad_Opcode },
8638    { Bad_Opcode },
8639    { Bad_Opcode },
8640    { Bad_Opcode },
8641    { Bad_Opcode },
8642    { Bad_Opcode },
8643    { Bad_Opcode },
8644    { Bad_Opcode },
8645    /* 20 */
8646    { Bad_Opcode },
8647    { Bad_Opcode },
8648    { Bad_Opcode },
8649    { Bad_Opcode },
8650    { Bad_Opcode },
8651    { Bad_Opcode },
8652    { Bad_Opcode },
8653    { Bad_Opcode },
8654    /* 28 */
8655    { VEX_W_TABLE (VEX_W_0F28) },
8656    { VEX_W_TABLE (VEX_W_0F29) },
8657    { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8658    { MOD_TABLE (MOD_VEX_0F2B) },
8659    { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8660    { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8661    { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8662    { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8663    /* 30 */
8664    { Bad_Opcode },
8665    { Bad_Opcode },
8666    { Bad_Opcode },
8667    { Bad_Opcode },
8668    { Bad_Opcode },
8669    { Bad_Opcode },
8670    { Bad_Opcode },
8671    { Bad_Opcode },
8672    /* 38 */
8673    { Bad_Opcode },
8674    { Bad_Opcode },
8675    { Bad_Opcode },
8676    { Bad_Opcode },
8677    { Bad_Opcode },
8678    { Bad_Opcode },
8679    { Bad_Opcode },
8680    { Bad_Opcode },
8681    /* 40 */
8682    { Bad_Opcode },
8683    { PREFIX_TABLE (PREFIX_VEX_0F41) },
8684    { PREFIX_TABLE (PREFIX_VEX_0F42) },
8685    { Bad_Opcode },
8686    { PREFIX_TABLE (PREFIX_VEX_0F44) },
8687    { PREFIX_TABLE (PREFIX_VEX_0F45) },
8688    { PREFIX_TABLE (PREFIX_VEX_0F46) },
8689    { PREFIX_TABLE (PREFIX_VEX_0F47) },
8690    /* 48 */
8691    { Bad_Opcode },
8692    { Bad_Opcode },
8693    { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8694    { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8695    { Bad_Opcode },
8696    { Bad_Opcode },
8697    { Bad_Opcode },
8698    { Bad_Opcode },
8699    /* 50 */
8700    { MOD_TABLE (MOD_VEX_0F50) },
8701    { PREFIX_TABLE (PREFIX_VEX_0F51) },
8702    { PREFIX_TABLE (PREFIX_VEX_0F52) },
8703    { PREFIX_TABLE (PREFIX_VEX_0F53) },
8704    { "vandpX",		{ XM, Vex, EXx } },
8705    { "vandnpX",	{ XM, Vex, EXx } },
8706    { "vorpX",		{ XM, Vex, EXx } },
8707    { "vxorpX",		{ XM, Vex, EXx } },
8708    /* 58 */
8709    { PREFIX_TABLE (PREFIX_VEX_0F58) },
8710    { PREFIX_TABLE (PREFIX_VEX_0F59) },
8711    { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8712    { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8713    { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8714    { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8715    { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8716    { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8717    /* 60 */
8718    { PREFIX_TABLE (PREFIX_VEX_0F60) },
8719    { PREFIX_TABLE (PREFIX_VEX_0F61) },
8720    { PREFIX_TABLE (PREFIX_VEX_0F62) },
8721    { PREFIX_TABLE (PREFIX_VEX_0F63) },
8722    { PREFIX_TABLE (PREFIX_VEX_0F64) },
8723    { PREFIX_TABLE (PREFIX_VEX_0F65) },
8724    { PREFIX_TABLE (PREFIX_VEX_0F66) },
8725    { PREFIX_TABLE (PREFIX_VEX_0F67) },
8726    /* 68 */
8727    { PREFIX_TABLE (PREFIX_VEX_0F68) },
8728    { PREFIX_TABLE (PREFIX_VEX_0F69) },
8729    { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8730    { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8731    { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8732    { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8733    { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8734    { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8735    /* 70 */
8736    { PREFIX_TABLE (PREFIX_VEX_0F70) },
8737    { REG_TABLE (REG_VEX_0F71) },
8738    { REG_TABLE (REG_VEX_0F72) },
8739    { REG_TABLE (REG_VEX_0F73) },
8740    { PREFIX_TABLE (PREFIX_VEX_0F74) },
8741    { PREFIX_TABLE (PREFIX_VEX_0F75) },
8742    { PREFIX_TABLE (PREFIX_VEX_0F76) },
8743    { PREFIX_TABLE (PREFIX_VEX_0F77) },
8744    /* 78 */
8745    { Bad_Opcode },
8746    { Bad_Opcode },
8747    { Bad_Opcode },
8748    { Bad_Opcode },
8749    { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8750    { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8751    { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8752    { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8753    /* 80 */
8754    { Bad_Opcode },
8755    { Bad_Opcode },
8756    { Bad_Opcode },
8757    { Bad_Opcode },
8758    { Bad_Opcode },
8759    { Bad_Opcode },
8760    { Bad_Opcode },
8761    { Bad_Opcode },
8762    /* 88 */
8763    { Bad_Opcode },
8764    { Bad_Opcode },
8765    { Bad_Opcode },
8766    { Bad_Opcode },
8767    { Bad_Opcode },
8768    { Bad_Opcode },
8769    { Bad_Opcode },
8770    { Bad_Opcode },
8771    /* 90 */
8772    { PREFIX_TABLE (PREFIX_VEX_0F90) },
8773    { PREFIX_TABLE (PREFIX_VEX_0F91) },
8774    { PREFIX_TABLE (PREFIX_VEX_0F92) },
8775    { PREFIX_TABLE (PREFIX_VEX_0F93) },
8776    { Bad_Opcode },
8777    { Bad_Opcode },
8778    { Bad_Opcode },
8779    { Bad_Opcode },
8780    /* 98 */
8781    { PREFIX_TABLE (PREFIX_VEX_0F98) },
8782    { PREFIX_TABLE (PREFIX_VEX_0F99) },
8783    { Bad_Opcode },
8784    { Bad_Opcode },
8785    { Bad_Opcode },
8786    { Bad_Opcode },
8787    { Bad_Opcode },
8788    { Bad_Opcode },
8789    /* a0 */
8790    { Bad_Opcode },
8791    { Bad_Opcode },
8792    { Bad_Opcode },
8793    { Bad_Opcode },
8794    { Bad_Opcode },
8795    { Bad_Opcode },
8796    { Bad_Opcode },
8797    { Bad_Opcode },
8798    /* a8 */
8799    { Bad_Opcode },
8800    { Bad_Opcode },
8801    { Bad_Opcode },
8802    { Bad_Opcode },
8803    { Bad_Opcode },
8804    { Bad_Opcode },
8805    { REG_TABLE (REG_VEX_0FAE) },
8806    { Bad_Opcode },
8807    /* b0 */
8808    { Bad_Opcode },
8809    { Bad_Opcode },
8810    { Bad_Opcode },
8811    { Bad_Opcode },
8812    { Bad_Opcode },
8813    { Bad_Opcode },
8814    { Bad_Opcode },
8815    { Bad_Opcode },
8816    /* b8 */
8817    { Bad_Opcode },
8818    { Bad_Opcode },
8819    { Bad_Opcode },
8820    { Bad_Opcode },
8821    { Bad_Opcode },
8822    { Bad_Opcode },
8823    { Bad_Opcode },
8824    { Bad_Opcode },
8825    /* c0 */
8826    { Bad_Opcode },
8827    { Bad_Opcode },
8828    { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8829    { Bad_Opcode },
8830    { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8831    { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8832    { "vshufpX",	{ XM, Vex, EXx, Ib } },
8833    { Bad_Opcode },
8834    /* c8 */
8835    { Bad_Opcode },
8836    { Bad_Opcode },
8837    { Bad_Opcode },
8838    { Bad_Opcode },
8839    { Bad_Opcode },
8840    { Bad_Opcode },
8841    { Bad_Opcode },
8842    { Bad_Opcode },
8843    /* d0 */
8844    { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8845    { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8846    { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8847    { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8848    { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8849    { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8850    { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8851    { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8852    /* d8 */
8853    { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8854    { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8855    { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8856    { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8857    { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8858    { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8859    { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8860    { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8861    /* e0 */
8862    { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8863    { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8864    { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8865    { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8866    { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8867    { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8868    { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8869    { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8870    /* e8 */
8871    { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8872    { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8873    { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8874    { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8875    { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8876    { PREFIX_TABLE (PREFIX_VEX_0FED) },
8877    { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8878    { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8879    /* f0 */
8880    { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8881    { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8882    { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8883    { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8884    { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8885    { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8886    { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8887    { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8888    /* f8 */
8889    { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8890    { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8891    { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8892    { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8893    { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8894    { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8895    { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8896    { Bad_Opcode },
8897  },
8898  /* VEX_0F38 */
8899  {
8900    /* 00 */
8901    { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8902    { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8903    { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8904    { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8905    { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8906    { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8907    { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8908    { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8909    /* 08 */
8910    { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8911    { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8912    { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8913    { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8914    { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8915    { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8916    { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8917    { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8918    /* 10 */
8919    { Bad_Opcode },
8920    { Bad_Opcode },
8921    { Bad_Opcode },
8922    { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8923    { Bad_Opcode },
8924    { Bad_Opcode },
8925    { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8926    { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8927    /* 18 */
8928    { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8929    { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8930    { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8931    { Bad_Opcode },
8932    { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8933    { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8934    { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8935    { Bad_Opcode },
8936    /* 20 */
8937    { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8938    { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8939    { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8940    { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8941    { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8942    { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8943    { Bad_Opcode },
8944    { Bad_Opcode },
8945    /* 28 */
8946    { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8947    { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8948    { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8949    { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8950    { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8951    { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8952    { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8953    { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8954    /* 30 */
8955    { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8956    { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8957    { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8958    { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8959    { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8960    { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8961    { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8962    { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8963    /* 38 */
8964    { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8965    { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8966    { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8967    { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8968    { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8969    { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8970    { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8971    { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8972    /* 40 */
8973    { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8974    { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8975    { Bad_Opcode },
8976    { Bad_Opcode },
8977    { Bad_Opcode },
8978    { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8979    { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8980    { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8981    /* 48 */
8982    { Bad_Opcode },
8983    { Bad_Opcode },
8984    { Bad_Opcode },
8985    { Bad_Opcode },
8986    { Bad_Opcode },
8987    { Bad_Opcode },
8988    { Bad_Opcode },
8989    { Bad_Opcode },
8990    /* 50 */
8991    { Bad_Opcode },
8992    { Bad_Opcode },
8993    { Bad_Opcode },
8994    { Bad_Opcode },
8995    { Bad_Opcode },
8996    { Bad_Opcode },
8997    { Bad_Opcode },
8998    { Bad_Opcode },
8999    /* 58 */
9000    { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9001    { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9002    { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9003    { Bad_Opcode },
9004    { Bad_Opcode },
9005    { Bad_Opcode },
9006    { Bad_Opcode },
9007    { Bad_Opcode },
9008    /* 60 */
9009    { Bad_Opcode },
9010    { Bad_Opcode },
9011    { Bad_Opcode },
9012    { Bad_Opcode },
9013    { Bad_Opcode },
9014    { Bad_Opcode },
9015    { Bad_Opcode },
9016    { Bad_Opcode },
9017    /* 68 */
9018    { Bad_Opcode },
9019    { Bad_Opcode },
9020    { Bad_Opcode },
9021    { Bad_Opcode },
9022    { Bad_Opcode },
9023    { Bad_Opcode },
9024    { Bad_Opcode },
9025    { Bad_Opcode },
9026    /* 70 */
9027    { Bad_Opcode },
9028    { Bad_Opcode },
9029    { Bad_Opcode },
9030    { Bad_Opcode },
9031    { Bad_Opcode },
9032    { Bad_Opcode },
9033    { Bad_Opcode },
9034    { Bad_Opcode },
9035    /* 78 */
9036    { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9037    { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9038    { Bad_Opcode },
9039    { Bad_Opcode },
9040    { Bad_Opcode },
9041    { Bad_Opcode },
9042    { Bad_Opcode },
9043    { Bad_Opcode },
9044    /* 80 */
9045    { Bad_Opcode },
9046    { Bad_Opcode },
9047    { Bad_Opcode },
9048    { Bad_Opcode },
9049    { Bad_Opcode },
9050    { Bad_Opcode },
9051    { Bad_Opcode },
9052    { Bad_Opcode },
9053    /* 88 */
9054    { Bad_Opcode },
9055    { Bad_Opcode },
9056    { Bad_Opcode },
9057    { Bad_Opcode },
9058    { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9059    { Bad_Opcode },
9060    { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9061    { Bad_Opcode },
9062    /* 90 */
9063    { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9064    { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9065    { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9066    { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9067    { Bad_Opcode },
9068    { Bad_Opcode },
9069    { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9070    { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9071    /* 98 */
9072    { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9073    { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9074    { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9075    { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9076    { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9077    { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9078    { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9079    { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9080    /* a0 */
9081    { Bad_Opcode },
9082    { Bad_Opcode },
9083    { Bad_Opcode },
9084    { Bad_Opcode },
9085    { Bad_Opcode },
9086    { Bad_Opcode },
9087    { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9088    { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9089    /* a8 */
9090    { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9091    { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9092    { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9093    { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9094    { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9095    { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9096    { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9097    { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9098    /* b0 */
9099    { Bad_Opcode },
9100    { Bad_Opcode },
9101    { Bad_Opcode },
9102    { Bad_Opcode },
9103    { Bad_Opcode },
9104    { Bad_Opcode },
9105    { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9106    { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9107    /* b8 */
9108    { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9109    { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9110    { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9111    { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9112    { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9113    { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9114    { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9115    { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9116    /* c0 */
9117    { Bad_Opcode },
9118    { Bad_Opcode },
9119    { Bad_Opcode },
9120    { Bad_Opcode },
9121    { Bad_Opcode },
9122    { Bad_Opcode },
9123    { Bad_Opcode },
9124    { Bad_Opcode },
9125    /* c8 */
9126    { Bad_Opcode },
9127    { Bad_Opcode },
9128    { Bad_Opcode },
9129    { Bad_Opcode },
9130    { Bad_Opcode },
9131    { Bad_Opcode },
9132    { Bad_Opcode },
9133    { Bad_Opcode },
9134    /* d0 */
9135    { Bad_Opcode },
9136    { Bad_Opcode },
9137    { Bad_Opcode },
9138    { Bad_Opcode },
9139    { Bad_Opcode },
9140    { Bad_Opcode },
9141    { Bad_Opcode },
9142    { Bad_Opcode },
9143    /* d8 */
9144    { Bad_Opcode },
9145    { Bad_Opcode },
9146    { Bad_Opcode },
9147    { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9148    { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9149    { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9150    { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9151    { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9152    /* e0 */
9153    { Bad_Opcode },
9154    { Bad_Opcode },
9155    { Bad_Opcode },
9156    { Bad_Opcode },
9157    { Bad_Opcode },
9158    { Bad_Opcode },
9159    { Bad_Opcode },
9160    { Bad_Opcode },
9161    /* e8 */
9162    { Bad_Opcode },
9163    { Bad_Opcode },
9164    { Bad_Opcode },
9165    { Bad_Opcode },
9166    { Bad_Opcode },
9167    { Bad_Opcode },
9168    { Bad_Opcode },
9169    { Bad_Opcode },
9170    /* f0 */
9171    { Bad_Opcode },
9172    { Bad_Opcode },
9173    { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9174    { REG_TABLE (REG_VEX_0F38F3) },
9175    { Bad_Opcode },
9176    { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9177    { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9178    { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9179    /* f8 */
9180    { Bad_Opcode },
9181    { Bad_Opcode },
9182    { Bad_Opcode },
9183    { Bad_Opcode },
9184    { Bad_Opcode },
9185    { Bad_Opcode },
9186    { Bad_Opcode },
9187    { Bad_Opcode },
9188  },
9189  /* VEX_0F3A */
9190  {
9191    /* 00 */
9192    { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9193    { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9194    { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9195    { Bad_Opcode },
9196    { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9197    { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9198    { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9199    { Bad_Opcode },
9200    /* 08 */
9201    { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9202    { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9203    { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9204    { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9205    { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9206    { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9207    { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9208    { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9209    /* 10 */
9210    { Bad_Opcode },
9211    { Bad_Opcode },
9212    { Bad_Opcode },
9213    { Bad_Opcode },
9214    { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9215    { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9216    { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9217    { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9218    /* 18 */
9219    { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9220    { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9221    { Bad_Opcode },
9222    { Bad_Opcode },
9223    { Bad_Opcode },
9224    { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9225    { Bad_Opcode },
9226    { Bad_Opcode },
9227    /* 20 */
9228    { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9229    { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9230    { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9231    { Bad_Opcode },
9232    { Bad_Opcode },
9233    { Bad_Opcode },
9234    { Bad_Opcode },
9235    { Bad_Opcode },
9236    /* 28 */
9237    { Bad_Opcode },
9238    { Bad_Opcode },
9239    { Bad_Opcode },
9240    { Bad_Opcode },
9241    { Bad_Opcode },
9242    { Bad_Opcode },
9243    { Bad_Opcode },
9244    { Bad_Opcode },
9245    /* 30 */
9246    { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9247    { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9248    { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9249    { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9250    { Bad_Opcode },
9251    { Bad_Opcode },
9252    { Bad_Opcode },
9253    { Bad_Opcode },
9254    /* 38 */
9255    { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9256    { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9257    { Bad_Opcode },
9258    { Bad_Opcode },
9259    { Bad_Opcode },
9260    { Bad_Opcode },
9261    { Bad_Opcode },
9262    { Bad_Opcode },
9263    /* 40 */
9264    { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9265    { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9266    { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9267    { Bad_Opcode },
9268    { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9269    { Bad_Opcode },
9270    { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9271    { Bad_Opcode },
9272    /* 48 */
9273    { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9274    { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9275    { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9276    { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9277    { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9278    { Bad_Opcode },
9279    { Bad_Opcode },
9280    { Bad_Opcode },
9281    /* 50 */
9282    { Bad_Opcode },
9283    { Bad_Opcode },
9284    { Bad_Opcode },
9285    { Bad_Opcode },
9286    { Bad_Opcode },
9287    { Bad_Opcode },
9288    { Bad_Opcode },
9289    { Bad_Opcode },
9290    /* 58 */
9291    { Bad_Opcode },
9292    { Bad_Opcode },
9293    { Bad_Opcode },
9294    { Bad_Opcode },
9295    { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9296    { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9297    { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9298    { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9299    /* 60 */
9300    { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9301    { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9302    { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9303    { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9304    { Bad_Opcode },
9305    { Bad_Opcode },
9306    { Bad_Opcode },
9307    { Bad_Opcode },
9308    /* 68 */
9309    { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9310    { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9311    { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9312    { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9313    { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9314    { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9315    { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9316    { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9317    /* 70 */
9318    { Bad_Opcode },
9319    { Bad_Opcode },
9320    { Bad_Opcode },
9321    { Bad_Opcode },
9322    { Bad_Opcode },
9323    { Bad_Opcode },
9324    { Bad_Opcode },
9325    { Bad_Opcode },
9326    /* 78 */
9327    { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9328    { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9329    { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9330    { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9331    { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9332    { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9333    { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9334    { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9335    /* 80 */
9336    { Bad_Opcode },
9337    { Bad_Opcode },
9338    { Bad_Opcode },
9339    { Bad_Opcode },
9340    { Bad_Opcode },
9341    { Bad_Opcode },
9342    { Bad_Opcode },
9343    { Bad_Opcode },
9344    /* 88 */
9345    { Bad_Opcode },
9346    { Bad_Opcode },
9347    { Bad_Opcode },
9348    { Bad_Opcode },
9349    { Bad_Opcode },
9350    { Bad_Opcode },
9351    { Bad_Opcode },
9352    { Bad_Opcode },
9353    /* 90 */
9354    { Bad_Opcode },
9355    { Bad_Opcode },
9356    { Bad_Opcode },
9357    { Bad_Opcode },
9358    { Bad_Opcode },
9359    { Bad_Opcode },
9360    { Bad_Opcode },
9361    { Bad_Opcode },
9362    /* 98 */
9363    { Bad_Opcode },
9364    { Bad_Opcode },
9365    { Bad_Opcode },
9366    { Bad_Opcode },
9367    { Bad_Opcode },
9368    { Bad_Opcode },
9369    { Bad_Opcode },
9370    { Bad_Opcode },
9371    /* a0 */
9372    { Bad_Opcode },
9373    { Bad_Opcode },
9374    { Bad_Opcode },
9375    { Bad_Opcode },
9376    { Bad_Opcode },
9377    { Bad_Opcode },
9378    { Bad_Opcode },
9379    { Bad_Opcode },
9380    /* a8 */
9381    { Bad_Opcode },
9382    { Bad_Opcode },
9383    { Bad_Opcode },
9384    { Bad_Opcode },
9385    { Bad_Opcode },
9386    { Bad_Opcode },
9387    { Bad_Opcode },
9388    { Bad_Opcode },
9389    /* b0 */
9390    { Bad_Opcode },
9391    { Bad_Opcode },
9392    { Bad_Opcode },
9393    { Bad_Opcode },
9394    { Bad_Opcode },
9395    { Bad_Opcode },
9396    { Bad_Opcode },
9397    { Bad_Opcode },
9398    /* b8 */
9399    { Bad_Opcode },
9400    { Bad_Opcode },
9401    { Bad_Opcode },
9402    { Bad_Opcode },
9403    { Bad_Opcode },
9404    { Bad_Opcode },
9405    { Bad_Opcode },
9406    { Bad_Opcode },
9407    /* c0 */
9408    { Bad_Opcode },
9409    { Bad_Opcode },
9410    { Bad_Opcode },
9411    { Bad_Opcode },
9412    { Bad_Opcode },
9413    { Bad_Opcode },
9414    { Bad_Opcode },
9415    { Bad_Opcode },
9416    /* c8 */
9417    { Bad_Opcode },
9418    { Bad_Opcode },
9419    { Bad_Opcode },
9420    { Bad_Opcode },
9421    { Bad_Opcode },
9422    { Bad_Opcode },
9423    { Bad_Opcode },
9424    { Bad_Opcode },
9425    /* d0 */
9426    { Bad_Opcode },
9427    { Bad_Opcode },
9428    { Bad_Opcode },
9429    { Bad_Opcode },
9430    { Bad_Opcode },
9431    { Bad_Opcode },
9432    { Bad_Opcode },
9433    { Bad_Opcode },
9434    /* d8 */
9435    { Bad_Opcode },
9436    { Bad_Opcode },
9437    { Bad_Opcode },
9438    { Bad_Opcode },
9439    { Bad_Opcode },
9440    { Bad_Opcode },
9441    { Bad_Opcode },
9442    { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9443    /* e0 */
9444    { Bad_Opcode },
9445    { Bad_Opcode },
9446    { Bad_Opcode },
9447    { Bad_Opcode },
9448    { Bad_Opcode },
9449    { Bad_Opcode },
9450    { Bad_Opcode },
9451    { Bad_Opcode },
9452    /* e8 */
9453    { Bad_Opcode },
9454    { Bad_Opcode },
9455    { Bad_Opcode },
9456    { Bad_Opcode },
9457    { Bad_Opcode },
9458    { Bad_Opcode },
9459    { Bad_Opcode },
9460    { Bad_Opcode },
9461    /* f0 */
9462    { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9463    { Bad_Opcode },
9464    { Bad_Opcode },
9465    { Bad_Opcode },
9466    { Bad_Opcode },
9467    { Bad_Opcode },
9468    { Bad_Opcode },
9469    { Bad_Opcode },
9470    /* f8 */
9471    { Bad_Opcode },
9472    { Bad_Opcode },
9473    { Bad_Opcode },
9474    { Bad_Opcode },
9475    { Bad_Opcode },
9476    { Bad_Opcode },
9477    { Bad_Opcode },
9478    { Bad_Opcode },
9479  },
9480};
9481
9482#define NEED_OPCODE_TABLE
9483#include "i386-dis-evex.h"
9484#undef NEED_OPCODE_TABLE
9485static const struct dis386 vex_len_table[][2] = {
9486  /* VEX_LEN_0F10_P_1 */
9487  {
9488    { VEX_W_TABLE (VEX_W_0F10_P_1) },
9489    { VEX_W_TABLE (VEX_W_0F10_P_1) },
9490  },
9491
9492  /* VEX_LEN_0F10_P_3 */
9493  {
9494    { VEX_W_TABLE (VEX_W_0F10_P_3) },
9495    { VEX_W_TABLE (VEX_W_0F10_P_3) },
9496  },
9497
9498  /* VEX_LEN_0F11_P_1 */
9499  {
9500    { VEX_W_TABLE (VEX_W_0F11_P_1) },
9501    { VEX_W_TABLE (VEX_W_0F11_P_1) },
9502  },
9503
9504  /* VEX_LEN_0F11_P_3 */
9505  {
9506    { VEX_W_TABLE (VEX_W_0F11_P_3) },
9507    { VEX_W_TABLE (VEX_W_0F11_P_3) },
9508  },
9509
9510  /* VEX_LEN_0F12_P_0_M_0 */
9511  {
9512    { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9513  },
9514
9515  /* VEX_LEN_0F12_P_0_M_1 */
9516  {
9517    { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9518  },
9519
9520  /* VEX_LEN_0F12_P_2 */
9521  {
9522    { VEX_W_TABLE (VEX_W_0F12_P_2) },
9523  },
9524
9525  /* VEX_LEN_0F13_M_0 */
9526  {
9527    { VEX_W_TABLE (VEX_W_0F13_M_0) },
9528  },
9529
9530  /* VEX_LEN_0F16_P_0_M_0 */
9531  {
9532    { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9533  },
9534
9535  /* VEX_LEN_0F16_P_0_M_1 */
9536  {
9537    { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9538  },
9539
9540  /* VEX_LEN_0F16_P_2 */
9541  {
9542    { VEX_W_TABLE (VEX_W_0F16_P_2) },
9543  },
9544
9545  /* VEX_LEN_0F17_M_0 */
9546  {
9547    { VEX_W_TABLE (VEX_W_0F17_M_0) },
9548  },
9549
9550  /* VEX_LEN_0F2A_P_1 */
9551  {
9552    { "vcvtsi2ss%LQ",	{ XMScalar, VexScalar, Ev } },
9553    { "vcvtsi2ss%LQ",	{ XMScalar, VexScalar, Ev } },
9554  },
9555
9556  /* VEX_LEN_0F2A_P_3 */
9557  {
9558    { "vcvtsi2sd%LQ",	{ XMScalar, VexScalar, Ev } },
9559    { "vcvtsi2sd%LQ",	{ XMScalar, VexScalar, Ev } },
9560  },
9561
9562  /* VEX_LEN_0F2C_P_1 */
9563  {
9564    { "vcvttss2siY",	{ Gv, EXdScalar } },
9565    { "vcvttss2siY",	{ Gv, EXdScalar } },
9566  },
9567
9568  /* VEX_LEN_0F2C_P_3 */
9569  {
9570    { "vcvttsd2siY",	{ Gv, EXqScalar } },
9571    { "vcvttsd2siY",	{ Gv, EXqScalar } },
9572  },
9573
9574  /* VEX_LEN_0F2D_P_1 */
9575  {
9576    { "vcvtss2siY",	{ Gv, EXdScalar } },
9577    { "vcvtss2siY",	{ Gv, EXdScalar } },
9578  },
9579
9580  /* VEX_LEN_0F2D_P_3 */
9581  {
9582    { "vcvtsd2siY",	{ Gv, EXqScalar } },
9583    { "vcvtsd2siY",	{ Gv, EXqScalar } },
9584  },
9585
9586  /* VEX_LEN_0F2E_P_0 */
9587  {
9588    { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9589    { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9590  },
9591
9592  /* VEX_LEN_0F2E_P_2 */
9593  {
9594    { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9595    { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9596  },
9597
9598  /* VEX_LEN_0F2F_P_0 */
9599  {
9600    { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9601    { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9602  },
9603
9604  /* VEX_LEN_0F2F_P_2 */
9605  {
9606    { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9607    { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9608  },
9609
9610  /* VEX_LEN_0F41_P_0 */
9611  {
9612    { Bad_Opcode },
9613    { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9614  },
9615  /* VEX_LEN_0F41_P_2 */
9616  {
9617    { Bad_Opcode },
9618    { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9619  },
9620  /* VEX_LEN_0F42_P_0 */
9621  {
9622    { Bad_Opcode },
9623    { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9624  },
9625  /* VEX_LEN_0F42_P_2 */
9626  {
9627    { Bad_Opcode },
9628    { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9629  },
9630  /* VEX_LEN_0F44_P_0 */
9631  {
9632    { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9633  },
9634  /* VEX_LEN_0F44_P_2 */
9635  {
9636    { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9637  },
9638  /* VEX_LEN_0F45_P_0 */
9639  {
9640    { Bad_Opcode },
9641    { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9642  },
9643  /* VEX_LEN_0F45_P_2 */
9644  {
9645    { Bad_Opcode },
9646    { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9647  },
9648  /* VEX_LEN_0F46_P_0 */
9649  {
9650    { Bad_Opcode },
9651    { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9652  },
9653  /* VEX_LEN_0F46_P_2 */
9654  {
9655    { Bad_Opcode },
9656    { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9657  },
9658  /* VEX_LEN_0F47_P_0 */
9659  {
9660    { Bad_Opcode },
9661    { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9662  },
9663  /* VEX_LEN_0F47_P_2 */
9664  {
9665    { Bad_Opcode },
9666    { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9667  },
9668  /* VEX_LEN_0F4A_P_0 */
9669  {
9670    { Bad_Opcode },
9671    { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9672  },
9673  /* VEX_LEN_0F4A_P_2 */
9674  {
9675    { Bad_Opcode },
9676    { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9677  },
9678  /* VEX_LEN_0F4B_P_0 */
9679  {
9680    { Bad_Opcode },
9681    { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9682  },
9683  /* VEX_LEN_0F4B_P_2 */
9684  {
9685    { Bad_Opcode },
9686    { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9687  },
9688
9689  /* VEX_LEN_0F51_P_1 */
9690  {
9691    { VEX_W_TABLE (VEX_W_0F51_P_1) },
9692    { VEX_W_TABLE (VEX_W_0F51_P_1) },
9693  },
9694
9695  /* VEX_LEN_0F51_P_3 */
9696  {
9697    { VEX_W_TABLE (VEX_W_0F51_P_3) },
9698    { VEX_W_TABLE (VEX_W_0F51_P_3) },
9699  },
9700
9701  /* VEX_LEN_0F52_P_1 */
9702  {
9703    { VEX_W_TABLE (VEX_W_0F52_P_1) },
9704    { VEX_W_TABLE (VEX_W_0F52_P_1) },
9705  },
9706
9707  /* VEX_LEN_0F53_P_1 */
9708  {
9709    { VEX_W_TABLE (VEX_W_0F53_P_1) },
9710    { VEX_W_TABLE (VEX_W_0F53_P_1) },
9711  },
9712
9713  /* VEX_LEN_0F58_P_1 */
9714  {
9715    { VEX_W_TABLE (VEX_W_0F58_P_1) },
9716    { VEX_W_TABLE (VEX_W_0F58_P_1) },
9717  },
9718
9719  /* VEX_LEN_0F58_P_3 */
9720  {
9721    { VEX_W_TABLE (VEX_W_0F58_P_3) },
9722    { VEX_W_TABLE (VEX_W_0F58_P_3) },
9723  },
9724
9725  /* VEX_LEN_0F59_P_1 */
9726  {
9727    { VEX_W_TABLE (VEX_W_0F59_P_1) },
9728    { VEX_W_TABLE (VEX_W_0F59_P_1) },
9729  },
9730
9731  /* VEX_LEN_0F59_P_3 */
9732  {
9733    { VEX_W_TABLE (VEX_W_0F59_P_3) },
9734    { VEX_W_TABLE (VEX_W_0F59_P_3) },
9735  },
9736
9737  /* VEX_LEN_0F5A_P_1 */
9738  {
9739    { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9740    { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9741  },
9742
9743  /* VEX_LEN_0F5A_P_3 */
9744  {
9745    { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9746    { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9747  },
9748
9749  /* VEX_LEN_0F5C_P_1 */
9750  {
9751    { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9752    { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9753  },
9754
9755  /* VEX_LEN_0F5C_P_3 */
9756  {
9757    { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9758    { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9759  },
9760
9761  /* VEX_LEN_0F5D_P_1 */
9762  {
9763    { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9764    { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9765  },
9766
9767  /* VEX_LEN_0F5D_P_3 */
9768  {
9769    { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9770    { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9771  },
9772
9773  /* VEX_LEN_0F5E_P_1 */
9774  {
9775    { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9776    { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9777  },
9778
9779  /* VEX_LEN_0F5E_P_3 */
9780  {
9781    { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9782    { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9783  },
9784
9785  /* VEX_LEN_0F5F_P_1 */
9786  {
9787    { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9788    { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9789  },
9790
9791  /* VEX_LEN_0F5F_P_3 */
9792  {
9793    { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9794    { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9795  },
9796
9797  /* VEX_LEN_0F6E_P_2 */
9798  {
9799    { "vmovK",		{ XMScalar, Edq } },
9800    { "vmovK",		{ XMScalar, Edq } },
9801  },
9802
9803  /* VEX_LEN_0F7E_P_1 */
9804  {
9805    { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9806    { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9807  },
9808
9809  /* VEX_LEN_0F7E_P_2 */
9810  {
9811    { "vmovK",		{ Edq, XMScalar } },
9812    { "vmovK",		{ Edq, XMScalar } },
9813  },
9814
9815  /* VEX_LEN_0F90_P_0 */
9816  {
9817    { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9818  },
9819
9820  /* VEX_LEN_0F90_P_2 */
9821  {
9822    { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9823  },
9824
9825  /* VEX_LEN_0F91_P_0 */
9826  {
9827    { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9828  },
9829
9830  /* VEX_LEN_0F91_P_2 */
9831  {
9832    { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9833  },
9834
9835  /* VEX_LEN_0F92_P_0 */
9836  {
9837    { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9838  },
9839
9840  /* VEX_LEN_0F92_P_2 */
9841  {
9842    { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9843  },
9844
9845  /* VEX_LEN_0F92_P_3 */
9846  {
9847    { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9848  },
9849
9850  /* VEX_LEN_0F93_P_0 */
9851  {
9852    { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9853  },
9854
9855  /* VEX_LEN_0F93_P_2 */
9856  {
9857    { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9858  },
9859
9860  /* VEX_LEN_0F93_P_3 */
9861  {
9862    { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9863  },
9864
9865  /* VEX_LEN_0F98_P_0 */
9866  {
9867    { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9868  },
9869
9870  /* VEX_LEN_0F98_P_2 */
9871  {
9872    { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9873  },
9874
9875  /* VEX_LEN_0F99_P_0 */
9876  {
9877    { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9878  },
9879
9880  /* VEX_LEN_0F99_P_2 */
9881  {
9882    { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9883  },
9884
9885  /* VEX_LEN_0FAE_R_2_M_0 */
9886  {
9887    { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9888  },
9889
9890  /* VEX_LEN_0FAE_R_3_M_0 */
9891  {
9892    { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9893  },
9894
9895  /* VEX_LEN_0FC2_P_1 */
9896  {
9897    { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9898    { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9899  },
9900
9901  /* VEX_LEN_0FC2_P_3 */
9902  {
9903    { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9904    { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9905  },
9906
9907  /* VEX_LEN_0FC4_P_2 */
9908  {
9909    { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9910  },
9911
9912  /* VEX_LEN_0FC5_P_2 */
9913  {
9914    { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9915  },
9916
9917  /* VEX_LEN_0FD6_P_2 */
9918  {
9919    { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9920    { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9921  },
9922
9923  /* VEX_LEN_0FF7_P_2 */
9924  {
9925    { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9926  },
9927
9928  /* VEX_LEN_0F3816_P_2 */
9929  {
9930    { Bad_Opcode },
9931    { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9932  },
9933
9934  /* VEX_LEN_0F3819_P_2 */
9935  {
9936    { Bad_Opcode },
9937    { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9938  },
9939
9940  /* VEX_LEN_0F381A_P_2_M_0 */
9941  {
9942    { Bad_Opcode },
9943    { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9944  },
9945
9946  /* VEX_LEN_0F3836_P_2 */
9947  {
9948    { Bad_Opcode },
9949    { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9950  },
9951
9952  /* VEX_LEN_0F3841_P_2 */
9953  {
9954    { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9955  },
9956
9957  /* VEX_LEN_0F385A_P_2_M_0 */
9958  {
9959    { Bad_Opcode },
9960    { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9961  },
9962
9963  /* VEX_LEN_0F38DB_P_2 */
9964  {
9965    { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9966  },
9967
9968  /* VEX_LEN_0F38DC_P_2 */
9969  {
9970    { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
9971  },
9972
9973  /* VEX_LEN_0F38DD_P_2 */
9974  {
9975    { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
9976  },
9977
9978  /* VEX_LEN_0F38DE_P_2 */
9979  {
9980    { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
9981  },
9982
9983  /* VEX_LEN_0F38DF_P_2 */
9984  {
9985    { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
9986  },
9987
9988  /* VEX_LEN_0F38F2_P_0 */
9989  {
9990    { "andnS",		{ Gdq, VexGdq, Edq } },
9991  },
9992
9993  /* VEX_LEN_0F38F3_R_1_P_0 */
9994  {
9995    { "blsrS",		{ VexGdq, Edq } },
9996  },
9997
9998  /* VEX_LEN_0F38F3_R_2_P_0 */
9999  {
10000    { "blsmskS",	{ VexGdq, Edq } },
10001  },
10002
10003  /* VEX_LEN_0F38F3_R_3_P_0 */
10004  {
10005    { "blsiS",		{ VexGdq, Edq } },
10006  },
10007
10008  /* VEX_LEN_0F38F5_P_0 */
10009  {
10010    { "bzhiS",		{ Gdq, Edq, VexGdq } },
10011  },
10012
10013  /* VEX_LEN_0F38F5_P_1 */
10014  {
10015    { "pextS",		{ Gdq, VexGdq, Edq } },
10016  },
10017
10018  /* VEX_LEN_0F38F5_P_3 */
10019  {
10020    { "pdepS",		{ Gdq, VexGdq, Edq } },
10021  },
10022
10023  /* VEX_LEN_0F38F6_P_3 */
10024  {
10025    { "mulxS",		{ Gdq, VexGdq, Edq } },
10026  },
10027
10028  /* VEX_LEN_0F38F7_P_0 */
10029  {
10030    { "bextrS",		{ Gdq, Edq, VexGdq } },
10031  },
10032
10033  /* VEX_LEN_0F38F7_P_1 */
10034  {
10035    { "sarxS",		{ Gdq, Edq, VexGdq } },
10036  },
10037
10038  /* VEX_LEN_0F38F7_P_2 */
10039  {
10040    { "shlxS",		{ Gdq, Edq, VexGdq } },
10041  },
10042
10043  /* VEX_LEN_0F38F7_P_3 */
10044  {
10045    { "shrxS",		{ Gdq, Edq, VexGdq } },
10046  },
10047
10048  /* VEX_LEN_0F3A00_P_2 */
10049  {
10050    { Bad_Opcode },
10051    { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10052  },
10053
10054  /* VEX_LEN_0F3A01_P_2 */
10055  {
10056    { Bad_Opcode },
10057    { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10058  },
10059
10060  /* VEX_LEN_0F3A06_P_2 */
10061  {
10062    { Bad_Opcode },
10063    { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10064  },
10065
10066  /* VEX_LEN_0F3A0A_P_2 */
10067  {
10068    { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10069    { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10070  },
10071
10072  /* VEX_LEN_0F3A0B_P_2 */
10073  {
10074    { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10075    { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10076  },
10077
10078  /* VEX_LEN_0F3A14_P_2 */
10079  {
10080    { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10081  },
10082
10083  /* VEX_LEN_0F3A15_P_2 */
10084  {
10085    { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10086  },
10087
10088  /* VEX_LEN_0F3A16_P_2  */
10089  {
10090    { "vpextrK",	{ Edq, XM, Ib } },
10091  },
10092
10093  /* VEX_LEN_0F3A17_P_2 */
10094  {
10095    { "vextractps",	{ Edqd, XM, Ib } },
10096  },
10097
10098  /* VEX_LEN_0F3A18_P_2 */
10099  {
10100    { Bad_Opcode },
10101    { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10102  },
10103
10104  /* VEX_LEN_0F3A19_P_2 */
10105  {
10106    { Bad_Opcode },
10107    { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10108  },
10109
10110  /* VEX_LEN_0F3A20_P_2 */
10111  {
10112    { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10113  },
10114
10115  /* VEX_LEN_0F3A21_P_2 */
10116  {
10117    { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10118  },
10119
10120  /* VEX_LEN_0F3A22_P_2 */
10121  {
10122    { "vpinsrK",	{ XM, Vex128, Edq, Ib } },
10123  },
10124
10125  /* VEX_LEN_0F3A30_P_2 */
10126  {
10127    { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10128  },
10129
10130  /* VEX_LEN_0F3A31_P_2 */
10131  {
10132    { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10133  },
10134
10135  /* VEX_LEN_0F3A32_P_2 */
10136  {
10137    { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10138  },
10139
10140  /* VEX_LEN_0F3A33_P_2 */
10141  {
10142    { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10143  },
10144
10145  /* VEX_LEN_0F3A38_P_2 */
10146  {
10147    { Bad_Opcode },
10148    { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10149  },
10150
10151  /* VEX_LEN_0F3A39_P_2 */
10152  {
10153    { Bad_Opcode },
10154    { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10155  },
10156
10157  /* VEX_LEN_0F3A41_P_2 */
10158  {
10159    { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10160  },
10161
10162  /* VEX_LEN_0F3A44_P_2 */
10163  {
10164    { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
10165  },
10166
10167  /* VEX_LEN_0F3A46_P_2 */
10168  {
10169    { Bad_Opcode },
10170    { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10171  },
10172
10173  /* VEX_LEN_0F3A60_P_2 */
10174  {
10175    { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
10176  },
10177
10178  /* VEX_LEN_0F3A61_P_2 */
10179  {
10180    { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
10181  },
10182
10183  /* VEX_LEN_0F3A62_P_2 */
10184  {
10185    { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10186  },
10187
10188  /* VEX_LEN_0F3A63_P_2 */
10189  {
10190    { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10191  },
10192
10193  /* VEX_LEN_0F3A6A_P_2 */
10194  {
10195    { "vfmaddss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10196  },
10197
10198  /* VEX_LEN_0F3A6B_P_2 */
10199  {
10200    { "vfmaddsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10201  },
10202
10203  /* VEX_LEN_0F3A6E_P_2 */
10204  {
10205    { "vfmsubss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10206  },
10207
10208  /* VEX_LEN_0F3A6F_P_2 */
10209  {
10210    { "vfmsubsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10211  },
10212
10213  /* VEX_LEN_0F3A7A_P_2 */
10214  {
10215    { "vfnmaddss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10216  },
10217
10218  /* VEX_LEN_0F3A7B_P_2 */
10219  {
10220    { "vfnmaddsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10221  },
10222
10223  /* VEX_LEN_0F3A7E_P_2 */
10224  {
10225    { "vfnmsubss",	{ XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
10226  },
10227
10228  /* VEX_LEN_0F3A7F_P_2 */
10229  {
10230    { "vfnmsubsd",	{ XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
10231  },
10232
10233  /* VEX_LEN_0F3ADF_P_2 */
10234  {
10235    { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10236  },
10237
10238  /* VEX_LEN_0F3AF0_P_3 */
10239  {
10240    { "rorxS",		{ Gdq, Edq, Ib } },
10241  },
10242
10243  /* VEX_LEN_0FXOP_08_CC */
10244  {
10245     { "vpcomb",	{ XM, Vex128, EXx, Ib } },
10246  },
10247
10248  /* VEX_LEN_0FXOP_08_CD */
10249  {
10250     { "vpcomw",	{ XM, Vex128, EXx, Ib } },
10251  },
10252
10253  /* VEX_LEN_0FXOP_08_CE */
10254  {
10255     { "vpcomd",	{ XM, Vex128, EXx, Ib } },
10256  },
10257
10258  /* VEX_LEN_0FXOP_08_CF */
10259  {
10260     { "vpcomq",	{ XM, Vex128, EXx, Ib } },
10261  },
10262
10263  /* VEX_LEN_0FXOP_08_EC */
10264  {
10265     { "vpcomub",	{ XM, Vex128, EXx, Ib } },
10266  },
10267
10268  /* VEX_LEN_0FXOP_08_ED */
10269  {
10270     { "vpcomuw",	{ XM, Vex128, EXx, Ib } },
10271  },
10272
10273  /* VEX_LEN_0FXOP_08_EE */
10274  {
10275     { "vpcomud",	{ XM, Vex128, EXx, Ib } },
10276  },
10277
10278  /* VEX_LEN_0FXOP_08_EF */
10279  {
10280     { "vpcomuq",	{ XM, Vex128, EXx, Ib } },
10281  },
10282
10283  /* VEX_LEN_0FXOP_09_80 */
10284  {
10285    { "vfrczps",	{ XM, EXxmm } },
10286    { "vfrczps",	{ XM, EXymmq } },
10287  },
10288
10289  /* VEX_LEN_0FXOP_09_81 */
10290  {
10291    { "vfrczpd",	{ XM, EXxmm } },
10292    { "vfrczpd",	{ XM, EXymmq } },
10293  },
10294};
10295
10296static const struct dis386 vex_w_table[][2] = {
10297  {
10298    /* VEX_W_0F10_P_0 */
10299    { "vmovups",	{ XM, EXx } },
10300  },
10301  {
10302    /* VEX_W_0F10_P_1 */
10303    { "vmovss",		{ XMVexScalar, VexScalar, EXdScalar } },
10304  },
10305  {
10306    /* VEX_W_0F10_P_2 */
10307    { "vmovupd",	{ XM, EXx } },
10308  },
10309  {
10310    /* VEX_W_0F10_P_3 */
10311    { "vmovsd",		{ XMVexScalar, VexScalar, EXqScalar } },
10312  },
10313  {
10314    /* VEX_W_0F11_P_0 */
10315    { "vmovups",	{ EXxS, XM } },
10316  },
10317  {
10318    /* VEX_W_0F11_P_1 */
10319    { "vmovss",		{ EXdVexScalarS, VexScalar, XMScalar } },
10320  },
10321  {
10322    /* VEX_W_0F11_P_2 */
10323    { "vmovupd",	{ EXxS, XM } },
10324  },
10325  {
10326    /* VEX_W_0F11_P_3 */
10327    { "vmovsd",		{ EXqVexScalarS, VexScalar, XMScalar } },
10328  },
10329  {
10330    /* VEX_W_0F12_P_0_M_0 */
10331    { "vmovlps",	{ XM, Vex128, EXq } },
10332  },
10333  {
10334    /* VEX_W_0F12_P_0_M_1 */
10335    { "vmovhlps",	{ XM, Vex128, EXq } },
10336  },
10337  {
10338    /* VEX_W_0F12_P_1 */
10339    { "vmovsldup",	{ XM, EXx } },
10340  },
10341  {
10342    /* VEX_W_0F12_P_2 */
10343    { "vmovlpd",	{ XM, Vex128, EXq } },
10344  },
10345  {
10346    /* VEX_W_0F12_P_3 */
10347    { "vmovddup",	{ XM, EXymmq } },
10348  },
10349  {
10350    /* VEX_W_0F13_M_0 */
10351    { "vmovlpX",	{ EXq, XM } },
10352  },
10353  {
10354    /* VEX_W_0F14 */
10355    { "vunpcklpX",	{ XM, Vex, EXx } },
10356  },
10357  {
10358    /* VEX_W_0F15 */
10359    { "vunpckhpX",	{ XM, Vex, EXx } },
10360  },
10361  {
10362    /* VEX_W_0F16_P_0_M_0 */
10363    { "vmovhps",	{ XM, Vex128, EXq } },
10364  },
10365  {
10366    /* VEX_W_0F16_P_0_M_1 */
10367    { "vmovlhps",	{ XM, Vex128, EXq } },
10368  },
10369  {
10370    /* VEX_W_0F16_P_1 */
10371    { "vmovshdup",	{ XM, EXx } },
10372  },
10373  {
10374    /* VEX_W_0F16_P_2 */
10375    { "vmovhpd",	{ XM, Vex128, EXq } },
10376  },
10377  {
10378    /* VEX_W_0F17_M_0 */
10379    { "vmovhpX",	{ EXq, XM } },
10380  },
10381  {
10382    /* VEX_W_0F28 */
10383    { "vmovapX",	{ XM, EXx } },
10384  },
10385  {
10386    /* VEX_W_0F29 */
10387    { "vmovapX",	{ EXxS, XM } },
10388  },
10389  {
10390    /* VEX_W_0F2B_M_0 */
10391    { "vmovntpX",	{ Mx, XM } },
10392  },
10393  {
10394    /* VEX_W_0F2E_P_0 */
10395    { "vucomiss",	{ XMScalar, EXdScalar } },
10396  },
10397  {
10398    /* VEX_W_0F2E_P_2 */
10399    { "vucomisd",	{ XMScalar, EXqScalar } },
10400  },
10401  {
10402    /* VEX_W_0F2F_P_0 */
10403    { "vcomiss",	{ XMScalar, EXdScalar } },
10404  },
10405  {
10406    /* VEX_W_0F2F_P_2 */
10407    { "vcomisd",	{ XMScalar, EXqScalar } },
10408  },
10409  {
10410    /* VEX_W_0F41_P_0_LEN_1 */
10411    { "kandw",          { MaskG, MaskVex, MaskR } },
10412    { "kandq",          { MaskG, MaskVex, MaskR } },
10413  },
10414  {
10415    /* VEX_W_0F41_P_2_LEN_1 */
10416    { "kandb",          { MaskG, MaskVex, MaskR } },
10417    { "kandd",          { MaskG, MaskVex, MaskR } },
10418  },
10419  {
10420    /* VEX_W_0F42_P_0_LEN_1 */
10421    { "kandnw",         { MaskG, MaskVex, MaskR } },
10422    { "kandnq",         { MaskG, MaskVex, MaskR } },
10423  },
10424  {
10425    /* VEX_W_0F42_P_2_LEN_1 */
10426    { "kandnb",         { MaskG, MaskVex, MaskR } },
10427    { "kandnd",         { MaskG, MaskVex, MaskR } },
10428  },
10429  {
10430    /* VEX_W_0F44_P_0_LEN_0 */
10431    { "knotw",		{ MaskG, MaskR } },
10432    { "knotq",		{ MaskG, MaskR } },
10433  },
10434  {
10435    /* VEX_W_0F44_P_2_LEN_0 */
10436    { "knotb",		{ MaskG, MaskR } },
10437    { "knotd",		{ MaskG, MaskR } },
10438  },
10439  {
10440    /* VEX_W_0F45_P_0_LEN_1 */
10441    { "korw",           { MaskG, MaskVex, MaskR } },
10442    { "korq",           { MaskG, MaskVex, MaskR } },
10443  },
10444  {
10445    /* VEX_W_0F45_P_2_LEN_1 */
10446    { "korb",           { MaskG, MaskVex, MaskR } },
10447    { "kord",           { MaskG, MaskVex, MaskR } },
10448  },
10449  {
10450    /* VEX_W_0F46_P_0_LEN_1 */
10451    { "kxnorw",         { MaskG, MaskVex, MaskR } },
10452    { "kxnorq",         { MaskG, MaskVex, MaskR } },
10453  },
10454  {
10455    /* VEX_W_0F46_P_2_LEN_1 */
10456    { "kxnorb",         { MaskG, MaskVex, MaskR } },
10457    { "kxnord",         { MaskG, MaskVex, MaskR } },
10458  },
10459  {
10460    /* VEX_W_0F47_P_0_LEN_1 */
10461    { "kxorw",          { MaskG, MaskVex, MaskR } },
10462    { "kxorq",          { MaskG, MaskVex, MaskR } },
10463  },
10464  {
10465    /* VEX_W_0F47_P_2_LEN_1 */
10466    { "kxorb",          { MaskG, MaskVex, MaskR } },
10467    { "kxord",          { MaskG, MaskVex, MaskR } },
10468  },
10469  {
10470    /* VEX_W_0F4A_P_0_LEN_1 */
10471    { "kaddw",          { MaskG, MaskVex, MaskR } },
10472    { "kaddq",          { MaskG, MaskVex, MaskR } },
10473  },
10474  {
10475    /* VEX_W_0F4A_P_2_LEN_1 */
10476    { "kaddb",          { MaskG, MaskVex, MaskR } },
10477    { "kaddd",          { MaskG, MaskVex, MaskR } },
10478  },
10479  {
10480    /* VEX_W_0F4B_P_0_LEN_1 */
10481    { "kunpckwd",	{ MaskG, MaskVex, MaskR } },
10482    { "kunpckdq",	{ MaskG, MaskVex, MaskR } },
10483  },
10484  {
10485    /* VEX_W_0F4B_P_2_LEN_1 */
10486    { "kunpckbw",	{ MaskG, MaskVex, MaskR } },
10487  },
10488  {
10489    /* VEX_W_0F50_M_0 */
10490    { "vmovmskpX",	{ Gdq, XS } },
10491  },
10492  {
10493    /* VEX_W_0F51_P_0 */
10494    { "vsqrtps",	{ XM, EXx } },
10495  },
10496  {
10497    /* VEX_W_0F51_P_1 */
10498    { "vsqrtss",	{ XMScalar, VexScalar, EXdScalar } },
10499  },
10500  {
10501    /* VEX_W_0F51_P_2  */
10502    { "vsqrtpd",	{ XM, EXx } },
10503  },
10504  {
10505    /* VEX_W_0F51_P_3 */
10506    { "vsqrtsd",	{ XMScalar, VexScalar, EXqScalar } },
10507  },
10508  {
10509    /* VEX_W_0F52_P_0 */
10510    { "vrsqrtps",	{ XM, EXx } },
10511  },
10512  {
10513    /* VEX_W_0F52_P_1 */
10514    { "vrsqrtss",	{ XMScalar, VexScalar, EXdScalar } },
10515  },
10516  {
10517    /* VEX_W_0F53_P_0  */
10518    { "vrcpps",		{ XM, EXx } },
10519  },
10520  {
10521    /* VEX_W_0F53_P_1  */
10522    { "vrcpss",		{ XMScalar, VexScalar, EXdScalar } },
10523  },
10524  {
10525    /* VEX_W_0F58_P_0  */
10526    { "vaddps",		{ XM, Vex, EXx } },
10527  },
10528  {
10529    /* VEX_W_0F58_P_1  */
10530    { "vaddss",		{ XMScalar, VexScalar, EXdScalar } },
10531  },
10532  {
10533    /* VEX_W_0F58_P_2  */
10534    { "vaddpd",		{ XM, Vex, EXx } },
10535  },
10536  {
10537    /* VEX_W_0F58_P_3  */
10538    { "vaddsd",		{ XMScalar, VexScalar, EXqScalar } },
10539  },
10540  {
10541    /* VEX_W_0F59_P_0  */
10542    { "vmulps",		{ XM, Vex, EXx } },
10543  },
10544  {
10545    /* VEX_W_0F59_P_1  */
10546    { "vmulss",		{ XMScalar, VexScalar, EXdScalar } },
10547  },
10548  {
10549    /* VEX_W_0F59_P_2  */
10550    { "vmulpd",		{ XM, Vex, EXx } },
10551  },
10552  {
10553    /* VEX_W_0F59_P_3  */
10554    { "vmulsd",		{ XMScalar, VexScalar, EXqScalar } },
10555  },
10556  {
10557    /* VEX_W_0F5A_P_0  */
10558    { "vcvtps2pd",	{ XM, EXxmmq } },
10559  },
10560  {
10561    /* VEX_W_0F5A_P_1  */
10562    { "vcvtss2sd",	{ XMScalar, VexScalar, EXdScalar } },
10563  },
10564  {
10565    /* VEX_W_0F5A_P_3  */
10566    { "vcvtsd2ss",	{ XMScalar, VexScalar, EXqScalar } },
10567  },
10568  {
10569    /* VEX_W_0F5B_P_0  */
10570    { "vcvtdq2ps",	{ XM, EXx } },
10571  },
10572  {
10573    /* VEX_W_0F5B_P_1  */
10574    { "vcvttps2dq",	{ XM, EXx } },
10575  },
10576  {
10577    /* VEX_W_0F5B_P_2  */
10578    { "vcvtps2dq",	{ XM, EXx } },
10579  },
10580  {
10581    /* VEX_W_0F5C_P_0  */
10582    { "vsubps",		{ XM, Vex, EXx } },
10583  },
10584  {
10585    /* VEX_W_0F5C_P_1  */
10586    { "vsubss",		{ XMScalar, VexScalar, EXdScalar } },
10587  },
10588  {
10589    /* VEX_W_0F5C_P_2  */
10590    { "vsubpd",		{ XM, Vex, EXx } },
10591  },
10592  {
10593    /* VEX_W_0F5C_P_3  */
10594    { "vsubsd",		{ XMScalar, VexScalar, EXqScalar } },
10595  },
10596  {
10597    /* VEX_W_0F5D_P_0  */
10598    { "vminps",		{ XM, Vex, EXx } },
10599  },
10600  {
10601    /* VEX_W_0F5D_P_1  */
10602    { "vminss",		{ XMScalar, VexScalar, EXdScalar } },
10603  },
10604  {
10605    /* VEX_W_0F5D_P_2  */
10606    { "vminpd",		{ XM, Vex, EXx } },
10607  },
10608  {
10609    /* VEX_W_0F5D_P_3  */
10610    { "vminsd",		{ XMScalar, VexScalar, EXqScalar } },
10611  },
10612  {
10613    /* VEX_W_0F5E_P_0  */
10614    { "vdivps",		{ XM, Vex, EXx } },
10615  },
10616  {
10617    /* VEX_W_0F5E_P_1  */
10618    { "vdivss",		{ XMScalar, VexScalar, EXdScalar } },
10619  },
10620  {
10621    /* VEX_W_0F5E_P_2  */
10622    { "vdivpd",		{ XM, Vex, EXx } },
10623  },
10624  {
10625    /* VEX_W_0F5E_P_3  */
10626    { "vdivsd",		{ XMScalar, VexScalar, EXqScalar } },
10627  },
10628  {
10629    /* VEX_W_0F5F_P_0  */
10630    { "vmaxps",		{ XM, Vex, EXx } },
10631  },
10632  {
10633    /* VEX_W_0F5F_P_1  */
10634    { "vmaxss",		{ XMScalar, VexScalar, EXdScalar } },
10635  },
10636  {
10637    /* VEX_W_0F5F_P_2  */
10638    { "vmaxpd",		{ XM, Vex, EXx } },
10639  },
10640  {
10641    /* VEX_W_0F5F_P_3  */
10642    { "vmaxsd",		{ XMScalar, VexScalar, EXqScalar } },
10643  },
10644  {
10645    /* VEX_W_0F60_P_2  */
10646    { "vpunpcklbw",	{ XM, Vex, EXx } },
10647  },
10648  {
10649    /* VEX_W_0F61_P_2  */
10650    { "vpunpcklwd",	{ XM, Vex, EXx } },
10651  },
10652  {
10653    /* VEX_W_0F62_P_2  */
10654    { "vpunpckldq",	{ XM, Vex, EXx } },
10655  },
10656  {
10657    /* VEX_W_0F63_P_2  */
10658    { "vpacksswb",	{ XM, Vex, EXx } },
10659  },
10660  {
10661    /* VEX_W_0F64_P_2  */
10662    { "vpcmpgtb",	{ XM, Vex, EXx } },
10663  },
10664  {
10665    /* VEX_W_0F65_P_2  */
10666    { "vpcmpgtw",	{ XM, Vex, EXx } },
10667  },
10668  {
10669    /* VEX_W_0F66_P_2  */
10670    { "vpcmpgtd",	{ XM, Vex, EXx } },
10671  },
10672  {
10673    /* VEX_W_0F67_P_2  */
10674    { "vpackuswb",	{ XM, Vex, EXx } },
10675  },
10676  {
10677    /* VEX_W_0F68_P_2  */
10678    { "vpunpckhbw",	{ XM, Vex, EXx } },
10679  },
10680  {
10681    /* VEX_W_0F69_P_2  */
10682    { "vpunpckhwd",	{ XM, Vex, EXx } },
10683  },
10684  {
10685    /* VEX_W_0F6A_P_2  */
10686    { "vpunpckhdq",	{ XM, Vex, EXx } },
10687  },
10688  {
10689    /* VEX_W_0F6B_P_2  */
10690    { "vpackssdw",	{ XM, Vex, EXx } },
10691  },
10692  {
10693    /* VEX_W_0F6C_P_2  */
10694    { "vpunpcklqdq",	{ XM, Vex, EXx } },
10695  },
10696  {
10697    /* VEX_W_0F6D_P_2  */
10698    { "vpunpckhqdq",	{ XM, Vex, EXx } },
10699  },
10700  {
10701    /* VEX_W_0F6F_P_1  */
10702    { "vmovdqu",	{ XM, EXx } },
10703  },
10704  {
10705    /* VEX_W_0F6F_P_2  */
10706    { "vmovdqa",	{ XM, EXx } },
10707  },
10708  {
10709    /* VEX_W_0F70_P_1 */
10710    { "vpshufhw",	{ XM, EXx, Ib } },
10711  },
10712  {
10713    /* VEX_W_0F70_P_2 */
10714    { "vpshufd",	{ XM, EXx, Ib } },
10715  },
10716  {
10717    /* VEX_W_0F70_P_3 */
10718    { "vpshuflw",	{ XM, EXx, Ib } },
10719  },
10720  {
10721    /* VEX_W_0F71_R_2_P_2  */
10722    { "vpsrlw",		{ Vex, XS, Ib } },
10723  },
10724  {
10725    /* VEX_W_0F71_R_4_P_2  */
10726    { "vpsraw",		{ Vex, XS, Ib } },
10727  },
10728  {
10729    /* VEX_W_0F71_R_6_P_2  */
10730    { "vpsllw",		{ Vex, XS, Ib } },
10731  },
10732  {
10733    /* VEX_W_0F72_R_2_P_2  */
10734    { "vpsrld",		{ Vex, XS, Ib } },
10735  },
10736  {
10737    /* VEX_W_0F72_R_4_P_2  */
10738    { "vpsrad",		{ Vex, XS, Ib } },
10739  },
10740  {
10741    /* VEX_W_0F72_R_6_P_2  */
10742    { "vpslld",		{ Vex, XS, Ib } },
10743  },
10744  {
10745    /* VEX_W_0F73_R_2_P_2  */
10746    { "vpsrlq",		{ Vex, XS, Ib } },
10747  },
10748  {
10749    /* VEX_W_0F73_R_3_P_2  */
10750    { "vpsrldq",	{ Vex, XS, Ib } },
10751  },
10752  {
10753    /* VEX_W_0F73_R_6_P_2  */
10754    { "vpsllq",		{ Vex, XS, Ib } },
10755  },
10756  {
10757    /* VEX_W_0F73_R_7_P_2  */
10758    { "vpslldq",	{ Vex, XS, Ib } },
10759  },
10760  {
10761    /* VEX_W_0F74_P_2 */
10762    { "vpcmpeqb",	{ XM, Vex, EXx } },
10763  },
10764  {
10765    /* VEX_W_0F75_P_2 */
10766    { "vpcmpeqw",	{ XM, Vex, EXx } },
10767  },
10768  {
10769    /* VEX_W_0F76_P_2 */
10770    { "vpcmpeqd",	{ XM, Vex, EXx } },
10771  },
10772  {
10773    /* VEX_W_0F77_P_0 */
10774    { "",		{ VZERO } },
10775  },
10776  {
10777    /* VEX_W_0F7C_P_2 */
10778    { "vhaddpd",	{ XM, Vex, EXx } },
10779  },
10780  {
10781    /* VEX_W_0F7C_P_3 */
10782    { "vhaddps",	{ XM, Vex, EXx } },
10783  },
10784  {
10785    /* VEX_W_0F7D_P_2 */
10786    { "vhsubpd",	{ XM, Vex, EXx } },
10787  },
10788  {
10789    /* VEX_W_0F7D_P_3 */
10790    { "vhsubps",	{ XM, Vex, EXx } },
10791  },
10792  {
10793    /* VEX_W_0F7E_P_1 */
10794    { "vmovq",		{ XMScalar, EXqScalar } },
10795  },
10796  {
10797    /* VEX_W_0F7F_P_1 */
10798    { "vmovdqu",	{ EXxS, XM } },
10799  },
10800  {
10801    /* VEX_W_0F7F_P_2 */
10802    { "vmovdqa",	{ EXxS, XM } },
10803  },
10804  {
10805    /* VEX_W_0F90_P_0_LEN_0 */
10806    { "kmovw",		{ MaskG, MaskE } },
10807    { "kmovq",		{ MaskG, MaskE } },
10808  },
10809  {
10810    /* VEX_W_0F90_P_2_LEN_0 */
10811    { "kmovb",		{ MaskG, MaskBDE } },
10812    { "kmovd",		{ MaskG, MaskBDE } },
10813  },
10814  {
10815    /* VEX_W_0F91_P_0_LEN_0 */
10816    { "kmovw",		{ Ew, MaskG } },
10817    { "kmovq",		{ Eq, MaskG } },
10818  },
10819  {
10820    /* VEX_W_0F91_P_2_LEN_0 */
10821    { "kmovb",		{ Eb, MaskG } },
10822    { "kmovd",		{ Ed, MaskG } },
10823  },
10824  {
10825    /* VEX_W_0F92_P_0_LEN_0 */
10826    { "kmovw",		{ MaskG, Rdq } },
10827  },
10828  {
10829    /* VEX_W_0F92_P_2_LEN_0 */
10830    { "kmovb",		{ MaskG, Rdq } },
10831  },
10832  {
10833    /* VEX_W_0F92_P_3_LEN_0 */
10834    { "kmovd",		{ MaskG, Rdq } },
10835    { "kmovq",		{ MaskG, Rdq } },
10836  },
10837  {
10838    /* VEX_W_0F93_P_0_LEN_0 */
10839    { "kmovw",		{ Gdq, MaskR } },
10840  },
10841  {
10842    /* VEX_W_0F93_P_2_LEN_0 */
10843    { "kmovb",		{ Gdq, MaskR } },
10844  },
10845  {
10846    /* VEX_W_0F93_P_3_LEN_0 */
10847    { "kmovd",		{ Gdq, MaskR } },
10848    { "kmovq",		{ Gdq, MaskR } },
10849  },
10850  {
10851    /* VEX_W_0F98_P_0_LEN_0 */
10852    { "kortestw",	{ MaskG, MaskR } },
10853    { "kortestq",	{ MaskG, MaskR } },
10854  },
10855  {
10856    /* VEX_W_0F98_P_2_LEN_0 */
10857    { "kortestb",	{ MaskG, MaskR } },
10858    { "kortestd",	{ MaskG, MaskR } },
10859  },
10860  {
10861    /* VEX_W_0F99_P_0_LEN_0 */
10862    { "ktestw",	{ MaskG, MaskR } },
10863    { "ktestq",	{ MaskG, MaskR } },
10864  },
10865  {
10866    /* VEX_W_0F99_P_2_LEN_0 */
10867    { "ktestb",	{ MaskG, MaskR } },
10868    { "ktestd",	{ MaskG, MaskR } },
10869  },
10870  {
10871    /* VEX_W_0FAE_R_2_M_0 */
10872    { "vldmxcsr",	{ Md } },
10873  },
10874  {
10875    /* VEX_W_0FAE_R_3_M_0 */
10876    { "vstmxcsr",	{ Md } },
10877  },
10878  {
10879    /* VEX_W_0FC2_P_0 */
10880    { "vcmpps",		{ XM, Vex, EXx, VCMP } },
10881  },
10882  {
10883    /* VEX_W_0FC2_P_1 */
10884    { "vcmpss",		{ XMScalar, VexScalar, EXdScalar, VCMP } },
10885  },
10886  {
10887    /* VEX_W_0FC2_P_2 */
10888    { "vcmppd",		{ XM, Vex, EXx, VCMP } },
10889  },
10890  {
10891    /* VEX_W_0FC2_P_3 */
10892    { "vcmpsd",		{ XMScalar, VexScalar, EXqScalar, VCMP } },
10893  },
10894  {
10895    /* VEX_W_0FC4_P_2 */
10896    { "vpinsrw",	{ XM, Vex128, Edqw, Ib } },
10897  },
10898  {
10899    /* VEX_W_0FC5_P_2 */
10900    { "vpextrw",	{ Gdq, XS, Ib } },
10901  },
10902  {
10903    /* VEX_W_0FD0_P_2 */
10904    { "vaddsubpd",	{ XM, Vex, EXx } },
10905  },
10906  {
10907    /* VEX_W_0FD0_P_3 */
10908    { "vaddsubps",	{ XM, Vex, EXx } },
10909  },
10910  {
10911    /* VEX_W_0FD1_P_2 */
10912    { "vpsrlw",		{ XM, Vex, EXxmm } },
10913  },
10914  {
10915    /* VEX_W_0FD2_P_2 */
10916    { "vpsrld",		{ XM, Vex, EXxmm } },
10917  },
10918  {
10919    /* VEX_W_0FD3_P_2 */
10920    { "vpsrlq",		{ XM, Vex, EXxmm } },
10921  },
10922  {
10923    /* VEX_W_0FD4_P_2 */
10924    { "vpaddq",		{ XM, Vex, EXx } },
10925  },
10926  {
10927    /* VEX_W_0FD5_P_2 */
10928    { "vpmullw",	{ XM, Vex, EXx } },
10929  },
10930  {
10931    /* VEX_W_0FD6_P_2 */
10932    { "vmovq",		{ EXqScalarS, XMScalar } },
10933  },
10934  {
10935    /* VEX_W_0FD7_P_2_M_1 */
10936    { "vpmovmskb",	{ Gdq, XS } },
10937  },
10938  {
10939    /* VEX_W_0FD8_P_2 */
10940    { "vpsubusb",	{ XM, Vex, EXx } },
10941  },
10942  {
10943    /* VEX_W_0FD9_P_2 */
10944    { "vpsubusw",	{ XM, Vex, EXx } },
10945  },
10946  {
10947    /* VEX_W_0FDA_P_2 */
10948    { "vpminub",	{ XM, Vex, EXx } },
10949  },
10950  {
10951    /* VEX_W_0FDB_P_2 */
10952    { "vpand",		{ XM, Vex, EXx } },
10953  },
10954  {
10955    /* VEX_W_0FDC_P_2 */
10956    { "vpaddusb",	{ XM, Vex, EXx } },
10957  },
10958  {
10959    /* VEX_W_0FDD_P_2 */
10960    { "vpaddusw",	{ XM, Vex, EXx } },
10961  },
10962  {
10963    /* VEX_W_0FDE_P_2 */
10964    { "vpmaxub",	{ XM, Vex, EXx } },
10965  },
10966  {
10967    /* VEX_W_0FDF_P_2 */
10968    { "vpandn",		{ XM, Vex, EXx } },
10969  },
10970  {
10971    /* VEX_W_0FE0_P_2  */
10972    { "vpavgb",		{ XM, Vex, EXx } },
10973  },
10974  {
10975    /* VEX_W_0FE1_P_2  */
10976    { "vpsraw",		{ XM, Vex, EXxmm } },
10977  },
10978  {
10979    /* VEX_W_0FE2_P_2  */
10980    { "vpsrad",		{ XM, Vex, EXxmm } },
10981  },
10982  {
10983    /* VEX_W_0FE3_P_2  */
10984    { "vpavgw",		{ XM, Vex, EXx } },
10985  },
10986  {
10987    /* VEX_W_0FE4_P_2  */
10988    { "vpmulhuw",	{ XM, Vex, EXx } },
10989  },
10990  {
10991    /* VEX_W_0FE5_P_2  */
10992    { "vpmulhw",	{ XM, Vex, EXx } },
10993  },
10994  {
10995    /* VEX_W_0FE6_P_1  */
10996    { "vcvtdq2pd",	{ XM, EXxmmq } },
10997  },
10998  {
10999    /* VEX_W_0FE6_P_2  */
11000    { "vcvttpd2dq%XY",	{ XMM, EXx } },
11001  },
11002  {
11003    /* VEX_W_0FE6_P_3  */
11004    { "vcvtpd2dq%XY",	{ XMM, EXx } },
11005  },
11006  {
11007    /* VEX_W_0FE7_P_2_M_0 */
11008    { "vmovntdq",	{ Mx, XM } },
11009  },
11010  {
11011    /* VEX_W_0FE8_P_2  */
11012    { "vpsubsb",	{ XM, Vex, EXx } },
11013  },
11014  {
11015    /* VEX_W_0FE9_P_2  */
11016    { "vpsubsw",	{ XM, Vex, EXx } },
11017  },
11018  {
11019    /* VEX_W_0FEA_P_2  */
11020    { "vpminsw",	{ XM, Vex, EXx } },
11021  },
11022  {
11023    /* VEX_W_0FEB_P_2  */
11024    { "vpor",		{ XM, Vex, EXx } },
11025  },
11026  {
11027    /* VEX_W_0FEC_P_2  */
11028    { "vpaddsb",	{ XM, Vex, EXx } },
11029  },
11030  {
11031    /* VEX_W_0FED_P_2  */
11032    { "vpaddsw",	{ XM, Vex, EXx } },
11033  },
11034  {
11035    /* VEX_W_0FEE_P_2  */
11036    { "vpmaxsw",	{ XM, Vex, EXx } },
11037  },
11038  {
11039    /* VEX_W_0FEF_P_2  */
11040    { "vpxor",		{ XM, Vex, EXx } },
11041  },
11042  {
11043    /* VEX_W_0FF0_P_3_M_0 */
11044    { "vlddqu",		{ XM, M } },
11045  },
11046  {
11047    /* VEX_W_0FF1_P_2 */
11048    { "vpsllw",		{ XM, Vex, EXxmm } },
11049  },
11050  {
11051    /* VEX_W_0FF2_P_2 */
11052    { "vpslld",		{ XM, Vex, EXxmm } },
11053  },
11054  {
11055    /* VEX_W_0FF3_P_2 */
11056    { "vpsllq",		{ XM, Vex, EXxmm } },
11057  },
11058  {
11059    /* VEX_W_0FF4_P_2 */
11060    { "vpmuludq",	{ XM, Vex, EXx } },
11061  },
11062  {
11063    /* VEX_W_0FF5_P_2 */
11064    { "vpmaddwd",	{ XM, Vex, EXx } },
11065  },
11066  {
11067    /* VEX_W_0FF6_P_2 */
11068    { "vpsadbw",	{ XM, Vex, EXx } },
11069  },
11070  {
11071    /* VEX_W_0FF7_P_2 */
11072    { "vmaskmovdqu",	{ XM, XS } },
11073  },
11074  {
11075    /* VEX_W_0FF8_P_2 */
11076    { "vpsubb",		{ XM, Vex, EXx } },
11077  },
11078  {
11079    /* VEX_W_0FF9_P_2 */
11080    { "vpsubw",		{ XM, Vex, EXx } },
11081  },
11082  {
11083    /* VEX_W_0FFA_P_2 */
11084    { "vpsubd",		{ XM, Vex, EXx } },
11085  },
11086  {
11087    /* VEX_W_0FFB_P_2 */
11088    { "vpsubq",		{ XM, Vex, EXx } },
11089  },
11090  {
11091    /* VEX_W_0FFC_P_2 */
11092    { "vpaddb",		{ XM, Vex, EXx } },
11093  },
11094  {
11095    /* VEX_W_0FFD_P_2 */
11096    { "vpaddw",		{ XM, Vex, EXx } },
11097  },
11098  {
11099    /* VEX_W_0FFE_P_2 */
11100    { "vpaddd",		{ XM, Vex, EXx } },
11101  },
11102  {
11103    /* VEX_W_0F3800_P_2  */
11104    { "vpshufb",	{ XM, Vex, EXx } },
11105  },
11106  {
11107    /* VEX_W_0F3801_P_2  */
11108    { "vphaddw",	{ XM, Vex, EXx } },
11109  },
11110  {
11111    /* VEX_W_0F3802_P_2  */
11112    { "vphaddd",	{ XM, Vex, EXx } },
11113  },
11114  {
11115    /* VEX_W_0F3803_P_2  */
11116    { "vphaddsw",	{ XM, Vex, EXx } },
11117  },
11118  {
11119    /* VEX_W_0F3804_P_2  */
11120    { "vpmaddubsw",	{ XM, Vex, EXx } },
11121  },
11122  {
11123    /* VEX_W_0F3805_P_2  */
11124    { "vphsubw",	{ XM, Vex, EXx } },
11125  },
11126  {
11127    /* VEX_W_0F3806_P_2  */
11128    { "vphsubd",	{ XM, Vex, EXx } },
11129  },
11130  {
11131    /* VEX_W_0F3807_P_2  */
11132    { "vphsubsw",	{ XM, Vex, EXx } },
11133  },
11134  {
11135    /* VEX_W_0F3808_P_2  */
11136    { "vpsignb",	{ XM, Vex, EXx } },
11137  },
11138  {
11139    /* VEX_W_0F3809_P_2  */
11140    { "vpsignw",	{ XM, Vex, EXx } },
11141  },
11142  {
11143    /* VEX_W_0F380A_P_2  */
11144    { "vpsignd",	{ XM, Vex, EXx } },
11145  },
11146  {
11147    /* VEX_W_0F380B_P_2  */
11148    { "vpmulhrsw",	{ XM, Vex, EXx } },
11149  },
11150  {
11151    /* VEX_W_0F380C_P_2  */
11152    { "vpermilps",	{ XM, Vex, EXx } },
11153  },
11154  {
11155    /* VEX_W_0F380D_P_2  */
11156    { "vpermilpd",	{ XM, Vex, EXx } },
11157  },
11158  {
11159    /* VEX_W_0F380E_P_2  */
11160    { "vtestps",	{ XM, EXx } },
11161  },
11162  {
11163    /* VEX_W_0F380F_P_2  */
11164    { "vtestpd",	{ XM, EXx } },
11165  },
11166  {
11167    /* VEX_W_0F3816_P_2  */
11168    { "vpermps",	{ XM, Vex, EXx } },
11169  },
11170  {
11171    /* VEX_W_0F3817_P_2 */
11172    { "vptest",		{ XM, EXx } },
11173  },
11174  {
11175    /* VEX_W_0F3818_P_2 */
11176    { "vbroadcastss",	{ XM, EXxmm_md } },
11177  },
11178  {
11179    /* VEX_W_0F3819_P_2 */
11180    { "vbroadcastsd",	{ XM, EXxmm_mq } },
11181  },
11182  {
11183    /* VEX_W_0F381A_P_2_M_0 */
11184    { "vbroadcastf128",	{ XM, Mxmm } },
11185  },
11186  {
11187    /* VEX_W_0F381C_P_2 */
11188    { "vpabsb",		{ XM, EXx } },
11189  },
11190  {
11191    /* VEX_W_0F381D_P_2 */
11192    { "vpabsw",		{ XM, EXx } },
11193  },
11194  {
11195    /* VEX_W_0F381E_P_2 */
11196    { "vpabsd",		{ XM, EXx } },
11197  },
11198  {
11199    /* VEX_W_0F3820_P_2 */
11200    { "vpmovsxbw",	{ XM, EXxmmq } },
11201  },
11202  {
11203    /* VEX_W_0F3821_P_2 */
11204    { "vpmovsxbd",	{ XM, EXxmmqd } },
11205  },
11206  {
11207    /* VEX_W_0F3822_P_2 */
11208    { "vpmovsxbq",	{ XM, EXxmmdw } },
11209  },
11210  {
11211    /* VEX_W_0F3823_P_2 */
11212    { "vpmovsxwd",	{ XM, EXxmmq } },
11213  },
11214  {
11215    /* VEX_W_0F3824_P_2 */
11216    { "vpmovsxwq",	{ XM, EXxmmqd } },
11217  },
11218  {
11219    /* VEX_W_0F3825_P_2 */
11220    { "vpmovsxdq",	{ XM, EXxmmq } },
11221  },
11222  {
11223    /* VEX_W_0F3828_P_2 */
11224    { "vpmuldq",	{ XM, Vex, EXx } },
11225  },
11226  {
11227    /* VEX_W_0F3829_P_2 */
11228    { "vpcmpeqq",	{ XM, Vex, EXx } },
11229  },
11230  {
11231    /* VEX_W_0F382A_P_2_M_0 */
11232    { "vmovntdqa",	{ XM, Mx } },
11233  },
11234  {
11235    /* VEX_W_0F382B_P_2 */
11236    { "vpackusdw",	{ XM, Vex, EXx } },
11237  },
11238  {
11239    /* VEX_W_0F382C_P_2_M_0 */
11240    { "vmaskmovps",	{ XM, Vex, Mx } },
11241  },
11242  {
11243    /* VEX_W_0F382D_P_2_M_0 */
11244    { "vmaskmovpd",	{ XM, Vex, Mx } },
11245  },
11246  {
11247    /* VEX_W_0F382E_P_2_M_0 */
11248    { "vmaskmovps",	{ Mx, Vex, XM } },
11249  },
11250  {
11251    /* VEX_W_0F382F_P_2_M_0 */
11252    { "vmaskmovpd",	{ Mx, Vex, XM } },
11253  },
11254  {
11255    /* VEX_W_0F3830_P_2 */
11256    { "vpmovzxbw",	{ XM, EXxmmq } },
11257  },
11258  {
11259    /* VEX_W_0F3831_P_2 */
11260    { "vpmovzxbd",	{ XM, EXxmmqd } },
11261  },
11262  {
11263    /* VEX_W_0F3832_P_2 */
11264    { "vpmovzxbq",	{ XM, EXxmmdw } },
11265  },
11266  {
11267    /* VEX_W_0F3833_P_2 */
11268    { "vpmovzxwd",	{ XM, EXxmmq } },
11269  },
11270  {
11271    /* VEX_W_0F3834_P_2 */
11272    { "vpmovzxwq",	{ XM, EXxmmqd } },
11273  },
11274  {
11275    /* VEX_W_0F3835_P_2 */
11276    { "vpmovzxdq",	{ XM, EXxmmq } },
11277  },
11278  {
11279    /* VEX_W_0F3836_P_2  */
11280    { "vpermd",		{ XM, Vex, EXx } },
11281  },
11282  {
11283    /* VEX_W_0F3837_P_2 */
11284    { "vpcmpgtq",	{ XM, Vex, EXx } },
11285  },
11286  {
11287    /* VEX_W_0F3838_P_2 */
11288    { "vpminsb",	{ XM, Vex, EXx } },
11289  },
11290  {
11291    /* VEX_W_0F3839_P_2 */
11292    { "vpminsd",	{ XM, Vex, EXx } },
11293  },
11294  {
11295    /* VEX_W_0F383A_P_2 */
11296    { "vpminuw",	{ XM, Vex, EXx } },
11297  },
11298  {
11299    /* VEX_W_0F383B_P_2 */
11300    { "vpminud",	{ XM, Vex, EXx } },
11301  },
11302  {
11303    /* VEX_W_0F383C_P_2 */
11304    { "vpmaxsb",	{ XM, Vex, EXx } },
11305  },
11306  {
11307    /* VEX_W_0F383D_P_2 */
11308    { "vpmaxsd",	{ XM, Vex, EXx } },
11309  },
11310  {
11311    /* VEX_W_0F383E_P_2 */
11312    { "vpmaxuw",	{ XM, Vex, EXx } },
11313  },
11314  {
11315    /* VEX_W_0F383F_P_2 */
11316    { "vpmaxud",	{ XM, Vex, EXx } },
11317  },
11318  {
11319    /* VEX_W_0F3840_P_2 */
11320    { "vpmulld",	{ XM, Vex, EXx } },
11321  },
11322  {
11323    /* VEX_W_0F3841_P_2 */
11324    { "vphminposuw",	{ XM, EXx } },
11325  },
11326  {
11327    /* VEX_W_0F3846_P_2 */
11328    { "vpsravd",	{ XM, Vex, EXx } },
11329  },
11330  {
11331    /* VEX_W_0F3858_P_2 */
11332    { "vpbroadcastd", { XM, EXxmm_md } },
11333  },
11334  {
11335    /* VEX_W_0F3859_P_2 */
11336    { "vpbroadcastq",	{ XM, EXxmm_mq } },
11337  },
11338  {
11339    /* VEX_W_0F385A_P_2_M_0 */
11340    { "vbroadcasti128", { XM, Mxmm } },
11341  },
11342  {
11343    /* VEX_W_0F3878_P_2 */
11344    { "vpbroadcastb",	{ XM, EXxmm_mb } },
11345  },
11346  {
11347    /* VEX_W_0F3879_P_2 */
11348    { "vpbroadcastw",	{ XM, EXxmm_mw } },
11349  },
11350  {
11351    /* VEX_W_0F38DB_P_2 */
11352    { "vaesimc",	{ XM, EXx } },
11353  },
11354  {
11355    /* VEX_W_0F38DC_P_2 */
11356    { "vaesenc",	{ XM, Vex128, EXx } },
11357  },
11358  {
11359    /* VEX_W_0F38DD_P_2 */
11360    { "vaesenclast",	{ XM, Vex128, EXx } },
11361  },
11362  {
11363    /* VEX_W_0F38DE_P_2 */
11364    { "vaesdec",	{ XM, Vex128, EXx } },
11365  },
11366  {
11367    /* VEX_W_0F38DF_P_2 */
11368    { "vaesdeclast",	{ XM, Vex128, EXx } },
11369  },
11370  {
11371    /* VEX_W_0F3A00_P_2 */
11372    { Bad_Opcode },
11373    { "vpermq",		{ XM, EXx, Ib } },
11374  },
11375  {
11376    /* VEX_W_0F3A01_P_2 */
11377    { Bad_Opcode },
11378    { "vpermpd",	{ XM, EXx, Ib } },
11379  },
11380  {
11381    /* VEX_W_0F3A02_P_2 */
11382    { "vpblendd",	{ XM, Vex, EXx, Ib } },
11383  },
11384  {
11385    /* VEX_W_0F3A04_P_2 */
11386    { "vpermilps",	{ XM, EXx, Ib } },
11387  },
11388  {
11389    /* VEX_W_0F3A05_P_2 */
11390    { "vpermilpd",	{ XM, EXx, Ib } },
11391  },
11392  {
11393    /* VEX_W_0F3A06_P_2 */
11394    { "vperm2f128",	{ XM, Vex256, EXx, Ib } },
11395  },
11396  {
11397    /* VEX_W_0F3A08_P_2 */
11398    { "vroundps",	{ XM, EXx, Ib } },
11399  },
11400  {
11401    /* VEX_W_0F3A09_P_2 */
11402    { "vroundpd",	{ XM, EXx, Ib } },
11403  },
11404  {
11405    /* VEX_W_0F3A0A_P_2 */
11406    { "vroundss",	{ XMScalar, VexScalar, EXdScalar, Ib } },
11407  },
11408  {
11409    /* VEX_W_0F3A0B_P_2 */
11410    { "vroundsd",	{ XMScalar, VexScalar, EXqScalar, Ib } },
11411  },
11412  {
11413    /* VEX_W_0F3A0C_P_2 */
11414    { "vblendps",	{ XM, Vex, EXx, Ib } },
11415  },
11416  {
11417    /* VEX_W_0F3A0D_P_2 */
11418    { "vblendpd",	{ XM, Vex, EXx, Ib } },
11419  },
11420  {
11421    /* VEX_W_0F3A0E_P_2 */
11422    { "vpblendw",	{ XM, Vex, EXx, Ib } },
11423  },
11424  {
11425    /* VEX_W_0F3A0F_P_2 */
11426    { "vpalignr",	{ XM, Vex, EXx, Ib } },
11427  },
11428  {
11429    /* VEX_W_0F3A14_P_2 */
11430    { "vpextrb",	{ Edqb, XM, Ib } },
11431  },
11432  {
11433    /* VEX_W_0F3A15_P_2 */
11434    { "vpextrw",	{ Edqw, XM, Ib } },
11435  },
11436  {
11437    /* VEX_W_0F3A18_P_2 */
11438    { "vinsertf128",	{ XM, Vex256, EXxmm, Ib } },
11439  },
11440  {
11441    /* VEX_W_0F3A19_P_2 */
11442    { "vextractf128",	{ EXxmm, XM, Ib } },
11443  },
11444  {
11445    /* VEX_W_0F3A20_P_2 */
11446    { "vpinsrb",	{ XM, Vex128, Edqb, Ib } },
11447  },
11448  {
11449    /* VEX_W_0F3A21_P_2 */
11450    { "vinsertps",	{ XM, Vex128, EXd, Ib } },
11451  },
11452  {
11453    /* VEX_W_0F3A30_P_2_LEN_0 */
11454    { "kshiftrb",	{ MaskG, MaskR, Ib } },
11455    { "kshiftrw",	{ MaskG, MaskR, Ib } },
11456  },
11457  {
11458    /* VEX_W_0F3A31_P_2_LEN_0 */
11459    { "kshiftrd",	{ MaskG, MaskR, Ib } },
11460    { "kshiftrq",	{ MaskG, MaskR, Ib } },
11461  },
11462  {
11463    /* VEX_W_0F3A32_P_2_LEN_0 */
11464    { "kshiftlb",	{ MaskG, MaskR, Ib } },
11465    { "kshiftlw",	{ MaskG, MaskR, Ib } },
11466  },
11467  {
11468    /* VEX_W_0F3A33_P_2_LEN_0 */
11469    { "kshiftld",	{ MaskG, MaskR, Ib } },
11470    { "kshiftlq",	{ MaskG, MaskR, Ib } },
11471  },
11472  {
11473    /* VEX_W_0F3A38_P_2 */
11474    { "vinserti128",	{ XM, Vex256, EXxmm, Ib } },
11475  },
11476  {
11477    /* VEX_W_0F3A39_P_2 */
11478    { "vextracti128",	{ EXxmm, XM, Ib } },
11479  },
11480  {
11481    /* VEX_W_0F3A40_P_2 */
11482    { "vdpps",		{ XM, Vex, EXx, Ib } },
11483  },
11484  {
11485    /* VEX_W_0F3A41_P_2 */
11486    { "vdppd",		{ XM, Vex128, EXx, Ib } },
11487  },
11488  {
11489    /* VEX_W_0F3A42_P_2 */
11490    { "vmpsadbw",	{ XM, Vex, EXx, Ib } },
11491  },
11492  {
11493    /* VEX_W_0F3A44_P_2 */
11494    { "vpclmulqdq",	{ XM, Vex128, EXx, PCLMUL } },
11495  },
11496  {
11497    /* VEX_W_0F3A46_P_2 */
11498    { "vperm2i128",	{ XM, Vex256, EXx, Ib } },
11499  },
11500  {
11501    /* VEX_W_0F3A48_P_2 */
11502    { "vpermil2ps",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11503    { "vpermil2ps",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11504  },
11505  {
11506    /* VEX_W_0F3A49_P_2 */
11507    { "vpermil2pd",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11508    { "vpermil2pd",	{ XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
11509  },
11510  {
11511    /* VEX_W_0F3A4A_P_2 */
11512    { "vblendvps",	{ XM, Vex, EXx, XMVexI4 } },
11513  },
11514  {
11515    /* VEX_W_0F3A4B_P_2 */
11516    { "vblendvpd",	{ XM, Vex, EXx, XMVexI4 } },
11517  },
11518  {
11519    /* VEX_W_0F3A4C_P_2 */
11520    { "vpblendvb",	{ XM, Vex, EXx, XMVexI4 } },
11521  },
11522  {
11523    /* VEX_W_0F3A60_P_2 */
11524    { "vpcmpestrm",	{ XM, EXx, Ib } },
11525  },
11526  {
11527    /* VEX_W_0F3A61_P_2 */
11528    { "vpcmpestri",	{ XM, EXx, Ib } },
11529  },
11530  {
11531    /* VEX_W_0F3A62_P_2 */
11532    { "vpcmpistrm",	{ XM, EXx, Ib } },
11533  },
11534  {
11535    /* VEX_W_0F3A63_P_2 */
11536    { "vpcmpistri",	{ XM, EXx, Ib } },
11537  },
11538  {
11539    /* VEX_W_0F3ADF_P_2 */
11540    { "vaeskeygenassist", { XM, EXx, Ib } },
11541  },
11542#define NEED_VEX_W_TABLE
11543#include "i386-dis-evex.h"
11544#undef NEED_VEX_W_TABLE
11545};
11546
11547static const struct dis386 mod_table[][2] = {
11548  {
11549    /* MOD_8D */
11550    { "leaS",		{ Gv, M } },
11551  },
11552  {
11553    /* MOD_C6_REG_7 */
11554    { Bad_Opcode },
11555    { RM_TABLE (RM_C6_REG_7) },
11556  },
11557  {
11558    /* MOD_C7_REG_7 */
11559    { Bad_Opcode },
11560    { RM_TABLE (RM_C7_REG_7) },
11561  },
11562  {
11563    /* MOD_FF_REG_3 */
11564    { "Jcall{T|}", { indirEp } },
11565  },
11566  {
11567    /* MOD_FF_REG_5 */
11568    { "Jjmp{T|}", { indirEp } },
11569  },
11570  {
11571    /* MOD_0F01_REG_0 */
11572    { X86_64_TABLE (X86_64_0F01_REG_0) },
11573    { RM_TABLE (RM_0F01_REG_0) },
11574  },
11575  {
11576    /* MOD_0F01_REG_1 */
11577    { X86_64_TABLE (X86_64_0F01_REG_1) },
11578    { RM_TABLE (RM_0F01_REG_1) },
11579  },
11580  {
11581    /* MOD_0F01_REG_2 */
11582    { X86_64_TABLE (X86_64_0F01_REG_2) },
11583    { RM_TABLE (RM_0F01_REG_2) },
11584  },
11585  {
11586    /* MOD_0F01_REG_3 */
11587    { X86_64_TABLE (X86_64_0F01_REG_3) },
11588    { RM_TABLE (RM_0F01_REG_3) },
11589  },
11590  {
11591    /* MOD_0F01_REG_7 */
11592    { "invlpg",		{ Mb } },
11593    { RM_TABLE (RM_0F01_REG_7) },
11594  },
11595  {
11596    /* MOD_0F12_PREFIX_0 */
11597    { "movlps",		{ XM, EXq } },
11598    { "movhlps",	{ XM, EXq } },
11599  },
11600  {
11601    /* MOD_0F13 */
11602    { "movlpX",		{ EXq, XM } },
11603  },
11604  {
11605    /* MOD_0F16_PREFIX_0 */
11606    { "movhps",		{ XM, EXq } },
11607    { "movlhps",	{ XM, EXq } },
11608  },
11609  {
11610    /* MOD_0F17 */
11611    { "movhpX",		{ EXq, XM } },
11612  },
11613  {
11614    /* MOD_0F18_REG_0 */
11615    { "prefetchnta",	{ Mb } },
11616  },
11617  {
11618    /* MOD_0F18_REG_1 */
11619    { "prefetcht0",	{ Mb } },
11620  },
11621  {
11622    /* MOD_0F18_REG_2 */
11623    { "prefetcht1",	{ Mb } },
11624  },
11625  {
11626    /* MOD_0F18_REG_3 */
11627    { "prefetcht2",	{ Mb } },
11628  },
11629  {
11630    /* MOD_0F18_REG_4 */
11631    { "nop/reserved",	{ Mb } },
11632  },
11633  {
11634    /* MOD_0F18_REG_5 */
11635    { "nop/reserved",	{ Mb } },
11636  },
11637  {
11638    /* MOD_0F18_REG_6 */
11639    { "nop/reserved",	{ Mb } },
11640  },
11641  {
11642    /* MOD_0F18_REG_7 */
11643    { "nop/reserved",	{ Mb } },
11644  },
11645  {
11646    /* MOD_0F1A_PREFIX_0 */
11647    { "bndldx",		{ Gbnd, Ev_bnd } },
11648    { "nopQ",		{ Ev } },
11649  },
11650  {
11651    /* MOD_0F1B_PREFIX_0 */
11652    { "bndstx",		{ Ev_bnd, Gbnd } },
11653    { "nopQ",		{ Ev } },
11654  },
11655  {
11656    /* MOD_0F1B_PREFIX_1 */
11657    { "bndmk",		{ Gbnd, Ev_bnd } },
11658    { "nopQ",		{ Ev } },
11659  },
11660  {
11661    /* MOD_0F24 */
11662    { Bad_Opcode },
11663    { "movL",		{ Rd, Td } },
11664  },
11665  {
11666    /* MOD_0F26 */
11667    { Bad_Opcode },
11668    { "movL",		{ Td, Rd } },
11669  },
11670  {
11671    /* MOD_0F2B_PREFIX_0 */
11672    {"movntps",		{ Mx, XM } },
11673  },
11674  {
11675    /* MOD_0F2B_PREFIX_1 */
11676    {"movntss",		{ Md, XM } },
11677  },
11678  {
11679    /* MOD_0F2B_PREFIX_2 */
11680    {"movntpd",		{ Mx, XM } },
11681  },
11682  {
11683    /* MOD_0F2B_PREFIX_3 */
11684    {"movntsd",		{ Mq, XM } },
11685  },
11686  {
11687    /* MOD_0F51 */
11688    { Bad_Opcode },
11689    { "movmskpX",	{ Gdq, XS } },
11690  },
11691  {
11692    /* MOD_0F71_REG_2 */
11693    { Bad_Opcode },
11694    { "psrlw",		{ MS, Ib } },
11695  },
11696  {
11697    /* MOD_0F71_REG_4 */
11698    { Bad_Opcode },
11699    { "psraw",		{ MS, Ib } },
11700  },
11701  {
11702    /* MOD_0F71_REG_6 */
11703    { Bad_Opcode },
11704    { "psllw",		{ MS, Ib } },
11705  },
11706  {
11707    /* MOD_0F72_REG_2 */
11708    { Bad_Opcode },
11709    { "psrld",		{ MS, Ib } },
11710  },
11711  {
11712    /* MOD_0F72_REG_4 */
11713    { Bad_Opcode },
11714    { "psrad",		{ MS, Ib } },
11715  },
11716  {
11717    /* MOD_0F72_REG_6 */
11718    { Bad_Opcode },
11719    { "pslld",		{ MS, Ib } },
11720  },
11721  {
11722    /* MOD_0F73_REG_2 */
11723    { Bad_Opcode },
11724    { "psrlq",		{ MS, Ib } },
11725  },
11726  {
11727    /* MOD_0F73_REG_3 */
11728    { Bad_Opcode },
11729    { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11730  },
11731  {
11732    /* MOD_0F73_REG_6 */
11733    { Bad_Opcode },
11734    { "psllq",		{ MS, Ib } },
11735  },
11736  {
11737    /* MOD_0F73_REG_7 */
11738    { Bad_Opcode },
11739    { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11740  },
11741  {
11742    /* MOD_0FAE_REG_0 */
11743    { "fxsave",		{ FXSAVE } },
11744    { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11745  },
11746  {
11747    /* MOD_0FAE_REG_1 */
11748    { "fxrstor",	{ FXSAVE } },
11749    { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11750  },
11751  {
11752    /* MOD_0FAE_REG_2 */
11753    { "ldmxcsr",	{ Md } },
11754    { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11755  },
11756  {
11757    /* MOD_0FAE_REG_3 */
11758    { "stmxcsr",	{ Md } },
11759    { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11760  },
11761  {
11762    /* MOD_0FAE_REG_4 */
11763    { "xsave",		{ FXSAVE } },
11764  },
11765  {
11766    /* MOD_0FAE_REG_5 */
11767    { "xrstor",		{ FXSAVE } },
11768    { RM_TABLE (RM_0FAE_REG_5) },
11769  },
11770  {
11771    /* MOD_0FAE_REG_6 */
11772    { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11773    { RM_TABLE (RM_0FAE_REG_6) },
11774  },
11775  {
11776    /* MOD_0FAE_REG_7 */
11777    { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11778    { RM_TABLE (RM_0FAE_REG_7) },
11779  },
11780  {
11781    /* MOD_0FB2 */
11782    { "lssS",		{ Gv, Mp } },
11783  },
11784  {
11785    /* MOD_0FB4 */
11786    { "lfsS",		{ Gv, Mp } },
11787  },
11788  {
11789    /* MOD_0FB5 */
11790    { "lgsS",		{ Gv, Mp } },
11791  },
11792  {
11793    /* MOD_0FC7_REG_3 */
11794    { "xrstors",		{ FXSAVE } },
11795  },
11796  {
11797    /* MOD_0FC7_REG_4 */
11798    { "xsavec",		{ FXSAVE } },
11799  },
11800  {
11801    /* MOD_0FC7_REG_5 */
11802    { "xsaves",		{ FXSAVE } },
11803  },
11804  {
11805    /* MOD_0FC7_REG_6 */
11806    { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
11807    { "rdrand",		{ Ev } },
11808  },
11809  {
11810    /* MOD_0FC7_REG_7 */
11811    { "vmptrst",	{ Mq } },
11812    { "rdseed",		{ Ev } },
11813  },
11814  {
11815    /* MOD_0FD7 */
11816    { Bad_Opcode },
11817    { "pmovmskb",	{ Gdq, MS } },
11818  },
11819  {
11820    /* MOD_0FE7_PREFIX_2 */
11821    { "movntdq",	{ Mx, XM } },
11822  },
11823  {
11824    /* MOD_0FF0_PREFIX_3 */
11825    { "lddqu",		{ XM, M } },
11826  },
11827  {
11828    /* MOD_0F382A_PREFIX_2 */
11829    { "movntdqa",	{ XM, Mx } },
11830  },
11831  {
11832    /* MOD_62_32BIT */
11833    { "bound{S|}",	{ Gv, Ma } },
11834    { EVEX_TABLE (EVEX_0F) },
11835  },
11836  {
11837    /* MOD_C4_32BIT */
11838    { "lesS",		{ Gv, Mp } },
11839    { VEX_C4_TABLE (VEX_0F) },
11840  },
11841  {
11842    /* MOD_C5_32BIT */
11843    { "ldsS",		{ Gv, Mp } },
11844    { VEX_C5_TABLE (VEX_0F) },
11845  },
11846  {
11847    /* MOD_VEX_0F12_PREFIX_0 */
11848    { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11849    { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11850  },
11851  {
11852    /* MOD_VEX_0F13 */
11853    { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11854  },
11855  {
11856    /* MOD_VEX_0F16_PREFIX_0 */
11857    { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11858    { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11859  },
11860  {
11861    /* MOD_VEX_0F17 */
11862    { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11863  },
11864  {
11865    /* MOD_VEX_0F2B */
11866    { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11867  },
11868  {
11869    /* MOD_VEX_0F50 */
11870    { Bad_Opcode },
11871    { VEX_W_TABLE (VEX_W_0F50_M_0) },
11872  },
11873  {
11874    /* MOD_VEX_0F71_REG_2 */
11875    { Bad_Opcode },
11876    { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11877  },
11878  {
11879    /* MOD_VEX_0F71_REG_4 */
11880    { Bad_Opcode },
11881    { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11882  },
11883  {
11884    /* MOD_VEX_0F71_REG_6 */
11885    { Bad_Opcode },
11886    { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11887  },
11888  {
11889    /* MOD_VEX_0F72_REG_2 */
11890    { Bad_Opcode },
11891    { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
11892  },
11893  {
11894    /* MOD_VEX_0F72_REG_4 */
11895    { Bad_Opcode },
11896    { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
11897  },
11898  {
11899    /* MOD_VEX_0F72_REG_6 */
11900    { Bad_Opcode },
11901    { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
11902  },
11903  {
11904    /* MOD_VEX_0F73_REG_2 */
11905    { Bad_Opcode },
11906    { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
11907  },
11908  {
11909    /* MOD_VEX_0F73_REG_3 */
11910    { Bad_Opcode },
11911    { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
11912  },
11913  {
11914    /* MOD_VEX_0F73_REG_6 */
11915    { Bad_Opcode },
11916    { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
11917  },
11918  {
11919    /* MOD_VEX_0F73_REG_7 */
11920    { Bad_Opcode },
11921    { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
11922  },
11923  {
11924    /* MOD_VEX_0FAE_REG_2 */
11925    { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
11926  },
11927  {
11928    /* MOD_VEX_0FAE_REG_3 */
11929    { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
11930  },
11931  {
11932    /* MOD_VEX_0FD7_PREFIX_2 */
11933    { Bad_Opcode },
11934    { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
11935  },
11936  {
11937    /* MOD_VEX_0FE7_PREFIX_2 */
11938    { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
11939  },
11940  {
11941    /* MOD_VEX_0FF0_PREFIX_3 */
11942    { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
11943  },
11944  {
11945    /* MOD_VEX_0F381A_PREFIX_2 */
11946    { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
11947  },
11948  {
11949    /* MOD_VEX_0F382A_PREFIX_2 */
11950    { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
11951  },
11952  {
11953    /* MOD_VEX_0F382C_PREFIX_2 */
11954    { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
11955  },
11956  {
11957    /* MOD_VEX_0F382D_PREFIX_2 */
11958    { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
11959  },
11960  {
11961    /* MOD_VEX_0F382E_PREFIX_2 */
11962    { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
11963  },
11964  {
11965    /* MOD_VEX_0F382F_PREFIX_2 */
11966    { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
11967  },
11968  {
11969    /* MOD_VEX_0F385A_PREFIX_2 */
11970    { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
11971  },
11972  {
11973    /* MOD_VEX_0F388C_PREFIX_2 */
11974    { "vpmaskmov%LW",	{ XM, Vex, Mx } },
11975  },
11976  {
11977    /* MOD_VEX_0F388E_PREFIX_2 */
11978    { "vpmaskmov%LW",	{ Mx, Vex, XM } },
11979  },
11980#define NEED_MOD_TABLE
11981#include "i386-dis-evex.h"
11982#undef NEED_MOD_TABLE
11983};
11984
11985static const struct dis386 rm_table[][8] = {
11986  {
11987    /* RM_C6_REG_7 */
11988    { "xabort",		{ Skip_MODRM, Ib } },
11989  },
11990  {
11991    /* RM_C7_REG_7 */
11992    { "xbeginT",	{ Skip_MODRM, Jv } },
11993  },
11994  {
11995    /* RM_0F01_REG_0 */
11996    { Bad_Opcode },
11997    { "vmcall",		{ Skip_MODRM } },
11998    { "vmlaunch",	{ Skip_MODRM } },
11999    { "vmresume",	{ Skip_MODRM } },
12000    { "vmxoff",		{ Skip_MODRM } },
12001  },
12002  {
12003    /* RM_0F01_REG_1 */
12004    { "monitor",	{ { OP_Monitor, 0 } } },
12005    { "mwait",		{ { OP_Mwait, 0 } } },
12006    { "clac",		{ Skip_MODRM } },
12007    { "stac",		{ Skip_MODRM } },
12008    { Bad_Opcode },
12009    { Bad_Opcode },
12010    { Bad_Opcode },
12011    { "encls",		{ Skip_MODRM } },
12012  },
12013  {
12014    /* RM_0F01_REG_2 */
12015    { "xgetbv",		{ Skip_MODRM } },
12016    { "xsetbv",		{ Skip_MODRM } },
12017    { Bad_Opcode },
12018    { Bad_Opcode },
12019    { "vmfunc",		{ Skip_MODRM } },
12020    { "xend",		{ Skip_MODRM } },
12021    { "xtest",		{ Skip_MODRM } },
12022    { "enclu",		{ Skip_MODRM } },
12023  },
12024  {
12025    /* RM_0F01_REG_3 */
12026    { "vmrun",		{ Skip_MODRM } },
12027    { "vmmcall",	{ Skip_MODRM } },
12028    { "vmload",		{ Skip_MODRM } },
12029    { "vmsave",		{ Skip_MODRM } },
12030    { "stgi",		{ Skip_MODRM } },
12031    { "clgi",		{ Skip_MODRM } },
12032    { "skinit",		{ Skip_MODRM } },
12033    { "invlpga",	{ Skip_MODRM } },
12034  },
12035  {
12036    /* RM_0F01_REG_7 */
12037    { "swapgs",		{ Skip_MODRM } },
12038    { "rdtscp",		{ Skip_MODRM } },
12039  },
12040  {
12041    /* RM_0FAE_REG_5 */
12042    { "lfence",		{ Skip_MODRM } },
12043  },
12044  {
12045    /* RM_0FAE_REG_6 */
12046    { "mfence",		{ Skip_MODRM } },
12047  },
12048  {
12049    /* RM_0FAE_REG_7 */
12050    { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) },
12051  },
12052};
12053
12054#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12055
12056/* We use the high bit to indicate different name for the same
12057   prefix.  */
12058#define REP_PREFIX	(0xf3 | 0x100)
12059#define XACQUIRE_PREFIX	(0xf2 | 0x200)
12060#define XRELEASE_PREFIX	(0xf3 | 0x400)
12061#define BND_PREFIX	(0xf2 | 0x400)
12062
12063static int
12064ckprefix (void)
12065{
12066  int newrex, i, length;
12067  rex = 0;
12068  rex_ignored = 0;
12069  prefixes = 0;
12070  used_prefixes = 0;
12071  rex_used = 0;
12072  last_lock_prefix = -1;
12073  last_repz_prefix = -1;
12074  last_repnz_prefix = -1;
12075  last_data_prefix = -1;
12076  last_addr_prefix = -1;
12077  last_rex_prefix = -1;
12078  last_seg_prefix = -1;
12079  fwait_prefix = -1;
12080  active_seg_prefix = 0;
12081  for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12082    all_prefixes[i] = 0;
12083  i = 0;
12084  length = 0;
12085  /* The maximum instruction length is 15bytes.  */
12086  while (length < MAX_CODE_LENGTH - 1)
12087    {
12088      FETCH_DATA (the_info, codep + 1);
12089      newrex = 0;
12090      switch (*codep)
12091	{
12092	/* REX prefixes family.  */
12093	case 0x40:
12094	case 0x41:
12095	case 0x42:
12096	case 0x43:
12097	case 0x44:
12098	case 0x45:
12099	case 0x46:
12100	case 0x47:
12101	case 0x48:
12102	case 0x49:
12103	case 0x4a:
12104	case 0x4b:
12105	case 0x4c:
12106	case 0x4d:
12107	case 0x4e:
12108	case 0x4f:
12109	  if (address_mode == mode_64bit)
12110	    newrex = *codep;
12111	  else
12112	    return 1;
12113	  last_rex_prefix = i;
12114	  break;
12115	case 0xf3:
12116	  prefixes |= PREFIX_REPZ;
12117	  last_repz_prefix = i;
12118	  break;
12119	case 0xf2:
12120	  prefixes |= PREFIX_REPNZ;
12121	  last_repnz_prefix = i;
12122	  break;
12123	case 0xf0:
12124	  prefixes |= PREFIX_LOCK;
12125	  last_lock_prefix = i;
12126	  break;
12127	case 0x2e:
12128	  prefixes |= PREFIX_CS;
12129	  last_seg_prefix = i;
12130	  active_seg_prefix = PREFIX_CS;
12131	  break;
12132	case 0x36:
12133	  prefixes |= PREFIX_SS;
12134	  last_seg_prefix = i;
12135	  active_seg_prefix = PREFIX_SS;
12136	  break;
12137	case 0x3e:
12138	  prefixes |= PREFIX_DS;
12139	  last_seg_prefix = i;
12140	  active_seg_prefix = PREFIX_DS;
12141	  break;
12142	case 0x26:
12143	  prefixes |= PREFIX_ES;
12144	  last_seg_prefix = i;
12145	  active_seg_prefix = PREFIX_ES;
12146	  break;
12147	case 0x64:
12148	  prefixes |= PREFIX_FS;
12149	  last_seg_prefix = i;
12150	  active_seg_prefix = PREFIX_FS;
12151	  break;
12152	case 0x65:
12153	  prefixes |= PREFIX_GS;
12154	  last_seg_prefix = i;
12155	  active_seg_prefix = PREFIX_GS;
12156	  break;
12157	case 0x66:
12158	  prefixes |= PREFIX_DATA;
12159	  last_data_prefix = i;
12160	  break;
12161	case 0x67:
12162	  prefixes |= PREFIX_ADDR;
12163	  last_addr_prefix = i;
12164	  break;
12165	case FWAIT_OPCODE:
12166	  /* fwait is really an instruction.  If there are prefixes
12167	     before the fwait, they belong to the fwait, *not* to the
12168	     following instruction.  */
12169	  fwait_prefix = i;
12170	  if (prefixes || rex)
12171	    {
12172	      prefixes |= PREFIX_FWAIT;
12173	      codep++;
12174	      /* This ensures that the previous REX prefixes are noticed
12175		 as unused prefixes, as in the return case below.  */
12176	      rex_used = rex;
12177	      return 1;
12178	    }
12179	  prefixes = PREFIX_FWAIT;
12180	  break;
12181	default:
12182	  return 1;
12183	}
12184      /* Rex is ignored when followed by another prefix.  */
12185      if (rex)
12186	{
12187	  rex_used = rex;
12188	  return 1;
12189	}
12190      if (*codep != FWAIT_OPCODE)
12191	all_prefixes[i++] = *codep;
12192      rex = newrex;
12193      codep++;
12194      length++;
12195    }
12196  return 0;
12197}
12198
12199/* Return the name of the prefix byte PREF, or NULL if PREF is not a
12200   prefix byte.  */
12201
12202static const char *
12203prefix_name (int pref, int sizeflag)
12204{
12205  static const char *rexes [16] =
12206    {
12207      "rex",		/* 0x40 */
12208      "rex.B",		/* 0x41 */
12209      "rex.X",		/* 0x42 */
12210      "rex.XB",		/* 0x43 */
12211      "rex.R",		/* 0x44 */
12212      "rex.RB",		/* 0x45 */
12213      "rex.RX",		/* 0x46 */
12214      "rex.RXB",	/* 0x47 */
12215      "rex.W",		/* 0x48 */
12216      "rex.WB",		/* 0x49 */
12217      "rex.WX",		/* 0x4a */
12218      "rex.WXB",	/* 0x4b */
12219      "rex.WR",		/* 0x4c */
12220      "rex.WRB",	/* 0x4d */
12221      "rex.WRX",	/* 0x4e */
12222      "rex.WRXB",	/* 0x4f */
12223    };
12224
12225  switch (pref)
12226    {
12227    /* REX prefixes family.  */
12228    case 0x40:
12229    case 0x41:
12230    case 0x42:
12231    case 0x43:
12232    case 0x44:
12233    case 0x45:
12234    case 0x46:
12235    case 0x47:
12236    case 0x48:
12237    case 0x49:
12238    case 0x4a:
12239    case 0x4b:
12240    case 0x4c:
12241    case 0x4d:
12242    case 0x4e:
12243    case 0x4f:
12244      return rexes [pref - 0x40];
12245    case 0xf3:
12246      return "repz";
12247    case 0xf2:
12248      return "repnz";
12249    case 0xf0:
12250      return "lock";
12251    case 0x2e:
12252      return "cs";
12253    case 0x36:
12254      return "ss";
12255    case 0x3e:
12256      return "ds";
12257    case 0x26:
12258      return "es";
12259    case 0x64:
12260      return "fs";
12261    case 0x65:
12262      return "gs";
12263    case 0x66:
12264      return (sizeflag & DFLAG) ? "data16" : "data32";
12265    case 0x67:
12266      if (address_mode == mode_64bit)
12267	return (sizeflag & AFLAG) ? "addr32" : "addr64";
12268      else
12269	return (sizeflag & AFLAG) ? "addr16" : "addr32";
12270    case FWAIT_OPCODE:
12271      return "fwait";
12272    case REP_PREFIX:
12273      return "rep";
12274    case XACQUIRE_PREFIX:
12275      return "xacquire";
12276    case XRELEASE_PREFIX:
12277      return "xrelease";
12278    case BND_PREFIX:
12279      return "bnd";
12280    default:
12281      return NULL;
12282    }
12283}
12284
12285static char op_out[MAX_OPERANDS][100];
12286static int op_ad, op_index[MAX_OPERANDS];
12287static int two_source_ops;
12288static bfd_vma op_address[MAX_OPERANDS];
12289static bfd_vma op_riprel[MAX_OPERANDS];
12290static bfd_vma start_pc;
12291
12292/*
12293 *   On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12294 *   (see topic "Redundant prefixes" in the "Differences from 8086"
12295 *   section of the "Virtual 8086 Mode" chapter.)
12296 * 'pc' should be the address of this instruction, it will
12297 *   be used to print the target address if this is a relative jump or call
12298 * The function returns the length of this instruction in bytes.
12299 */
12300
12301static char intel_syntax;
12302static char intel_mnemonic = !SYSV386_COMPAT;
12303static char open_char;
12304static char close_char;
12305static char separator_char;
12306static char scale_char;
12307
12308/* Here for backwards compatibility.  When gdb stops using
12309   print_insn_i386_att and print_insn_i386_intel these functions can
12310   disappear, and print_insn_i386 be merged into print_insn.  */
12311int
12312print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12313{
12314  intel_syntax = 0;
12315
12316  return print_insn (pc, info);
12317}
12318
12319int
12320print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12321{
12322  intel_syntax = 1;
12323
12324  return print_insn (pc, info);
12325}
12326
12327int
12328print_insn_i386 (bfd_vma pc, disassemble_info *info)
12329{
12330  intel_syntax = -1;
12331
12332  return print_insn (pc, info);
12333}
12334
12335void
12336print_i386_disassembler_options (FILE *stream)
12337{
12338  fprintf (stream, _("\n\
12339The following i386/x86-64 specific disassembler options are supported for use\n\
12340with the -M switch (multiple options should be separated by commas):\n"));
12341
12342  fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
12343  fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
12344  fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
12345  fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
12346  fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
12347  fprintf (stream, _("  att-mnemonic\n"
12348		     "              Display instruction in AT&T mnemonic\n"));
12349  fprintf (stream, _("  intel-mnemonic\n"
12350		     "              Display instruction in Intel mnemonic\n"));
12351  fprintf (stream, _("  addr64      Assume 64bit address size\n"));
12352  fprintf (stream, _("  addr32      Assume 32bit address size\n"));
12353  fprintf (stream, _("  addr16      Assume 16bit address size\n"));
12354  fprintf (stream, _("  data32      Assume 32bit data size\n"));
12355  fprintf (stream, _("  data16      Assume 16bit data size\n"));
12356  fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
12357}
12358
12359/* Bad opcode.  */
12360static const struct dis386 bad_opcode = { "(bad)", { XX } };
12361
12362/* Get a pointer to struct dis386 with a valid name.  */
12363
12364static const struct dis386 *
12365get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12366{
12367  int vindex, vex_table_index;
12368
12369  if (dp->name != NULL)
12370    return dp;
12371
12372  switch (dp->op[0].bytemode)
12373    {
12374    case USE_REG_TABLE:
12375      dp = &reg_table[dp->op[1].bytemode][modrm.reg];
12376      break;
12377
12378    case USE_MOD_TABLE:
12379      vindex = modrm.mod == 0x3 ? 1 : 0;
12380      dp = &mod_table[dp->op[1].bytemode][vindex];
12381      break;
12382
12383    case USE_RM_TABLE:
12384      dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12385      break;
12386
12387    case USE_PREFIX_TABLE:
12388      if (need_vex)
12389	{
12390	  /* The prefix in VEX is implicit.  */
12391	  switch (vex.prefix)
12392	    {
12393	    case 0:
12394	      vindex = 0;
12395	      break;
12396	    case REPE_PREFIX_OPCODE:
12397	      vindex = 1;
12398	      break;
12399	    case DATA_PREFIX_OPCODE:
12400	      vindex = 2;
12401	      break;
12402	    case REPNE_PREFIX_OPCODE:
12403	      vindex = 3;
12404	      break;
12405	    default:
12406	      abort ();
12407	      break;
12408	    }
12409	}
12410      else
12411	{
12412	  int last_prefix = -1;
12413	  int prefix = 0;
12414	  vindex = 0;
12415	  /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12416	     When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12417	     last one wins.  */
12418	  if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12419	    {
12420	      if (last_repz_prefix > last_repnz_prefix)
12421		{
12422		  vindex = 1;
12423		  prefix = PREFIX_REPZ;
12424		  last_prefix = last_repz_prefix;
12425		}
12426	      else
12427		{
12428		  vindex = 3;
12429		  prefix = PREFIX_REPNZ;
12430		  last_prefix = last_repnz_prefix;
12431		}
12432
12433	      /* Ignore the invalid index if it isn't mandatory.  */
12434	      if (!mandatory_prefix
12435		  && (prefix_table[dp->op[1].bytemode][vindex].name
12436		      == NULL)
12437		  && (prefix_table[dp->op[1].bytemode][vindex].op[0].bytemode
12438		      == 0))
12439		vindex = 0;
12440	    }
12441
12442	  if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12443	    {
12444	      vindex = 2;
12445	      prefix = PREFIX_DATA;
12446	      last_prefix = last_data_prefix;
12447	    }
12448
12449	  if (vindex != 0)
12450	    {
12451	      used_prefixes |= prefix;
12452	      all_prefixes[last_prefix] = 0;
12453	    }
12454	}
12455      dp = &prefix_table[dp->op[1].bytemode][vindex];
12456      break;
12457
12458    case USE_X86_64_TABLE:
12459      vindex = address_mode == mode_64bit ? 1 : 0;
12460      dp = &x86_64_table[dp->op[1].bytemode][vindex];
12461      break;
12462
12463    case USE_3BYTE_TABLE:
12464      FETCH_DATA (info, codep + 2);
12465      vindex = *codep++;
12466      dp = &three_byte_table[dp->op[1].bytemode][vindex];
12467      end_codep = codep;
12468      modrm.mod = (*codep >> 6) & 3;
12469      modrm.reg = (*codep >> 3) & 7;
12470      modrm.rm = *codep & 7;
12471      break;
12472
12473    case USE_VEX_LEN_TABLE:
12474      if (!need_vex)
12475	abort ();
12476
12477      switch (vex.length)
12478	{
12479	case 128:
12480	  vindex = 0;
12481	  break;
12482	case 256:
12483	  vindex = 1;
12484	  break;
12485	default:
12486	  abort ();
12487	  break;
12488	}
12489
12490      dp = &vex_len_table[dp->op[1].bytemode][vindex];
12491      break;
12492
12493    case USE_XOP_8F_TABLE:
12494      FETCH_DATA (info, codep + 3);
12495      /* All bits in the REX prefix are ignored.  */
12496      rex_ignored = rex;
12497      rex = ~(*codep >> 5) & 0x7;
12498
12499      /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
12500      switch ((*codep & 0x1f))
12501	{
12502	default:
12503	  dp = &bad_opcode;
12504	  return dp;
12505	case 0x8:
12506	  vex_table_index = XOP_08;
12507	  break;
12508	case 0x9:
12509	  vex_table_index = XOP_09;
12510	  break;
12511	case 0xa:
12512	  vex_table_index = XOP_0A;
12513	  break;
12514	}
12515      codep++;
12516      vex.w = *codep & 0x80;
12517      if (vex.w && address_mode == mode_64bit)
12518	rex |= REX_W;
12519
12520      vex.register_specifier = (~(*codep >> 3)) & 0xf;
12521      if (address_mode != mode_64bit
12522	  && vex.register_specifier > 0x7)
12523	{
12524	  dp = &bad_opcode;
12525	  return dp;
12526	}
12527
12528      vex.length = (*codep & 0x4) ? 256 : 128;
12529      switch ((*codep & 0x3))
12530	{
12531	case 0:
12532	  vex.prefix = 0;
12533	  break;
12534	case 1:
12535	  vex.prefix = DATA_PREFIX_OPCODE;
12536	  break;
12537	case 2:
12538	  vex.prefix = REPE_PREFIX_OPCODE;
12539	  break;
12540	case 3:
12541	  vex.prefix = REPNE_PREFIX_OPCODE;
12542	  break;
12543	}
12544      need_vex = 1;
12545      need_vex_reg = 1;
12546      codep++;
12547      vindex = *codep++;
12548      dp = &xop_table[vex_table_index][vindex];
12549
12550      end_codep = codep;
12551      FETCH_DATA (info, codep + 1);
12552      modrm.mod = (*codep >> 6) & 3;
12553      modrm.reg = (*codep >> 3) & 7;
12554      modrm.rm = *codep & 7;
12555      break;
12556
12557    case USE_VEX_C4_TABLE:
12558      /* VEX prefix.  */
12559      FETCH_DATA (info, codep + 3);
12560      /* All bits in the REX prefix are ignored.  */
12561      rex_ignored = rex;
12562      rex = ~(*codep >> 5) & 0x7;
12563      switch ((*codep & 0x1f))
12564	{
12565	default:
12566	  dp = &bad_opcode;
12567	  return dp;
12568	case 0x1:
12569	  vex_table_index = VEX_0F;
12570	  break;
12571	case 0x2:
12572	  vex_table_index = VEX_0F38;
12573	  break;
12574	case 0x3:
12575	  vex_table_index = VEX_0F3A;
12576	  break;
12577	}
12578      codep++;
12579      vex.w = *codep & 0x80;
12580      if (vex.w && address_mode == mode_64bit)
12581	rex |= REX_W;
12582
12583      vex.register_specifier = (~(*codep >> 3)) & 0xf;
12584      if (address_mode != mode_64bit
12585	  && vex.register_specifier > 0x7)
12586	{
12587	  dp = &bad_opcode;
12588	  return dp;
12589	}
12590
12591      vex.length = (*codep & 0x4) ? 256 : 128;
12592      switch ((*codep & 0x3))
12593	{
12594	case 0:
12595	  vex.prefix = 0;
12596	  break;
12597	case 1:
12598	  vex.prefix = DATA_PREFIX_OPCODE;
12599	  break;
12600	case 2:
12601	  vex.prefix = REPE_PREFIX_OPCODE;
12602	  break;
12603	case 3:
12604	  vex.prefix = REPNE_PREFIX_OPCODE;
12605	  break;
12606	}
12607      need_vex = 1;
12608      need_vex_reg = 1;
12609      codep++;
12610      vindex = *codep++;
12611      dp = &vex_table[vex_table_index][vindex];
12612      end_codep = codep;
12613      /* There is no MODRM byte for VEX [82|77].  */
12614      if (vindex != 0x77 && vindex != 0x82)
12615	{
12616	  FETCH_DATA (info, codep + 1);
12617	  modrm.mod = (*codep >> 6) & 3;
12618	  modrm.reg = (*codep >> 3) & 7;
12619	  modrm.rm = *codep & 7;
12620	}
12621      break;
12622
12623    case USE_VEX_C5_TABLE:
12624      /* VEX prefix.  */
12625      FETCH_DATA (info, codep + 2);
12626      /* All bits in the REX prefix are ignored.  */
12627      rex_ignored = rex;
12628      rex = (*codep & 0x80) ? 0 : REX_R;
12629
12630      vex.register_specifier = (~(*codep >> 3)) & 0xf;
12631      if (address_mode != mode_64bit
12632	  && vex.register_specifier > 0x7)
12633	{
12634	  dp = &bad_opcode;
12635	  return dp;
12636	}
12637
12638      vex.w = 0;
12639
12640      vex.length = (*codep & 0x4) ? 256 : 128;
12641      switch ((*codep & 0x3))
12642	{
12643	case 0:
12644	  vex.prefix = 0;
12645	  break;
12646	case 1:
12647	  vex.prefix = DATA_PREFIX_OPCODE;
12648	  break;
12649	case 2:
12650	  vex.prefix = REPE_PREFIX_OPCODE;
12651	  break;
12652	case 3:
12653	  vex.prefix = REPNE_PREFIX_OPCODE;
12654	  break;
12655	}
12656      need_vex = 1;
12657      need_vex_reg = 1;
12658      codep++;
12659      vindex = *codep++;
12660      dp = &vex_table[dp->op[1].bytemode][vindex];
12661      end_codep = codep;
12662      /* There is no MODRM byte for VEX [82|77].  */
12663      if (vindex != 0x77 && vindex != 0x82)
12664	{
12665	  FETCH_DATA (info, codep + 1);
12666	  modrm.mod = (*codep >> 6) & 3;
12667	  modrm.reg = (*codep >> 3) & 7;
12668	  modrm.rm = *codep & 7;
12669	}
12670      break;
12671
12672    case USE_VEX_W_TABLE:
12673      if (!need_vex)
12674	abort ();
12675
12676      dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12677      break;
12678
12679    case USE_EVEX_TABLE:
12680      two_source_ops = 0;
12681      /* EVEX prefix.  */
12682      vex.evex = 1;
12683      FETCH_DATA (info, codep + 4);
12684      /* All bits in the REX prefix are ignored.  */
12685      rex_ignored = rex;
12686      /* The first byte after 0x62.  */
12687      rex = ~(*codep >> 5) & 0x7;
12688      vex.r = *codep & 0x10;
12689      switch ((*codep & 0xf))
12690	{
12691	default:
12692	  return &bad_opcode;
12693	case 0x1:
12694	  vex_table_index = EVEX_0F;
12695	  break;
12696	case 0x2:
12697	  vex_table_index = EVEX_0F38;
12698	  break;
12699	case 0x3:
12700	  vex_table_index = EVEX_0F3A;
12701	  break;
12702	}
12703
12704      /* The second byte after 0x62.  */
12705      codep++;
12706      vex.w = *codep & 0x80;
12707      if (vex.w && address_mode == mode_64bit)
12708	rex |= REX_W;
12709
12710      vex.register_specifier = (~(*codep >> 3)) & 0xf;
12711      if (address_mode != mode_64bit)
12712	{
12713	  /* In 16/32-bit mode silently ignore following bits.  */
12714	  rex &= ~REX_B;
12715	  vex.r = 1;
12716	  vex.v = 1;
12717	  vex.register_specifier &= 0x7;
12718	}
12719
12720      /* The U bit.  */
12721      if (!(*codep & 0x4))
12722	return &bad_opcode;
12723
12724      switch ((*codep & 0x3))
12725	{
12726	case 0:
12727	  vex.prefix = 0;
12728	  break;
12729	case 1:
12730	  vex.prefix = DATA_PREFIX_OPCODE;
12731	  break;
12732	case 2:
12733	  vex.prefix = REPE_PREFIX_OPCODE;
12734	  break;
12735	case 3:
12736	  vex.prefix = REPNE_PREFIX_OPCODE;
12737	  break;
12738	}
12739
12740      /* The third byte after 0x62.  */
12741      codep++;
12742
12743      /* Remember the static rounding bits.  */
12744      vex.ll = (*codep >> 5) & 3;
12745      vex.b = (*codep & 0x10) != 0;
12746
12747      vex.v = *codep & 0x8;
12748      vex.mask_register_specifier = *codep & 0x7;
12749      vex.zeroing = *codep & 0x80;
12750
12751      need_vex = 1;
12752      need_vex_reg = 1;
12753      codep++;
12754      vindex = *codep++;
12755      dp = &evex_table[vex_table_index][vindex];
12756      end_codep = codep;
12757      FETCH_DATA (info, codep + 1);
12758      modrm.mod = (*codep >> 6) & 3;
12759      modrm.reg = (*codep >> 3) & 7;
12760      modrm.rm = *codep & 7;
12761
12762      /* Set vector length.  */
12763      if (modrm.mod == 3 && vex.b)
12764	vex.length = 512;
12765      else
12766	{
12767	  switch (vex.ll)
12768	    {
12769	    case 0x0:
12770	      vex.length = 128;
12771	      break;
12772	    case 0x1:
12773	      vex.length = 256;
12774	      break;
12775	    case 0x2:
12776	      vex.length = 512;
12777	      break;
12778	    default:
12779	      return &bad_opcode;
12780	    }
12781	}
12782      break;
12783
12784    case 0:
12785      dp = &bad_opcode;
12786      break;
12787
12788    default:
12789      abort ();
12790    }
12791
12792  if (dp->name != NULL)
12793    return dp;
12794  else
12795    return get_valid_dis386 (dp, info);
12796}
12797
12798static void
12799get_sib (disassemble_info *info, int sizeflag)
12800{
12801  /* If modrm.mod == 3, operand must be register.  */
12802  if (need_modrm
12803      && ((sizeflag & AFLAG) || address_mode == mode_64bit)
12804      && modrm.mod != 3
12805      && modrm.rm == 4)
12806    {
12807      FETCH_DATA (info, codep + 2);
12808      sib.index = (codep [1] >> 3) & 7;
12809      sib.scale = (codep [1] >> 6) & 3;
12810      sib.base = codep [1] & 7;
12811    }
12812}
12813
12814static int
12815print_insn (bfd_vma pc, disassemble_info *info)
12816{
12817  const struct dis386 *dp;
12818  int i;
12819  char *op_txt[MAX_OPERANDS];
12820  int needcomma;
12821  int sizeflag, orig_sizeflag;
12822  const char *p;
12823  struct dis_private priv;
12824  int prefix_length;
12825
12826  priv.orig_sizeflag = AFLAG | DFLAG;
12827  if ((info->mach & bfd_mach_i386_i386) != 0)
12828    address_mode = mode_32bit;
12829  else if (info->mach == bfd_mach_i386_i8086)
12830    {
12831      address_mode = mode_16bit;
12832      priv.orig_sizeflag = 0;
12833    }
12834  else
12835    address_mode = mode_64bit;
12836
12837  if (intel_syntax == (char) -1)
12838    intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
12839
12840  for (p = info->disassembler_options; p != NULL; )
12841    {
12842      if (CONST_STRNEQ (p, "x86-64"))
12843	{
12844	  address_mode = mode_64bit;
12845	  priv.orig_sizeflag = AFLAG | DFLAG;
12846	}
12847      else if (CONST_STRNEQ (p, "i386"))
12848	{
12849	  address_mode = mode_32bit;
12850	  priv.orig_sizeflag = AFLAG | DFLAG;
12851	}
12852      else if (CONST_STRNEQ (p, "i8086"))
12853	{
12854	  address_mode = mode_16bit;
12855	  priv.orig_sizeflag = 0;
12856	}
12857      else if (CONST_STRNEQ (p, "intel"))
12858	{
12859	  intel_syntax = 1;
12860	  if (CONST_STRNEQ (p + 5, "-mnemonic"))
12861	    intel_mnemonic = 1;
12862	}
12863      else if (CONST_STRNEQ (p, "att"))
12864	{
12865	  intel_syntax = 0;
12866	  if (CONST_STRNEQ (p + 3, "-mnemonic"))
12867	    intel_mnemonic = 0;
12868	}
12869      else if (CONST_STRNEQ (p, "addr"))
12870	{
12871	  if (address_mode == mode_64bit)
12872	    {
12873	      if (p[4] == '3' && p[5] == '2')
12874		priv.orig_sizeflag &= ~AFLAG;
12875	      else if (p[4] == '6' && p[5] == '4')
12876		priv.orig_sizeflag |= AFLAG;
12877	    }
12878	  else
12879	    {
12880	      if (p[4] == '1' && p[5] == '6')
12881		priv.orig_sizeflag &= ~AFLAG;
12882	      else if (p[4] == '3' && p[5] == '2')
12883		priv.orig_sizeflag |= AFLAG;
12884	    }
12885	}
12886      else if (CONST_STRNEQ (p, "data"))
12887	{
12888	  if (p[4] == '1' && p[5] == '6')
12889	    priv.orig_sizeflag &= ~DFLAG;
12890	  else if (p[4] == '3' && p[5] == '2')
12891	    priv.orig_sizeflag |= DFLAG;
12892	}
12893      else if (CONST_STRNEQ (p, "suffix"))
12894	priv.orig_sizeflag |= SUFFIX_ALWAYS;
12895
12896      p = strchr (p, ',');
12897      if (p != NULL)
12898	p++;
12899    }
12900
12901  if (intel_syntax)
12902    {
12903      names64 = intel_names64;
12904      names32 = intel_names32;
12905      names16 = intel_names16;
12906      names8 = intel_names8;
12907      names8rex = intel_names8rex;
12908      names_seg = intel_names_seg;
12909      names_mm = intel_names_mm;
12910      names_bnd = intel_names_bnd;
12911      names_xmm = intel_names_xmm;
12912      names_ymm = intel_names_ymm;
12913      names_zmm = intel_names_zmm;
12914      index64 = intel_index64;
12915      index32 = intel_index32;
12916      names_mask = intel_names_mask;
12917      index16 = intel_index16;
12918      open_char = '[';
12919      close_char = ']';
12920      separator_char = '+';
12921      scale_char = '*';
12922    }
12923  else
12924    {
12925      names64 = att_names64;
12926      names32 = att_names32;
12927      names16 = att_names16;
12928      names8 = att_names8;
12929      names8rex = att_names8rex;
12930      names_seg = att_names_seg;
12931      names_mm = att_names_mm;
12932      names_bnd = att_names_bnd;
12933      names_xmm = att_names_xmm;
12934      names_ymm = att_names_ymm;
12935      names_zmm = att_names_zmm;
12936      index64 = att_index64;
12937      index32 = att_index32;
12938      names_mask = att_names_mask;
12939      index16 = att_index16;
12940      open_char = '(';
12941      close_char =  ')';
12942      separator_char = ',';
12943      scale_char = ',';
12944    }
12945
12946  /* The output looks better if we put 7 bytes on a line, since that
12947     puts most long word instructions on a single line.  Use 8 bytes
12948     for Intel L1OM.  */
12949  if ((info->mach & bfd_mach_l1om) != 0)
12950    info->bytes_per_line = 8;
12951  else
12952    info->bytes_per_line = 7;
12953
12954  info->private_data = &priv;
12955  priv.max_fetched = priv.the_buffer;
12956  priv.insn_start = pc;
12957
12958  obuf[0] = 0;
12959  for (i = 0; i < MAX_OPERANDS; ++i)
12960    {
12961      op_out[i][0] = 0;
12962      op_index[i] = -1;
12963    }
12964
12965  the_info = info;
12966  start_pc = pc;
12967  start_codep = priv.the_buffer;
12968  codep = priv.the_buffer;
12969
12970  if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12971    {
12972      const char *name;
12973
12974      /* Getting here means we tried for data but didn't get it.  That
12975	 means we have an incomplete instruction of some sort.  Just
12976	 print the first byte as a prefix or a .byte pseudo-op.  */
12977      if (codep > priv.the_buffer)
12978	{
12979	  name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12980	  if (name != NULL)
12981	    (*info->fprintf_func) (info->stream, "%s", name);
12982	  else
12983	    {
12984	      /* Just print the first byte as a .byte instruction.  */
12985	      (*info->fprintf_func) (info->stream, ".byte 0x%x",
12986				     (unsigned int) priv.the_buffer[0]);
12987	    }
12988
12989	  return 1;
12990	}
12991
12992      return -1;
12993    }
12994
12995  obufp = obuf;
12996  sizeflag = priv.orig_sizeflag;
12997
12998  if (!ckprefix () || rex_used)
12999    {
13000      /* Too many prefixes or unused REX prefixes.  */
13001      for (i = 0;
13002	   i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13003	   i++)
13004	(*info->fprintf_func) (info->stream, "%s%s",
13005			       i == 0 ? "" : " ",
13006			       prefix_name (all_prefixes[i], sizeflag));
13007      return i;
13008    }
13009
13010  insn_codep = codep;
13011
13012  FETCH_DATA (info, codep + 1);
13013  two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13014
13015  if (((prefixes & PREFIX_FWAIT)
13016       && ((*codep < 0xd8) || (*codep > 0xdf))))
13017    {
13018      /* Handle prefixes before fwait.  */
13019      for (i = 0; i < fwait_prefix && all_prefixes[i];
13020	   i++)
13021	(*info->fprintf_func) (info->stream, "%s ",
13022			       prefix_name (all_prefixes[i], sizeflag));
13023      (*info->fprintf_func) (info->stream, "fwait");
13024      return i + 1;
13025    }
13026
13027  if (*codep == 0x0f)
13028    {
13029      unsigned char threebyte;
13030      FETCH_DATA (info, codep + 2);
13031      threebyte = *++codep;
13032      dp = &dis386_twobyte[threebyte];
13033      need_modrm = twobyte_has_modrm[*codep];
13034      mandatory_prefix = twobyte_has_mandatory_prefix[*codep];
13035      codep++;
13036    }
13037  else
13038    {
13039      dp = &dis386[*codep];
13040      need_modrm = onebyte_has_modrm[*codep];
13041      mandatory_prefix = 0;
13042      codep++;
13043    }
13044
13045  /* Save sizeflag for printing the extra prefixes later before updating
13046     it for mnemonic and operand processing.  The prefix names depend
13047     only on the address mode.  */
13048  orig_sizeflag = sizeflag;
13049  if (prefixes & PREFIX_ADDR)
13050    sizeflag ^= AFLAG;
13051  if ((prefixes & PREFIX_DATA))
13052    sizeflag ^= DFLAG;
13053
13054  end_codep = codep;
13055  if (need_modrm)
13056    {
13057      FETCH_DATA (info, codep + 1);
13058      modrm.mod = (*codep >> 6) & 3;
13059      modrm.reg = (*codep >> 3) & 7;
13060      modrm.rm = *codep & 7;
13061    }
13062
13063  need_vex = 0;
13064  need_vex_reg = 0;
13065  vex_w_done = 0;
13066  vex.evex = 0;
13067
13068  if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13069    {
13070      get_sib (info, sizeflag);
13071      dofloat (sizeflag);
13072    }
13073  else
13074    {
13075      dp = get_valid_dis386 (dp, info);
13076      if (dp != NULL && putop (dp->name, sizeflag) == 0)
13077	{
13078	  get_sib (info, sizeflag);
13079	  for (i = 0; i < MAX_OPERANDS; ++i)
13080	    {
13081	      obufp = op_out[i];
13082	      op_ad = MAX_OPERANDS - 1 - i;
13083	      if (dp->op[i].rtn)
13084		(*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13085	      /* For EVEX instruction after the last operand masking
13086		 should be printed.  */
13087	      if (i == 0 && vex.evex)
13088		{
13089		  /* Don't print {%k0}.  */
13090		  if (vex.mask_register_specifier)
13091		    {
13092		      oappend ("{");
13093		      oappend (names_mask[vex.mask_register_specifier]);
13094		      oappend ("}");
13095		    }
13096		  if (vex.zeroing)
13097		    oappend ("{z}");
13098		}
13099	    }
13100	}
13101    }
13102
13103  /* Check if the REX prefix is used.  */
13104  if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13105    all_prefixes[last_rex_prefix] = 0;
13106
13107  /* Check if the SEG prefix is used.  */
13108  if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13109		   | PREFIX_FS | PREFIX_GS)) != 0
13110      && (used_prefixes & active_seg_prefix) != 0)
13111    all_prefixes[last_seg_prefix] = 0;
13112
13113  /* Check if the ADDR prefix is used.  */
13114  if ((prefixes & PREFIX_ADDR) != 0
13115      && (used_prefixes & PREFIX_ADDR) != 0)
13116    all_prefixes[last_addr_prefix] = 0;
13117
13118  /* Check if the DATA prefix is used.  */
13119  if ((prefixes & PREFIX_DATA) != 0
13120      && (used_prefixes & PREFIX_DATA) != 0)
13121    all_prefixes[last_data_prefix] = 0;
13122
13123  /* Print the extra prefixes.  */
13124  prefix_length = 0;
13125  for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13126    if (all_prefixes[i])
13127      {
13128	const char *name;
13129	name = prefix_name (all_prefixes[i], orig_sizeflag);
13130	if (name == NULL)
13131	  abort ();
13132	prefix_length += strlen (name) + 1;
13133	(*info->fprintf_func) (info->stream, "%s ", name);
13134      }
13135
13136  /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13137     unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
13138     used by putop and MMX/SSE operand and may be overriden by the
13139     PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13140     separately.  */
13141  if (mandatory_prefix
13142      && dp != &bad_opcode
13143      && (((prefixes
13144	    & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13145	   && (used_prefixes
13146	       & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13147	  || ((((prefixes
13148		 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13149		== PREFIX_DATA)
13150	       && (used_prefixes & PREFIX_DATA) == 0))))
13151    {
13152      (*info->fprintf_func) (info->stream, "(bad)");
13153      return end_codep - priv.the_buffer;
13154    }
13155
13156  /* Check maximum code length.  */
13157  if ((codep - start_codep) > MAX_CODE_LENGTH)
13158    {
13159      (*info->fprintf_func) (info->stream, "(bad)");
13160      return MAX_CODE_LENGTH;
13161    }
13162
13163  obufp = mnemonicendp;
13164  for (i = strlen (obuf) + prefix_length; i < 6; i++)
13165    oappend (" ");
13166  oappend (" ");
13167  (*info->fprintf_func) (info->stream, "%s", obuf);
13168
13169  /* The enter and bound instructions are printed with operands in the same
13170     order as the intel book; everything else is printed in reverse order.  */
13171  if (intel_syntax || two_source_ops)
13172    {
13173      bfd_vma riprel;
13174
13175      for (i = 0; i < MAX_OPERANDS; ++i)
13176	op_txt[i] = op_out[i];
13177
13178      for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13179	{
13180	  op_ad = op_index[i];
13181	  op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13182	  op_index[MAX_OPERANDS - 1 - i] = op_ad;
13183	  riprel = op_riprel[i];
13184	  op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13185	  op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13186	}
13187    }
13188  else
13189    {
13190      for (i = 0; i < MAX_OPERANDS; ++i)
13191	op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13192    }
13193
13194  needcomma = 0;
13195  for (i = 0; i < MAX_OPERANDS; ++i)
13196    if (*op_txt[i])
13197      {
13198	if (needcomma)
13199	  (*info->fprintf_func) (info->stream, ",");
13200	if (op_index[i] != -1 && !op_riprel[i])
13201	  (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13202	else
13203	  (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13204	needcomma = 1;
13205      }
13206
13207  for (i = 0; i < MAX_OPERANDS; i++)
13208    if (op_index[i] != -1 && op_riprel[i])
13209      {
13210	(*info->fprintf_func) (info->stream, "        # ");
13211	(*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
13212						+ op_address[op_index[i]]), info);
13213	break;
13214      }
13215  return codep - priv.the_buffer;
13216}
13217
13218static const char *float_mem[] = {
13219  /* d8 */
13220  "fadd{s|}",
13221  "fmul{s|}",
13222  "fcom{s|}",
13223  "fcomp{s|}",
13224  "fsub{s|}",
13225  "fsubr{s|}",
13226  "fdiv{s|}",
13227  "fdivr{s|}",
13228  /* d9 */
13229  "fld{s|}",
13230  "(bad)",
13231  "fst{s|}",
13232  "fstp{s|}",
13233  "fldenvIC",
13234  "fldcw",
13235  "fNstenvIC",
13236  "fNstcw",
13237  /* da */
13238  "fiadd{l|}",
13239  "fimul{l|}",
13240  "ficom{l|}",
13241  "ficomp{l|}",
13242  "fisub{l|}",
13243  "fisubr{l|}",
13244  "fidiv{l|}",
13245  "fidivr{l|}",
13246  /* db */
13247  "fild{l|}",
13248  "fisttp{l|}",
13249  "fist{l|}",
13250  "fistp{l|}",
13251  "(bad)",
13252  "fld{t||t|}",
13253  "(bad)",
13254  "fstp{t||t|}",
13255  /* dc */
13256  "fadd{l|}",
13257  "fmul{l|}",
13258  "fcom{l|}",
13259  "fcomp{l|}",
13260  "fsub{l|}",
13261  "fsubr{l|}",
13262  "fdiv{l|}",
13263  "fdivr{l|}",
13264  /* dd */
13265  "fld{l|}",
13266  "fisttp{ll|}",
13267  "fst{l||}",
13268  "fstp{l|}",
13269  "frstorIC",
13270  "(bad)",
13271  "fNsaveIC",
13272  "fNstsw",
13273  /* de */
13274  "fiadd",
13275  "fimul",
13276  "ficom",
13277  "ficomp",
13278  "fisub",
13279  "fisubr",
13280  "fidiv",
13281  "fidivr",
13282  /* df */
13283  "fild",
13284  "fisttp",
13285  "fist",
13286  "fistp",
13287  "fbld",
13288  "fild{ll|}",
13289  "fbstp",
13290  "fistp{ll|}",
13291};
13292
13293static const unsigned char float_mem_mode[] = {
13294  /* d8 */
13295  d_mode,
13296  d_mode,
13297  d_mode,
13298  d_mode,
13299  d_mode,
13300  d_mode,
13301  d_mode,
13302  d_mode,
13303  /* d9 */
13304  d_mode,
13305  0,
13306  d_mode,
13307  d_mode,
13308  0,
13309  w_mode,
13310  0,
13311  w_mode,
13312  /* da */
13313  d_mode,
13314  d_mode,
13315  d_mode,
13316  d_mode,
13317  d_mode,
13318  d_mode,
13319  d_mode,
13320  d_mode,
13321  /* db */
13322  d_mode,
13323  d_mode,
13324  d_mode,
13325  d_mode,
13326  0,
13327  t_mode,
13328  0,
13329  t_mode,
13330  /* dc */
13331  q_mode,
13332  q_mode,
13333  q_mode,
13334  q_mode,
13335  q_mode,
13336  q_mode,
13337  q_mode,
13338  q_mode,
13339  /* dd */
13340  q_mode,
13341  q_mode,
13342  q_mode,
13343  q_mode,
13344  0,
13345  0,
13346  0,
13347  w_mode,
13348  /* de */
13349  w_mode,
13350  w_mode,
13351  w_mode,
13352  w_mode,
13353  w_mode,
13354  w_mode,
13355  w_mode,
13356  w_mode,
13357  /* df */
13358  w_mode,
13359  w_mode,
13360  w_mode,
13361  w_mode,
13362  t_mode,
13363  q_mode,
13364  t_mode,
13365  q_mode
13366};
13367
13368#define ST { OP_ST, 0 }
13369#define STi { OP_STi, 0 }
13370
13371#define FGRPd9_2 NULL, { { NULL, 0 } }
13372#define FGRPd9_4 NULL, { { NULL, 1 } }
13373#define FGRPd9_5 NULL, { { NULL, 2 } }
13374#define FGRPd9_6 NULL, { { NULL, 3 } }
13375#define FGRPd9_7 NULL, { { NULL, 4 } }
13376#define FGRPda_5 NULL, { { NULL, 5 } }
13377#define FGRPdb_4 NULL, { { NULL, 6 } }
13378#define FGRPde_3 NULL, { { NULL, 7 } }
13379#define FGRPdf_4 NULL, { { NULL, 8 } }
13380
13381static const struct dis386 float_reg[][8] = {
13382  /* d8 */
13383  {
13384    { "fadd",	{ ST, STi } },
13385    { "fmul",	{ ST, STi } },
13386    { "fcom",	{ STi } },
13387    { "fcomp",	{ STi } },
13388    { "fsub",	{ ST, STi } },
13389    { "fsubr",	{ ST, STi } },
13390    { "fdiv",	{ ST, STi } },
13391    { "fdivr",	{ ST, STi } },
13392  },
13393  /* d9 */
13394  {
13395    { "fld",	{ STi } },
13396    { "fxch",	{ STi } },
13397    { FGRPd9_2 },
13398    { Bad_Opcode },
13399    { FGRPd9_4 },
13400    { FGRPd9_5 },
13401    { FGRPd9_6 },
13402    { FGRPd9_7 },
13403  },
13404  /* da */
13405  {
13406    { "fcmovb",	{ ST, STi } },
13407    { "fcmove",	{ ST, STi } },
13408    { "fcmovbe",{ ST, STi } },
13409    { "fcmovu",	{ ST, STi } },
13410    { Bad_Opcode },
13411    { FGRPda_5 },
13412    { Bad_Opcode },
13413    { Bad_Opcode },
13414  },
13415  /* db */
13416  {
13417    { "fcmovnb",{ ST, STi } },
13418    { "fcmovne",{ ST, STi } },
13419    { "fcmovnbe",{ ST, STi } },
13420    { "fcmovnu",{ ST, STi } },
13421    { FGRPdb_4 },
13422    { "fucomi",	{ ST, STi } },
13423    { "fcomi",	{ ST, STi } },
13424    { Bad_Opcode },
13425  },
13426  /* dc */
13427  {
13428    { "fadd",	{ STi, ST } },
13429    { "fmul",	{ STi, ST } },
13430    { Bad_Opcode },
13431    { Bad_Opcode },
13432    { "fsub!M",	{ STi, ST } },
13433    { "fsubM",	{ STi, ST } },
13434    { "fdiv!M",	{ STi, ST } },
13435    { "fdivM",	{ STi, ST } },
13436  },
13437  /* dd */
13438  {
13439    { "ffree",	{ STi } },
13440    { Bad_Opcode },
13441    { "fst",	{ STi } },
13442    { "fstp",	{ STi } },
13443    { "fucom",	{ STi } },
13444    { "fucomp",	{ STi } },
13445    { Bad_Opcode },
13446    { Bad_Opcode },
13447  },
13448  /* de */
13449  {
13450    { "faddp",	{ STi, ST } },
13451    { "fmulp",	{ STi, ST } },
13452    { Bad_Opcode },
13453    { FGRPde_3 },
13454    { "fsub!Mp", { STi, ST } },
13455    { "fsubMp",	{ STi, ST } },
13456    { "fdiv!Mp", { STi, ST } },
13457    { "fdivMp",	{ STi, ST } },
13458  },
13459  /* df */
13460  {
13461    { "ffreep",	{ STi } },
13462    { Bad_Opcode },
13463    { Bad_Opcode },
13464    { Bad_Opcode },
13465    { FGRPdf_4 },
13466    { "fucomip", { ST, STi } },
13467    { "fcomip", { ST, STi } },
13468    { Bad_Opcode },
13469  },
13470};
13471
13472static char *fgrps[][8] = {
13473  /* d9_2  0 */
13474  {
13475    "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13476  },
13477
13478  /* d9_4  1 */
13479  {
13480    "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13481  },
13482
13483  /* d9_5  2 */
13484  {
13485    "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13486  },
13487
13488  /* d9_6  3 */
13489  {
13490    "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13491  },
13492
13493  /* d9_7  4 */
13494  {
13495    "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13496  },
13497
13498  /* da_5  5 */
13499  {
13500    "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13501  },
13502
13503  /* db_4  6 */
13504  {
13505    "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13506    "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13507  },
13508
13509  /* de_3  7 */
13510  {
13511    "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13512  },
13513
13514  /* df_4  8 */
13515  {
13516    "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13517  },
13518};
13519
13520static void
13521swap_operand (void)
13522{
13523  mnemonicendp[0] = '.';
13524  mnemonicendp[1] = 's';
13525  mnemonicendp += 2;
13526}
13527
13528static void
13529OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13530	       int sizeflag ATTRIBUTE_UNUSED)
13531{
13532  /* Skip mod/rm byte.  */
13533  MODRM_CHECK;
13534  codep++;
13535}
13536
13537static void
13538dofloat (int sizeflag)
13539{
13540  const struct dis386 *dp;
13541  unsigned char floatop;
13542
13543  floatop = codep[-1];
13544
13545  if (modrm.mod != 3)
13546    {
13547      int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13548
13549      putop (float_mem[fp_indx], sizeflag);
13550      obufp = op_out[0];
13551      op_ad = 2;
13552      OP_E (float_mem_mode[fp_indx], sizeflag);
13553      return;
13554    }
13555  /* Skip mod/rm byte.  */
13556  MODRM_CHECK;
13557  codep++;
13558
13559  dp = &float_reg[floatop - 0xd8][modrm.reg];
13560  if (dp->name == NULL)
13561    {
13562      putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13563
13564      /* Instruction fnstsw is only one with strange arg.  */
13565      if (floatop == 0xdf && codep[-1] == 0xe0)
13566	strcpy (op_out[0], names16[0]);
13567    }
13568  else
13569    {
13570      putop (dp->name, sizeflag);
13571
13572      obufp = op_out[0];
13573      op_ad = 2;
13574      if (dp->op[0].rtn)
13575	(*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13576
13577      obufp = op_out[1];
13578      op_ad = 1;
13579      if (dp->op[1].rtn)
13580	(*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13581    }
13582}
13583
13584/* Like oappend (below), but S is a string starting with '%'.
13585   In Intel syntax, the '%' is elided.  */
13586static void
13587oappend_maybe_intel (const char *s)
13588{
13589  oappend (s + intel_syntax);
13590}
13591
13592static void
13593OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13594{
13595  oappend_maybe_intel ("%st");
13596}
13597
13598static void
13599OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13600{
13601  sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13602  oappend_maybe_intel (scratchbuf);
13603}
13604
13605/* Capital letters in template are macros.  */
13606static int
13607putop (const char *in_template, int sizeflag)
13608{
13609  const char *p;
13610  int alt = 0;
13611  int cond = 1;
13612  unsigned int l = 0, len = 1;
13613  char last[4];
13614
13615#define SAVE_LAST(c)			\
13616  if (l < len && l < sizeof (last))	\
13617    last[l++] = c;			\
13618  else					\
13619    abort ();
13620
13621  for (p = in_template; *p; p++)
13622    {
13623      switch (*p)
13624	{
13625	default:
13626	  *obufp++ = *p;
13627	  break;
13628	case '%':
13629	  len++;
13630	  break;
13631	case '!':
13632	  cond = 0;
13633	  break;
13634	case '{':
13635	  alt = 0;
13636	  if (intel_syntax)
13637	    {
13638	      while (*++p != '|')
13639		if (*p == '}' || *p == '\0')
13640		  abort ();
13641	    }
13642	  /* Fall through.  */
13643	case 'I':
13644	  alt = 1;
13645	  continue;
13646	case '|':
13647	  while (*++p != '}')
13648	    {
13649	      if (*p == '\0')
13650		abort ();
13651	    }
13652	  break;
13653	case '}':
13654	  break;
13655	case 'A':
13656	  if (intel_syntax)
13657	    break;
13658	  if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13659	    *obufp++ = 'b';
13660	  break;
13661	case 'B':
13662	  if (l == 0 && len == 1)
13663	    {
13664case_B:
13665	      if (intel_syntax)
13666		break;
13667	      if (sizeflag & SUFFIX_ALWAYS)
13668		*obufp++ = 'b';
13669	    }
13670	  else
13671	    {
13672	      if (l != 1
13673		  || len != 2
13674		  || last[0] != 'L')
13675		{
13676		  SAVE_LAST (*p);
13677		  break;
13678		}
13679
13680	      if (address_mode == mode_64bit
13681		  && !(prefixes & PREFIX_ADDR))
13682		{
13683		  *obufp++ = 'a';
13684		  *obufp++ = 'b';
13685		  *obufp++ = 's';
13686		}
13687
13688	      goto case_B;
13689	    }
13690	  break;
13691	case 'C':
13692	  if (intel_syntax && !alt)
13693	    break;
13694	  if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13695	    {
13696	      if (sizeflag & DFLAG)
13697		*obufp++ = intel_syntax ? 'd' : 'l';
13698	      else
13699		*obufp++ = intel_syntax ? 'w' : 's';
13700	      used_prefixes |= (prefixes & PREFIX_DATA);
13701	    }
13702	  break;
13703	case 'D':
13704	  if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
13705	    break;
13706	  USED_REX (REX_W);
13707	  if (modrm.mod == 3)
13708	    {
13709	      if (rex & REX_W)
13710		*obufp++ = 'q';
13711	      else
13712		{
13713		  if (sizeflag & DFLAG)
13714		    *obufp++ = intel_syntax ? 'd' : 'l';
13715		  else
13716		    *obufp++ = 'w';
13717		  used_prefixes |= (prefixes & PREFIX_DATA);
13718		}
13719	    }
13720	  else
13721	    *obufp++ = 'w';
13722	  break;
13723	case 'E':		/* For jcxz/jecxz */
13724	  if (address_mode == mode_64bit)
13725	    {
13726	      if (sizeflag & AFLAG)
13727		*obufp++ = 'r';
13728	      else
13729		*obufp++ = 'e';
13730	    }
13731	  else
13732	    if (sizeflag & AFLAG)
13733	      *obufp++ = 'e';
13734	  used_prefixes |= (prefixes & PREFIX_ADDR);
13735	  break;
13736	case 'F':
13737	  if (intel_syntax)
13738	    break;
13739	  if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
13740	    {
13741	      if (sizeflag & AFLAG)
13742		*obufp++ = address_mode == mode_64bit ? 'q' : 'l';
13743	      else
13744		*obufp++ = address_mode == mode_64bit ? 'l' : 'w';
13745	      used_prefixes |= (prefixes & PREFIX_ADDR);
13746	    }
13747	  break;
13748	case 'G':
13749	  if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
13750	    break;
13751	  if ((rex & REX_W) || (sizeflag & DFLAG))
13752	    *obufp++ = 'l';
13753	  else
13754	    *obufp++ = 'w';
13755	  if (!(rex & REX_W))
13756	    used_prefixes |= (prefixes & PREFIX_DATA);
13757	  break;
13758	case 'H':
13759	  if (intel_syntax)
13760	    break;
13761	  if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
13762	      || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
13763	    {
13764	      used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
13765	      *obufp++ = ',';
13766	      *obufp++ = 'p';
13767	      if (prefixes & PREFIX_DS)
13768		*obufp++ = 't';
13769	      else
13770		*obufp++ = 'n';
13771	    }
13772	  break;
13773	case 'J':
13774	  if (intel_syntax)
13775	    break;
13776	  *obufp++ = 'l';
13777	  break;
13778	case 'K':
13779	  USED_REX (REX_W);
13780	  if (rex & REX_W)
13781	    *obufp++ = 'q';
13782	  else
13783	    *obufp++ = 'd';
13784	  break;
13785	case 'Z':
13786	  if (intel_syntax)
13787	    break;
13788	  if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
13789	    {
13790	      *obufp++ = 'q';
13791	      break;
13792	    }
13793	  /* Fall through.  */
13794	  goto case_L;
13795	case 'L':
13796	  if (l != 0 || len != 1)
13797	    {
13798	      SAVE_LAST (*p);
13799	      break;
13800	    }
13801case_L:
13802	  if (intel_syntax)
13803	    break;
13804	  if (sizeflag & SUFFIX_ALWAYS)
13805	    *obufp++ = 'l';
13806	  break;
13807	case 'M':
13808	  if (intel_mnemonic != cond)
13809	    *obufp++ = 'r';
13810	  break;
13811	case 'N':
13812	  if ((prefixes & PREFIX_FWAIT) == 0)
13813	    *obufp++ = 'n';
13814	  else
13815	    used_prefixes |= PREFIX_FWAIT;
13816	  break;
13817	case 'O':
13818	  USED_REX (REX_W);
13819	  if (rex & REX_W)
13820	    *obufp++ = 'o';
13821	  else if (intel_syntax && (sizeflag & DFLAG))
13822	    *obufp++ = 'q';
13823	  else
13824	    *obufp++ = 'd';
13825	  if (!(rex & REX_W))
13826	    used_prefixes |= (prefixes & PREFIX_DATA);
13827	  break;
13828	case 'T':
13829	  if (!intel_syntax
13830	      && address_mode == mode_64bit
13831	      && ((sizeflag & DFLAG) || (rex & REX_W)))
13832	    {
13833	      *obufp++ = 'q';
13834	      break;
13835	    }
13836	  /* Fall through.  */
13837	  goto case_P;
13838	case 'P':
13839	  if (l == 0 && len == 1)
13840	    {
13841case_P:
13842	      if (intel_syntax)
13843		{
13844		  if ((rex & REX_W) == 0
13845		      && (prefixes & PREFIX_DATA))
13846		    {
13847		      if ((sizeflag & DFLAG) == 0)
13848			*obufp++ = 'w';
13849		      used_prefixes |= (prefixes & PREFIX_DATA);
13850		    }
13851		  break;
13852		}
13853	      if ((prefixes & PREFIX_DATA)
13854		  || (rex & REX_W)
13855		  || (sizeflag & SUFFIX_ALWAYS))
13856		{
13857		  USED_REX (REX_W);
13858		  if (rex & REX_W)
13859		    *obufp++ = 'q';
13860		  else
13861		    {
13862		      if (sizeflag & DFLAG)
13863			*obufp++ = 'l';
13864		      else
13865			*obufp++ = 'w';
13866		      used_prefixes |= (prefixes & PREFIX_DATA);
13867		    }
13868		}
13869	    }
13870	  else
13871	    {
13872	      if (l != 1 || len != 2 || last[0] != 'L')
13873		{
13874		  SAVE_LAST (*p);
13875		  break;
13876		}
13877
13878	      if ((prefixes & PREFIX_DATA)
13879		  || (rex & REX_W)
13880		  || (sizeflag & SUFFIX_ALWAYS))
13881		{
13882		  USED_REX (REX_W);
13883		  if (rex & REX_W)
13884		    *obufp++ = 'q';
13885		  else
13886		    {
13887		      if (sizeflag & DFLAG)
13888			*obufp++ = intel_syntax ? 'd' : 'l';
13889		      else
13890			*obufp++ = 'w';
13891		      used_prefixes |= (prefixes & PREFIX_DATA);
13892		    }
13893		}
13894	    }
13895	  break;
13896	case 'U':
13897	  if (intel_syntax)
13898	    break;
13899	  if (address_mode == mode_64bit
13900	      && ((sizeflag & DFLAG) || (rex & REX_W)))
13901	    {
13902	      if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13903		*obufp++ = 'q';
13904	      break;
13905	    }
13906	  /* Fall through.  */
13907	  goto case_Q;
13908	case 'Q':
13909	  if (l == 0 && len == 1)
13910	    {
13911case_Q:
13912	      if (intel_syntax && !alt)
13913		break;
13914	      USED_REX (REX_W);
13915	      if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13916		{
13917		  if (rex & REX_W)
13918		    *obufp++ = 'q';
13919		  else
13920		    {
13921		      if (sizeflag & DFLAG)
13922			*obufp++ = intel_syntax ? 'd' : 'l';
13923		      else
13924			*obufp++ = 'w';
13925		      used_prefixes |= (prefixes & PREFIX_DATA);
13926		    }
13927		}
13928	    }
13929	  else
13930	    {
13931	      if (l != 1 || len != 2 || last[0] != 'L')
13932		{
13933		  SAVE_LAST (*p);
13934		  break;
13935		}
13936	      if (intel_syntax
13937		  || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13938		break;
13939	      if ((rex & REX_W))
13940		{
13941		  USED_REX (REX_W);
13942		  *obufp++ = 'q';
13943		}
13944	      else
13945		*obufp++ = 'l';
13946	    }
13947	  break;
13948	case 'R':
13949	  USED_REX (REX_W);
13950	  if (rex & REX_W)
13951	    *obufp++ = 'q';
13952	  else if (sizeflag & DFLAG)
13953	    {
13954	      if (intel_syntax)
13955		  *obufp++ = 'd';
13956	      else
13957		  *obufp++ = 'l';
13958	    }
13959	  else
13960	    *obufp++ = 'w';
13961	  if (intel_syntax && !p[1]
13962	      && ((rex & REX_W) || (sizeflag & DFLAG)))
13963	    *obufp++ = 'e';
13964	  if (!(rex & REX_W))
13965	    used_prefixes |= (prefixes & PREFIX_DATA);
13966	  break;
13967	case 'V':
13968	  if (l == 0 && len == 1)
13969	    {
13970	      if (intel_syntax)
13971		break;
13972	      if (address_mode == mode_64bit
13973		  && ((sizeflag & DFLAG) || (rex & REX_W)))
13974		{
13975		  if (sizeflag & SUFFIX_ALWAYS)
13976		    *obufp++ = 'q';
13977		  break;
13978		}
13979	    }
13980	  else
13981	    {
13982	      if (l != 1
13983		  || len != 2
13984		  || last[0] != 'L')
13985		{
13986		  SAVE_LAST (*p);
13987		  break;
13988		}
13989
13990	      if (rex & REX_W)
13991		{
13992		  *obufp++ = 'a';
13993		  *obufp++ = 'b';
13994		  *obufp++ = 's';
13995		}
13996	    }
13997	  /* Fall through.  */
13998	  goto case_S;
13999	case 'S':
14000	  if (l == 0 && len == 1)
14001	    {
14002case_S:
14003	      if (intel_syntax)
14004		break;
14005	      if (sizeflag & SUFFIX_ALWAYS)
14006		{
14007		  if (rex & REX_W)
14008		    *obufp++ = 'q';
14009		  else
14010		    {
14011		      if (sizeflag & DFLAG)
14012			*obufp++ = 'l';
14013		      else
14014			*obufp++ = 'w';
14015		      used_prefixes |= (prefixes & PREFIX_DATA);
14016		    }
14017		}
14018	    }
14019	  else
14020	    {
14021	      if (l != 1
14022		  || len != 2
14023		  || last[0] != 'L')
14024		{
14025		  SAVE_LAST (*p);
14026		  break;
14027		}
14028
14029	      if (address_mode == mode_64bit
14030		  && !(prefixes & PREFIX_ADDR))
14031		{
14032		  *obufp++ = 'a';
14033		  *obufp++ = 'b';
14034		  *obufp++ = 's';
14035		}
14036
14037	      goto case_S;
14038	    }
14039	  break;
14040	case 'X':
14041	  if (l != 0 || len != 1)
14042	    {
14043	      SAVE_LAST (*p);
14044	      break;
14045	    }
14046	  if (need_vex && vex.prefix)
14047	    {
14048	      if (vex.prefix == DATA_PREFIX_OPCODE)
14049		*obufp++ = 'd';
14050	      else
14051		*obufp++ = 's';
14052	    }
14053	  else
14054	    {
14055	      if (prefixes & PREFIX_DATA)
14056		*obufp++ = 'd';
14057	      else
14058		*obufp++ = 's';
14059	      used_prefixes |= (prefixes & PREFIX_DATA);
14060	    }
14061	  break;
14062	case 'Y':
14063	  if (l == 0 && len == 1)
14064	    {
14065	      if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14066		break;
14067	      if (rex & REX_W)
14068		{
14069		  USED_REX (REX_W);
14070		  *obufp++ = 'q';
14071		}
14072	      break;
14073	    }
14074	  else
14075	    {
14076	      if (l != 1 || len != 2 || last[0] != 'X')
14077		{
14078		  SAVE_LAST (*p);
14079		  break;
14080		}
14081	      if (!need_vex)
14082		abort ();
14083	      if (intel_syntax
14084		  || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14085		break;
14086	      switch (vex.length)
14087		{
14088		case 128:
14089		  *obufp++ = 'x';
14090		  break;
14091		case 256:
14092		  *obufp++ = 'y';
14093		  break;
14094		default:
14095		  abort ();
14096		}
14097	    }
14098	  break;
14099	case 'W':
14100	  if (l == 0 && len == 1)
14101	    {
14102	      /* operand size flag for cwtl, cbtw */
14103	      USED_REX (REX_W);
14104	      if (rex & REX_W)
14105		{
14106		  if (intel_syntax)
14107		    *obufp++ = 'd';
14108		  else
14109		    *obufp++ = 'l';
14110		}
14111	      else if (sizeflag & DFLAG)
14112		*obufp++ = 'w';
14113	      else
14114		*obufp++ = 'b';
14115	      if (!(rex & REX_W))
14116		used_prefixes |= (prefixes & PREFIX_DATA);
14117	    }
14118	  else
14119	    {
14120	      if (l != 1
14121		  || len != 2
14122		  || (last[0] != 'X'
14123		      && last[0] != 'L'))
14124		{
14125		  SAVE_LAST (*p);
14126		  break;
14127		}
14128	      if (!need_vex)
14129		abort ();
14130	      if (last[0] == 'X')
14131		*obufp++ = vex.w ? 'd': 's';
14132	      else
14133		*obufp++ = vex.w ? 'q': 'd';
14134	    }
14135	  break;
14136	}
14137      alt = 0;
14138    }
14139  *obufp = 0;
14140  mnemonicendp = obufp;
14141  return 0;
14142}
14143
14144static void
14145oappend (const char *s)
14146{
14147  obufp = stpcpy (obufp, s);
14148}
14149
14150static void
14151append_seg (void)
14152{
14153  /* Only print the active segment register.  */
14154  if (!active_seg_prefix)
14155    return;
14156
14157  used_prefixes |= active_seg_prefix;
14158  switch (active_seg_prefix)
14159    {
14160    case PREFIX_CS:
14161      oappend_maybe_intel ("%cs:");
14162      break;
14163    case PREFIX_DS:
14164      oappend_maybe_intel ("%ds:");
14165      break;
14166    case PREFIX_SS:
14167      oappend_maybe_intel ("%ss:");
14168      break;
14169    case PREFIX_ES:
14170      oappend_maybe_intel ("%es:");
14171      break;
14172    case PREFIX_FS:
14173      oappend_maybe_intel ("%fs:");
14174      break;
14175    case PREFIX_GS:
14176      oappend_maybe_intel ("%gs:");
14177      break;
14178    default:
14179      break;
14180    }
14181}
14182
14183static void
14184OP_indirE (int bytemode, int sizeflag)
14185{
14186  if (!intel_syntax)
14187    oappend ("*");
14188  OP_E (bytemode, sizeflag);
14189}
14190
14191static void
14192print_operand_value (char *buf, int hex, bfd_vma disp)
14193{
14194  if (address_mode == mode_64bit)
14195    {
14196      if (hex)
14197	{
14198	  char tmp[30];
14199	  int i;
14200	  buf[0] = '0';
14201	  buf[1] = 'x';
14202	  sprintf_vma (tmp, disp);
14203	  for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14204	  strcpy (buf + 2, tmp + i);
14205	}
14206      else
14207	{
14208	  bfd_signed_vma v = disp;
14209	  char tmp[30];
14210	  int i;
14211	  if (v < 0)
14212	    {
14213	      *(buf++) = '-';
14214	      v = -disp;
14215	      /* Check for possible overflow on 0x8000000000000000.  */
14216	      if (v < 0)
14217		{
14218		  strcpy (buf, "9223372036854775808");
14219		  return;
14220		}
14221	    }
14222	  if (!v)
14223	    {
14224	      strcpy (buf, "0");
14225	      return;
14226	    }
14227
14228	  i = 0;
14229	  tmp[29] = 0;
14230	  while (v)
14231	    {
14232	      tmp[28 - i] = (v % 10) + '0';
14233	      v /= 10;
14234	      i++;
14235	    }
14236	  strcpy (buf, tmp + 29 - i);
14237	}
14238    }
14239  else
14240    {
14241      if (hex)
14242	sprintf (buf, "0x%x", (unsigned int) disp);
14243      else
14244	sprintf (buf, "%d", (int) disp);
14245    }
14246}
14247
14248/* Put DISP in BUF as signed hex number.  */
14249
14250static void
14251print_displacement (char *buf, bfd_vma disp)
14252{
14253  bfd_signed_vma val = disp;
14254  char tmp[30];
14255  int i, j = 0;
14256
14257  if (val < 0)
14258    {
14259      buf[j++] = '-';
14260      val = -disp;
14261
14262      /* Check for possible overflow.  */
14263      if (val < 0)
14264	{
14265	  switch (address_mode)
14266	    {
14267	    case mode_64bit:
14268	      strcpy (buf + j, "0x8000000000000000");
14269	      break;
14270	    case mode_32bit:
14271	      strcpy (buf + j, "0x80000000");
14272	      break;
14273	    case mode_16bit:
14274	      strcpy (buf + j, "0x8000");
14275	      break;
14276	    }
14277	  return;
14278	}
14279    }
14280
14281  buf[j++] = '0';
14282  buf[j++] = 'x';
14283
14284  sprintf_vma (tmp, (bfd_vma) val);
14285  for (i = 0; tmp[i] == '0'; i++)
14286    continue;
14287  if (tmp[i] == '\0')
14288    i--;
14289  strcpy (buf + j, tmp + i);
14290}
14291
14292static void
14293intel_operand_size (int bytemode, int sizeflag)
14294{
14295  if (vex.evex
14296      && vex.b
14297      && (bytemode == x_mode
14298	  || bytemode == evex_half_bcst_xmmq_mode))
14299    {
14300      if (vex.w)
14301	oappend ("QWORD PTR ");
14302      else
14303	oappend ("DWORD PTR ");
14304      return;
14305    }
14306  switch (bytemode)
14307    {
14308    case b_mode:
14309    case b_swap_mode:
14310    case dqb_mode:
14311    case db_mode:
14312      oappend ("BYTE PTR ");
14313      break;
14314    case w_mode:
14315    case dw_mode:
14316    case dqw_mode:
14317    case dqw_swap_mode:
14318      oappend ("WORD PTR ");
14319      break;
14320    case stack_v_mode:
14321      if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14322	{
14323	  oappend ("QWORD PTR ");
14324	  break;
14325	}
14326      /* FALLTHRU */
14327    case v_mode:
14328    case v_swap_mode:
14329    case dq_mode:
14330      USED_REX (REX_W);
14331      if (rex & REX_W)
14332	oappend ("QWORD PTR ");
14333      else
14334	{
14335	  if ((sizeflag & DFLAG) || bytemode == dq_mode)
14336	    oappend ("DWORD PTR ");
14337	  else
14338	    oappend ("WORD PTR ");
14339	  used_prefixes |= (prefixes & PREFIX_DATA);
14340	}
14341      break;
14342    case z_mode:
14343      if ((rex & REX_W) || (sizeflag & DFLAG))
14344	*obufp++ = 'D';
14345      oappend ("WORD PTR ");
14346      if (!(rex & REX_W))
14347	used_prefixes |= (prefixes & PREFIX_DATA);
14348      break;
14349    case a_mode:
14350      if (sizeflag & DFLAG)
14351	oappend ("QWORD PTR ");
14352      else
14353	oappend ("DWORD PTR ");
14354      used_prefixes |= (prefixes & PREFIX_DATA);
14355      break;
14356    case d_mode:
14357    case d_scalar_mode:
14358    case d_scalar_swap_mode:
14359    case d_swap_mode:
14360    case dqd_mode:
14361      oappend ("DWORD PTR ");
14362      break;
14363    case q_mode:
14364    case q_scalar_mode:
14365    case q_scalar_swap_mode:
14366    case q_swap_mode:
14367      oappend ("QWORD PTR ");
14368      break;
14369    case m_mode:
14370      if (address_mode == mode_64bit)
14371	oappend ("QWORD PTR ");
14372      else
14373	oappend ("DWORD PTR ");
14374      break;
14375    case f_mode:
14376      if (sizeflag & DFLAG)
14377	oappend ("FWORD PTR ");
14378      else
14379	oappend ("DWORD PTR ");
14380      used_prefixes |= (prefixes & PREFIX_DATA);
14381      break;
14382    case t_mode:
14383      oappend ("TBYTE PTR ");
14384      break;
14385    case x_mode:
14386    case x_swap_mode:
14387    case evex_x_gscat_mode:
14388    case evex_x_nobcst_mode:
14389      if (need_vex)
14390	{
14391	  switch (vex.length)
14392	    {
14393	    case 128:
14394	      oappend ("XMMWORD PTR ");
14395	      break;
14396	    case 256:
14397	      oappend ("YMMWORD PTR ");
14398	      break;
14399	    case 512:
14400	      oappend ("ZMMWORD PTR ");
14401	      break;
14402	    default:
14403	      abort ();
14404	    }
14405	}
14406      else
14407	oappend ("XMMWORD PTR ");
14408      break;
14409    case xmm_mode:
14410      oappend ("XMMWORD PTR ");
14411      break;
14412    case ymm_mode:
14413      oappend ("YMMWORD PTR ");
14414      break;
14415    case xmmq_mode:
14416    case evex_half_bcst_xmmq_mode:
14417      if (!need_vex)
14418	abort ();
14419
14420      switch (vex.length)
14421	{
14422	case 128:
14423	  oappend ("QWORD PTR ");
14424	  break;
14425	case 256:
14426	  oappend ("XMMWORD PTR ");
14427	  break;
14428	case 512:
14429	  oappend ("YMMWORD PTR ");
14430	  break;
14431	default:
14432	  abort ();
14433	}
14434      break;
14435    case xmm_mb_mode:
14436      if (!need_vex)
14437	abort ();
14438
14439      switch (vex.length)
14440	{
14441	case 128:
14442	case 256:
14443	case 512:
14444	  oappend ("BYTE PTR ");
14445	  break;
14446	default:
14447	  abort ();
14448	}
14449      break;
14450    case xmm_mw_mode:
14451      if (!need_vex)
14452	abort ();
14453
14454      switch (vex.length)
14455	{
14456	case 128:
14457	case 256:
14458	case 512:
14459	  oappend ("WORD PTR ");
14460	  break;
14461	default:
14462	  abort ();
14463	}
14464      break;
14465    case xmm_md_mode:
14466      if (!need_vex)
14467	abort ();
14468
14469      switch (vex.length)
14470	{
14471	case 128:
14472	case 256:
14473	case 512:
14474	  oappend ("DWORD PTR ");
14475	  break;
14476	default:
14477	  abort ();
14478	}
14479      break;
14480    case xmm_mq_mode:
14481      if (!need_vex)
14482	abort ();
14483
14484      switch (vex.length)
14485	{
14486	case 128:
14487	case 256:
14488	case 512:
14489	  oappend ("QWORD PTR ");
14490	  break;
14491	default:
14492	  abort ();
14493	}
14494      break;
14495    case xmmdw_mode:
14496      if (!need_vex)
14497	abort ();
14498
14499      switch (vex.length)
14500	{
14501	case 128:
14502	  oappend ("WORD PTR ");
14503	  break;
14504	case 256:
14505	  oappend ("DWORD PTR ");
14506	  break;
14507	case 512:
14508	  oappend ("QWORD PTR ");
14509	  break;
14510	default:
14511	  abort ();
14512	}
14513      break;
14514    case xmmqd_mode:
14515      if (!need_vex)
14516	abort ();
14517
14518      switch (vex.length)
14519	{
14520	case 128:
14521	  oappend ("DWORD PTR ");
14522	  break;
14523	case 256:
14524	  oappend ("QWORD PTR ");
14525	  break;
14526	case 512:
14527	  oappend ("XMMWORD PTR ");
14528	  break;
14529	default:
14530	  abort ();
14531	}
14532      break;
14533    case ymmq_mode:
14534      if (!need_vex)
14535	abort ();
14536
14537      switch (vex.length)
14538	{
14539	case 128:
14540	  oappend ("QWORD PTR ");
14541	  break;
14542	case 256:
14543	  oappend ("YMMWORD PTR ");
14544	  break;
14545	case 512:
14546	  oappend ("ZMMWORD PTR ");
14547	  break;
14548	default:
14549	  abort ();
14550	}
14551      break;
14552    case ymmxmm_mode:
14553      if (!need_vex)
14554	abort ();
14555
14556      switch (vex.length)
14557	{
14558	case 128:
14559	case 256:
14560	  oappend ("XMMWORD PTR ");
14561	  break;
14562	default:
14563	  abort ();
14564	}
14565      break;
14566    case o_mode:
14567      oappend ("OWORD PTR ");
14568      break;
14569    case xmm_mdq_mode:
14570    case vex_w_dq_mode:
14571    case vex_scalar_w_dq_mode:
14572      if (!need_vex)
14573	abort ();
14574
14575      if (vex.w)
14576	oappend ("QWORD PTR ");
14577      else
14578	oappend ("DWORD PTR ");
14579      break;
14580    case vex_vsib_d_w_dq_mode:
14581    case vex_vsib_q_w_dq_mode:
14582      if (!need_vex)
14583	abort ();
14584
14585      if (!vex.evex)
14586	{
14587	  if (vex.w)
14588	    oappend ("QWORD PTR ");
14589	  else
14590	    oappend ("DWORD PTR ");
14591	}
14592      else
14593	{
14594	  switch (vex.length)
14595	    {
14596	    case 128:
14597	      oappend ("XMMWORD PTR ");
14598	      break;
14599	    case 256:
14600	      oappend ("YMMWORD PTR ");
14601	      break;
14602	    case 512:
14603	      oappend ("ZMMWORD PTR ");
14604	      break;
14605	    default:
14606	      abort ();
14607	    }
14608	}
14609      break;
14610    case vex_vsib_q_w_d_mode:
14611    case vex_vsib_d_w_d_mode:
14612      if (!need_vex || !vex.evex)
14613	abort ();
14614
14615      switch (vex.length)
14616	{
14617	case 128:
14618	  oappend ("QWORD PTR ");
14619	  break;
14620	case 256:
14621	  oappend ("XMMWORD PTR ");
14622	  break;
14623	case 512:
14624	  oappend ("YMMWORD PTR ");
14625	  break;
14626	default:
14627	  abort ();
14628	}
14629
14630      break;
14631    case mask_bd_mode:
14632      if (!need_vex || vex.length != 128)
14633	abort ();
14634      if (vex.w)
14635	oappend ("DWORD PTR ");
14636      else
14637	oappend ("BYTE PTR ");
14638      break;
14639    case mask_mode:
14640      if (!need_vex)
14641	abort ();
14642      if (vex.w)
14643	oappend ("QWORD PTR ");
14644      else
14645	oappend ("WORD PTR ");
14646      break;
14647    case v_bnd_mode:
14648    default:
14649      break;
14650    }
14651}
14652
14653static void
14654OP_E_register (int bytemode, int sizeflag)
14655{
14656  int reg = modrm.rm;
14657  const char **names;
14658
14659  USED_REX (REX_B);
14660  if ((rex & REX_B))
14661    reg += 8;
14662
14663  if ((sizeflag & SUFFIX_ALWAYS)
14664      && (bytemode == b_swap_mode
14665	  || bytemode == v_swap_mode
14666	  || bytemode == dqw_swap_mode))
14667    swap_operand ();
14668
14669  switch (bytemode)
14670    {
14671    case b_mode:
14672    case b_swap_mode:
14673      USED_REX (0);
14674      if (rex)
14675	names = names8rex;
14676      else
14677	names = names8;
14678      break;
14679    case w_mode:
14680      names = names16;
14681      break;
14682    case d_mode:
14683    case dw_mode:
14684    case db_mode:
14685      names = names32;
14686      break;
14687    case q_mode:
14688      names = names64;
14689      break;
14690    case m_mode:
14691    case v_bnd_mode:
14692      names = address_mode == mode_64bit ? names64 : names32;
14693      break;
14694    case bnd_mode:
14695      names = names_bnd;
14696      break;
14697    case stack_v_mode:
14698      if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14699	{
14700	  names = names64;
14701	  break;
14702	}
14703      bytemode = v_mode;
14704      /* FALLTHRU */
14705    case v_mode:
14706    case v_swap_mode:
14707    case dq_mode:
14708    case dqb_mode:
14709    case dqd_mode:
14710    case dqw_mode:
14711    case dqw_swap_mode:
14712      USED_REX (REX_W);
14713      if (rex & REX_W)
14714	names = names64;
14715      else
14716	{
14717	  if ((sizeflag & DFLAG)
14718	      || (bytemode != v_mode
14719		  && bytemode != v_swap_mode))
14720	    names = names32;
14721	  else
14722	    names = names16;
14723	  used_prefixes |= (prefixes & PREFIX_DATA);
14724	}
14725      break;
14726    case mask_bd_mode:
14727    case mask_mode:
14728      names = names_mask;
14729      break;
14730    case 0:
14731      return;
14732    default:
14733      oappend (INTERNAL_DISASSEMBLER_ERROR);
14734      return;
14735    }
14736  oappend (names[reg]);
14737}
14738
14739static void
14740OP_E_memory (int bytemode, int sizeflag)
14741{
14742  bfd_vma disp = 0;
14743  int add = (rex & REX_B) ? 8 : 0;
14744  int riprel = 0;
14745  int shift;
14746
14747  if (vex.evex)
14748    {
14749      /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0.  */
14750      if (vex.b
14751	  && bytemode != x_mode
14752	  && bytemode != xmmq_mode
14753	  && bytemode != evex_half_bcst_xmmq_mode)
14754	{
14755	  BadOp ();
14756	  return;
14757	}
14758      switch (bytemode)
14759	{
14760	case dqw_mode:
14761	case dw_mode:
14762	case dqw_swap_mode:
14763	  shift = 1;
14764	  break;
14765	case dqb_mode:
14766	case db_mode:
14767	  shift = 0;
14768	  break;
14769	case vex_vsib_d_w_dq_mode:
14770	case vex_vsib_d_w_d_mode:
14771	case vex_vsib_q_w_dq_mode:
14772	case vex_vsib_q_w_d_mode:
14773	case evex_x_gscat_mode:
14774	case xmm_mdq_mode:
14775	  shift = vex.w ? 3 : 2;
14776	  break;
14777	case x_mode:
14778	case evex_half_bcst_xmmq_mode:
14779	case xmmq_mode:
14780	  if (vex.b)
14781	    {
14782	      shift = vex.w ? 3 : 2;
14783	      break;
14784	    }
14785	  /* Fall through if vex.b == 0.  */
14786	case xmmqd_mode:
14787	case xmmdw_mode:
14788	case ymmq_mode:
14789	case evex_x_nobcst_mode:
14790	case x_swap_mode:
14791	  switch (vex.length)
14792	    {
14793	    case 128:
14794	      shift = 4;
14795	      break;
14796	    case 256:
14797	      shift = 5;
14798	      break;
14799	    case 512:
14800	      shift = 6;
14801	      break;
14802	    default:
14803	      abort ();
14804	    }
14805	  break;
14806	case ymm_mode:
14807	  shift = 5;
14808	  break;
14809	case xmm_mode:
14810	  shift = 4;
14811	  break;
14812	case xmm_mq_mode:
14813	case q_mode:
14814	case q_scalar_mode:
14815	case q_swap_mode:
14816	case q_scalar_swap_mode:
14817	  shift = 3;
14818	  break;
14819	case dqd_mode:
14820	case xmm_md_mode:
14821	case d_mode:
14822	case d_scalar_mode:
14823	case d_swap_mode:
14824	case d_scalar_swap_mode:
14825	  shift = 2;
14826	  break;
14827	case xmm_mw_mode:
14828	  shift = 1;
14829	  break;
14830	case xmm_mb_mode:
14831	  shift = 0;
14832	  break;
14833	default:
14834	  abort ();
14835	}
14836      /* Make necessary corrections to shift for modes that need it.
14837	 For these modes we currently have shift 4, 5 or 6 depending on
14838	 vex.length (it corresponds to xmmword, ymmword or zmmword
14839	 operand).  We might want to make it 3, 4 or 5 (e.g. for
14840	 xmmq_mode).  In case of broadcast enabled the corrections
14841	 aren't needed, as element size is always 32 or 64 bits.  */
14842      if (!vex.b
14843	  && (bytemode == xmmq_mode
14844	      || bytemode == evex_half_bcst_xmmq_mode))
14845	shift -= 1;
14846      else if (bytemode == xmmqd_mode)
14847	shift -= 2;
14848      else if (bytemode == xmmdw_mode)
14849	shift -= 3;
14850      else if (bytemode == ymmq_mode && vex.length == 128)
14851	shift -= 1;
14852    }
14853  else
14854    shift = 0;
14855
14856  USED_REX (REX_B);
14857  if (intel_syntax)
14858    intel_operand_size (bytemode, sizeflag);
14859  append_seg ();
14860
14861  if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14862    {
14863      /* 32/64 bit address mode */
14864      int havedisp;
14865      int havesib;
14866      int havebase;
14867      int haveindex;
14868      int needindex;
14869      int base, rbase;
14870      int vindex = 0;
14871      int scale = 0;
14872      int addr32flag = !((sizeflag & AFLAG)
14873			 || bytemode == v_bnd_mode
14874			 || bytemode == bnd_mode);
14875      const char **indexes64 = names64;
14876      const char **indexes32 = names32;
14877
14878      havesib = 0;
14879      havebase = 1;
14880      haveindex = 0;
14881      base = modrm.rm;
14882
14883      if (base == 4)
14884	{
14885	  havesib = 1;
14886	  vindex = sib.index;
14887	  USED_REX (REX_X);
14888	  if (rex & REX_X)
14889	    vindex += 8;
14890	  switch (bytemode)
14891	    {
14892	    case vex_vsib_d_w_dq_mode:
14893	    case vex_vsib_d_w_d_mode:
14894	    case vex_vsib_q_w_dq_mode:
14895	    case vex_vsib_q_w_d_mode:
14896	      if (!need_vex)
14897		abort ();
14898	      if (vex.evex)
14899		{
14900		  if (!vex.v)
14901		    vindex += 16;
14902		}
14903
14904	      haveindex = 1;
14905	      switch (vex.length)
14906		{
14907		case 128:
14908		  indexes64 = indexes32 = names_xmm;
14909		  break;
14910		case 256:
14911		  if (!vex.w
14912		      || bytemode == vex_vsib_q_w_dq_mode
14913		      || bytemode == vex_vsib_q_w_d_mode)
14914		    indexes64 = indexes32 = names_ymm;
14915		  else
14916		    indexes64 = indexes32 = names_xmm;
14917		  break;
14918		case 512:
14919		  if (!vex.w
14920		      || bytemode == vex_vsib_q_w_dq_mode
14921		      || bytemode == vex_vsib_q_w_d_mode)
14922		    indexes64 = indexes32 = names_zmm;
14923		  else
14924		    indexes64 = indexes32 = names_ymm;
14925		  break;
14926		default:
14927		  abort ();
14928		}
14929	      break;
14930	    default:
14931	      haveindex = vindex != 4;
14932	      break;
14933	    }
14934	  scale = sib.scale;
14935	  base = sib.base;
14936	  codep++;
14937	}
14938      rbase = base + add;
14939
14940      switch (modrm.mod)
14941	{
14942	case 0:
14943	  if (base == 5)
14944	    {
14945	      havebase = 0;
14946	      if (address_mode == mode_64bit && !havesib)
14947		riprel = 1;
14948	      disp = get32s ();
14949	    }
14950	  break;
14951	case 1:
14952	  FETCH_DATA (the_info, codep + 1);
14953	  disp = *codep++;
14954	  if ((disp & 0x80) != 0)
14955	    disp -= 0x100;
14956	  if (vex.evex && shift > 0)
14957	    disp <<= shift;
14958	  break;
14959	case 2:
14960	  disp = get32s ();
14961	  break;
14962	}
14963
14964      /* In 32bit mode, we need index register to tell [offset] from
14965	 [eiz*1 + offset].  */
14966      needindex = (havesib
14967		   && !havebase
14968		   && !haveindex
14969		   && address_mode == mode_32bit);
14970      havedisp = (havebase
14971		  || needindex
14972		  || (havesib && (haveindex || scale != 0)));
14973
14974      if (!intel_syntax)
14975	if (modrm.mod != 0 || base == 5)
14976	  {
14977	    if (havedisp || riprel)
14978	      print_displacement (scratchbuf, disp);
14979	    else
14980	      print_operand_value (scratchbuf, 1, disp);
14981	    oappend (scratchbuf);
14982	    if (riprel)
14983	      {
14984		set_op (disp, 1);
14985		oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
14986	      }
14987	  }
14988
14989      if ((havebase || haveindex || riprel)
14990	  && (bytemode != v_bnd_mode)
14991	  && (bytemode != bnd_mode))
14992	used_prefixes |= PREFIX_ADDR;
14993
14994      if (havedisp || (intel_syntax && riprel))
14995	{
14996	  *obufp++ = open_char;
14997	  if (intel_syntax && riprel)
14998	    {
14999	      set_op (disp, 1);
15000	      oappend (sizeflag & AFLAG ? "rip" : "eip");
15001	    }
15002	  *obufp = '\0';
15003	  if (havebase)
15004	    oappend (address_mode == mode_64bit && !addr32flag
15005		     ? names64[rbase] : names32[rbase]);
15006	  if (havesib)
15007	    {
15008	      /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
15009		 print index to tell base + index from base.  */
15010	      if (scale != 0
15011		  || needindex
15012		  || haveindex
15013		  || (havebase && base != ESP_REG_NUM))
15014		{
15015		  if (!intel_syntax || havebase)
15016		    {
15017		      *obufp++ = separator_char;
15018		      *obufp = '\0';
15019		    }
15020		  if (haveindex)
15021		    oappend (address_mode == mode_64bit && !addr32flag
15022			     ? indexes64[vindex] : indexes32[vindex]);
15023		  else
15024		    oappend (address_mode == mode_64bit && !addr32flag
15025			     ? index64 : index32);
15026
15027		  *obufp++ = scale_char;
15028		  *obufp = '\0';
15029		  sprintf (scratchbuf, "%d", 1 << scale);
15030		  oappend (scratchbuf);
15031		}
15032	    }
15033	  if (intel_syntax
15034	      && (disp || modrm.mod != 0 || base == 5))
15035	    {
15036	      if (!havedisp || (bfd_signed_vma) disp >= 0)
15037		{
15038		  *obufp++ = '+';
15039		  *obufp = '\0';
15040		}
15041	      else if (modrm.mod != 1 && disp != -disp)
15042		{
15043		  *obufp++ = '-';
15044		  *obufp = '\0';
15045		  disp = - (bfd_signed_vma) disp;
15046		}
15047
15048	      if (havedisp)
15049		print_displacement (scratchbuf, disp);
15050	      else
15051		print_operand_value (scratchbuf, 1, disp);
15052	      oappend (scratchbuf);
15053	    }
15054
15055	  *obufp++ = close_char;
15056	  *obufp = '\0';
15057	}
15058      else if (intel_syntax)
15059	{
15060	  if (modrm.mod != 0 || base == 5)
15061	    {
15062	      if (!active_seg_prefix)
15063		{
15064		  oappend (names_seg[ds_reg - es_reg]);
15065		  oappend (":");
15066		}
15067	      print_operand_value (scratchbuf, 1, disp);
15068	      oappend (scratchbuf);
15069	    }
15070	}
15071    }
15072  else
15073    {
15074      /* 16 bit address mode */
15075      used_prefixes |= prefixes & PREFIX_ADDR;
15076      switch (modrm.mod)
15077	{
15078	case 0:
15079	  if (modrm.rm == 6)
15080	    {
15081	      disp = get16 ();
15082	      if ((disp & 0x8000) != 0)
15083		disp -= 0x10000;
15084	    }
15085	  break;
15086	case 1:
15087	  FETCH_DATA (the_info, codep + 1);
15088	  disp = *codep++;
15089	  if ((disp & 0x80) != 0)
15090	    disp -= 0x100;
15091	  break;
15092	case 2:
15093	  disp = get16 ();
15094	  if ((disp & 0x8000) != 0)
15095	    disp -= 0x10000;
15096	  break;
15097	}
15098
15099      if (!intel_syntax)
15100	if (modrm.mod != 0 || modrm.rm == 6)
15101	  {
15102	    print_displacement (scratchbuf, disp);
15103	    oappend (scratchbuf);
15104	  }
15105
15106      if (modrm.mod != 0 || modrm.rm != 6)
15107	{
15108	  *obufp++ = open_char;
15109	  *obufp = '\0';
15110	  oappend (index16[modrm.rm]);
15111	  if (intel_syntax
15112	      && (disp || modrm.mod != 0 || modrm.rm == 6))
15113	    {
15114	      if ((bfd_signed_vma) disp >= 0)
15115		{
15116		  *obufp++ = '+';
15117		  *obufp = '\0';
15118		}
15119	      else if (modrm.mod != 1)
15120		{
15121		  *obufp++ = '-';
15122		  *obufp = '\0';
15123		  disp = - (bfd_signed_vma) disp;
15124		}
15125
15126	      print_displacement (scratchbuf, disp);
15127	      oappend (scratchbuf);
15128	    }
15129
15130	  *obufp++ = close_char;
15131	  *obufp = '\0';
15132	}
15133      else if (intel_syntax)
15134	{
15135	  if (!active_seg_prefix)
15136	    {
15137	      oappend (names_seg[ds_reg - es_reg]);
15138	      oappend (":");
15139	    }
15140	  print_operand_value (scratchbuf, 1, disp & 0xffff);
15141	  oappend (scratchbuf);
15142	}
15143    }
15144  if (vex.evex && vex.b
15145      && (bytemode == x_mode
15146	  || bytemode == xmmq_mode
15147	  || bytemode == evex_half_bcst_xmmq_mode))
15148    {
15149      if (vex.w
15150	  || bytemode == xmmq_mode
15151	  || bytemode == evex_half_bcst_xmmq_mode)
15152	{
15153	  switch (vex.length)
15154	    {
15155	    case 128:
15156	      oappend ("{1to2}");
15157	      break;
15158	    case 256:
15159	      oappend ("{1to4}");
15160	      break;
15161	    case 512:
15162	      oappend ("{1to8}");
15163	      break;
15164	    default:
15165	      abort ();
15166	    }
15167	}
15168      else
15169	{
15170	  switch (vex.length)
15171	    {
15172	    case 128:
15173	      oappend ("{1to4}");
15174	      break;
15175	    case 256:
15176	      oappend ("{1to8}");
15177	      break;
15178	    case 512:
15179	      oappend ("{1to16}");
15180	      break;
15181	    default:
15182	      abort ();
15183	    }
15184	}
15185    }
15186}
15187
15188static void
15189OP_E (int bytemode, int sizeflag)
15190{
15191  /* Skip mod/rm byte.  */
15192  MODRM_CHECK;
15193  codep++;
15194
15195  if (modrm.mod == 3)
15196    OP_E_register (bytemode, sizeflag);
15197  else
15198    OP_E_memory (bytemode, sizeflag);
15199}
15200
15201static void
15202OP_G (int bytemode, int sizeflag)
15203{
15204  int add = 0;
15205  USED_REX (REX_R);
15206  if (rex & REX_R)
15207    add += 8;
15208  switch (bytemode)
15209    {
15210    case b_mode:
15211      USED_REX (0);
15212      if (rex)
15213	oappend (names8rex[modrm.reg + add]);
15214      else
15215	oappend (names8[modrm.reg + add]);
15216      break;
15217    case w_mode:
15218      oappend (names16[modrm.reg + add]);
15219      break;
15220    case d_mode:
15221    case db_mode:
15222    case dw_mode:
15223      oappend (names32[modrm.reg + add]);
15224      break;
15225    case q_mode:
15226      oappend (names64[modrm.reg + add]);
15227      break;
15228    case bnd_mode:
15229      oappend (names_bnd[modrm.reg]);
15230      break;
15231    case v_mode:
15232    case dq_mode:
15233    case dqb_mode:
15234    case dqd_mode:
15235    case dqw_mode:
15236    case dqw_swap_mode:
15237      USED_REX (REX_W);
15238      if (rex & REX_W)
15239	oappend (names64[modrm.reg + add]);
15240      else
15241	{
15242	  if ((sizeflag & DFLAG) || bytemode != v_mode)
15243	    oappend (names32[modrm.reg + add]);
15244	  else
15245	    oappend (names16[modrm.reg + add]);
15246	  used_prefixes |= (prefixes & PREFIX_DATA);
15247	}
15248      break;
15249    case m_mode:
15250      if (address_mode == mode_64bit)
15251	oappend (names64[modrm.reg + add]);
15252      else
15253	oappend (names32[modrm.reg + add]);
15254      break;
15255    case mask_bd_mode:
15256    case mask_mode:
15257      oappend (names_mask[modrm.reg + add]);
15258      break;
15259    default:
15260      oappend (INTERNAL_DISASSEMBLER_ERROR);
15261      break;
15262    }
15263}
15264
15265static bfd_vma
15266get64 (void)
15267{
15268  bfd_vma x;
15269#ifdef BFD64
15270  unsigned int a;
15271  unsigned int b;
15272
15273  FETCH_DATA (the_info, codep + 8);
15274  a = *codep++ & 0xff;
15275  a |= (*codep++ & 0xff) << 8;
15276  a |= (*codep++ & 0xff) << 16;
15277  a |= (*codep++ & 0xff) << 24;
15278  b = *codep++ & 0xff;
15279  b |= (*codep++ & 0xff) << 8;
15280  b |= (*codep++ & 0xff) << 16;
15281  b |= (*codep++ & 0xff) << 24;
15282  x = a + ((bfd_vma) b << 32);
15283#else
15284  abort ();
15285  x = 0;
15286#endif
15287  return x;
15288}
15289
15290static bfd_signed_vma
15291get32 (void)
15292{
15293  bfd_signed_vma x = 0;
15294
15295  FETCH_DATA (the_info, codep + 4);
15296  x = *codep++ & (bfd_signed_vma) 0xff;
15297  x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15298  x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15299  x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15300  return x;
15301}
15302
15303static bfd_signed_vma
15304get32s (void)
15305{
15306  bfd_signed_vma x = 0;
15307
15308  FETCH_DATA (the_info, codep + 4);
15309  x = *codep++ & (bfd_signed_vma) 0xff;
15310  x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15311  x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15312  x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15313
15314  x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15315
15316  return x;
15317}
15318
15319static int
15320get16 (void)
15321{
15322  int x = 0;
15323
15324  FETCH_DATA (the_info, codep + 2);
15325  x = *codep++ & 0xff;
15326  x |= (*codep++ & 0xff) << 8;
15327  return x;
15328}
15329
15330static void
15331set_op (bfd_vma op, int riprel)
15332{
15333  op_index[op_ad] = op_ad;
15334  if (address_mode == mode_64bit)
15335    {
15336      op_address[op_ad] = op;
15337      op_riprel[op_ad] = riprel;
15338    }
15339  else
15340    {
15341      /* Mask to get a 32-bit address.  */
15342      op_address[op_ad] = op & 0xffffffff;
15343      op_riprel[op_ad] = riprel & 0xffffffff;
15344    }
15345}
15346
15347static void
15348OP_REG (int code, int sizeflag)
15349{
15350  const char *s;
15351  int add;
15352
15353  switch (code)
15354    {
15355    case es_reg: case ss_reg: case cs_reg:
15356    case ds_reg: case fs_reg: case gs_reg:
15357      oappend (names_seg[code - es_reg]);
15358      return;
15359    }
15360
15361  USED_REX (REX_B);
15362  if (rex & REX_B)
15363    add = 8;
15364  else
15365    add = 0;
15366
15367  switch (code)
15368    {
15369    case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15370    case sp_reg: case bp_reg: case si_reg: case di_reg:
15371      s = names16[code - ax_reg + add];
15372      break;
15373    case al_reg: case ah_reg: case cl_reg: case ch_reg:
15374    case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15375      USED_REX (0);
15376      if (rex)
15377	s = names8rex[code - al_reg + add];
15378      else
15379	s = names8[code - al_reg];
15380      break;
15381    case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15382    case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15383      if (address_mode == mode_64bit
15384	  && ((sizeflag & DFLAG) || (rex & REX_W)))
15385	{
15386	  s = names64[code - rAX_reg + add];
15387	  break;
15388	}
15389      code += eAX_reg - rAX_reg;
15390      /* Fall through.  */
15391    case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15392    case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15393      USED_REX (REX_W);
15394      if (rex & REX_W)
15395	s = names64[code - eAX_reg + add];
15396      else
15397	{
15398	  if (sizeflag & DFLAG)
15399	    s = names32[code - eAX_reg + add];
15400	  else
15401	    s = names16[code - eAX_reg + add];
15402	  used_prefixes |= (prefixes & PREFIX_DATA);
15403	}
15404      break;
15405    default:
15406      s = INTERNAL_DISASSEMBLER_ERROR;
15407      break;
15408    }
15409  oappend (s);
15410}
15411
15412static void
15413OP_IMREG (int code, int sizeflag)
15414{
15415  const char *s;
15416
15417  switch (code)
15418    {
15419    case indir_dx_reg:
15420      if (intel_syntax)
15421	s = "dx";
15422      else
15423	s = "(%dx)";
15424      break;
15425    case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15426    case sp_reg: case bp_reg: case si_reg: case di_reg:
15427      s = names16[code - ax_reg];
15428      break;
15429    case es_reg: case ss_reg: case cs_reg:
15430    case ds_reg: case fs_reg: case gs_reg:
15431      s = names_seg[code - es_reg];
15432      break;
15433    case al_reg: case ah_reg: case cl_reg: case ch_reg:
15434    case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15435      USED_REX (0);
15436      if (rex)
15437	s = names8rex[code - al_reg];
15438      else
15439	s = names8[code - al_reg];
15440      break;
15441    case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15442    case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15443      USED_REX (REX_W);
15444      if (rex & REX_W)
15445	s = names64[code - eAX_reg];
15446      else
15447	{
15448	  if (sizeflag & DFLAG)
15449	    s = names32[code - eAX_reg];
15450	  else
15451	    s = names16[code - eAX_reg];
15452	  used_prefixes |= (prefixes & PREFIX_DATA);
15453	}
15454      break;
15455    case z_mode_ax_reg:
15456      if ((rex & REX_W) || (sizeflag & DFLAG))
15457	s = *names32;
15458      else
15459	s = *names16;
15460      if (!(rex & REX_W))
15461	used_prefixes |= (prefixes & PREFIX_DATA);
15462      break;
15463    default:
15464      s = INTERNAL_DISASSEMBLER_ERROR;
15465      break;
15466    }
15467  oappend (s);
15468}
15469
15470static void
15471OP_I (int bytemode, int sizeflag)
15472{
15473  bfd_signed_vma op;
15474  bfd_signed_vma mask = -1;
15475
15476  switch (bytemode)
15477    {
15478    case b_mode:
15479      FETCH_DATA (the_info, codep + 1);
15480      op = *codep++;
15481      mask = 0xff;
15482      break;
15483    case q_mode:
15484      if (address_mode == mode_64bit)
15485	{
15486	  op = get32s ();
15487	  break;
15488	}
15489      /* Fall through.  */
15490    case v_mode:
15491      USED_REX (REX_W);
15492      if (rex & REX_W)
15493	op = get32s ();
15494      else
15495	{
15496	  if (sizeflag & DFLAG)
15497	    {
15498	      op = get32 ();
15499	      mask = 0xffffffff;
15500	    }
15501	  else
15502	    {
15503	      op = get16 ();
15504	      mask = 0xfffff;
15505	    }
15506	  used_prefixes |= (prefixes & PREFIX_DATA);
15507	}
15508      break;
15509    case w_mode:
15510      mask = 0xfffff;
15511      op = get16 ();
15512      break;
15513    case const_1_mode:
15514      if (intel_syntax)
15515	oappend ("1");
15516      return;
15517    default:
15518      oappend (INTERNAL_DISASSEMBLER_ERROR);
15519      return;
15520    }
15521
15522  op &= mask;
15523  scratchbuf[0] = '$';
15524  print_operand_value (scratchbuf + 1, 1, op);
15525  oappend_maybe_intel (scratchbuf);
15526  scratchbuf[0] = '\0';
15527}
15528
15529static void
15530OP_I64 (int bytemode, int sizeflag)
15531{
15532  bfd_signed_vma op;
15533  bfd_signed_vma mask = -1;
15534
15535  if (address_mode != mode_64bit)
15536    {
15537      OP_I (bytemode, sizeflag);
15538      return;
15539    }
15540
15541  switch (bytemode)
15542    {
15543    case b_mode:
15544      FETCH_DATA (the_info, codep + 1);
15545      op = *codep++;
15546      mask = 0xff;
15547      break;
15548    case v_mode:
15549      USED_REX (REX_W);
15550      if (rex & REX_W)
15551	op = get64 ();
15552      else
15553	{
15554	  if (sizeflag & DFLAG)
15555	    {
15556	      op = get32 ();
15557	      mask = 0xffffffff;
15558	    }
15559	  else
15560	    {
15561	      op = get16 ();
15562	      mask = 0xfffff;
15563	    }
15564	  used_prefixes |= (prefixes & PREFIX_DATA);
15565	}
15566      break;
15567    case w_mode:
15568      mask = 0xfffff;
15569      op = get16 ();
15570      break;
15571    default:
15572      oappend (INTERNAL_DISASSEMBLER_ERROR);
15573      return;
15574    }
15575
15576  op &= mask;
15577  scratchbuf[0] = '$';
15578  print_operand_value (scratchbuf + 1, 1, op);
15579  oappend_maybe_intel (scratchbuf);
15580  scratchbuf[0] = '\0';
15581}
15582
15583static void
15584OP_sI (int bytemode, int sizeflag)
15585{
15586  bfd_signed_vma op;
15587
15588  switch (bytemode)
15589    {
15590    case b_mode:
15591    case b_T_mode:
15592      FETCH_DATA (the_info, codep + 1);
15593      op = *codep++;
15594      if ((op & 0x80) != 0)
15595	op -= 0x100;
15596      if (bytemode == b_T_mode)
15597	{
15598	  if (address_mode != mode_64bit
15599	      || !((sizeflag & DFLAG) || (rex & REX_W)))
15600	    {
15601	      /* The operand-size prefix is overridden by a REX prefix.  */
15602	      if ((sizeflag & DFLAG) || (rex & REX_W))
15603		op &= 0xffffffff;
15604	      else
15605		op &= 0xffff;
15606	  }
15607	}
15608      else
15609	{
15610	  if (!(rex & REX_W))
15611	    {
15612	      if (sizeflag & DFLAG)
15613		op &= 0xffffffff;
15614	      else
15615		op &= 0xffff;
15616	    }
15617	}
15618      break;
15619    case v_mode:
15620      /* The operand-size prefix is overridden by a REX prefix.  */
15621      if ((sizeflag & DFLAG) || (rex & REX_W))
15622	op = get32s ();
15623      else
15624	op = get16 ();
15625      break;
15626    default:
15627      oappend (INTERNAL_DISASSEMBLER_ERROR);
15628      return;
15629    }
15630
15631  scratchbuf[0] = '$';
15632  print_operand_value (scratchbuf + 1, 1, op);
15633  oappend_maybe_intel (scratchbuf);
15634}
15635
15636static void
15637OP_J (int bytemode, int sizeflag)
15638{
15639  bfd_vma disp;
15640  bfd_vma mask = -1;
15641  bfd_vma segment = 0;
15642
15643  switch (bytemode)
15644    {
15645    case b_mode:
15646      FETCH_DATA (the_info, codep + 1);
15647      disp = *codep++;
15648      if ((disp & 0x80) != 0)
15649	disp -= 0x100;
15650      break;
15651    case v_mode:
15652      USED_REX (REX_W);
15653      if ((sizeflag & DFLAG) || (rex & REX_W))
15654	disp = get32s ();
15655      else
15656	{
15657	  disp = get16 ();
15658	  if ((disp & 0x8000) != 0)
15659	    disp -= 0x10000;
15660	  /* In 16bit mode, address is wrapped around at 64k within
15661	     the same segment.  Otherwise, a data16 prefix on a jump
15662	     instruction means that the pc is masked to 16 bits after
15663	     the displacement is added!  */
15664	  mask = 0xffff;
15665	  if ((prefixes & PREFIX_DATA) == 0)
15666	    segment = ((start_pc + codep - start_codep)
15667		       & ~((bfd_vma) 0xffff));
15668	}
15669      if (!(rex & REX_W))
15670	used_prefixes |= (prefixes & PREFIX_DATA);
15671      break;
15672    default:
15673      oappend (INTERNAL_DISASSEMBLER_ERROR);
15674      return;
15675    }
15676  disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
15677  set_op (disp, 0);
15678  print_operand_value (scratchbuf, 1, disp);
15679  oappend (scratchbuf);
15680}
15681
15682static void
15683OP_SEG (int bytemode, int sizeflag)
15684{
15685  if (bytemode == w_mode)
15686    oappend (names_seg[modrm.reg]);
15687  else
15688    OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
15689}
15690
15691static void
15692OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
15693{
15694  int seg, offset;
15695
15696  if (sizeflag & DFLAG)
15697    {
15698      offset = get32 ();
15699      seg = get16 ();
15700    }
15701  else
15702    {
15703      offset = get16 ();
15704      seg = get16 ();
15705    }
15706  used_prefixes |= (prefixes & PREFIX_DATA);
15707  if (intel_syntax)
15708    sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
15709  else
15710    sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
15711  oappend (scratchbuf);
15712}
15713
15714static void
15715OP_OFF (int bytemode, int sizeflag)
15716{
15717  bfd_vma off;
15718
15719  if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15720    intel_operand_size (bytemode, sizeflag);
15721  append_seg ();
15722
15723  if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15724    off = get32 ();
15725  else
15726    off = get16 ();
15727
15728  if (intel_syntax)
15729    {
15730      if (!active_seg_prefix)
15731	{
15732	  oappend (names_seg[ds_reg - es_reg]);
15733	  oappend (":");
15734	}
15735    }
15736  print_operand_value (scratchbuf, 1, off);
15737  oappend (scratchbuf);
15738}
15739
15740static void
15741OP_OFF64 (int bytemode, int sizeflag)
15742{
15743  bfd_vma off;
15744
15745  if (address_mode != mode_64bit
15746      || (prefixes & PREFIX_ADDR))
15747    {
15748      OP_OFF (bytemode, sizeflag);
15749      return;
15750    }
15751
15752  if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15753    intel_operand_size (bytemode, sizeflag);
15754  append_seg ();
15755
15756  off = get64 ();
15757
15758  if (intel_syntax)
15759    {
15760      if (!active_seg_prefix)
15761	{
15762	  oappend (names_seg[ds_reg - es_reg]);
15763	  oappend (":");
15764	}
15765    }
15766  print_operand_value (scratchbuf, 1, off);
15767  oappend (scratchbuf);
15768}
15769
15770static void
15771ptr_reg (int code, int sizeflag)
15772{
15773  const char *s;
15774
15775  *obufp++ = open_char;
15776  used_prefixes |= (prefixes & PREFIX_ADDR);
15777  if (address_mode == mode_64bit)
15778    {
15779      if (!(sizeflag & AFLAG))
15780	s = names32[code - eAX_reg];
15781      else
15782	s = names64[code - eAX_reg];
15783    }
15784  else if (sizeflag & AFLAG)
15785    s = names32[code - eAX_reg];
15786  else
15787    s = names16[code - eAX_reg];
15788  oappend (s);
15789  *obufp++ = close_char;
15790  *obufp = 0;
15791}
15792
15793static void
15794OP_ESreg (int code, int sizeflag)
15795{
15796  if (intel_syntax)
15797    {
15798      switch (codep[-1])
15799	{
15800	case 0x6d:	/* insw/insl */
15801	  intel_operand_size (z_mode, sizeflag);
15802	  break;
15803	case 0xa5:	/* movsw/movsl/movsq */
15804	case 0xa7:	/* cmpsw/cmpsl/cmpsq */
15805	case 0xab:	/* stosw/stosl */
15806	case 0xaf:	/* scasw/scasl */
15807	  intel_operand_size (v_mode, sizeflag);
15808	  break;
15809	default:
15810	  intel_operand_size (b_mode, sizeflag);
15811	}
15812    }
15813  oappend_maybe_intel ("%es:");
15814  ptr_reg (code, sizeflag);
15815}
15816
15817static void
15818OP_DSreg (int code, int sizeflag)
15819{
15820  if (intel_syntax)
15821    {
15822      switch (codep[-1])
15823	{
15824	case 0x6f:	/* outsw/outsl */
15825	  intel_operand_size (z_mode, sizeflag);
15826	  break;
15827	case 0xa5:	/* movsw/movsl/movsq */
15828	case 0xa7:	/* cmpsw/cmpsl/cmpsq */
15829	case 0xad:	/* lodsw/lodsl/lodsq */
15830	  intel_operand_size (v_mode, sizeflag);
15831	  break;
15832	default:
15833	  intel_operand_size (b_mode, sizeflag);
15834	}
15835    }
15836  /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15837     default segment register DS is printed.  */
15838  if (!active_seg_prefix)
15839    active_seg_prefix = PREFIX_DS;
15840  append_seg ();
15841  ptr_reg (code, sizeflag);
15842}
15843
15844static void
15845OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15846{
15847  int add;
15848  if (rex & REX_R)
15849    {
15850      USED_REX (REX_R);
15851      add = 8;
15852    }
15853  else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15854    {
15855      all_prefixes[last_lock_prefix] = 0;
15856      used_prefixes |= PREFIX_LOCK;
15857      add = 8;
15858    }
15859  else
15860    add = 0;
15861  sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15862  oappend_maybe_intel (scratchbuf);
15863}
15864
15865static void
15866OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15867{
15868  int add;
15869  USED_REX (REX_R);
15870  if (rex & REX_R)
15871    add = 8;
15872  else
15873    add = 0;
15874  if (intel_syntax)
15875    sprintf (scratchbuf, "db%d", modrm.reg + add);
15876  else
15877    sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15878  oappend (scratchbuf);
15879}
15880
15881static void
15882OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15883{
15884  sprintf (scratchbuf, "%%tr%d", modrm.reg);
15885  oappend_maybe_intel (scratchbuf);
15886}
15887
15888static void
15889OP_R (int bytemode, int sizeflag)
15890{
15891  /* Skip mod/rm byte.  */
15892  MODRM_CHECK;
15893  codep++;
15894  OP_E_register (bytemode, sizeflag);
15895}
15896
15897static void
15898OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15899{
15900  int reg = modrm.reg;
15901  const char **names;
15902
15903  used_prefixes |= (prefixes & PREFIX_DATA);
15904  if (prefixes & PREFIX_DATA)
15905    {
15906      names = names_xmm;
15907      USED_REX (REX_R);
15908      if (rex & REX_R)
15909	reg += 8;
15910    }
15911  else
15912    names = names_mm;
15913  oappend (names[reg]);
15914}
15915
15916static void
15917OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15918{
15919  int reg = modrm.reg;
15920  const char **names;
15921
15922  USED_REX (REX_R);
15923  if (rex & REX_R)
15924    reg += 8;
15925  if (vex.evex)
15926    {
15927      if (!vex.r)
15928	reg += 16;
15929    }
15930
15931  if (need_vex
15932      && bytemode != xmm_mode
15933      && bytemode != xmmq_mode
15934      && bytemode != evex_half_bcst_xmmq_mode
15935      && bytemode != ymm_mode
15936      && bytemode != scalar_mode)
15937    {
15938      switch (vex.length)
15939	{
15940	case 128:
15941	  names = names_xmm;
15942	  break;
15943	case 256:
15944	  if (vex.w
15945	      || (bytemode != vex_vsib_q_w_dq_mode
15946		  && bytemode != vex_vsib_q_w_d_mode))
15947	    names = names_ymm;
15948	  else
15949	    names = names_xmm;
15950	  break;
15951	case 512:
15952	  names = names_zmm;
15953	  break;
15954	default:
15955	  abort ();
15956	}
15957    }
15958  else if (bytemode == xmmq_mode
15959	   || bytemode == evex_half_bcst_xmmq_mode)
15960    {
15961      switch (vex.length)
15962	{
15963	case 128:
15964	case 256:
15965	  names = names_xmm;
15966	  break;
15967	case 512:
15968	  names = names_ymm;
15969	  break;
15970	default:
15971	  abort ();
15972	}
15973    }
15974  else if (bytemode == ymm_mode)
15975    names = names_ymm;
15976  else
15977    names = names_xmm;
15978  oappend (names[reg]);
15979}
15980
15981static void
15982OP_EM (int bytemode, int sizeflag)
15983{
15984  int reg;
15985  const char **names;
15986
15987  if (modrm.mod != 3)
15988    {
15989      if (intel_syntax
15990	  && (bytemode == v_mode || bytemode == v_swap_mode))
15991	{
15992	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15993	  used_prefixes |= (prefixes & PREFIX_DATA);
15994	}
15995      OP_E (bytemode, sizeflag);
15996      return;
15997    }
15998
15999  if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16000    swap_operand ();
16001
16002  /* Skip mod/rm byte.  */
16003  MODRM_CHECK;
16004  codep++;
16005  used_prefixes |= (prefixes & PREFIX_DATA);
16006  reg = modrm.rm;
16007  if (prefixes & PREFIX_DATA)
16008    {
16009      names = names_xmm;
16010      USED_REX (REX_B);
16011      if (rex & REX_B)
16012	reg += 8;
16013    }
16014  else
16015    names = names_mm;
16016  oappend (names[reg]);
16017}
16018
16019/* cvt* are the only instructions in sse2 which have
16020   both SSE and MMX operands and also have 0x66 prefix
16021   in their opcode. 0x66 was originally used to differentiate
16022   between SSE and MMX instruction(operands). So we have to handle the
16023   cvt* separately using OP_EMC and OP_MXC */
16024static void
16025OP_EMC (int bytemode, int sizeflag)
16026{
16027  if (modrm.mod != 3)
16028    {
16029      if (intel_syntax && bytemode == v_mode)
16030	{
16031	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16032	  used_prefixes |= (prefixes & PREFIX_DATA);
16033	}
16034      OP_E (bytemode, sizeflag);
16035      return;
16036    }
16037
16038  /* Skip mod/rm byte.  */
16039  MODRM_CHECK;
16040  codep++;
16041  used_prefixes |= (prefixes & PREFIX_DATA);
16042  oappend (names_mm[modrm.rm]);
16043}
16044
16045static void
16046OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16047{
16048  used_prefixes |= (prefixes & PREFIX_DATA);
16049  oappend (names_mm[modrm.reg]);
16050}
16051
16052static void
16053OP_EX (int bytemode, int sizeflag)
16054{
16055  int reg;
16056  const char **names;
16057
16058  /* Skip mod/rm byte.  */
16059  MODRM_CHECK;
16060  codep++;
16061
16062  if (modrm.mod != 3)
16063    {
16064      OP_E_memory (bytemode, sizeflag);
16065      return;
16066    }
16067
16068  reg = modrm.rm;
16069  USED_REX (REX_B);
16070  if (rex & REX_B)
16071    reg += 8;
16072  if (vex.evex)
16073    {
16074      USED_REX (REX_X);
16075      if ((rex & REX_X))
16076	reg += 16;
16077    }
16078
16079  if ((sizeflag & SUFFIX_ALWAYS)
16080      && (bytemode == x_swap_mode
16081	  || bytemode == d_swap_mode
16082	  || bytemode == dqw_swap_mode
16083	  || bytemode == d_scalar_swap_mode
16084	  || bytemode == q_swap_mode
16085	  || bytemode == q_scalar_swap_mode))
16086    swap_operand ();
16087
16088  if (need_vex
16089      && bytemode != xmm_mode
16090      && bytemode != xmmdw_mode
16091      && bytemode != xmmqd_mode
16092      && bytemode != xmm_mb_mode
16093      && bytemode != xmm_mw_mode
16094      && bytemode != xmm_md_mode
16095      && bytemode != xmm_mq_mode
16096      && bytemode != xmm_mdq_mode
16097      && bytemode != xmmq_mode
16098      && bytemode != evex_half_bcst_xmmq_mode
16099      && bytemode != ymm_mode
16100      && bytemode != d_scalar_mode
16101      && bytemode != d_scalar_swap_mode
16102      && bytemode != q_scalar_mode
16103      && bytemode != q_scalar_swap_mode
16104      && bytemode != vex_scalar_w_dq_mode)
16105    {
16106      switch (vex.length)
16107	{
16108	case 128:
16109	  names = names_xmm;
16110	  break;
16111	case 256:
16112	  names = names_ymm;
16113	  break;
16114	case 512:
16115	  names = names_zmm;
16116	  break;
16117	default:
16118	  abort ();
16119	}
16120    }
16121  else if (bytemode == xmmq_mode
16122	   || bytemode == evex_half_bcst_xmmq_mode)
16123    {
16124      switch (vex.length)
16125	{
16126	case 128:
16127	case 256:
16128	  names = names_xmm;
16129	  break;
16130	case 512:
16131	  names = names_ymm;
16132	  break;
16133	default:
16134	  abort ();
16135	}
16136    }
16137  else if (bytemode == ymm_mode)
16138    names = names_ymm;
16139  else
16140    names = names_xmm;
16141  oappend (names[reg]);
16142}
16143
16144static void
16145OP_MS (int bytemode, int sizeflag)
16146{
16147  if (modrm.mod == 3)
16148    OP_EM (bytemode, sizeflag);
16149  else
16150    BadOp ();
16151}
16152
16153static void
16154OP_XS (int bytemode, int sizeflag)
16155{
16156  if (modrm.mod == 3)
16157    OP_EX (bytemode, sizeflag);
16158  else
16159    BadOp ();
16160}
16161
16162static void
16163OP_M (int bytemode, int sizeflag)
16164{
16165  if (modrm.mod == 3)
16166    /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16167    BadOp ();
16168  else
16169    OP_E (bytemode, sizeflag);
16170}
16171
16172static void
16173OP_0f07 (int bytemode, int sizeflag)
16174{
16175  if (modrm.mod != 3 || modrm.rm != 0)
16176    BadOp ();
16177  else
16178    OP_E (bytemode, sizeflag);
16179}
16180
16181/* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16182   32bit mode and "xchg %rax,%rax" in 64bit mode.  */
16183
16184static void
16185NOP_Fixup1 (int bytemode, int sizeflag)
16186{
16187  if ((prefixes & PREFIX_DATA) != 0
16188      || (rex != 0
16189	  && rex != 0x48
16190	  && address_mode == mode_64bit))
16191    OP_REG (bytemode, sizeflag);
16192  else
16193    strcpy (obuf, "nop");
16194}
16195
16196static void
16197NOP_Fixup2 (int bytemode, int sizeflag)
16198{
16199  if ((prefixes & PREFIX_DATA) != 0
16200      || (rex != 0
16201	  && rex != 0x48
16202	  && address_mode == mode_64bit))
16203    OP_IMREG (bytemode, sizeflag);
16204}
16205
16206static const char *const Suffix3DNow[] = {
16207/* 00 */	NULL,		NULL,		NULL,		NULL,
16208/* 04 */	NULL,		NULL,		NULL,		NULL,
16209/* 08 */	NULL,		NULL,		NULL,		NULL,
16210/* 0C */	"pi2fw",	"pi2fd",	NULL,		NULL,
16211/* 10 */	NULL,		NULL,		NULL,		NULL,
16212/* 14 */	NULL,		NULL,		NULL,		NULL,
16213/* 18 */	NULL,		NULL,		NULL,		NULL,
16214/* 1C */	"pf2iw",	"pf2id",	NULL,		NULL,
16215/* 20 */	NULL,		NULL,		NULL,		NULL,
16216/* 24 */	NULL,		NULL,		NULL,		NULL,
16217/* 28 */	NULL,		NULL,		NULL,		NULL,
16218/* 2C */	NULL,		NULL,		NULL,		NULL,
16219/* 30 */	NULL,		NULL,		NULL,		NULL,
16220/* 34 */	NULL,		NULL,		NULL,		NULL,
16221/* 38 */	NULL,		NULL,		NULL,		NULL,
16222/* 3C */	NULL,		NULL,		NULL,		NULL,
16223/* 40 */	NULL,		NULL,		NULL,		NULL,
16224/* 44 */	NULL,		NULL,		NULL,		NULL,
16225/* 48 */	NULL,		NULL,		NULL,		NULL,
16226/* 4C */	NULL,		NULL,		NULL,		NULL,
16227/* 50 */	NULL,		NULL,		NULL,		NULL,
16228/* 54 */	NULL,		NULL,		NULL,		NULL,
16229/* 58 */	NULL,		NULL,		NULL,		NULL,
16230/* 5C */	NULL,		NULL,		NULL,		NULL,
16231/* 60 */	NULL,		NULL,		NULL,		NULL,
16232/* 64 */	NULL,		NULL,		NULL,		NULL,
16233/* 68 */	NULL,		NULL,		NULL,		NULL,
16234/* 6C */	NULL,		NULL,		NULL,		NULL,
16235/* 70 */	NULL,		NULL,		NULL,		NULL,
16236/* 74 */	NULL,		NULL,		NULL,		NULL,
16237/* 78 */	NULL,		NULL,		NULL,		NULL,
16238/* 7C */	NULL,		NULL,		NULL,		NULL,
16239/* 80 */	NULL,		NULL,		NULL,		NULL,
16240/* 84 */	NULL,		NULL,		NULL,		NULL,
16241/* 88 */	NULL,		NULL,		"pfnacc",	NULL,
16242/* 8C */	NULL,		NULL,		"pfpnacc",	NULL,
16243/* 90 */	"pfcmpge",	NULL,		NULL,		NULL,
16244/* 94 */	"pfmin",	NULL,		"pfrcp",	"pfrsqrt",
16245/* 98 */	NULL,		NULL,		"pfsub",	NULL,
16246/* 9C */	NULL,		NULL,		"pfadd",	NULL,
16247/* A0 */	"pfcmpgt",	NULL,		NULL,		NULL,
16248/* A4 */	"pfmax",	NULL,		"pfrcpit1",	"pfrsqit1",
16249/* A8 */	NULL,		NULL,		"pfsubr",	NULL,
16250/* AC */	NULL,		NULL,		"pfacc",	NULL,
16251/* B0 */	"pfcmpeq",	NULL,		NULL,		NULL,
16252/* B4 */	"pfmul",	NULL,		"pfrcpit2",	"pmulhrw",
16253/* B8 */	NULL,		NULL,		NULL,		"pswapd",
16254/* BC */	NULL,		NULL,		NULL,		"pavgusb",
16255/* C0 */	NULL,		NULL,		NULL,		NULL,
16256/* C4 */	NULL,		NULL,		NULL,		NULL,
16257/* C8 */	NULL,		NULL,		NULL,		NULL,
16258/* CC */	NULL,		NULL,		NULL,		NULL,
16259/* D0 */	NULL,		NULL,		NULL,		NULL,
16260/* D4 */	NULL,		NULL,		NULL,		NULL,
16261/* D8 */	NULL,		NULL,		NULL,		NULL,
16262/* DC */	NULL,		NULL,		NULL,		NULL,
16263/* E0 */	NULL,		NULL,		NULL,		NULL,
16264/* E4 */	NULL,		NULL,		NULL,		NULL,
16265/* E8 */	NULL,		NULL,		NULL,		NULL,
16266/* EC */	NULL,		NULL,		NULL,		NULL,
16267/* F0 */	NULL,		NULL,		NULL,		NULL,
16268/* F4 */	NULL,		NULL,		NULL,		NULL,
16269/* F8 */	NULL,		NULL,		NULL,		NULL,
16270/* FC */	NULL,		NULL,		NULL,		NULL,
16271};
16272
16273static void
16274OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16275{
16276  const char *mnemonic;
16277
16278  FETCH_DATA (the_info, codep + 1);
16279  /* AMD 3DNow! instructions are specified by an opcode suffix in the
16280     place where an 8-bit immediate would normally go.  ie. the last
16281     byte of the instruction.  */
16282  obufp = mnemonicendp;
16283  mnemonic = Suffix3DNow[*codep++ & 0xff];
16284  if (mnemonic)
16285    oappend (mnemonic);
16286  else
16287    {
16288      /* Since a variable sized modrm/sib chunk is between the start
16289	 of the opcode (0x0f0f) and the opcode suffix, we need to do
16290	 all the modrm processing first, and don't know until now that
16291	 we have a bad opcode.  This necessitates some cleaning up.  */
16292      op_out[0][0] = '\0';
16293      op_out[1][0] = '\0';
16294      BadOp ();
16295    }
16296  mnemonicendp = obufp;
16297}
16298
16299static struct op simd_cmp_op[] =
16300{
16301  { STRING_COMMA_LEN ("eq") },
16302  { STRING_COMMA_LEN ("lt") },
16303  { STRING_COMMA_LEN ("le") },
16304  { STRING_COMMA_LEN ("unord") },
16305  { STRING_COMMA_LEN ("neq") },
16306  { STRING_COMMA_LEN ("nlt") },
16307  { STRING_COMMA_LEN ("nle") },
16308  { STRING_COMMA_LEN ("ord") }
16309};
16310
16311static void
16312CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16313{
16314  unsigned int cmp_type;
16315
16316  FETCH_DATA (the_info, codep + 1);
16317  cmp_type = *codep++ & 0xff;
16318  if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16319    {
16320      char suffix [3];
16321      char *p = mnemonicendp - 2;
16322      suffix[0] = p[0];
16323      suffix[1] = p[1];
16324      suffix[2] = '\0';
16325      sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16326      mnemonicendp += simd_cmp_op[cmp_type].len;
16327    }
16328  else
16329    {
16330      /* We have a reserved extension byte.  Output it directly.  */
16331      scratchbuf[0] = '$';
16332      print_operand_value (scratchbuf + 1, 1, cmp_type);
16333      oappend_maybe_intel (scratchbuf);
16334      scratchbuf[0] = '\0';
16335    }
16336}
16337
16338static void
16339OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16340	  int sizeflag ATTRIBUTE_UNUSED)
16341{
16342  /* mwait %eax,%ecx  */
16343  if (!intel_syntax)
16344    {
16345      const char **names = (address_mode == mode_64bit
16346			    ? names64 : names32);
16347      strcpy (op_out[0], names[0]);
16348      strcpy (op_out[1], names[1]);
16349      two_source_ops = 1;
16350    }
16351  /* Skip mod/rm byte.  */
16352  MODRM_CHECK;
16353  codep++;
16354}
16355
16356static void
16357OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16358	    int sizeflag ATTRIBUTE_UNUSED)
16359{
16360  /* monitor %eax,%ecx,%edx"  */
16361  if (!intel_syntax)
16362    {
16363      const char **op1_names;
16364      const char **names = (address_mode == mode_64bit
16365			    ? names64 : names32);
16366
16367      if (!(prefixes & PREFIX_ADDR))
16368	op1_names = (address_mode == mode_16bit
16369		     ? names16 : names);
16370      else
16371	{
16372	  /* Remove "addr16/addr32".  */
16373	  all_prefixes[last_addr_prefix] = 0;
16374	  op1_names = (address_mode != mode_32bit
16375		       ? names32 : names16);
16376	  used_prefixes |= PREFIX_ADDR;
16377	}
16378      strcpy (op_out[0], op1_names[0]);
16379      strcpy (op_out[1], names[1]);
16380      strcpy (op_out[2], names[2]);
16381      two_source_ops = 1;
16382    }
16383  /* Skip mod/rm byte.  */
16384  MODRM_CHECK;
16385  codep++;
16386}
16387
16388static void
16389BadOp (void)
16390{
16391  /* Throw away prefixes and 1st. opcode byte.  */
16392  codep = insn_codep + 1;
16393  oappend ("(bad)");
16394}
16395
16396static void
16397REP_Fixup (int bytemode, int sizeflag)
16398{
16399  /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16400     lods and stos.  */
16401  if (prefixes & PREFIX_REPZ)
16402    all_prefixes[last_repz_prefix] = REP_PREFIX;
16403
16404  switch (bytemode)
16405    {
16406    case al_reg:
16407    case eAX_reg:
16408    case indir_dx_reg:
16409      OP_IMREG (bytemode, sizeflag);
16410      break;
16411    case eDI_reg:
16412      OP_ESreg (bytemode, sizeflag);
16413      break;
16414    case eSI_reg:
16415      OP_DSreg (bytemode, sizeflag);
16416      break;
16417    default:
16418      abort ();
16419      break;
16420    }
16421}
16422
16423/* For BND-prefixed instructions 0xF2 prefix should be displayed as
16424   "bnd".  */
16425
16426static void
16427BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16428{
16429  if (prefixes & PREFIX_REPNZ)
16430    all_prefixes[last_repnz_prefix] = BND_PREFIX;
16431}
16432
16433/* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16434   "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16435 */
16436
16437static void
16438HLE_Fixup1 (int bytemode, int sizeflag)
16439{
16440  if (modrm.mod != 3
16441      && (prefixes & PREFIX_LOCK) != 0)
16442    {
16443      if (prefixes & PREFIX_REPZ)
16444	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16445      if (prefixes & PREFIX_REPNZ)
16446	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16447    }
16448
16449  OP_E (bytemode, sizeflag);
16450}
16451
16452/* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
16453   "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
16454 */
16455
16456static void
16457HLE_Fixup2 (int bytemode, int sizeflag)
16458{
16459  if (modrm.mod != 3)
16460    {
16461      if (prefixes & PREFIX_REPZ)
16462	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16463      if (prefixes & PREFIX_REPNZ)
16464	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16465    }
16466
16467  OP_E (bytemode, sizeflag);
16468}
16469
16470/* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
16471   "xrelease" for memory operand.  No check for LOCK prefix.   */
16472
16473static void
16474HLE_Fixup3 (int bytemode, int sizeflag)
16475{
16476  if (modrm.mod != 3
16477      && last_repz_prefix > last_repnz_prefix
16478      && (prefixes & PREFIX_REPZ) != 0)
16479    all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16480
16481  OP_E (bytemode, sizeflag);
16482}
16483
16484static void
16485CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16486{
16487  USED_REX (REX_W);
16488  if (rex & REX_W)
16489    {
16490      /* Change cmpxchg8b to cmpxchg16b.  */
16491      char *p = mnemonicendp - 2;
16492      mnemonicendp = stpcpy (p, "16b");
16493      bytemode = o_mode;
16494    }
16495  else if ((prefixes & PREFIX_LOCK) != 0)
16496    {
16497      if (prefixes & PREFIX_REPZ)
16498	all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16499      if (prefixes & PREFIX_REPNZ)
16500	all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16501    }
16502
16503  OP_M (bytemode, sizeflag);
16504}
16505
16506static void
16507XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16508{
16509  const char **names;
16510
16511  if (need_vex)
16512    {
16513      switch (vex.length)
16514	{
16515	case 128:
16516	  names = names_xmm;
16517	  break;
16518	case 256:
16519	  names = names_ymm;
16520	  break;
16521	default:
16522	  abort ();
16523	}
16524    }
16525  else
16526    names = names_xmm;
16527  oappend (names[reg]);
16528}
16529
16530static void
16531CRC32_Fixup (int bytemode, int sizeflag)
16532{
16533  /* Add proper suffix to "crc32".  */
16534  char *p = mnemonicendp;
16535
16536  switch (bytemode)
16537    {
16538    case b_mode:
16539      if (intel_syntax)
16540	goto skip;
16541
16542      *p++ = 'b';
16543      break;
16544    case v_mode:
16545      if (intel_syntax)
16546	goto skip;
16547
16548      USED_REX (REX_W);
16549      if (rex & REX_W)
16550	*p++ = 'q';
16551      else
16552	{
16553	  if (sizeflag & DFLAG)
16554	    *p++ = 'l';
16555	  else
16556	    *p++ = 'w';
16557	  used_prefixes |= (prefixes & PREFIX_DATA);
16558	}
16559      break;
16560    default:
16561      oappend (INTERNAL_DISASSEMBLER_ERROR);
16562      break;
16563    }
16564  mnemonicendp = p;
16565  *p = '\0';
16566
16567skip:
16568  if (modrm.mod == 3)
16569    {
16570      int add;
16571
16572      /* Skip mod/rm byte.  */
16573      MODRM_CHECK;
16574      codep++;
16575
16576      USED_REX (REX_B);
16577      add = (rex & REX_B) ? 8 : 0;
16578      if (bytemode == b_mode)
16579	{
16580	  USED_REX (0);
16581	  if (rex)
16582	    oappend (names8rex[modrm.rm + add]);
16583	  else
16584	    oappend (names8[modrm.rm + add]);
16585	}
16586      else
16587	{
16588	  USED_REX (REX_W);
16589	  if (rex & REX_W)
16590	    oappend (names64[modrm.rm + add]);
16591	  else if ((prefixes & PREFIX_DATA))
16592	    oappend (names16[modrm.rm + add]);
16593	  else
16594	    oappend (names32[modrm.rm + add]);
16595	}
16596    }
16597  else
16598    OP_E (bytemode, sizeflag);
16599}
16600
16601static void
16602FXSAVE_Fixup (int bytemode, int sizeflag)
16603{
16604  /* Add proper suffix to "fxsave" and "fxrstor".  */
16605  USED_REX (REX_W);
16606  if (rex & REX_W)
16607    {
16608      char *p = mnemonicendp;
16609      *p++ = '6';
16610      *p++ = '4';
16611      *p = '\0';
16612      mnemonicendp = p;
16613    }
16614  OP_M (bytemode, sizeflag);
16615}
16616
16617/* Display the destination register operand for instructions with
16618   VEX. */
16619
16620static void
16621OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16622{
16623  int reg;
16624  const char **names;
16625
16626  if (!need_vex)
16627    abort ();
16628
16629  if (!need_vex_reg)
16630    return;
16631
16632  reg = vex.register_specifier;
16633  if (vex.evex)
16634    {
16635      if (!vex.v)
16636	reg += 16;
16637    }
16638
16639  if (bytemode == vex_scalar_mode)
16640    {
16641      oappend (names_xmm[reg]);
16642      return;
16643    }
16644
16645  switch (vex.length)
16646    {
16647    case 128:
16648      switch (bytemode)
16649	{
16650	case vex_mode:
16651	case vex128_mode:
16652	case vex_vsib_q_w_dq_mode:
16653	case vex_vsib_q_w_d_mode:
16654	  names = names_xmm;
16655	  break;
16656	case dq_mode:
16657	  if (vex.w)
16658	    names = names64;
16659	  else
16660	    names = names32;
16661	  break;
16662	case mask_bd_mode:
16663	case mask_mode:
16664	  names = names_mask;
16665	  break;
16666	default:
16667	  abort ();
16668	  return;
16669	}
16670      break;
16671    case 256:
16672      switch (bytemode)
16673	{
16674	case vex_mode:
16675	case vex256_mode:
16676	  names = names_ymm;
16677	  break;
16678	case vex_vsib_q_w_dq_mode:
16679	case vex_vsib_q_w_d_mode:
16680	  names = vex.w ? names_ymm : names_xmm;
16681	  break;
16682	case mask_bd_mode:
16683	case mask_mode:
16684	  names = names_mask;
16685	  break;
16686	default:
16687	  abort ();
16688	  return;
16689	}
16690      break;
16691    case 512:
16692      names = names_zmm;
16693      break;
16694    default:
16695      abort ();
16696      break;
16697    }
16698  oappend (names[reg]);
16699}
16700
16701/* Get the VEX immediate byte without moving codep.  */
16702
16703static unsigned char
16704get_vex_imm8 (int sizeflag, int opnum)
16705{
16706  int bytes_before_imm = 0;
16707
16708  if (modrm.mod != 3)
16709    {
16710      /* There are SIB/displacement bytes.  */
16711      if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16712	{
16713	  /* 32/64 bit address mode */
16714	  int base = modrm.rm;
16715
16716	  /* Check SIB byte.  */
16717	  if (base == 4)
16718	    {
16719	      FETCH_DATA (the_info, codep + 1);
16720	      base = *codep & 7;
16721	      /* When decoding the third source, don't increase
16722		 bytes_before_imm as this has already been incremented
16723		 by one in OP_E_memory while decoding the second
16724		 source operand.  */
16725	      if (opnum == 0)
16726		bytes_before_imm++;
16727	    }
16728
16729	  /* Don't increase bytes_before_imm when decoding the third source,
16730	     it has already been incremented by OP_E_memory while decoding
16731	     the second source operand.  */
16732	  if (opnum == 0)
16733	    {
16734	      switch (modrm.mod)
16735		{
16736		  case 0:
16737		    /* When modrm.rm == 5 or modrm.rm == 4 and base in
16738		       SIB == 5, there is a 4 byte displacement.  */
16739		    if (base != 5)
16740		      /* No displacement. */
16741		      break;
16742		  case 2:
16743		    /* 4 byte displacement.  */
16744		    bytes_before_imm += 4;
16745		    break;
16746		  case 1:
16747		    /* 1 byte displacement.  */
16748		    bytes_before_imm++;
16749		    break;
16750		}
16751	    }
16752	}
16753      else
16754	{
16755	  /* 16 bit address mode */
16756	  /* Don't increase bytes_before_imm when decoding the third source,
16757	     it has already been incremented by OP_E_memory while decoding
16758	     the second source operand.  */
16759	  if (opnum == 0)
16760	    {
16761	      switch (modrm.mod)
16762		{
16763		case 0:
16764		  /* When modrm.rm == 6, there is a 2 byte displacement.  */
16765		  if (modrm.rm != 6)
16766		    /* No displacement. */
16767		    break;
16768		case 2:
16769		  /* 2 byte displacement.  */
16770		  bytes_before_imm += 2;
16771		  break;
16772		case 1:
16773		  /* 1 byte displacement: when decoding the third source,
16774		     don't increase bytes_before_imm as this has already
16775		     been incremented by one in OP_E_memory while decoding
16776		     the second source operand.  */
16777		  if (opnum == 0)
16778		    bytes_before_imm++;
16779
16780		  break;
16781		}
16782	    }
16783	}
16784    }
16785
16786  FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16787  return codep [bytes_before_imm];
16788}
16789
16790static void
16791OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16792{
16793  const char **names;
16794
16795  if (reg == -1 && modrm.mod != 3)
16796    {
16797      OP_E_memory (bytemode, sizeflag);
16798      return;
16799    }
16800  else
16801    {
16802      if (reg == -1)
16803	{
16804	  reg = modrm.rm;
16805	  USED_REX (REX_B);
16806	  if (rex & REX_B)
16807	    reg += 8;
16808	}
16809      else if (reg > 7 && address_mode != mode_64bit)
16810	BadOp ();
16811    }
16812
16813  switch (vex.length)
16814    {
16815    case 128:
16816      names = names_xmm;
16817      break;
16818    case 256:
16819      names = names_ymm;
16820      break;
16821    default:
16822      abort ();
16823    }
16824  oappend (names[reg]);
16825}
16826
16827static void
16828OP_EX_VexImmW (int bytemode, int sizeflag)
16829{
16830  int reg = -1;
16831  static unsigned char vex_imm8;
16832
16833  if (vex_w_done == 0)
16834    {
16835      vex_w_done = 1;
16836
16837      /* Skip mod/rm byte.  */
16838      MODRM_CHECK;
16839      codep++;
16840
16841      vex_imm8 = get_vex_imm8 (sizeflag, 0);
16842
16843      if (vex.w)
16844	  reg = vex_imm8 >> 4;
16845
16846      OP_EX_VexReg (bytemode, sizeflag, reg);
16847    }
16848  else if (vex_w_done == 1)
16849    {
16850      vex_w_done = 2;
16851
16852      if (!vex.w)
16853	  reg = vex_imm8 >> 4;
16854
16855      OP_EX_VexReg (bytemode, sizeflag, reg);
16856    }
16857  else
16858    {
16859      /* Output the imm8 directly.  */
16860      scratchbuf[0] = '$';
16861      print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16862      oappend_maybe_intel (scratchbuf);
16863      scratchbuf[0] = '\0';
16864      codep++;
16865    }
16866}
16867
16868static void
16869OP_Vex_2src (int bytemode, int sizeflag)
16870{
16871  if (modrm.mod == 3)
16872    {
16873      int reg = modrm.rm;
16874      USED_REX (REX_B);
16875      if (rex & REX_B)
16876	reg += 8;
16877      oappend (names_xmm[reg]);
16878    }
16879  else
16880    {
16881      if (intel_syntax
16882	  && (bytemode == v_mode || bytemode == v_swap_mode))
16883	{
16884	  bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16885	  used_prefixes |= (prefixes & PREFIX_DATA);
16886	}
16887      OP_E (bytemode, sizeflag);
16888    }
16889}
16890
16891static void
16892OP_Vex_2src_1 (int bytemode, int sizeflag)
16893{
16894  if (modrm.mod == 3)
16895    {
16896      /* Skip mod/rm byte.   */
16897      MODRM_CHECK;
16898      codep++;
16899    }
16900
16901  if (vex.w)
16902    oappend (names_xmm[vex.register_specifier]);
16903  else
16904    OP_Vex_2src (bytemode, sizeflag);
16905}
16906
16907static void
16908OP_Vex_2src_2 (int bytemode, int sizeflag)
16909{
16910  if (vex.w)
16911    OP_Vex_2src (bytemode, sizeflag);
16912  else
16913    oappend (names_xmm[vex.register_specifier]);
16914}
16915
16916static void
16917OP_EX_VexW (int bytemode, int sizeflag)
16918{
16919  int reg = -1;
16920
16921  if (!vex_w_done)
16922    {
16923      vex_w_done = 1;
16924
16925      /* Skip mod/rm byte.  */
16926      MODRM_CHECK;
16927      codep++;
16928
16929      if (vex.w)
16930	reg = get_vex_imm8 (sizeflag, 0) >> 4;
16931    }
16932  else
16933    {
16934      if (!vex.w)
16935	reg = get_vex_imm8 (sizeflag, 1) >> 4;
16936    }
16937
16938  OP_EX_VexReg (bytemode, sizeflag, reg);
16939}
16940
16941static void
16942VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
16943	     int sizeflag ATTRIBUTE_UNUSED)
16944{
16945  /* Skip the immediate byte and check for invalid bits.  */
16946  FETCH_DATA (the_info, codep + 1);
16947  if (*codep++ & 0xf)
16948    BadOp ();
16949}
16950
16951static void
16952OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16953{
16954  int reg;
16955  const char **names;
16956
16957  FETCH_DATA (the_info, codep + 1);
16958  reg = *codep++;
16959
16960  if (bytemode != x_mode)
16961    abort ();
16962
16963  if (reg & 0xf)
16964      BadOp ();
16965
16966  reg >>= 4;
16967  if (reg > 7 && address_mode != mode_64bit)
16968    BadOp ();
16969
16970  switch (vex.length)
16971    {
16972    case 128:
16973      names = names_xmm;
16974      break;
16975    case 256:
16976      names = names_ymm;
16977      break;
16978    default:
16979      abort ();
16980    }
16981  oappend (names[reg]);
16982}
16983
16984static void
16985OP_XMM_VexW (int bytemode, int sizeflag)
16986{
16987  /* Turn off the REX.W bit since it is used for swapping operands
16988     now.  */
16989  rex &= ~REX_W;
16990  OP_XMM (bytemode, sizeflag);
16991}
16992
16993static void
16994OP_EX_Vex (int bytemode, int sizeflag)
16995{
16996  if (modrm.mod != 3)
16997    {
16998      if (vex.register_specifier != 0)
16999	BadOp ();
17000      need_vex_reg = 0;
17001    }
17002  OP_EX (bytemode, sizeflag);
17003}
17004
17005static void
17006OP_XMM_Vex (int bytemode, int sizeflag)
17007{
17008  if (modrm.mod != 3)
17009    {
17010      if (vex.register_specifier != 0)
17011	BadOp ();
17012      need_vex_reg = 0;
17013    }
17014  OP_XMM (bytemode, sizeflag);
17015}
17016
17017static void
17018VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17019{
17020  switch (vex.length)
17021    {
17022    case 128:
17023      mnemonicendp = stpcpy (obuf, "vzeroupper");
17024      break;
17025    case 256:
17026      mnemonicendp = stpcpy (obuf, "vzeroall");
17027      break;
17028    default:
17029      abort ();
17030    }
17031}
17032
17033static struct op vex_cmp_op[] =
17034{
17035  { STRING_COMMA_LEN ("eq") },
17036  { STRING_COMMA_LEN ("lt") },
17037  { STRING_COMMA_LEN ("le") },
17038  { STRING_COMMA_LEN ("unord") },
17039  { STRING_COMMA_LEN ("neq") },
17040  { STRING_COMMA_LEN ("nlt") },
17041  { STRING_COMMA_LEN ("nle") },
17042  { STRING_COMMA_LEN ("ord") },
17043  { STRING_COMMA_LEN ("eq_uq") },
17044  { STRING_COMMA_LEN ("nge") },
17045  { STRING_COMMA_LEN ("ngt") },
17046  { STRING_COMMA_LEN ("false") },
17047  { STRING_COMMA_LEN ("neq_oq") },
17048  { STRING_COMMA_LEN ("ge") },
17049  { STRING_COMMA_LEN ("gt") },
17050  { STRING_COMMA_LEN ("true") },
17051  { STRING_COMMA_LEN ("eq_os") },
17052  { STRING_COMMA_LEN ("lt_oq") },
17053  { STRING_COMMA_LEN ("le_oq") },
17054  { STRING_COMMA_LEN ("unord_s") },
17055  { STRING_COMMA_LEN ("neq_us") },
17056  { STRING_COMMA_LEN ("nlt_uq") },
17057  { STRING_COMMA_LEN ("nle_uq") },
17058  { STRING_COMMA_LEN ("ord_s") },
17059  { STRING_COMMA_LEN ("eq_us") },
17060  { STRING_COMMA_LEN ("nge_uq") },
17061  { STRING_COMMA_LEN ("ngt_uq") },
17062  { STRING_COMMA_LEN ("false_os") },
17063  { STRING_COMMA_LEN ("neq_os") },
17064  { STRING_COMMA_LEN ("ge_oq") },
17065  { STRING_COMMA_LEN ("gt_oq") },
17066  { STRING_COMMA_LEN ("true_us") },
17067};
17068
17069static void
17070VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17071{
17072  unsigned int cmp_type;
17073
17074  FETCH_DATA (the_info, codep + 1);
17075  cmp_type = *codep++ & 0xff;
17076  if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17077    {
17078      char suffix [3];
17079      char *p = mnemonicendp - 2;
17080      suffix[0] = p[0];
17081      suffix[1] = p[1];
17082      suffix[2] = '\0';
17083      sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17084      mnemonicendp += vex_cmp_op[cmp_type].len;
17085    }
17086  else
17087    {
17088      /* We have a reserved extension byte.  Output it directly.  */
17089      scratchbuf[0] = '$';
17090      print_operand_value (scratchbuf + 1, 1, cmp_type);
17091      oappend_maybe_intel (scratchbuf);
17092      scratchbuf[0] = '\0';
17093    }
17094}
17095
17096static void
17097VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17098	     int sizeflag ATTRIBUTE_UNUSED)
17099{
17100  unsigned int cmp_type;
17101
17102  if (!vex.evex)
17103    abort ();
17104
17105  FETCH_DATA (the_info, codep + 1);
17106  cmp_type = *codep++ & 0xff;
17107  /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17108     If it's the case, print suffix, otherwise - print the immediate.  */
17109  if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17110      && cmp_type != 3
17111      && cmp_type != 7)
17112    {
17113      char suffix [3];
17114      char *p = mnemonicendp - 2;
17115
17116      /* vpcmp* can have both one- and two-lettered suffix.  */
17117      if (p[0] == 'p')
17118	{
17119	  p++;
17120	  suffix[0] = p[0];
17121	  suffix[1] = '\0';
17122	}
17123      else
17124	{
17125	  suffix[0] = p[0];
17126	  suffix[1] = p[1];
17127	  suffix[2] = '\0';
17128	}
17129
17130      sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17131      mnemonicendp += simd_cmp_op[cmp_type].len;
17132    }
17133  else
17134    {
17135      /* We have a reserved extension byte.  Output it directly.  */
17136      scratchbuf[0] = '$';
17137      print_operand_value (scratchbuf + 1, 1, cmp_type);
17138      oappend_maybe_intel (scratchbuf);
17139      scratchbuf[0] = '\0';
17140    }
17141}
17142
17143static const struct op pclmul_op[] =
17144{
17145  { STRING_COMMA_LEN ("lql") },
17146  { STRING_COMMA_LEN ("hql") },
17147  { STRING_COMMA_LEN ("lqh") },
17148  { STRING_COMMA_LEN ("hqh") }
17149};
17150
17151static void
17152PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17153	      int sizeflag ATTRIBUTE_UNUSED)
17154{
17155  unsigned int pclmul_type;
17156
17157  FETCH_DATA (the_info, codep + 1);
17158  pclmul_type = *codep++ & 0xff;
17159  switch (pclmul_type)
17160    {
17161    case 0x10:
17162      pclmul_type = 2;
17163      break;
17164    case 0x11:
17165      pclmul_type = 3;
17166      break;
17167    default:
17168      break;
17169    }
17170  if (pclmul_type < ARRAY_SIZE (pclmul_op))
17171    {
17172      char suffix [4];
17173      char *p = mnemonicendp - 3;
17174      suffix[0] = p[0];
17175      suffix[1] = p[1];
17176      suffix[2] = p[2];
17177      suffix[3] = '\0';
17178      sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17179      mnemonicendp += pclmul_op[pclmul_type].len;
17180    }
17181  else
17182    {
17183      /* We have a reserved extension byte.  Output it directly.  */
17184      scratchbuf[0] = '$';
17185      print_operand_value (scratchbuf + 1, 1, pclmul_type);
17186      oappend_maybe_intel (scratchbuf);
17187      scratchbuf[0] = '\0';
17188    }
17189}
17190
17191static void
17192MOVBE_Fixup (int bytemode, int sizeflag)
17193{
17194  /* Add proper suffix to "movbe".  */
17195  char *p = mnemonicendp;
17196
17197  switch (bytemode)
17198    {
17199    case v_mode:
17200      if (intel_syntax)
17201	goto skip;
17202
17203      USED_REX (REX_W);
17204      if (sizeflag & SUFFIX_ALWAYS)
17205	{
17206	  if (rex & REX_W)
17207	    *p++ = 'q';
17208	  else
17209	    {
17210	      if (sizeflag & DFLAG)
17211		*p++ = 'l';
17212	      else
17213		*p++ = 'w';
17214	      used_prefixes |= (prefixes & PREFIX_DATA);
17215	    }
17216	}
17217      break;
17218    default:
17219      oappend (INTERNAL_DISASSEMBLER_ERROR);
17220      break;
17221    }
17222  mnemonicendp = p;
17223  *p = '\0';
17224
17225skip:
17226  OP_M (bytemode, sizeflag);
17227}
17228
17229static void
17230OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17231{
17232  int reg;
17233  const char **names;
17234
17235  /* Skip mod/rm byte.  */
17236  MODRM_CHECK;
17237  codep++;
17238
17239  if (vex.w)
17240    names = names64;
17241  else
17242    names = names32;
17243
17244  reg = modrm.rm;
17245  USED_REX (REX_B);
17246  if (rex & REX_B)
17247    reg += 8;
17248
17249  oappend (names[reg]);
17250}
17251
17252static void
17253OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17254{
17255  const char **names;
17256
17257  if (vex.w)
17258    names = names64;
17259  else
17260    names = names32;
17261
17262  oappend (names[vex.register_specifier]);
17263}
17264
17265static void
17266OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17267{
17268  if (!vex.evex
17269      || (bytemode != mask_mode && bytemode != mask_bd_mode))
17270    abort ();
17271
17272  USED_REX (REX_R);
17273  if ((rex & REX_R) != 0 || !vex.r)
17274    {
17275      BadOp ();
17276      return;
17277    }
17278
17279  oappend (names_mask [modrm.reg]);
17280}
17281
17282static void
17283OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17284{
17285  if (!vex.evex
17286      || (bytemode != evex_rounding_mode
17287	  && bytemode != evex_sae_mode))
17288    abort ();
17289  if (modrm.mod == 3 && vex.b)
17290    switch (bytemode)
17291      {
17292      case evex_rounding_mode:
17293	oappend (names_rounding[vex.ll]);
17294	break;
17295      case evex_sae_mode:
17296	oappend ("{sae}");
17297	break;
17298      default:
17299	break;
17300      }
17301}
17302