nios2-tdep.c revision 1.8
1/* Target-machine dependent code for Nios II, for GDB. 2 Copyright (C) 2012-2019 Free Software Foundation, Inc. 3 Contributed by Peter Brookes (pbrookes@altera.com) 4 and Andrew Draper (adraper@altera.com). 5 Contributed by Mentor Graphics, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22#include "defs.h" 23#include "frame.h" 24#include "frame-unwind.h" 25#include "frame-base.h" 26#include "trad-frame.h" 27#include "dwarf2-frame.h" 28#include "symtab.h" 29#include "inferior.h" 30#include "gdbtypes.h" 31#include "gdbcore.h" 32#include "gdbcmd.h" 33#include "osabi.h" 34#include "target.h" 35#include "dis-asm.h" 36#include "regcache.h" 37#include "value.h" 38#include "symfile.h" 39#include "arch-utils.h" 40#include "infcall.h" 41#include "regset.h" 42#include "target-descriptions.h" 43 44/* To get entry_point_address. */ 45#include "objfiles.h" 46#include <algorithm> 47 48/* Nios II specific header. */ 49#include "nios2-tdep.h" 50 51#include "features/nios2.c" 52 53/* Control debugging information emitted in this file. */ 54 55static int nios2_debug = 0; 56 57/* The following structures are used in the cache for prologue 58 analysis; see the reg_value and reg_saved tables in 59 struct nios2_unwind_cache, respectively. */ 60 61/* struct reg_value is used to record that a register has the same value 62 as reg at the given offset from the start of a function. */ 63 64struct reg_value 65{ 66 int reg; 67 unsigned int offset; 68}; 69 70/* struct reg_saved is used to record that a register value has been saved at 71 basereg + addr, for basereg >= 0. If basereg < 0, that indicates 72 that the register is not known to have been saved. Note that when 73 basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0), 74 addr is an absolute address. */ 75 76struct reg_saved 77{ 78 int basereg; 79 CORE_ADDR addr; 80}; 81 82struct nios2_unwind_cache 83{ 84 /* The frame's base, optionally used by the high-level debug info. */ 85 CORE_ADDR base; 86 87 /* The previous frame's inner most stack address. Used as this 88 frame ID's stack_addr. */ 89 CORE_ADDR cfa; 90 91 /* The address of the first instruction in this function. */ 92 CORE_ADDR pc; 93 94 /* Which register holds the return address for the frame. */ 95 int return_regnum; 96 97 /* Table indicating what changes have been made to each register. */ 98 struct reg_value reg_value[NIOS2_NUM_REGS]; 99 100 /* Table indicating where each register has been saved. */ 101 struct reg_saved reg_saved[NIOS2_NUM_REGS]; 102}; 103 104 105/* This array is a mapping from Dwarf-2 register numbering to GDB's. */ 106 107static int nios2_dwarf2gdb_regno_map[] = 108{ 109 0, 1, 2, 3, 110 4, 5, 6, 7, 111 8, 9, 10, 11, 112 12, 13, 14, 15, 113 16, 17, 18, 19, 114 20, 21, 22, 23, 115 24, 25, 116 NIOS2_GP_REGNUM, /* 26 */ 117 NIOS2_SP_REGNUM, /* 27 */ 118 NIOS2_FP_REGNUM, /* 28 */ 119 NIOS2_EA_REGNUM, /* 29 */ 120 NIOS2_BA_REGNUM, /* 30 */ 121 NIOS2_RA_REGNUM, /* 31 */ 122 NIOS2_PC_REGNUM, /* 32 */ 123 NIOS2_STATUS_REGNUM, /* 33 */ 124 NIOS2_ESTATUS_REGNUM, /* 34 */ 125 NIOS2_BSTATUS_REGNUM, /* 35 */ 126 NIOS2_IENABLE_REGNUM, /* 36 */ 127 NIOS2_IPENDING_REGNUM, /* 37 */ 128 NIOS2_CPUID_REGNUM, /* 38 */ 129 39, /* CTL6 */ /* 39 */ 130 NIOS2_EXCEPTION_REGNUM, /* 40 */ 131 NIOS2_PTEADDR_REGNUM, /* 41 */ 132 NIOS2_TLBACC_REGNUM, /* 42 */ 133 NIOS2_TLBMISC_REGNUM, /* 43 */ 134 NIOS2_ECCINJ_REGNUM, /* 44 */ 135 NIOS2_BADADDR_REGNUM, /* 45 */ 136 NIOS2_CONFIG_REGNUM, /* 46 */ 137 NIOS2_MPUBASE_REGNUM, /* 47 */ 138 NIOS2_MPUACC_REGNUM /* 48 */ 139}; 140 141gdb_static_assert (ARRAY_SIZE (nios2_dwarf2gdb_regno_map) == NIOS2_NUM_REGS); 142 143/* Implement the dwarf2_reg_to_regnum gdbarch method. */ 144 145static int 146nios2_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg) 147{ 148 if (dw_reg < 0 || dw_reg >= NIOS2_NUM_REGS) 149 return -1; 150 151 return nios2_dwarf2gdb_regno_map[dw_reg]; 152} 153 154/* Canonical names for the 49 registers. */ 155 156static const char *const nios2_reg_names[NIOS2_NUM_REGS] = 157{ 158 "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", 159 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 160 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 161 "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra", 162 "pc", 163 "status", "estatus", "bstatus", "ienable", 164 "ipending", "cpuid", "ctl6", "exception", 165 "pteaddr", "tlbacc", "tlbmisc", "eccinj", 166 "badaddr", "config", "mpubase", "mpuacc" 167}; 168 169/* Implement the register_name gdbarch method. */ 170 171static const char * 172nios2_register_name (struct gdbarch *gdbarch, int regno) 173{ 174 /* Use mnemonic aliases for GPRs. */ 175 if (regno >= 0 && regno < NIOS2_NUM_REGS) 176 return nios2_reg_names[regno]; 177 else 178 return tdesc_register_name (gdbarch, regno); 179} 180 181/* Implement the register_type gdbarch method. */ 182 183static struct type * 184nios2_register_type (struct gdbarch *gdbarch, int regno) 185{ 186 /* If the XML description has register information, use that to 187 determine the register type. */ 188 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 189 return tdesc_register_type (gdbarch, regno); 190 191 if (regno == NIOS2_PC_REGNUM) 192 return builtin_type (gdbarch)->builtin_func_ptr; 193 else if (regno == NIOS2_SP_REGNUM) 194 return builtin_type (gdbarch)->builtin_data_ptr; 195 else 196 return builtin_type (gdbarch)->builtin_uint32; 197} 198 199/* Given a return value in REGCACHE with a type VALTYPE, 200 extract and copy its value into VALBUF. */ 201 202static void 203nios2_extract_return_value (struct gdbarch *gdbarch, struct type *valtype, 204 struct regcache *regcache, gdb_byte *valbuf) 205{ 206 int len = TYPE_LENGTH (valtype); 207 208 /* Return values of up to 8 bytes are returned in $r2 $r3. */ 209 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) 210 regcache->cooked_read (NIOS2_R2_REGNUM, valbuf); 211 else 212 { 213 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) 214 + register_size (gdbarch, NIOS2_R3_REGNUM))); 215 regcache->cooked_read (NIOS2_R2_REGNUM, valbuf); 216 regcache->cooked_read (NIOS2_R3_REGNUM, valbuf + 4); 217 } 218} 219 220/* Write into appropriate registers a function return value 221 of type TYPE, given in virtual format. */ 222 223static void 224nios2_store_return_value (struct gdbarch *gdbarch, struct type *valtype, 225 struct regcache *regcache, const gdb_byte *valbuf) 226{ 227 int len = TYPE_LENGTH (valtype); 228 229 /* Return values of up to 8 bytes are returned in $r2 $r3. */ 230 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) 231 regcache->cooked_write (NIOS2_R2_REGNUM, valbuf); 232 else 233 { 234 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) 235 + register_size (gdbarch, NIOS2_R3_REGNUM))); 236 regcache->cooked_write (NIOS2_R2_REGNUM, valbuf); 237 regcache->cooked_write (NIOS2_R3_REGNUM, valbuf + 4); 238 } 239} 240 241 242/* Set up the default values of the registers. */ 243 244static void 245nios2_setup_default (struct nios2_unwind_cache *cache) 246{ 247 int i; 248 249 for (i = 0; i < NIOS2_NUM_REGS; i++) 250 { 251 /* All registers start off holding their previous values. */ 252 cache->reg_value[i].reg = i; 253 cache->reg_value[i].offset = 0; 254 255 /* All registers start off not saved. */ 256 cache->reg_saved[i].basereg = -1; 257 cache->reg_saved[i].addr = 0; 258 } 259} 260 261/* Initialize the unwind cache. */ 262 263static void 264nios2_init_cache (struct nios2_unwind_cache *cache, CORE_ADDR pc) 265{ 266 cache->base = 0; 267 cache->cfa = 0; 268 cache->pc = pc; 269 cache->return_regnum = NIOS2_RA_REGNUM; 270 nios2_setup_default (cache); 271} 272 273/* Read and identify an instruction at PC. If INSNP is non-null, 274 store the instruction word into that location. Return the opcode 275 pointer or NULL if the memory couldn't be read or disassembled. */ 276 277static const struct nios2_opcode * 278nios2_fetch_insn (struct gdbarch *gdbarch, CORE_ADDR pc, 279 unsigned int *insnp) 280{ 281 LONGEST memword; 282 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 283 unsigned int insn; 284 285 if (mach == bfd_mach_nios2r2) 286 { 287 if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE, 288 BFD_ENDIAN_LITTLE, &memword) 289 && !safe_read_memory_integer (pc, NIOS2_CDX_OPCODE_SIZE, 290 BFD_ENDIAN_LITTLE, &memword)) 291 return NULL; 292 } 293 else if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE, 294 gdbarch_byte_order (gdbarch), &memword)) 295 return NULL; 296 297 insn = (unsigned int) memword; 298 if (insnp) 299 *insnp = insn; 300 return nios2_find_opcode_hash (insn, mach); 301} 302 303 304/* Match and disassemble an ADD-type instruction, with 3 register operands. 305 Returns true on success, and fills in the operand pointers. */ 306 307static int 308nios2_match_add (uint32_t insn, const struct nios2_opcode *op, 309 unsigned long mach, int *ra, int *rb, int *rc) 310{ 311 int is_r2 = (mach == bfd_mach_nios2r2); 312 313 if (!is_r2 && (op->match == MATCH_R1_ADD || op->match == MATCH_R1_MOV)) 314 { 315 *ra = GET_IW_R_A (insn); 316 *rb = GET_IW_R_B (insn); 317 *rc = GET_IW_R_C (insn); 318 return 1; 319 } 320 else if (!is_r2) 321 return 0; 322 else if (op->match == MATCH_R2_ADD || op->match == MATCH_R2_MOV) 323 { 324 *ra = GET_IW_F3X6L5_A (insn); 325 *rb = GET_IW_F3X6L5_B (insn); 326 *rc = GET_IW_F3X6L5_C (insn); 327 return 1; 328 } 329 else if (op->match == MATCH_R2_ADD_N) 330 { 331 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)]; 332 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)]; 333 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)]; 334 return 1; 335 } 336 else if (op->match == MATCH_R2_MOV_N) 337 { 338 *ra = GET_IW_F2_A (insn); 339 *rb = 0; 340 *rc = GET_IW_F2_B (insn); 341 return 1; 342 } 343 return 0; 344} 345 346/* Match and disassemble a SUB-type instruction, with 3 register operands. 347 Returns true on success, and fills in the operand pointers. */ 348 349static int 350nios2_match_sub (uint32_t insn, const struct nios2_opcode *op, 351 unsigned long mach, int *ra, int *rb, int *rc) 352{ 353 int is_r2 = (mach == bfd_mach_nios2r2); 354 355 if (!is_r2 && op->match == MATCH_R1_SUB) 356 { 357 *ra = GET_IW_R_A (insn); 358 *rb = GET_IW_R_B (insn); 359 *rc = GET_IW_R_C (insn); 360 return 1; 361 } 362 else if (!is_r2) 363 return 0; 364 else if (op->match == MATCH_R2_SUB) 365 { 366 *ra = GET_IW_F3X6L5_A (insn); 367 *rb = GET_IW_F3X6L5_B (insn); 368 *rc = GET_IW_F3X6L5_C (insn); 369 return 1; 370 } 371 else if (op->match == MATCH_R2_SUB_N) 372 { 373 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)]; 374 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)]; 375 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)]; 376 return 1; 377 } 378 return 0; 379} 380 381/* Match and disassemble an ADDI-type instruction, with 2 register operands 382 and one immediate operand. 383 Returns true on success, and fills in the operand pointers. */ 384 385static int 386nios2_match_addi (uint32_t insn, const struct nios2_opcode *op, 387 unsigned long mach, int *ra, int *rb, int *imm) 388{ 389 int is_r2 = (mach == bfd_mach_nios2r2); 390 391 if (!is_r2 && op->match == MATCH_R1_ADDI) 392 { 393 *ra = GET_IW_I_A (insn); 394 *rb = GET_IW_I_B (insn); 395 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 396 return 1; 397 } 398 else if (!is_r2) 399 return 0; 400 else if (op->match == MATCH_R2_ADDI) 401 { 402 *ra = GET_IW_F2I16_A (insn); 403 *rb = GET_IW_F2I16_B (insn); 404 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 405 return 1; 406 } 407 else if (op->match == MATCH_R2_ADDI_N || op->match == MATCH_R2_SUBI_N) 408 { 409 *ra = nios2_r2_reg3_mappings[GET_IW_T2X1I3_A3 (insn)]; 410 *rb = nios2_r2_reg3_mappings[GET_IW_T2X1I3_B3 (insn)]; 411 *imm = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (insn)]; 412 if (op->match == MATCH_R2_SUBI_N) 413 *imm = - (*imm); 414 return 1; 415 } 416 else if (op->match == MATCH_R2_SPADDI_N) 417 { 418 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 419 *rb = NIOS2_SP_REGNUM; 420 *imm = GET_IW_T1I7_IMM7 (insn) << 2; 421 return 1; 422 } 423 else if (op->match == MATCH_R2_SPINCI_N || op->match == MATCH_R2_SPDECI_N) 424 { 425 *ra = NIOS2_SP_REGNUM; 426 *rb = NIOS2_SP_REGNUM; 427 *imm = GET_IW_X1I7_IMM7 (insn) << 2; 428 if (op->match == MATCH_R2_SPDECI_N) 429 *imm = - (*imm); 430 return 1; 431 } 432 return 0; 433} 434 435/* Match and disassemble an ORHI-type instruction, with 2 register operands 436 and one unsigned immediate operand. 437 Returns true on success, and fills in the operand pointers. */ 438 439static int 440nios2_match_orhi (uint32_t insn, const struct nios2_opcode *op, 441 unsigned long mach, int *ra, int *rb, unsigned int *uimm) 442{ 443 int is_r2 = (mach == bfd_mach_nios2r2); 444 445 if (!is_r2 && op->match == MATCH_R1_ORHI) 446 { 447 *ra = GET_IW_I_A (insn); 448 *rb = GET_IW_I_B (insn); 449 *uimm = GET_IW_I_IMM16 (insn); 450 return 1; 451 } 452 else if (!is_r2) 453 return 0; 454 else if (op->match == MATCH_R2_ORHI) 455 { 456 *ra = GET_IW_F2I16_A (insn); 457 *rb = GET_IW_F2I16_B (insn); 458 *uimm = GET_IW_F2I16_IMM16 (insn); 459 return 1; 460 } 461 return 0; 462} 463 464/* Match and disassemble a STW-type instruction, with 2 register operands 465 and one immediate operand. 466 Returns true on success, and fills in the operand pointers. */ 467 468static int 469nios2_match_stw (uint32_t insn, const struct nios2_opcode *op, 470 unsigned long mach, int *ra, int *rb, int *imm) 471{ 472 int is_r2 = (mach == bfd_mach_nios2r2); 473 474 if (!is_r2 && (op->match == MATCH_R1_STW || op->match == MATCH_R1_STWIO)) 475 { 476 *ra = GET_IW_I_A (insn); 477 *rb = GET_IW_I_B (insn); 478 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 479 return 1; 480 } 481 else if (!is_r2) 482 return 0; 483 else if (op->match == MATCH_R2_STW) 484 { 485 *ra = GET_IW_F2I16_A (insn); 486 *rb = GET_IW_F2I16_B (insn); 487 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 488 return 1; 489 } 490 else if (op->match == MATCH_R2_STWIO) 491 { 492 *ra = GET_IW_F2X4I12_A (insn); 493 *rb = GET_IW_F2X4I12_B (insn); 494 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20; 495 return 1; 496 } 497 else if (op->match == MATCH_R2_STW_N) 498 { 499 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)]; 500 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)]; 501 *imm = GET_IW_T2I4_IMM4 (insn) << 2; 502 return 1; 503 } 504 else if (op->match == MATCH_R2_STWSP_N) 505 { 506 *ra = NIOS2_SP_REGNUM; 507 *rb = GET_IW_F1I5_B (insn); 508 *imm = GET_IW_F1I5_IMM5 (insn) << 2; 509 return 1; 510 } 511 else if (op->match == MATCH_R2_STWZ_N) 512 { 513 *ra = nios2_r2_reg3_mappings[GET_IW_T1X1I6_A3 (insn)]; 514 *rb = 0; 515 *imm = GET_IW_T1X1I6_IMM6 (insn) << 2; 516 return 1; 517 } 518 return 0; 519} 520 521/* Match and disassemble a LDW-type instruction, with 2 register operands 522 and one immediate operand. 523 Returns true on success, and fills in the operand pointers. */ 524 525static int 526nios2_match_ldw (uint32_t insn, const struct nios2_opcode *op, 527 unsigned long mach, int *ra, int *rb, int *imm) 528{ 529 int is_r2 = (mach == bfd_mach_nios2r2); 530 531 if (!is_r2 && (op->match == MATCH_R1_LDW || op->match == MATCH_R1_LDWIO)) 532 { 533 *ra = GET_IW_I_A (insn); 534 *rb = GET_IW_I_B (insn); 535 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 536 return 1; 537 } 538 else if (!is_r2) 539 return 0; 540 else if (op->match == MATCH_R2_LDW) 541 { 542 *ra = GET_IW_F2I16_A (insn); 543 *rb = GET_IW_F2I16_B (insn); 544 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 545 return 1; 546 } 547 else if (op->match == MATCH_R2_LDWIO) 548 { 549 *ra = GET_IW_F2X4I12_A (insn); 550 *rb = GET_IW_F2X4I12_B (insn); 551 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20; 552 return 1; 553 } 554 else if (op->match == MATCH_R2_LDW_N) 555 { 556 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)]; 557 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)]; 558 *imm = GET_IW_T2I4_IMM4 (insn) << 2; 559 return 1; 560 } 561 else if (op->match == MATCH_R2_LDWSP_N) 562 { 563 *ra = NIOS2_SP_REGNUM; 564 *rb = GET_IW_F1I5_B (insn); 565 *imm = GET_IW_F1I5_IMM5 (insn) << 2; 566 return 1; 567 } 568 return 0; 569} 570 571/* Match and disassemble a RDCTL instruction, with 2 register operands. 572 Returns true on success, and fills in the operand pointers. */ 573 574static int 575nios2_match_rdctl (uint32_t insn, const struct nios2_opcode *op, 576 unsigned long mach, int *ra, int *rc) 577{ 578 int is_r2 = (mach == bfd_mach_nios2r2); 579 580 if (!is_r2 && (op->match == MATCH_R1_RDCTL)) 581 { 582 *ra = GET_IW_R_IMM5 (insn); 583 *rc = GET_IW_R_C (insn); 584 return 1; 585 } 586 else if (!is_r2) 587 return 0; 588 else if (op->match == MATCH_R2_RDCTL) 589 { 590 *ra = GET_IW_F3X6L5_IMM5 (insn); 591 *rc = GET_IW_F3X6L5_C (insn); 592 return 1; 593 } 594 return 0; 595} 596 597/* Match and disassemble a PUSH.N or STWM instruction. 598 Returns true on success, and fills in the operand pointers. */ 599 600static int 601nios2_match_stwm (uint32_t insn, const struct nios2_opcode *op, 602 unsigned long mach, unsigned int *reglist, 603 int *ra, int *imm, int *wb, int *id) 604{ 605 int is_r2 = (mach == bfd_mach_nios2r2); 606 607 if (!is_r2) 608 return 0; 609 else if (op->match == MATCH_R2_PUSH_N) 610 { 611 *reglist = 1 << 31; 612 if (GET_IW_L5I4X1_FP (insn)) 613 *reglist |= (1 << 28); 614 if (GET_IW_L5I4X1_CS (insn)) 615 { 616 int val = GET_IW_L5I4X1_REGRANGE (insn); 617 *reglist |= nios2_r2_reg_range_mappings[val]; 618 } 619 *ra = NIOS2_SP_REGNUM; 620 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2; 621 *wb = 1; 622 *id = 0; 623 return 1; 624 } 625 else if (op->match == MATCH_R2_STWM) 626 { 627 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn); 628 if (GET_IW_F1X4L17_RS (insn)) 629 { 630 *reglist = ((rawmask << 14) & 0x00ffc000); 631 if (rawmask & (1 << 10)) 632 *reglist |= (1 << 28); 633 if (rawmask & (1 << 11)) 634 *reglist |= (1 << 31); 635 } 636 else 637 *reglist = rawmask << 2; 638 *ra = GET_IW_F1X4L17_A (insn); 639 *imm = 0; 640 *wb = GET_IW_F1X4L17_WB (insn); 641 *id = GET_IW_F1X4L17_ID (insn); 642 return 1; 643 } 644 return 0; 645} 646 647/* Match and disassemble a POP.N or LDWM instruction. 648 Returns true on success, and fills in the operand pointers. */ 649 650static int 651nios2_match_ldwm (uint32_t insn, const struct nios2_opcode *op, 652 unsigned long mach, unsigned int *reglist, 653 int *ra, int *imm, int *wb, int *id, int *ret) 654{ 655 int is_r2 = (mach == bfd_mach_nios2r2); 656 657 if (!is_r2) 658 return 0; 659 else if (op->match == MATCH_R2_POP_N) 660 { 661 *reglist = 1 << 31; 662 if (GET_IW_L5I4X1_FP (insn)) 663 *reglist |= (1 << 28); 664 if (GET_IW_L5I4X1_CS (insn)) 665 { 666 int val = GET_IW_L5I4X1_REGRANGE (insn); 667 *reglist |= nios2_r2_reg_range_mappings[val]; 668 } 669 *ra = NIOS2_SP_REGNUM; 670 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2; 671 *wb = 1; 672 *id = 1; 673 *ret = 1; 674 return 1; 675 } 676 else if (op->match == MATCH_R2_LDWM) 677 { 678 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn); 679 if (GET_IW_F1X4L17_RS (insn)) 680 { 681 *reglist = ((rawmask << 14) & 0x00ffc000); 682 if (rawmask & (1 << 10)) 683 *reglist |= (1 << 28); 684 if (rawmask & (1 << 11)) 685 *reglist |= (1 << 31); 686 } 687 else 688 *reglist = rawmask << 2; 689 *ra = GET_IW_F1X4L17_A (insn); 690 *imm = 0; 691 *wb = GET_IW_F1X4L17_WB (insn); 692 *id = GET_IW_F1X4L17_ID (insn); 693 *ret = GET_IW_F1X4L17_PC (insn); 694 return 1; 695 } 696 return 0; 697} 698 699/* Match and disassemble a branch instruction, with (potentially) 700 2 register operands and one immediate operand. 701 Returns true on success, and fills in the operand pointers. */ 702 703enum branch_condition { 704 branch_none, 705 branch_eq, 706 branch_ne, 707 branch_ge, 708 branch_geu, 709 branch_lt, 710 branch_ltu 711}; 712 713static int 714nios2_match_branch (uint32_t insn, const struct nios2_opcode *op, 715 unsigned long mach, int *ra, int *rb, int *imm, 716 enum branch_condition *cond) 717{ 718 int is_r2 = (mach == bfd_mach_nios2r2); 719 720 if (!is_r2) 721 { 722 switch (op->match) 723 { 724 case MATCH_R1_BR: 725 *cond = branch_none; 726 break; 727 case MATCH_R1_BEQ: 728 *cond = branch_eq; 729 break; 730 case MATCH_R1_BNE: 731 *cond = branch_ne; 732 break; 733 case MATCH_R1_BGE: 734 *cond = branch_ge; 735 break; 736 case MATCH_R1_BGEU: 737 *cond = branch_geu; 738 break; 739 case MATCH_R1_BLT: 740 *cond = branch_lt; 741 break; 742 case MATCH_R1_BLTU: 743 *cond = branch_ltu; 744 break; 745 default: 746 return 0; 747 } 748 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 749 *ra = GET_IW_I_A (insn); 750 *rb = GET_IW_I_B (insn); 751 return 1; 752 } 753 else 754 { 755 switch (op->match) 756 { 757 case MATCH_R2_BR_N: 758 *cond = branch_none; 759 *ra = NIOS2_Z_REGNUM; 760 *rb = NIOS2_Z_REGNUM; 761 *imm = (signed) ((GET_IW_I10_IMM10 (insn) << 1) << 21) >> 21; 762 return 1; 763 case MATCH_R2_BEQZ_N: 764 *cond = branch_eq; 765 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 766 *rb = NIOS2_Z_REGNUM; 767 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24; 768 return 1; 769 case MATCH_R2_BNEZ_N: 770 *cond = branch_ne; 771 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 772 *rb = NIOS2_Z_REGNUM; 773 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24; 774 return 1; 775 case MATCH_R2_BR: 776 *cond = branch_none; 777 break; 778 case MATCH_R2_BEQ: 779 *cond = branch_eq; 780 break; 781 case MATCH_R2_BNE: 782 *cond = branch_ne; 783 break; 784 case MATCH_R2_BGE: 785 *cond = branch_ge; 786 break; 787 case MATCH_R2_BGEU: 788 *cond = branch_geu; 789 break; 790 case MATCH_R2_BLT: 791 *cond = branch_lt; 792 break; 793 case MATCH_R2_BLTU: 794 *cond = branch_ltu; 795 break; 796 default: 797 return 0; 798 } 799 *ra = GET_IW_F2I16_A (insn); 800 *rb = GET_IW_F2I16_B (insn); 801 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 802 return 1; 803 } 804 return 0; 805} 806 807/* Match and disassemble a direct jump instruction, with an 808 unsigned operand. Returns true on success, and fills in the operand 809 pointer. */ 810 811static int 812nios2_match_jmpi (uint32_t insn, const struct nios2_opcode *op, 813 unsigned long mach, unsigned int *uimm) 814{ 815 int is_r2 = (mach == bfd_mach_nios2r2); 816 817 if (!is_r2 && op->match == MATCH_R1_JMPI) 818 { 819 *uimm = GET_IW_J_IMM26 (insn) << 2; 820 return 1; 821 } 822 else if (!is_r2) 823 return 0; 824 else if (op->match == MATCH_R2_JMPI) 825 { 826 *uimm = GET_IW_L26_IMM26 (insn) << 2; 827 return 1; 828 } 829 return 0; 830} 831 832/* Match and disassemble a direct call instruction, with an 833 unsigned operand. Returns true on success, and fills in the operand 834 pointer. */ 835 836static int 837nios2_match_calli (uint32_t insn, const struct nios2_opcode *op, 838 unsigned long mach, unsigned int *uimm) 839{ 840 int is_r2 = (mach == bfd_mach_nios2r2); 841 842 if (!is_r2 && op->match == MATCH_R1_CALL) 843 { 844 *uimm = GET_IW_J_IMM26 (insn) << 2; 845 return 1; 846 } 847 else if (!is_r2) 848 return 0; 849 else if (op->match == MATCH_R2_CALL) 850 { 851 *uimm = GET_IW_L26_IMM26 (insn) << 2; 852 return 1; 853 } 854 return 0; 855} 856 857/* Match and disassemble an indirect jump instruction, with a 858 (possibly implicit) register operand. Returns true on success, and fills 859 in the operand pointer. */ 860 861static int 862nios2_match_jmpr (uint32_t insn, const struct nios2_opcode *op, 863 unsigned long mach, int *ra) 864{ 865 int is_r2 = (mach == bfd_mach_nios2r2); 866 867 if (!is_r2) 868 switch (op->match) 869 { 870 case MATCH_R1_JMP: 871 *ra = GET_IW_I_A (insn); 872 return 1; 873 case MATCH_R1_RET: 874 *ra = NIOS2_RA_REGNUM; 875 return 1; 876 case MATCH_R1_ERET: 877 *ra = NIOS2_EA_REGNUM; 878 return 1; 879 case MATCH_R1_BRET: 880 *ra = NIOS2_BA_REGNUM; 881 return 1; 882 default: 883 return 0; 884 } 885 else 886 switch (op->match) 887 { 888 case MATCH_R2_JMP: 889 *ra = GET_IW_F2I16_A (insn); 890 return 1; 891 case MATCH_R2_JMPR_N: 892 *ra = GET_IW_F1X1_A (insn); 893 return 1; 894 case MATCH_R2_RET: 895 case MATCH_R2_RET_N: 896 *ra = NIOS2_RA_REGNUM; 897 return 1; 898 case MATCH_R2_ERET: 899 *ra = NIOS2_EA_REGNUM; 900 return 1; 901 case MATCH_R2_BRET: 902 *ra = NIOS2_BA_REGNUM; 903 return 1; 904 default: 905 return 0; 906 } 907 return 0; 908} 909 910/* Match and disassemble an indirect call instruction, with a register 911 operand. Returns true on success, and fills in the operand pointer. */ 912 913static int 914nios2_match_callr (uint32_t insn, const struct nios2_opcode *op, 915 unsigned long mach, int *ra) 916{ 917 int is_r2 = (mach == bfd_mach_nios2r2); 918 919 if (!is_r2 && op->match == MATCH_R1_CALLR) 920 { 921 *ra = GET_IW_I_A (insn); 922 return 1; 923 } 924 else if (!is_r2) 925 return 0; 926 else if (op->match == MATCH_R2_CALLR) 927 { 928 *ra = GET_IW_F2I16_A (insn); 929 return 1; 930 } 931 else if (op->match == MATCH_R2_CALLR_N) 932 { 933 *ra = GET_IW_F1X1_A (insn); 934 return 1; 935 } 936 return 0; 937} 938 939/* Match and disassemble a break instruction, with an unsigned operand. 940 Returns true on success, and fills in the operand pointer. */ 941 942static int 943nios2_match_break (uint32_t insn, const struct nios2_opcode *op, 944 unsigned long mach, unsigned int *uimm) 945{ 946 int is_r2 = (mach == bfd_mach_nios2r2); 947 948 if (!is_r2 && op->match == MATCH_R1_BREAK) 949 { 950 *uimm = GET_IW_R_IMM5 (insn); 951 return 1; 952 } 953 else if (!is_r2) 954 return 0; 955 else if (op->match == MATCH_R2_BREAK) 956 { 957 *uimm = GET_IW_F3X6L5_IMM5 (insn); 958 return 1; 959 } 960 else if (op->match == MATCH_R2_BREAK_N) 961 { 962 *uimm = GET_IW_X2L5_IMM5 (insn); 963 return 1; 964 } 965 return 0; 966} 967 968/* Match and disassemble a trap instruction, with an unsigned operand. 969 Returns true on success, and fills in the operand pointer. */ 970 971static int 972nios2_match_trap (uint32_t insn, const struct nios2_opcode *op, 973 unsigned long mach, unsigned int *uimm) 974{ 975 int is_r2 = (mach == bfd_mach_nios2r2); 976 977 if (!is_r2 && op->match == MATCH_R1_TRAP) 978 { 979 *uimm = GET_IW_R_IMM5 (insn); 980 return 1; 981 } 982 else if (!is_r2) 983 return 0; 984 else if (op->match == MATCH_R2_TRAP) 985 { 986 *uimm = GET_IW_F3X6L5_IMM5 (insn); 987 return 1; 988 } 989 else if (op->match == MATCH_R2_TRAP_N) 990 { 991 *uimm = GET_IW_X2L5_IMM5 (insn); 992 return 1; 993 } 994 return 0; 995} 996 997/* Helper function to identify when we're in a function epilogue; 998 that is, the part of the function from the point at which the 999 stack adjustments are made, to the return or sibcall. 1000 Note that we may have several stack adjustment instructions, and 1001 this function needs to test whether the stack teardown has already 1002 started before current_pc, not whether it has completed. */ 1003 1004static int 1005nios2_in_epilogue_p (struct gdbarch *gdbarch, 1006 CORE_ADDR current_pc, 1007 CORE_ADDR start_pc) 1008{ 1009 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1010 int is_r2 = (mach == bfd_mach_nios2r2); 1011 /* Maximum number of possibly-epilogue instructions to check. 1012 Note that this number should not be too large, else we can 1013 potentially end up iterating through unmapped memory. */ 1014 int ninsns, max_insns = 5; 1015 unsigned int insn; 1016 const struct nios2_opcode *op = NULL; 1017 unsigned int uimm; 1018 int imm; 1019 int wb, id, ret; 1020 int ra, rb, rc; 1021 enum branch_condition cond; 1022 CORE_ADDR pc; 1023 1024 /* There has to be a previous instruction in the function. */ 1025 if (current_pc <= start_pc) 1026 return 0; 1027 1028 /* Find the previous instruction before current_pc. For R2, it might 1029 be either a 16-bit or 32-bit instruction; the only way to know for 1030 sure is to scan through from the beginning of the function, 1031 disassembling as we go. */ 1032 if (is_r2) 1033 for (pc = start_pc; ; ) 1034 { 1035 op = nios2_fetch_insn (gdbarch, pc, &insn); 1036 if (op == NULL) 1037 return 0; 1038 if (pc + op->size < current_pc) 1039 pc += op->size; 1040 else 1041 break; 1042 /* We can skip over insns to a forward branch target. Since 1043 the branch offset is relative to the next instruction, 1044 it's correct to do this after incrementing the pc above. */ 1045 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond) 1046 && imm > 0 1047 && pc + imm < current_pc) 1048 pc += imm; 1049 } 1050 /* Otherwise just go back to the previous 32-bit insn. */ 1051 else 1052 pc = current_pc - NIOS2_OPCODE_SIZE; 1053 1054 /* Beginning with the previous instruction we just located, check whether 1055 we are in a sequence of at least one stack adjustment instruction. 1056 Possible instructions here include: 1057 ADDI sp, sp, n 1058 ADD sp, sp, rn 1059 LDW sp, n(sp) 1060 SPINCI.N n 1061 LDWSP.N sp, n(sp) 1062 LDWM {reglist}, (sp)++, wb */ 1063 for (ninsns = 0; ninsns < max_insns; ninsns++) 1064 { 1065 int ok = 0; 1066 1067 /* Fetch the insn at pc. */ 1068 op = nios2_fetch_insn (gdbarch, pc, &insn); 1069 if (op == NULL) 1070 return 0; 1071 pc += op->size; 1072 1073 /* Was it a stack adjustment? */ 1074 if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) 1075 ok = (rb == NIOS2_SP_REGNUM); 1076 else if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) 1077 ok = (rc == NIOS2_SP_REGNUM); 1078 else if (nios2_match_ldw (insn, op, mach, &ra, &rb, &imm)) 1079 ok = (rb == NIOS2_SP_REGNUM); 1080 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, 1081 &imm, &wb, &ret, &id)) 1082 ok = (ra == NIOS2_SP_REGNUM && wb && id); 1083 if (!ok) 1084 break; 1085 } 1086 1087 /* No stack adjustments found. */ 1088 if (ninsns == 0) 1089 return 0; 1090 1091 /* We found more stack adjustments than we expect GCC to be generating. 1092 Since it looks like a stack unwind might be in progress tell GDB to 1093 treat it as such. */ 1094 if (ninsns == max_insns) 1095 return 1; 1096 1097 /* The next instruction following the stack adjustments must be a 1098 return, jump, or unconditional branch, or a CDX pop.n or ldwm 1099 that does an implicit return. */ 1100 if (nios2_match_jmpr (insn, op, mach, &ra) 1101 || nios2_match_jmpi (insn, op, mach, &uimm) 1102 || (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret) 1103 && ret) 1104 || (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond) 1105 && cond == branch_none)) 1106 return 1; 1107 1108 return 0; 1109} 1110 1111/* Implement the stack_frame_destroyed_p gdbarch method. */ 1112 1113static int 1114nios2_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 1115{ 1116 CORE_ADDR func_addr; 1117 1118 if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) 1119 return nios2_in_epilogue_p (gdbarch, pc, func_addr); 1120 1121 return 0; 1122} 1123 1124/* Do prologue analysis, returning the PC of the first instruction 1125 after the function prologue. Assumes CACHE has already been 1126 initialized. THIS_FRAME can be null, in which case we are only 1127 interested in skipping the prologue. Otherwise CACHE is filled in 1128 from the frame information. 1129 1130 The prologue may consist of the following parts: 1131 1) Profiling instrumentation. For non-PIC code it looks like: 1132 mov r8, ra 1133 call mcount 1134 mov ra, r8 1135 1136 2) A stack adjustment and save of R4-R7 for varargs functions. 1137 For R2 CDX this is typically handled with a STWM, otherwise 1138 this is typically merged with item 3. 1139 1140 3) A stack adjustment and save of the callee-saved registers. 1141 For R2 CDX these are typically handled with a PUSH.N or STWM, 1142 otherwise as an explicit SP decrement and individual register 1143 saves. 1144 1145 There may also be a stack switch here in an exception handler 1146 in place of a stack adjustment. It looks like: 1147 movhi rx, %hiadj(newstack) 1148 addhi rx, rx, %lo(newstack) 1149 stw sp, constant(rx) 1150 mov sp, rx 1151 1152 4) A frame pointer save, which can be either a MOV or ADDI. 1153 1154 5) A further stack pointer adjustment. This is normally included 1155 adjustment in step 3 unless the total adjustment is too large 1156 to be done in one step. 1157 1158 7) A stack overflow check, which can take either of these forms: 1159 bgeu sp, rx, +8 1160 trap 3 1161 or 1162 bltu sp, rx, .Lstack_overflow 1163 ... 1164 .Lstack_overflow: 1165 trap 3 1166 1167 Older versions of GCC emitted "break 3" instead of "trap 3" here, 1168 so we check for both cases. 1169 1170 Older GCC versions emitted stack overflow checks after the SP 1171 adjustments in both steps 3 and 4. Starting with GCC 6, there is 1172 at most one overflow check, which is placed before the first 1173 stack adjustment for R2 CDX and after the first stack adjustment 1174 otherwise. 1175 1176 The prologue instructions may be combined or interleaved with other 1177 instructions. 1178 1179 To cope with all this variability we decode all the instructions 1180 from the start of the prologue until we hit an instruction that 1181 cannot possibly be a prologue instruction, such as a branch, call, 1182 return, or epilogue instruction. The prologue is considered to end 1183 at the last instruction that can definitely be considered a 1184 prologue instruction. */ 1185 1186static CORE_ADDR 1187nios2_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, 1188 const CORE_ADDR current_pc, 1189 struct nios2_unwind_cache *cache, 1190 struct frame_info *this_frame) 1191{ 1192 /* Maximum number of possibly-prologue instructions to check. 1193 Note that this number should not be too large, else we can 1194 potentially end up iterating through unmapped memory. */ 1195 int ninsns, max_insns = 50; 1196 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1197 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1198 1199 /* Does the frame set up the FP register? */ 1200 int base_reg = 0; 1201 1202 struct reg_value *value = cache->reg_value; 1203 struct reg_value temp_value[NIOS2_NUM_REGS]; 1204 1205 /* Save the starting PC so we can correct the pc after running 1206 through the prolog, using symbol info. */ 1207 CORE_ADDR pc = start_pc; 1208 1209 /* Is this an exception handler? */ 1210 int exception_handler = 0; 1211 1212 /* What was the original value of SP (or fake original value for 1213 functions which switch stacks? */ 1214 CORE_ADDR frame_high; 1215 1216 /* The last definitely-prologue instruction seen. */ 1217 CORE_ADDR prologue_end; 1218 1219 /* Is this the innermost function? */ 1220 int innermost = (this_frame ? (frame_relative_level (this_frame) == 0) : 1); 1221 1222 if (nios2_debug) 1223 fprintf_unfiltered (gdb_stdlog, 1224 "{ nios2_analyze_prologue start=%s, current=%s ", 1225 paddress (gdbarch, start_pc), 1226 paddress (gdbarch, current_pc)); 1227 1228 /* Set up the default values of the registers. */ 1229 nios2_setup_default (cache); 1230 1231 /* Find the prologue instructions. */ 1232 prologue_end = start_pc; 1233 for (ninsns = 0; ninsns < max_insns; ninsns++) 1234 { 1235 /* Present instruction. */ 1236 uint32_t insn; 1237 const struct nios2_opcode *op; 1238 int ra, rb, rc, imm; 1239 unsigned int uimm; 1240 unsigned int reglist; 1241 int wb, id, ret; 1242 enum branch_condition cond; 1243 1244 if (pc == current_pc) 1245 { 1246 /* When we reach the current PC we must save the current 1247 register state (for the backtrace) but keep analysing 1248 because there might be more to find out (eg. is this an 1249 exception handler). */ 1250 memcpy (temp_value, value, sizeof (temp_value)); 1251 value = temp_value; 1252 if (nios2_debug) 1253 fprintf_unfiltered (gdb_stdlog, "*"); 1254 } 1255 1256 op = nios2_fetch_insn (gdbarch, pc, &insn); 1257 1258 /* Unknown opcode? Stop scanning. */ 1259 if (op == NULL) 1260 break; 1261 pc += op->size; 1262 1263 if (nios2_debug) 1264 { 1265 if (op->size == 2) 1266 fprintf_unfiltered (gdb_stdlog, "[%04X]", insn & 0xffff); 1267 else 1268 fprintf_unfiltered (gdb_stdlog, "[%08X]", insn); 1269 } 1270 1271 /* The following instructions can appear in the prologue. */ 1272 1273 if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) 1274 { 1275 /* ADD rc, ra, rb (also used for MOV) */ 1276 if (rc == NIOS2_SP_REGNUM 1277 && rb == 0 1278 && value[ra].reg == cache->reg_saved[NIOS2_SP_REGNUM].basereg) 1279 { 1280 /* If the previous value of SP is available somewhere 1281 near the new stack pointer value then this is a 1282 stack switch. */ 1283 1284 /* If any registers were saved on the stack before then 1285 we can't backtrace into them now. */ 1286 for (int i = 0 ; i < NIOS2_NUM_REGS ; i++) 1287 { 1288 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) 1289 cache->reg_saved[i].basereg = -1; 1290 if (value[i].reg == NIOS2_SP_REGNUM) 1291 value[i].reg = -1; 1292 } 1293 1294 /* Create a fake "high water mark" 4 bytes above where SP 1295 was stored and fake up the registers to be consistent 1296 with that. */ 1297 value[NIOS2_SP_REGNUM].reg = NIOS2_SP_REGNUM; 1298 value[NIOS2_SP_REGNUM].offset 1299 = (value[ra].offset 1300 - cache->reg_saved[NIOS2_SP_REGNUM].addr 1301 - 4); 1302 cache->reg_saved[NIOS2_SP_REGNUM].basereg = NIOS2_SP_REGNUM; 1303 cache->reg_saved[NIOS2_SP_REGNUM].addr = -4; 1304 } 1305 1306 else if (rc == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) 1307 /* This is setting SP from FP. This only happens in the 1308 function epilogue. */ 1309 break; 1310 1311 else if (rc != 0) 1312 { 1313 if (value[rb].reg == 0) 1314 value[rc].reg = value[ra].reg; 1315 else if (value[ra].reg == 0) 1316 value[rc].reg = value[rb].reg; 1317 else 1318 value[rc].reg = -1; 1319 value[rc].offset = value[ra].offset + value[rb].offset; 1320 } 1321 1322 /* The add/move is only considered a prologue instruction 1323 if the destination is SP or FP. */ 1324 if (rc == NIOS2_SP_REGNUM || rc == NIOS2_FP_REGNUM) 1325 prologue_end = pc; 1326 } 1327 1328 else if (nios2_match_sub (insn, op, mach, &ra, &rb, &rc)) 1329 { 1330 /* SUB rc, ra, rb */ 1331 if (rc == NIOS2_SP_REGNUM && rb == NIOS2_SP_REGNUM 1332 && value[rc].reg != 0) 1333 /* If we are decrementing the SP by a non-constant amount, 1334 this is alloca, not part of the prologue. */ 1335 break; 1336 else if (rc != 0) 1337 { 1338 if (value[rb].reg == 0) 1339 value[rc].reg = value[ra].reg; 1340 else 1341 value[rc].reg = -1; 1342 value[rc].offset = value[ra].offset - value[rb].offset; 1343 } 1344 } 1345 1346 else if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) 1347 { 1348 /* ADDI rb, ra, imm */ 1349 1350 /* A positive stack adjustment has to be part of the epilogue. */ 1351 if (rb == NIOS2_SP_REGNUM 1352 && (imm > 0 || value[ra].reg != NIOS2_SP_REGNUM)) 1353 break; 1354 1355 /* Likewise restoring SP from FP. */ 1356 else if (rb == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) 1357 break; 1358 1359 if (rb != 0) 1360 { 1361 value[rb].reg = value[ra].reg; 1362 value[rb].offset = value[ra].offset + imm; 1363 } 1364 1365 /* The add is only considered a prologue instruction 1366 if the destination is SP or FP. */ 1367 if (rb == NIOS2_SP_REGNUM || rb == NIOS2_FP_REGNUM) 1368 prologue_end = pc; 1369 } 1370 1371 else if (nios2_match_orhi (insn, op, mach, &ra, &rb, &uimm)) 1372 { 1373 /* ORHI rb, ra, uimm (also used for MOVHI) */ 1374 if (rb != 0) 1375 { 1376 value[rb].reg = (value[ra].reg == 0) ? 0 : -1; 1377 value[rb].offset = value[ra].offset | (uimm << 16); 1378 } 1379 } 1380 1381 else if (nios2_match_stw (insn, op, mach, &ra, &rb, &imm)) 1382 { 1383 /* STW rb, imm(ra) */ 1384 1385 /* Are we storing the original value of a register to the stack? 1386 For exception handlers the value of EA-4 (return 1387 address from interrupts etc) is sometimes stored. */ 1388 int orig = value[rb].reg; 1389 if (orig > 0 1390 && (value[rb].offset == 0 1391 || (orig == NIOS2_EA_REGNUM && value[rb].offset == -4)) 1392 && value[ra].reg == NIOS2_SP_REGNUM) 1393 { 1394 if (pc < current_pc) 1395 { 1396 /* Save off callee saved registers. */ 1397 cache->reg_saved[orig].basereg = value[ra].reg; 1398 cache->reg_saved[orig].addr = value[ra].offset + imm; 1399 } 1400 1401 prologue_end = pc; 1402 1403 if (orig == NIOS2_EA_REGNUM || orig == NIOS2_ESTATUS_REGNUM) 1404 exception_handler = 1; 1405 } 1406 else 1407 /* Non-stack memory writes cannot appear in the prologue. */ 1408 break; 1409 } 1410 1411 else if (nios2_match_stwm (insn, op, mach, 1412 ®list, &ra, &imm, &wb, &id)) 1413 { 1414 /* PUSH.N {reglist}, adjust 1415 or 1416 STWM {reglist}, --(SP)[, writeback] */ 1417 int off = 0; 1418 1419 if (ra != NIOS2_SP_REGNUM || id != 0) 1420 /* This is a non-stack-push memory write and cannot be 1421 part of the prologue. */ 1422 break; 1423 1424 for (int i = 31; i >= 0; i--) 1425 if (reglist & (1 << i)) 1426 { 1427 int orig = value[i].reg; 1428 1429 off += 4; 1430 if (orig > 0 && value[i].offset == 0 && pc < current_pc) 1431 { 1432 cache->reg_saved[orig].basereg 1433 = value[NIOS2_SP_REGNUM].reg; 1434 cache->reg_saved[orig].addr 1435 = value[NIOS2_SP_REGNUM].offset - off; 1436 } 1437 } 1438 1439 if (wb) 1440 value[NIOS2_SP_REGNUM].offset -= off; 1441 value[NIOS2_SP_REGNUM].offset -= imm; 1442 1443 prologue_end = pc; 1444 } 1445 1446 else if (nios2_match_rdctl (insn, op, mach, &ra, &rc)) 1447 { 1448 /* RDCTL rC, ctlN 1449 This can appear in exception handlers in combination with 1450 a subsequent save to the stack frame. */ 1451 if (rc != 0) 1452 { 1453 value[rc].reg = NIOS2_STATUS_REGNUM + ra; 1454 value[rc].offset = 0; 1455 } 1456 } 1457 1458 else if (nios2_match_calli (insn, op, mach, &uimm)) 1459 { 1460 if (value[8].reg == NIOS2_RA_REGNUM 1461 && value[8].offset == 0 1462 && value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM 1463 && value[NIOS2_SP_REGNUM].offset == 0) 1464 { 1465 /* A CALL instruction. This is treated as a call to mcount 1466 if ra has been stored into r8 beforehand and if it's 1467 before the stack adjust. 1468 Note mcount corrupts r2-r3, r9-r15 & ra. */ 1469 for (int i = 2 ; i <= 3 ; i++) 1470 value[i].reg = -1; 1471 for (int i = 9 ; i <= 15 ; i++) 1472 value[i].reg = -1; 1473 value[NIOS2_RA_REGNUM].reg = -1; 1474 1475 prologue_end = pc; 1476 } 1477 1478 /* Other calls are not part of the prologue. */ 1479 else 1480 break; 1481 } 1482 1483 else if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) 1484 { 1485 /* Branches not involving a stack overflow check aren't part of 1486 the prologue. */ 1487 if (ra != NIOS2_SP_REGNUM) 1488 break; 1489 else if (cond == branch_geu) 1490 { 1491 /* BGEU sp, rx, +8 1492 TRAP 3 (or BREAK 3) 1493 This instruction sequence is used in stack checking; 1494 we can ignore it. */ 1495 unsigned int next_insn; 1496 const struct nios2_opcode *next_op 1497 = nios2_fetch_insn (gdbarch, pc, &next_insn); 1498 if (next_op != NULL 1499 && (nios2_match_trap (next_insn, op, mach, &uimm) 1500 || nios2_match_break (next_insn, op, mach, &uimm))) 1501 pc += next_op->size; 1502 else 1503 break; 1504 } 1505 else if (cond == branch_ltu) 1506 { 1507 /* BLTU sp, rx, .Lstackoverflow 1508 If the location branched to holds a TRAP or BREAK 1509 instruction then this is also stack overflow detection. */ 1510 unsigned int next_insn; 1511 const struct nios2_opcode *next_op 1512 = nios2_fetch_insn (gdbarch, pc + imm, &next_insn); 1513 if (next_op != NULL 1514 && (nios2_match_trap (next_insn, op, mach, &uimm) 1515 || nios2_match_break (next_insn, op, mach, &uimm))) 1516 ; 1517 else 1518 break; 1519 } 1520 else 1521 break; 1522 } 1523 1524 /* All other calls, jumps, returns, TRAPs, or BREAKs terminate 1525 the prologue. */ 1526 else if (nios2_match_callr (insn, op, mach, &ra) 1527 || nios2_match_jmpr (insn, op, mach, &ra) 1528 || nios2_match_jmpi (insn, op, mach, &uimm) 1529 || (nios2_match_ldwm (insn, op, mach, ®list, &ra, 1530 &imm, &wb, &id, &ret) 1531 && ret) 1532 || nios2_match_trap (insn, op, mach, &uimm) 1533 || nios2_match_break (insn, op, mach, &uimm)) 1534 break; 1535 } 1536 1537 /* If THIS_FRAME is NULL, we are being called from skip_prologue 1538 and are only interested in the PROLOGUE_END value, so just 1539 return that now and skip over the cache updates, which depend 1540 on having frame information. */ 1541 if (this_frame == NULL) 1542 return prologue_end; 1543 1544 /* If we are in the function epilogue and have already popped 1545 registers off the stack in preparation for returning, then we 1546 want to go back to the original register values. */ 1547 if (innermost && nios2_in_epilogue_p (gdbarch, current_pc, start_pc)) 1548 nios2_setup_default (cache); 1549 1550 /* Exception handlers use a different return address register. */ 1551 if (exception_handler) 1552 cache->return_regnum = NIOS2_EA_REGNUM; 1553 1554 if (nios2_debug) 1555 fprintf_unfiltered (gdb_stdlog, "\n-> retreg=%d, ", cache->return_regnum); 1556 1557 if (cache->reg_value[NIOS2_FP_REGNUM].reg == NIOS2_SP_REGNUM) 1558 /* If the FP now holds an offset from the CFA then this is a 1559 normal frame which uses the frame pointer. */ 1560 base_reg = NIOS2_FP_REGNUM; 1561 else if (cache->reg_value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM) 1562 /* FP doesn't hold an offset from the CFA. If SP still holds an 1563 offset from the CFA then we might be in a function which omits 1564 the frame pointer, or we might be partway through the prologue. 1565 In both cases we can find the CFA using SP. */ 1566 base_reg = NIOS2_SP_REGNUM; 1567 else 1568 { 1569 /* Somehow the stack pointer has been corrupted. 1570 We can't return. */ 1571 if (nios2_debug) 1572 fprintf_unfiltered (gdb_stdlog, "<can't reach cfa> }\n"); 1573 return 0; 1574 } 1575 1576 if (cache->reg_value[base_reg].offset == 0 1577 || cache->reg_saved[NIOS2_RA_REGNUM].basereg != NIOS2_SP_REGNUM 1578 || cache->reg_saved[cache->return_regnum].basereg != NIOS2_SP_REGNUM) 1579 { 1580 /* If the frame didn't adjust the stack, didn't save RA or 1581 didn't save EA in an exception handler then it must either 1582 be a leaf function (doesn't call any other functions) or it 1583 can't return. If it has called another function then it 1584 can't be a leaf, so set base == 0 to indicate that we can't 1585 backtrace past it. */ 1586 1587 if (!innermost) 1588 { 1589 /* If it isn't the innermost function then it can't be a 1590 leaf, unless it was interrupted. Check whether RA for 1591 this frame is the same as PC. If so then it probably 1592 wasn't interrupted. */ 1593 CORE_ADDR ra 1594 = get_frame_register_unsigned (this_frame, NIOS2_RA_REGNUM); 1595 1596 if (ra == current_pc) 1597 { 1598 if (nios2_debug) 1599 fprintf_unfiltered 1600 (gdb_stdlog, 1601 "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n", 1602 paddress (gdbarch, cache->reg_value[base_reg].offset), 1603 cache->reg_saved[NIOS2_RA_REGNUM].basereg, 1604 cache->return_regnum, 1605 cache->reg_saved[cache->return_regnum].basereg); 1606 return 0; 1607 } 1608 } 1609 } 1610 1611 /* Get the value of whichever register we are using for the 1612 base. */ 1613 cache->base = get_frame_register_unsigned (this_frame, base_reg); 1614 1615 /* What was the value of SP at the start of this function (or just 1616 after the stack switch). */ 1617 frame_high = cache->base - cache->reg_value[base_reg].offset; 1618 1619 /* Adjust all the saved registers such that they contain addresses 1620 instead of offsets. */ 1621 for (int i = 0; i < NIOS2_NUM_REGS; i++) 1622 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) 1623 { 1624 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; 1625 cache->reg_saved[i].addr += frame_high; 1626 } 1627 1628 for (int i = 0; i < NIOS2_NUM_REGS; i++) 1629 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) 1630 { 1631 CORE_ADDR gp = get_frame_register_unsigned (this_frame, 1632 NIOS2_GP_REGNUM); 1633 1634 for ( ; i < NIOS2_NUM_REGS; i++) 1635 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) 1636 { 1637 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; 1638 cache->reg_saved[i].addr += gp; 1639 } 1640 } 1641 1642 /* Work out what the value of SP was on the first instruction of 1643 this function. If we didn't switch stacks then this can be 1644 trivially computed from the base address. */ 1645 if (cache->reg_saved[NIOS2_SP_REGNUM].basereg == NIOS2_Z_REGNUM) 1646 cache->cfa 1647 = read_memory_unsigned_integer (cache->reg_saved[NIOS2_SP_REGNUM].addr, 1648 4, byte_order); 1649 else 1650 cache->cfa = frame_high; 1651 1652 /* Exception handlers restore ESTATUS into STATUS. */ 1653 if (exception_handler) 1654 { 1655 cache->reg_saved[NIOS2_STATUS_REGNUM] 1656 = cache->reg_saved[NIOS2_ESTATUS_REGNUM]; 1657 cache->reg_saved[NIOS2_ESTATUS_REGNUM].basereg = -1; 1658 } 1659 1660 if (nios2_debug) 1661 fprintf_unfiltered (gdb_stdlog, "cfa=%s }\n", 1662 paddress (gdbarch, cache->cfa)); 1663 1664 return prologue_end; 1665} 1666 1667/* Implement the skip_prologue gdbarch hook. */ 1668 1669static CORE_ADDR 1670nios2_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1671{ 1672 CORE_ADDR func_addr; 1673 1674 struct nios2_unwind_cache cache; 1675 1676 /* See if we can determine the end of the prologue via the symbol 1677 table. If so, then return either PC, or the PC after the 1678 prologue, whichever is greater. */ 1679 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 1680 { 1681 CORE_ADDR post_prologue_pc 1682 = skip_prologue_using_sal (gdbarch, func_addr); 1683 1684 if (post_prologue_pc != 0) 1685 return std::max (start_pc, post_prologue_pc); 1686 } 1687 1688 /* Prologue analysis does the rest.... */ 1689 nios2_init_cache (&cache, start_pc); 1690 return nios2_analyze_prologue (gdbarch, start_pc, start_pc, &cache, NULL); 1691} 1692 1693/* Implement the breakpoint_kind_from_pc gdbarch method. */ 1694 1695static int 1696nios2_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 1697{ 1698 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1699 1700 if (mach == bfd_mach_nios2r2) 1701 { 1702 unsigned int insn; 1703 const struct nios2_opcode *op 1704 = nios2_fetch_insn (gdbarch, *pcptr, &insn); 1705 1706 if (op && op->size == NIOS2_CDX_OPCODE_SIZE) 1707 return NIOS2_CDX_OPCODE_SIZE; 1708 else 1709 return NIOS2_OPCODE_SIZE; 1710 } 1711 else 1712 return NIOS2_OPCODE_SIZE; 1713} 1714 1715/* Implement the sw_breakpoint_from_kind gdbarch method. */ 1716 1717static const gdb_byte * 1718nios2_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 1719{ 1720/* The Nios II ABI for Linux says: "Userspace programs should not use 1721 the break instruction and userspace debuggers should not insert 1722 one." and "Userspace breakpoints are accomplished using the trap 1723 instruction with immediate operand 31 (all ones)." 1724 1725 So, we use "trap 31" consistently as the breakpoint on bare-metal 1726 as well as Linux targets. */ 1727 1728 /* R2 trap encoding: 1729 ((0x2d << 26) | (0x1f << 21) | (0x1d << 16) | (0x20 << 0)) 1730 0xb7fd0020 1731 CDX trap.n encoding: 1732 ((0xd << 12) | (0x1f << 6) | (0x9 << 0)) 1733 0xd7c9 1734 Note that code is always little-endian on R2. */ 1735 *size = kind; 1736 1737 if (kind == NIOS2_CDX_OPCODE_SIZE) 1738 { 1739 static const gdb_byte cdx_breakpoint_le[] = {0xc9, 0xd7}; 1740 1741 return cdx_breakpoint_le; 1742 } 1743 else 1744 { 1745 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1746 1747 if (mach == bfd_mach_nios2r2) 1748 { 1749 static const gdb_byte r2_breakpoint_le[] = {0x20, 0x00, 0xfd, 0xb7}; 1750 1751 return r2_breakpoint_le; 1752 } 1753 else 1754 { 1755 enum bfd_endian byte_order_for_code 1756 = gdbarch_byte_order_for_code (gdbarch); 1757 /* R1 trap encoding: 1758 ((0x1d << 17) | (0x2d << 11) | (0x1f << 6) | (0x3a << 0)) 1759 0x003b6ffa */ 1760 static const gdb_byte r1_breakpoint_le[] = {0xfa, 0x6f, 0x3b, 0x0}; 1761 static const gdb_byte r1_breakpoint_be[] = {0x0, 0x3b, 0x6f, 0xfa}; 1762 1763 if (byte_order_for_code == BFD_ENDIAN_BIG) 1764 return r1_breakpoint_be; 1765 else 1766 return r1_breakpoint_le; 1767 } 1768 } 1769} 1770 1771/* Implement the frame_align gdbarch method. */ 1772 1773static CORE_ADDR 1774nios2_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 1775{ 1776 return align_down (addr, 4); 1777} 1778 1779 1780/* Implement the return_value gdbarch method. */ 1781 1782static enum return_value_convention 1783nios2_return_value (struct gdbarch *gdbarch, struct value *function, 1784 struct type *type, struct regcache *regcache, 1785 gdb_byte *readbuf, const gdb_byte *writebuf) 1786{ 1787 if (TYPE_LENGTH (type) > 8) 1788 return RETURN_VALUE_STRUCT_CONVENTION; 1789 1790 if (readbuf) 1791 nios2_extract_return_value (gdbarch, type, regcache, readbuf); 1792 if (writebuf) 1793 nios2_store_return_value (gdbarch, type, regcache, writebuf); 1794 1795 return RETURN_VALUE_REGISTER_CONVENTION; 1796} 1797 1798/* Implement the dummy_id gdbarch method. */ 1799 1800static struct frame_id 1801nios2_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1802{ 1803 return frame_id_build 1804 (get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM), 1805 get_frame_pc (this_frame)); 1806} 1807 1808/* Implement the push_dummy_call gdbarch method. */ 1809 1810static CORE_ADDR 1811nios2_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1812 struct regcache *regcache, CORE_ADDR bp_addr, 1813 int nargs, struct value **args, CORE_ADDR sp, 1814 function_call_return_method return_method, 1815 CORE_ADDR struct_addr) 1816{ 1817 int argreg; 1818 int argnum; 1819 int arg_space = 0; 1820 int stack_offset = 0; 1821 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1822 1823 /* Set the return address register to point to the entry point of 1824 the program, where a breakpoint lies in wait. */ 1825 regcache_cooked_write_signed (regcache, NIOS2_RA_REGNUM, bp_addr); 1826 1827 /* Now make space on the stack for the args. */ 1828 for (argnum = 0; argnum < nargs; argnum++) 1829 arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), 4); 1830 sp -= arg_space; 1831 1832 /* Initialize the register pointer. */ 1833 argreg = NIOS2_FIRST_ARGREG; 1834 1835 /* The struct_return pointer occupies the first parameter-passing 1836 register. */ 1837 if (return_method == return_method_struct) 1838 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 1839 1840 /* Now load as many as possible of the first arguments into 1841 registers, and push the rest onto the stack. Loop through args 1842 from first to last. */ 1843 for (argnum = 0; argnum < nargs; argnum++) 1844 { 1845 const gdb_byte *val; 1846 struct value *arg = args[argnum]; 1847 struct type *arg_type = check_typedef (value_type (arg)); 1848 int len = TYPE_LENGTH (arg_type); 1849 1850 val = value_contents (arg); 1851 1852 /* Copy the argument to general registers or the stack in 1853 register-sized pieces. Large arguments are split between 1854 registers and stack. */ 1855 while (len > 0) 1856 { 1857 int partial_len = (len < 4 ? len : 4); 1858 1859 if (argreg <= NIOS2_LAST_ARGREG) 1860 { 1861 /* The argument is being passed in a register. */ 1862 CORE_ADDR regval = extract_unsigned_integer (val, partial_len, 1863 byte_order); 1864 1865 regcache_cooked_write_unsigned (regcache, argreg, regval); 1866 argreg++; 1867 } 1868 else 1869 { 1870 /* The argument is being passed on the stack. */ 1871 CORE_ADDR addr = sp + stack_offset; 1872 1873 write_memory (addr, val, partial_len); 1874 stack_offset += align_up (partial_len, 4); 1875 } 1876 1877 len -= partial_len; 1878 val += partial_len; 1879 } 1880 } 1881 1882 regcache_cooked_write_signed (regcache, NIOS2_SP_REGNUM, sp); 1883 1884 /* Return adjusted stack pointer. */ 1885 return sp; 1886} 1887 1888/* Implement the unwind_pc gdbarch method. */ 1889 1890static CORE_ADDR 1891nios2_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1892{ 1893 gdb_byte buf[4]; 1894 1895 frame_unwind_register (next_frame, NIOS2_PC_REGNUM, buf); 1896 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1897} 1898 1899/* Implement the unwind_sp gdbarch method. */ 1900 1901static CORE_ADDR 1902nios2_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) 1903{ 1904 return frame_unwind_register_unsigned (this_frame, NIOS2_SP_REGNUM); 1905} 1906 1907/* Use prologue analysis to fill in the register cache 1908 *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes 1909 *THIS_PROLOGUE_CACHE first. */ 1910 1911static struct nios2_unwind_cache * 1912nios2_frame_unwind_cache (struct frame_info *this_frame, 1913 void **this_prologue_cache) 1914{ 1915 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1916 CORE_ADDR current_pc; 1917 struct nios2_unwind_cache *cache; 1918 1919 if (*this_prologue_cache) 1920 return (struct nios2_unwind_cache *) *this_prologue_cache; 1921 1922 cache = FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache); 1923 *this_prologue_cache = cache; 1924 1925 /* Zero all fields. */ 1926 nios2_init_cache (cache, get_frame_func (this_frame)); 1927 1928 /* Prologue analysis does the rest... */ 1929 current_pc = get_frame_pc (this_frame); 1930 if (cache->pc != 0) 1931 nios2_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); 1932 1933 return cache; 1934} 1935 1936/* Implement the this_id function for the normal unwinder. */ 1937 1938static void 1939nios2_frame_this_id (struct frame_info *this_frame, void **this_cache, 1940 struct frame_id *this_id) 1941{ 1942 struct nios2_unwind_cache *cache = 1943 nios2_frame_unwind_cache (this_frame, this_cache); 1944 1945 /* This marks the outermost frame. */ 1946 if (cache->base == 0) 1947 return; 1948 1949 *this_id = frame_id_build (cache->cfa, cache->pc); 1950} 1951 1952/* Implement the prev_register function for the normal unwinder. */ 1953 1954static struct value * 1955nios2_frame_prev_register (struct frame_info *this_frame, void **this_cache, 1956 int regnum) 1957{ 1958 struct nios2_unwind_cache *cache = 1959 nios2_frame_unwind_cache (this_frame, this_cache); 1960 1961 gdb_assert (regnum >= 0 && regnum < NIOS2_NUM_REGS); 1962 1963 /* The PC of the previous frame is stored in the RA register of 1964 the current frame. Frob regnum so that we pull the value from 1965 the correct place. */ 1966 if (regnum == NIOS2_PC_REGNUM) 1967 regnum = cache->return_regnum; 1968 1969 if (regnum == NIOS2_SP_REGNUM && cache->cfa) 1970 return frame_unwind_got_constant (this_frame, regnum, cache->cfa); 1971 1972 /* If we've worked out where a register is stored then load it from 1973 there. */ 1974 if (cache->reg_saved[regnum].basereg == NIOS2_Z_REGNUM) 1975 return frame_unwind_got_memory (this_frame, regnum, 1976 cache->reg_saved[regnum].addr); 1977 1978 return frame_unwind_got_register (this_frame, regnum, regnum); 1979} 1980 1981/* Implement the this_base, this_locals, and this_args hooks 1982 for the normal unwinder. */ 1983 1984static CORE_ADDR 1985nios2_frame_base_address (struct frame_info *this_frame, void **this_cache) 1986{ 1987 struct nios2_unwind_cache *info 1988 = nios2_frame_unwind_cache (this_frame, this_cache); 1989 1990 return info->base; 1991} 1992 1993/* Data structures for the normal prologue-analysis-based 1994 unwinder. */ 1995 1996static const struct frame_unwind nios2_frame_unwind = 1997{ 1998 NORMAL_FRAME, 1999 default_frame_unwind_stop_reason, 2000 nios2_frame_this_id, 2001 nios2_frame_prev_register, 2002 NULL, 2003 default_frame_sniffer 2004}; 2005 2006static const struct frame_base nios2_frame_base = 2007{ 2008 &nios2_frame_unwind, 2009 nios2_frame_base_address, 2010 nios2_frame_base_address, 2011 nios2_frame_base_address 2012}; 2013 2014/* Fill in the register cache *THIS_CACHE for THIS_FRAME for use 2015 in the stub unwinder. */ 2016 2017static struct trad_frame_cache * 2018nios2_stub_frame_cache (struct frame_info *this_frame, void **this_cache) 2019{ 2020 CORE_ADDR pc; 2021 CORE_ADDR start_addr; 2022 CORE_ADDR stack_addr; 2023 struct trad_frame_cache *this_trad_cache; 2024 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2025 2026 if (*this_cache != NULL) 2027 return (struct trad_frame_cache *) *this_cache; 2028 this_trad_cache = trad_frame_cache_zalloc (this_frame); 2029 *this_cache = this_trad_cache; 2030 2031 /* The return address is in the link register. */ 2032 trad_frame_set_reg_realreg (this_trad_cache, 2033 gdbarch_pc_regnum (gdbarch), 2034 NIOS2_RA_REGNUM); 2035 2036 /* Frame ID, since it's a frameless / stackless function, no stack 2037 space is allocated and SP on entry is the current SP. */ 2038 pc = get_frame_pc (this_frame); 2039 find_pc_partial_function (pc, NULL, &start_addr, NULL); 2040 stack_addr = get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM); 2041 trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); 2042 /* Assume that the frame's base is the same as the stack pointer. */ 2043 trad_frame_set_this_base (this_trad_cache, stack_addr); 2044 2045 return this_trad_cache; 2046} 2047 2048/* Implement the this_id function for the stub unwinder. */ 2049 2050static void 2051nios2_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, 2052 struct frame_id *this_id) 2053{ 2054 struct trad_frame_cache *this_trad_cache 2055 = nios2_stub_frame_cache (this_frame, this_cache); 2056 2057 trad_frame_get_id (this_trad_cache, this_id); 2058} 2059 2060/* Implement the prev_register function for the stub unwinder. */ 2061 2062static struct value * 2063nios2_stub_frame_prev_register (struct frame_info *this_frame, 2064 void **this_cache, int regnum) 2065{ 2066 struct trad_frame_cache *this_trad_cache 2067 = nios2_stub_frame_cache (this_frame, this_cache); 2068 2069 return trad_frame_get_register (this_trad_cache, this_frame, regnum); 2070} 2071 2072/* Implement the sniffer function for the stub unwinder. 2073 This unwinder is used for cases where the normal 2074 prologue-analysis-based unwinder can't work, 2075 such as PLT stubs. */ 2076 2077static int 2078nios2_stub_frame_sniffer (const struct frame_unwind *self, 2079 struct frame_info *this_frame, void **cache) 2080{ 2081 gdb_byte dummy[4]; 2082 CORE_ADDR pc = get_frame_address_in_block (this_frame); 2083 2084 /* Use the stub unwinder for unreadable code. */ 2085 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) 2086 return 1; 2087 2088 if (in_plt_section (pc)) 2089 return 1; 2090 2091 return 0; 2092} 2093 2094/* Define the data structures for the stub unwinder. */ 2095 2096static const struct frame_unwind nios2_stub_frame_unwind = 2097{ 2098 NORMAL_FRAME, 2099 default_frame_unwind_stop_reason, 2100 nios2_stub_frame_this_id, 2101 nios2_stub_frame_prev_register, 2102 NULL, 2103 nios2_stub_frame_sniffer 2104}; 2105 2106 2107 2108/* Determine where to set a single step breakpoint while considering 2109 branch prediction. */ 2110 2111static CORE_ADDR 2112nios2_get_next_pc (struct regcache *regcache, CORE_ADDR pc) 2113{ 2114 struct gdbarch *gdbarch = regcache->arch (); 2115 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2116 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 2117 unsigned int insn; 2118 const struct nios2_opcode *op = nios2_fetch_insn (gdbarch, pc, &insn); 2119 int ra; 2120 int rb; 2121 int imm; 2122 unsigned int uimm; 2123 int wb, id, ret; 2124 enum branch_condition cond; 2125 2126 /* Do something stupid if we can't disassemble the insn at pc. */ 2127 if (op == NULL) 2128 return pc + NIOS2_OPCODE_SIZE; 2129 2130 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) 2131 { 2132 int ras = regcache_raw_get_signed (regcache, ra); 2133 int rbs = regcache_raw_get_signed (regcache, rb); 2134 unsigned int rau = regcache_raw_get_unsigned (regcache, ra); 2135 unsigned int rbu = regcache_raw_get_unsigned (regcache, rb); 2136 2137 pc += op->size; 2138 switch (cond) 2139 { 2140 case branch_none: 2141 pc += imm; 2142 break; 2143 case branch_eq: 2144 if (ras == rbs) 2145 pc += imm; 2146 break; 2147 case branch_ne: 2148 if (ras != rbs) 2149 pc += imm; 2150 break; 2151 case branch_ge: 2152 if (ras >= rbs) 2153 pc += imm; 2154 break; 2155 case branch_geu: 2156 if (rau >= rbu) 2157 pc += imm; 2158 break; 2159 case branch_lt: 2160 if (ras < rbs) 2161 pc += imm; 2162 break; 2163 case branch_ltu: 2164 if (rau < rbu) 2165 pc += imm; 2166 break; 2167 default: 2168 break; 2169 } 2170 } 2171 2172 else if (nios2_match_jmpi (insn, op, mach, &uimm) 2173 || nios2_match_calli (insn, op, mach, &uimm)) 2174 pc = (pc & 0xf0000000) | uimm; 2175 2176 else if (nios2_match_jmpr (insn, op, mach, &ra) 2177 || nios2_match_callr (insn, op, mach, &ra)) 2178 pc = regcache_raw_get_unsigned (regcache, ra); 2179 2180 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret) 2181 && ret) 2182 { 2183 /* If ra is in the reglist, we have to use the value saved in the 2184 stack frame rather than the current value. */ 2185 if (uimm & (1 << NIOS2_RA_REGNUM)) 2186 pc = nios2_unwind_pc (gdbarch, get_current_frame ()); 2187 else 2188 pc = regcache_raw_get_unsigned (regcache, NIOS2_RA_REGNUM); 2189 } 2190 2191 else if (nios2_match_trap (insn, op, mach, &uimm) && uimm == 0) 2192 { 2193 if (tdep->syscall_next_pc != NULL) 2194 return tdep->syscall_next_pc (get_current_frame (), op); 2195 } 2196 2197 else 2198 pc += op->size; 2199 2200 return pc; 2201} 2202 2203/* Implement the software_single_step gdbarch method. */ 2204 2205static std::vector<CORE_ADDR> 2206nios2_software_single_step (struct regcache *regcache) 2207{ 2208 CORE_ADDR next_pc = nios2_get_next_pc (regcache, regcache_read_pc (regcache)); 2209 2210 return {next_pc}; 2211} 2212 2213/* Implement the get_longjump_target gdbarch method. */ 2214 2215static int 2216nios2_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2217{ 2218 struct gdbarch *gdbarch = get_frame_arch (frame); 2219 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2220 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2221 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, NIOS2_R4_REGNUM); 2222 gdb_byte buf[4]; 2223 2224 if (target_read_memory (jb_addr + (tdep->jb_pc * 4), buf, 4)) 2225 return 0; 2226 2227 *pc = extract_unsigned_integer (buf, 4, byte_order); 2228 return 1; 2229} 2230 2231/* Implement the type_align gdbarch function. */ 2232 2233static ULONGEST 2234nios2_type_align (struct gdbarch *gdbarch, struct type *type) 2235{ 2236 type = check_typedef (type); 2237 return std::min<ULONGEST> (4, TYPE_LENGTH (type)); 2238} 2239 2240/* Implement the gcc_target_options gdbarch method. */ 2241static char * 2242nios2_gcc_target_options (struct gdbarch *gdbarch) 2243{ 2244 /* GCC doesn't know "-m32". */ 2245 return NULL; 2246} 2247 2248/* Initialize the Nios II gdbarch. */ 2249 2250static struct gdbarch * 2251nios2_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2252{ 2253 struct gdbarch *gdbarch; 2254 struct gdbarch_tdep *tdep; 2255 int i; 2256 struct tdesc_arch_data *tdesc_data = NULL; 2257 const struct target_desc *tdesc = info.target_desc; 2258 2259 if (!tdesc_has_registers (tdesc)) 2260 /* Pick a default target description. */ 2261 tdesc = tdesc_nios2; 2262 2263 /* Check any target description for validity. */ 2264 if (tdesc_has_registers (tdesc)) 2265 { 2266 const struct tdesc_feature *feature; 2267 int valid_p; 2268 2269 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nios2.cpu"); 2270 if (feature == NULL) 2271 return NULL; 2272 2273 tdesc_data = tdesc_data_alloc (); 2274 2275 valid_p = 1; 2276 2277 for (i = 0; i < NIOS2_NUM_REGS; i++) 2278 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, 2279 nios2_reg_names[i]); 2280 2281 if (!valid_p) 2282 { 2283 tdesc_data_cleanup (tdesc_data); 2284 return NULL; 2285 } 2286 } 2287 2288 /* Find a candidate among the list of pre-declared architectures. */ 2289 arches = gdbarch_list_lookup_by_info (arches, &info); 2290 if (arches != NULL) 2291 return arches->gdbarch; 2292 2293 /* None found, create a new architecture from the information 2294 provided. */ 2295 tdep = XCNEW (struct gdbarch_tdep); 2296 gdbarch = gdbarch_alloc (&info, tdep); 2297 2298 /* longjmp support not enabled by default. */ 2299 tdep->jb_pc = -1; 2300 2301 /* Data type sizes. */ 2302 set_gdbarch_ptr_bit (gdbarch, 32); 2303 set_gdbarch_addr_bit (gdbarch, 32); 2304 set_gdbarch_short_bit (gdbarch, 16); 2305 set_gdbarch_int_bit (gdbarch, 32); 2306 set_gdbarch_long_bit (gdbarch, 32); 2307 set_gdbarch_long_long_bit (gdbarch, 64); 2308 set_gdbarch_float_bit (gdbarch, 32); 2309 set_gdbarch_double_bit (gdbarch, 64); 2310 2311 set_gdbarch_type_align (gdbarch, nios2_type_align); 2312 2313 set_gdbarch_float_format (gdbarch, floatformats_ieee_single); 2314 set_gdbarch_double_format (gdbarch, floatformats_ieee_double); 2315 2316 /* The register set. */ 2317 set_gdbarch_num_regs (gdbarch, NIOS2_NUM_REGS); 2318 set_gdbarch_sp_regnum (gdbarch, NIOS2_SP_REGNUM); 2319 set_gdbarch_pc_regnum (gdbarch, NIOS2_PC_REGNUM); /* Pseudo register PC */ 2320 2321 set_gdbarch_register_name (gdbarch, nios2_register_name); 2322 set_gdbarch_register_type (gdbarch, nios2_register_type); 2323 2324 /* Provide register mappings for stabs and dwarf2. */ 2325 set_gdbarch_stab_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); 2326 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); 2327 2328 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2329 2330 /* Call dummy code. */ 2331 set_gdbarch_frame_align (gdbarch, nios2_frame_align); 2332 2333 set_gdbarch_return_value (gdbarch, nios2_return_value); 2334 2335 set_gdbarch_skip_prologue (gdbarch, nios2_skip_prologue); 2336 set_gdbarch_stack_frame_destroyed_p (gdbarch, nios2_stack_frame_destroyed_p); 2337 set_gdbarch_breakpoint_kind_from_pc (gdbarch, nios2_breakpoint_kind_from_pc); 2338 set_gdbarch_sw_breakpoint_from_kind (gdbarch, nios2_sw_breakpoint_from_kind); 2339 2340 set_gdbarch_dummy_id (gdbarch, nios2_dummy_id); 2341 set_gdbarch_unwind_pc (gdbarch, nios2_unwind_pc); 2342 set_gdbarch_unwind_sp (gdbarch, nios2_unwind_sp); 2343 2344 /* The dwarf2 unwinder will normally produce the best results if 2345 the debug information is available, so register it first. */ 2346 dwarf2_append_unwinders (gdbarch); 2347 frame_unwind_append_unwinder (gdbarch, &nios2_stub_frame_unwind); 2348 frame_unwind_append_unwinder (gdbarch, &nios2_frame_unwind); 2349 2350 /* Single stepping. */ 2351 set_gdbarch_software_single_step (gdbarch, nios2_software_single_step); 2352 2353 /* Target options for compile. */ 2354 set_gdbarch_gcc_target_options (gdbarch, nios2_gcc_target_options); 2355 2356 /* Hook in ABI-specific overrides, if they have been registered. */ 2357 gdbarch_init_osabi (info, gdbarch); 2358 2359 if (tdep->jb_pc >= 0) 2360 set_gdbarch_get_longjmp_target (gdbarch, nios2_get_longjmp_target); 2361 2362 frame_base_set_default (gdbarch, &nios2_frame_base); 2363 2364 /* Enable inferior call support. */ 2365 set_gdbarch_push_dummy_call (gdbarch, nios2_push_dummy_call); 2366 2367 if (tdesc_data) 2368 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 2369 2370 return gdbarch; 2371} 2372 2373void 2374_initialize_nios2_tdep (void) 2375{ 2376 gdbarch_register (bfd_arch_nios2, nios2_gdbarch_init, NULL); 2377 initialize_tdesc_nios2 (); 2378 2379 /* Allow debugging this file's internals. */ 2380 add_setshow_boolean_cmd ("nios2", class_maintenance, &nios2_debug, 2381 _("Set Nios II debugging."), 2382 _("Show Nios II debugging."), 2383 _("When on, Nios II specific debugging is enabled."), 2384 NULL, 2385 NULL, 2386 &setdebuglist, &showdebuglist); 2387} 2388