nios2-tdep.c revision 1.7
1/* Target-machine dependent code for Nios II, for GDB. 2 Copyright (C) 2012-2017 Free Software Foundation, Inc. 3 Contributed by Peter Brookes (pbrookes@altera.com) 4 and Andrew Draper (adraper@altera.com). 5 Contributed by Mentor Graphics, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22#include "defs.h" 23#include "frame.h" 24#include "frame-unwind.h" 25#include "frame-base.h" 26#include "trad-frame.h" 27#include "dwarf2-frame.h" 28#include "symtab.h" 29#include "inferior.h" 30#include "gdbtypes.h" 31#include "gdbcore.h" 32#include "gdbcmd.h" 33#include "osabi.h" 34#include "target.h" 35#include "dis-asm.h" 36#include "regcache.h" 37#include "value.h" 38#include "symfile.h" 39#include "arch-utils.h" 40#include "floatformat.h" 41#include "infcall.h" 42#include "regset.h" 43#include "target-descriptions.h" 44 45/* To get entry_point_address. */ 46#include "objfiles.h" 47#include <algorithm> 48 49/* Nios II specific header. */ 50#include "nios2-tdep.h" 51 52#include "features/nios2.c" 53 54/* Control debugging information emitted in this file. */ 55 56static int nios2_debug = 0; 57 58/* The following structures are used in the cache for prologue 59 analysis; see the reg_value and reg_saved tables in 60 struct nios2_unwind_cache, respectively. */ 61 62/* struct reg_value is used to record that a register has the same value 63 as reg at the given offset from the start of a function. */ 64 65struct reg_value 66{ 67 int reg; 68 unsigned int offset; 69}; 70 71/* struct reg_saved is used to record that a register value has been saved at 72 basereg + addr, for basereg >= 0. If basereg < 0, that indicates 73 that the register is not known to have been saved. Note that when 74 basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0), 75 addr is an absolute address. */ 76 77struct reg_saved 78{ 79 int basereg; 80 CORE_ADDR addr; 81}; 82 83struct nios2_unwind_cache 84{ 85 /* The frame's base, optionally used by the high-level debug info. */ 86 CORE_ADDR base; 87 88 /* The previous frame's inner most stack address. Used as this 89 frame ID's stack_addr. */ 90 CORE_ADDR cfa; 91 92 /* The address of the first instruction in this function. */ 93 CORE_ADDR pc; 94 95 /* Which register holds the return address for the frame. */ 96 int return_regnum; 97 98 /* Table indicating what changes have been made to each register. */ 99 struct reg_value reg_value[NIOS2_NUM_REGS]; 100 101 /* Table indicating where each register has been saved. */ 102 struct reg_saved reg_saved[NIOS2_NUM_REGS]; 103}; 104 105 106/* This array is a mapping from Dwarf-2 register numbering to GDB's. */ 107 108static int nios2_dwarf2gdb_regno_map[] = 109{ 110 0, 1, 2, 3, 111 4, 5, 6, 7, 112 8, 9, 10, 11, 113 12, 13, 14, 15, 114 16, 17, 18, 19, 115 20, 21, 22, 23, 116 24, 25, 117 NIOS2_GP_REGNUM, /* 26 */ 118 NIOS2_SP_REGNUM, /* 27 */ 119 NIOS2_FP_REGNUM, /* 28 */ 120 NIOS2_EA_REGNUM, /* 29 */ 121 NIOS2_BA_REGNUM, /* 30 */ 122 NIOS2_RA_REGNUM, /* 31 */ 123 NIOS2_PC_REGNUM, /* 32 */ 124 NIOS2_STATUS_REGNUM, /* 33 */ 125 NIOS2_ESTATUS_REGNUM, /* 34 */ 126 NIOS2_BSTATUS_REGNUM, /* 35 */ 127 NIOS2_IENABLE_REGNUM, /* 36 */ 128 NIOS2_IPENDING_REGNUM, /* 37 */ 129 NIOS2_CPUID_REGNUM, /* 38 */ 130 39, /* CTL6 */ /* 39 */ 131 NIOS2_EXCEPTION_REGNUM, /* 40 */ 132 NIOS2_PTEADDR_REGNUM, /* 41 */ 133 NIOS2_TLBACC_REGNUM, /* 42 */ 134 NIOS2_TLBMISC_REGNUM, /* 43 */ 135 NIOS2_ECCINJ_REGNUM, /* 44 */ 136 NIOS2_BADADDR_REGNUM, /* 45 */ 137 NIOS2_CONFIG_REGNUM, /* 46 */ 138 NIOS2_MPUBASE_REGNUM, /* 47 */ 139 NIOS2_MPUACC_REGNUM /* 48 */ 140}; 141 142gdb_static_assert (ARRAY_SIZE (nios2_dwarf2gdb_regno_map) == NIOS2_NUM_REGS); 143 144/* Implement the dwarf2_reg_to_regnum gdbarch method. */ 145 146static int 147nios2_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg) 148{ 149 if (dw_reg < 0 || dw_reg >= NIOS2_NUM_REGS) 150 return -1; 151 152 return nios2_dwarf2gdb_regno_map[dw_reg]; 153} 154 155/* Canonical names for the 49 registers. */ 156 157static const char *const nios2_reg_names[NIOS2_NUM_REGS] = 158{ 159 "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", 160 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 161 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 162 "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra", 163 "pc", 164 "status", "estatus", "bstatus", "ienable", 165 "ipending", "cpuid", "ctl6", "exception", 166 "pteaddr", "tlbacc", "tlbmisc", "eccinj", 167 "badaddr", "config", "mpubase", "mpuacc" 168}; 169 170/* Implement the register_name gdbarch method. */ 171 172static const char * 173nios2_register_name (struct gdbarch *gdbarch, int regno) 174{ 175 /* Use mnemonic aliases for GPRs. */ 176 if (regno >= 0 && regno < NIOS2_NUM_REGS) 177 return nios2_reg_names[regno]; 178 else 179 return tdesc_register_name (gdbarch, regno); 180} 181 182/* Implement the register_type gdbarch method. */ 183 184static struct type * 185nios2_register_type (struct gdbarch *gdbarch, int regno) 186{ 187 /* If the XML description has register information, use that to 188 determine the register type. */ 189 if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 190 return tdesc_register_type (gdbarch, regno); 191 192 if (regno == NIOS2_PC_REGNUM) 193 return builtin_type (gdbarch)->builtin_func_ptr; 194 else if (regno == NIOS2_SP_REGNUM) 195 return builtin_type (gdbarch)->builtin_data_ptr; 196 else 197 return builtin_type (gdbarch)->builtin_uint32; 198} 199 200/* Given a return value in REGCACHE with a type VALTYPE, 201 extract and copy its value into VALBUF. */ 202 203static void 204nios2_extract_return_value (struct gdbarch *gdbarch, struct type *valtype, 205 struct regcache *regcache, gdb_byte *valbuf) 206{ 207 int len = TYPE_LENGTH (valtype); 208 209 /* Return values of up to 8 bytes are returned in $r2 $r3. */ 210 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) 211 regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); 212 else 213 { 214 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) 215 + register_size (gdbarch, NIOS2_R3_REGNUM))); 216 regcache_cooked_read (regcache, NIOS2_R2_REGNUM, valbuf); 217 regcache_cooked_read (regcache, NIOS2_R3_REGNUM, valbuf + 4); 218 } 219} 220 221/* Write into appropriate registers a function return value 222 of type TYPE, given in virtual format. */ 223 224static void 225nios2_store_return_value (struct gdbarch *gdbarch, struct type *valtype, 226 struct regcache *regcache, const gdb_byte *valbuf) 227{ 228 int len = TYPE_LENGTH (valtype); 229 230 /* Return values of up to 8 bytes are returned in $r2 $r3. */ 231 if (len <= register_size (gdbarch, NIOS2_R2_REGNUM)) 232 regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); 233 else 234 { 235 gdb_assert (len <= (register_size (gdbarch, NIOS2_R2_REGNUM) 236 + register_size (gdbarch, NIOS2_R3_REGNUM))); 237 regcache_cooked_write (regcache, NIOS2_R2_REGNUM, valbuf); 238 regcache_cooked_write (regcache, NIOS2_R3_REGNUM, valbuf + 4); 239 } 240} 241 242 243/* Set up the default values of the registers. */ 244 245static void 246nios2_setup_default (struct nios2_unwind_cache *cache) 247{ 248 int i; 249 250 for (i = 0; i < NIOS2_NUM_REGS; i++) 251 { 252 /* All registers start off holding their previous values. */ 253 cache->reg_value[i].reg = i; 254 cache->reg_value[i].offset = 0; 255 256 /* All registers start off not saved. */ 257 cache->reg_saved[i].basereg = -1; 258 cache->reg_saved[i].addr = 0; 259 } 260} 261 262/* Initialize the unwind cache. */ 263 264static void 265nios2_init_cache (struct nios2_unwind_cache *cache, CORE_ADDR pc) 266{ 267 cache->base = 0; 268 cache->cfa = 0; 269 cache->pc = pc; 270 cache->return_regnum = NIOS2_RA_REGNUM; 271 nios2_setup_default (cache); 272} 273 274/* Read and identify an instruction at PC. If INSNP is non-null, 275 store the instruction word into that location. Return the opcode 276 pointer or NULL if the memory couldn't be read or disassembled. */ 277 278static const struct nios2_opcode * 279nios2_fetch_insn (struct gdbarch *gdbarch, CORE_ADDR pc, 280 unsigned int *insnp) 281{ 282 LONGEST memword; 283 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 284 unsigned int insn; 285 286 if (mach == bfd_mach_nios2r2) 287 { 288 if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE, 289 BFD_ENDIAN_LITTLE, &memword) 290 && !safe_read_memory_integer (pc, NIOS2_CDX_OPCODE_SIZE, 291 BFD_ENDIAN_LITTLE, &memword)) 292 return NULL; 293 } 294 else if (!safe_read_memory_integer (pc, NIOS2_OPCODE_SIZE, 295 gdbarch_byte_order (gdbarch), &memword)) 296 return NULL; 297 298 insn = (unsigned int) memword; 299 if (insnp) 300 *insnp = insn; 301 return nios2_find_opcode_hash (insn, mach); 302} 303 304 305/* Match and disassemble an ADD-type instruction, with 3 register operands. 306 Returns true on success, and fills in the operand pointers. */ 307 308static int 309nios2_match_add (uint32_t insn, const struct nios2_opcode *op, 310 unsigned long mach, int *ra, int *rb, int *rc) 311{ 312 int is_r2 = (mach == bfd_mach_nios2r2); 313 314 if (!is_r2 && (op->match == MATCH_R1_ADD || op->match == MATCH_R1_MOV)) 315 { 316 *ra = GET_IW_R_A (insn); 317 *rb = GET_IW_R_B (insn); 318 *rc = GET_IW_R_C (insn); 319 return 1; 320 } 321 else if (!is_r2) 322 return 0; 323 else if (op->match == MATCH_R2_ADD || op->match == MATCH_R2_MOV) 324 { 325 *ra = GET_IW_F3X6L5_A (insn); 326 *rb = GET_IW_F3X6L5_B (insn); 327 *rc = GET_IW_F3X6L5_C (insn); 328 return 1; 329 } 330 else if (op->match == MATCH_R2_ADD_N) 331 { 332 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)]; 333 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)]; 334 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)]; 335 return 1; 336 } 337 else if (op->match == MATCH_R2_MOV_N) 338 { 339 *ra = GET_IW_F2_A (insn); 340 *rb = 0; 341 *rc = GET_IW_F2_B (insn); 342 return 1; 343 } 344 return 0; 345} 346 347/* Match and disassemble a SUB-type instruction, with 3 register operands. 348 Returns true on success, and fills in the operand pointers. */ 349 350static int 351nios2_match_sub (uint32_t insn, const struct nios2_opcode *op, 352 unsigned long mach, int *ra, int *rb, int *rc) 353{ 354 int is_r2 = (mach == bfd_mach_nios2r2); 355 356 if (!is_r2 && op->match == MATCH_R1_SUB) 357 { 358 *ra = GET_IW_R_A (insn); 359 *rb = GET_IW_R_B (insn); 360 *rc = GET_IW_R_C (insn); 361 return 1; 362 } 363 else if (!is_r2) 364 return 0; 365 else if (op->match == MATCH_R2_SUB) 366 { 367 *ra = GET_IW_F3X6L5_A (insn); 368 *rb = GET_IW_F3X6L5_B (insn); 369 *rc = GET_IW_F3X6L5_C (insn); 370 return 1; 371 } 372 else if (op->match == MATCH_R2_SUB_N) 373 { 374 *ra = nios2_r2_reg3_mappings[GET_IW_T3X1_A3 (insn)]; 375 *rb = nios2_r2_reg3_mappings[GET_IW_T3X1_B3 (insn)]; 376 *rc = nios2_r2_reg3_mappings[GET_IW_T3X1_C3 (insn)]; 377 return 1; 378 } 379 return 0; 380} 381 382/* Match and disassemble an ADDI-type instruction, with 2 register operands 383 and one immediate operand. 384 Returns true on success, and fills in the operand pointers. */ 385 386static int 387nios2_match_addi (uint32_t insn, const struct nios2_opcode *op, 388 unsigned long mach, int *ra, int *rb, int *imm) 389{ 390 int is_r2 = (mach == bfd_mach_nios2r2); 391 392 if (!is_r2 && op->match == MATCH_R1_ADDI) 393 { 394 *ra = GET_IW_I_A (insn); 395 *rb = GET_IW_I_B (insn); 396 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 397 return 1; 398 } 399 else if (!is_r2) 400 return 0; 401 else if (op->match == MATCH_R2_ADDI) 402 { 403 *ra = GET_IW_F2I16_A (insn); 404 *rb = GET_IW_F2I16_B (insn); 405 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 406 return 1; 407 } 408 else if (op->match == MATCH_R2_ADDI_N || op->match == MATCH_R2_SUBI_N) 409 { 410 *ra = nios2_r2_reg3_mappings[GET_IW_T2X1I3_A3 (insn)]; 411 *rb = nios2_r2_reg3_mappings[GET_IW_T2X1I3_B3 (insn)]; 412 *imm = nios2_r2_asi_n_mappings[GET_IW_T2X1I3_IMM3 (insn)]; 413 if (op->match == MATCH_R2_SUBI_N) 414 *imm = - (*imm); 415 return 1; 416 } 417 else if (op->match == MATCH_R2_SPADDI_N) 418 { 419 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 420 *rb = NIOS2_SP_REGNUM; 421 *imm = GET_IW_T1I7_IMM7 (insn) << 2; 422 return 1; 423 } 424 else if (op->match == MATCH_R2_SPINCI_N || op->match == MATCH_R2_SPDECI_N) 425 { 426 *ra = NIOS2_SP_REGNUM; 427 *rb = NIOS2_SP_REGNUM; 428 *imm = GET_IW_X1I7_IMM7 (insn) << 2; 429 if (op->match == MATCH_R2_SPDECI_N) 430 *imm = - (*imm); 431 return 1; 432 } 433 return 0; 434} 435 436/* Match and disassemble an ORHI-type instruction, with 2 register operands 437 and one unsigned immediate operand. 438 Returns true on success, and fills in the operand pointers. */ 439 440static int 441nios2_match_orhi (uint32_t insn, const struct nios2_opcode *op, 442 unsigned long mach, int *ra, int *rb, unsigned int *uimm) 443{ 444 int is_r2 = (mach == bfd_mach_nios2r2); 445 446 if (!is_r2 && op->match == MATCH_R1_ORHI) 447 { 448 *ra = GET_IW_I_A (insn); 449 *rb = GET_IW_I_B (insn); 450 *uimm = GET_IW_I_IMM16 (insn); 451 return 1; 452 } 453 else if (!is_r2) 454 return 0; 455 else if (op->match == MATCH_R2_ORHI) 456 { 457 *ra = GET_IW_F2I16_A (insn); 458 *rb = GET_IW_F2I16_B (insn); 459 *uimm = GET_IW_F2I16_IMM16 (insn); 460 return 1; 461 } 462 return 0; 463} 464 465/* Match and disassemble a STW-type instruction, with 2 register operands 466 and one immediate operand. 467 Returns true on success, and fills in the operand pointers. */ 468 469static int 470nios2_match_stw (uint32_t insn, const struct nios2_opcode *op, 471 unsigned long mach, int *ra, int *rb, int *imm) 472{ 473 int is_r2 = (mach == bfd_mach_nios2r2); 474 475 if (!is_r2 && (op->match == MATCH_R1_STW || op->match == MATCH_R1_STWIO)) 476 { 477 *ra = GET_IW_I_A (insn); 478 *rb = GET_IW_I_B (insn); 479 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 480 return 1; 481 } 482 else if (!is_r2) 483 return 0; 484 else if (op->match == MATCH_R2_STW) 485 { 486 *ra = GET_IW_F2I16_A (insn); 487 *rb = GET_IW_F2I16_B (insn); 488 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 489 return 1; 490 } 491 else if (op->match == MATCH_R2_STWIO) 492 { 493 *ra = GET_IW_F2X4I12_A (insn); 494 *rb = GET_IW_F2X4I12_B (insn); 495 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20; 496 return 1; 497 } 498 else if (op->match == MATCH_R2_STW_N) 499 { 500 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)]; 501 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)]; 502 *imm = GET_IW_T2I4_IMM4 (insn) << 2; 503 return 1; 504 } 505 else if (op->match == MATCH_R2_STWSP_N) 506 { 507 *ra = NIOS2_SP_REGNUM; 508 *rb = GET_IW_F1I5_B (insn); 509 *imm = GET_IW_F1I5_IMM5 (insn) << 2; 510 return 1; 511 } 512 else if (op->match == MATCH_R2_STWZ_N) 513 { 514 *ra = nios2_r2_reg3_mappings[GET_IW_T1X1I6_A3 (insn)]; 515 *rb = 0; 516 *imm = GET_IW_T1X1I6_IMM6 (insn) << 2; 517 return 1; 518 } 519 return 0; 520} 521 522/* Match and disassemble a LDW-type instruction, with 2 register operands 523 and one immediate operand. 524 Returns true on success, and fills in the operand pointers. */ 525 526static int 527nios2_match_ldw (uint32_t insn, const struct nios2_opcode *op, 528 unsigned long mach, int *ra, int *rb, int *imm) 529{ 530 int is_r2 = (mach == bfd_mach_nios2r2); 531 532 if (!is_r2 && (op->match == MATCH_R1_LDW || op->match == MATCH_R1_LDWIO)) 533 { 534 *ra = GET_IW_I_A (insn); 535 *rb = GET_IW_I_B (insn); 536 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 537 return 1; 538 } 539 else if (!is_r2) 540 return 0; 541 else if (op->match == MATCH_R2_LDW) 542 { 543 *ra = GET_IW_F2I16_A (insn); 544 *rb = GET_IW_F2I16_B (insn); 545 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 546 return 1; 547 } 548 else if (op->match == MATCH_R2_LDWIO) 549 { 550 *ra = GET_IW_F2X4I12_A (insn); 551 *rb = GET_IW_F2X4I12_B (insn); 552 *imm = (signed) (GET_IW_F2X4I12_IMM12 (insn) << 20) >> 20; 553 return 1; 554 } 555 else if (op->match == MATCH_R2_LDW_N) 556 { 557 *ra = nios2_r2_reg3_mappings[GET_IW_T2I4_A3 (insn)]; 558 *rb = nios2_r2_reg3_mappings[GET_IW_T2I4_B3 (insn)]; 559 *imm = GET_IW_T2I4_IMM4 (insn) << 2; 560 return 1; 561 } 562 else if (op->match == MATCH_R2_LDWSP_N) 563 { 564 *ra = NIOS2_SP_REGNUM; 565 *rb = GET_IW_F1I5_B (insn); 566 *imm = GET_IW_F1I5_IMM5 (insn) << 2; 567 return 1; 568 } 569 return 0; 570} 571 572/* Match and disassemble a RDCTL instruction, with 2 register operands. 573 Returns true on success, and fills in the operand pointers. */ 574 575static int 576nios2_match_rdctl (uint32_t insn, const struct nios2_opcode *op, 577 unsigned long mach, int *ra, int *rc) 578{ 579 int is_r2 = (mach == bfd_mach_nios2r2); 580 581 if (!is_r2 && (op->match == MATCH_R1_RDCTL)) 582 { 583 *ra = GET_IW_R_IMM5 (insn); 584 *rc = GET_IW_R_C (insn); 585 return 1; 586 } 587 else if (!is_r2) 588 return 0; 589 else if (op->match == MATCH_R2_RDCTL) 590 { 591 *ra = GET_IW_F3X6L5_IMM5 (insn); 592 *rc = GET_IW_F3X6L5_C (insn); 593 return 1; 594 } 595 return 0; 596} 597 598/* Match and disassemble a PUSH.N or STWM instruction. 599 Returns true on success, and fills in the operand pointers. */ 600 601static int 602nios2_match_stwm (uint32_t insn, const struct nios2_opcode *op, 603 unsigned long mach, unsigned int *reglist, 604 int *ra, int *imm, int *wb, int *id) 605{ 606 int is_r2 = (mach == bfd_mach_nios2r2); 607 608 if (!is_r2) 609 return 0; 610 else if (op->match == MATCH_R2_PUSH_N) 611 { 612 *reglist = 1 << 31; 613 if (GET_IW_L5I4X1_FP (insn)) 614 *reglist |= (1 << 28); 615 if (GET_IW_L5I4X1_CS (insn)) 616 { 617 int val = GET_IW_L5I4X1_REGRANGE (insn); 618 *reglist |= nios2_r2_reg_range_mappings[val]; 619 } 620 *ra = NIOS2_SP_REGNUM; 621 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2; 622 *wb = 1; 623 *id = 0; 624 return 1; 625 } 626 else if (op->match == MATCH_R2_STWM) 627 { 628 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn); 629 if (GET_IW_F1X4L17_RS (insn)) 630 { 631 *reglist = ((rawmask << 14) & 0x00ffc000); 632 if (rawmask & (1 << 10)) 633 *reglist |= (1 << 28); 634 if (rawmask & (1 << 11)) 635 *reglist |= (1 << 31); 636 } 637 else 638 *reglist = rawmask << 2; 639 *ra = GET_IW_F1X4L17_A (insn); 640 *imm = 0; 641 *wb = GET_IW_F1X4L17_WB (insn); 642 *id = GET_IW_F1X4L17_ID (insn); 643 return 1; 644 } 645 return 0; 646} 647 648/* Match and disassemble a POP.N or LDWM instruction. 649 Returns true on success, and fills in the operand pointers. */ 650 651static int 652nios2_match_ldwm (uint32_t insn, const struct nios2_opcode *op, 653 unsigned long mach, unsigned int *reglist, 654 int *ra, int *imm, int *wb, int *id, int *ret) 655{ 656 int is_r2 = (mach == bfd_mach_nios2r2); 657 658 if (!is_r2) 659 return 0; 660 else if (op->match == MATCH_R2_POP_N) 661 { 662 *reglist = 1 << 31; 663 if (GET_IW_L5I4X1_FP (insn)) 664 *reglist |= (1 << 28); 665 if (GET_IW_L5I4X1_CS (insn)) 666 { 667 int val = GET_IW_L5I4X1_REGRANGE (insn); 668 *reglist |= nios2_r2_reg_range_mappings[val]; 669 } 670 *ra = NIOS2_SP_REGNUM; 671 *imm = GET_IW_L5I4X1_IMM4 (insn) << 2; 672 *wb = 1; 673 *id = 1; 674 *ret = 1; 675 return 1; 676 } 677 else if (op->match == MATCH_R2_LDWM) 678 { 679 unsigned int rawmask = GET_IW_F1X4L17_REGMASK (insn); 680 if (GET_IW_F1X4L17_RS (insn)) 681 { 682 *reglist = ((rawmask << 14) & 0x00ffc000); 683 if (rawmask & (1 << 10)) 684 *reglist |= (1 << 28); 685 if (rawmask & (1 << 11)) 686 *reglist |= (1 << 31); 687 } 688 else 689 *reglist = rawmask << 2; 690 *ra = GET_IW_F1X4L17_A (insn); 691 *imm = 0; 692 *wb = GET_IW_F1X4L17_WB (insn); 693 *id = GET_IW_F1X4L17_ID (insn); 694 *ret = GET_IW_F1X4L17_PC (insn); 695 return 1; 696 } 697 return 0; 698} 699 700/* Match and disassemble a branch instruction, with (potentially) 701 2 register operands and one immediate operand. 702 Returns true on success, and fills in the operand pointers. */ 703 704enum branch_condition { 705 branch_none, 706 branch_eq, 707 branch_ne, 708 branch_ge, 709 branch_geu, 710 branch_lt, 711 branch_ltu 712}; 713 714static int 715nios2_match_branch (uint32_t insn, const struct nios2_opcode *op, 716 unsigned long mach, int *ra, int *rb, int *imm, 717 enum branch_condition *cond) 718{ 719 int is_r2 = (mach == bfd_mach_nios2r2); 720 721 if (!is_r2) 722 { 723 switch (op->match) 724 { 725 case MATCH_R1_BR: 726 *cond = branch_none; 727 break; 728 case MATCH_R1_BEQ: 729 *cond = branch_eq; 730 break; 731 case MATCH_R1_BNE: 732 *cond = branch_ne; 733 break; 734 case MATCH_R1_BGE: 735 *cond = branch_ge; 736 break; 737 case MATCH_R1_BGEU: 738 *cond = branch_geu; 739 break; 740 case MATCH_R1_BLT: 741 *cond = branch_lt; 742 break; 743 case MATCH_R1_BLTU: 744 *cond = branch_ltu; 745 break; 746 default: 747 return 0; 748 } 749 *imm = (signed) (GET_IW_I_IMM16 (insn) << 16) >> 16; 750 *ra = GET_IW_I_A (insn); 751 *rb = GET_IW_I_B (insn); 752 return 1; 753 } 754 else 755 { 756 switch (op->match) 757 { 758 case MATCH_R2_BR_N: 759 *cond = branch_none; 760 *ra = NIOS2_Z_REGNUM; 761 *rb = NIOS2_Z_REGNUM; 762 *imm = (signed) ((GET_IW_I10_IMM10 (insn) << 1) << 21) >> 21; 763 return 1; 764 case MATCH_R2_BEQZ_N: 765 *cond = branch_eq; 766 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 767 *rb = NIOS2_Z_REGNUM; 768 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24; 769 return 1; 770 case MATCH_R2_BNEZ_N: 771 *cond = branch_ne; 772 *ra = nios2_r2_reg3_mappings[GET_IW_T1I7_A3 (insn)]; 773 *rb = NIOS2_Z_REGNUM; 774 *imm = (signed) ((GET_IW_T1I7_IMM7 (insn) << 1) << 24) >> 24; 775 return 1; 776 case MATCH_R2_BR: 777 *cond = branch_none; 778 break; 779 case MATCH_R2_BEQ: 780 *cond = branch_eq; 781 break; 782 case MATCH_R2_BNE: 783 *cond = branch_ne; 784 break; 785 case MATCH_R2_BGE: 786 *cond = branch_ge; 787 break; 788 case MATCH_R2_BGEU: 789 *cond = branch_geu; 790 break; 791 case MATCH_R2_BLT: 792 *cond = branch_lt; 793 break; 794 case MATCH_R2_BLTU: 795 *cond = branch_ltu; 796 break; 797 default: 798 return 0; 799 } 800 *ra = GET_IW_F2I16_A (insn); 801 *rb = GET_IW_F2I16_B (insn); 802 *imm = (signed) (GET_IW_F2I16_IMM16 (insn) << 16) >> 16; 803 return 1; 804 } 805 return 0; 806} 807 808/* Match and disassemble a direct jump instruction, with an 809 unsigned operand. Returns true on success, and fills in the operand 810 pointer. */ 811 812static int 813nios2_match_jmpi (uint32_t insn, const struct nios2_opcode *op, 814 unsigned long mach, unsigned int *uimm) 815{ 816 int is_r2 = (mach == bfd_mach_nios2r2); 817 818 if (!is_r2 && op->match == MATCH_R1_JMPI) 819 { 820 *uimm = GET_IW_J_IMM26 (insn) << 2; 821 return 1; 822 } 823 else if (!is_r2) 824 return 0; 825 else if (op->match == MATCH_R2_JMPI) 826 { 827 *uimm = GET_IW_L26_IMM26 (insn) << 2; 828 return 1; 829 } 830 return 0; 831} 832 833/* Match and disassemble a direct call instruction, with an 834 unsigned operand. Returns true on success, and fills in the operand 835 pointer. */ 836 837static int 838nios2_match_calli (uint32_t insn, const struct nios2_opcode *op, 839 unsigned long mach, unsigned int *uimm) 840{ 841 int is_r2 = (mach == bfd_mach_nios2r2); 842 843 if (!is_r2 && op->match == MATCH_R1_CALL) 844 { 845 *uimm = GET_IW_J_IMM26 (insn) << 2; 846 return 1; 847 } 848 else if (!is_r2) 849 return 0; 850 else if (op->match == MATCH_R2_CALL) 851 { 852 *uimm = GET_IW_L26_IMM26 (insn) << 2; 853 return 1; 854 } 855 return 0; 856} 857 858/* Match and disassemble an indirect jump instruction, with a 859 (possibly implicit) register operand. Returns true on success, and fills 860 in the operand pointer. */ 861 862static int 863nios2_match_jmpr (uint32_t insn, const struct nios2_opcode *op, 864 unsigned long mach, int *ra) 865{ 866 int is_r2 = (mach == bfd_mach_nios2r2); 867 868 if (!is_r2) 869 switch (op->match) 870 { 871 case MATCH_R1_JMP: 872 *ra = GET_IW_I_A (insn); 873 return 1; 874 case MATCH_R1_RET: 875 *ra = NIOS2_RA_REGNUM; 876 return 1; 877 case MATCH_R1_ERET: 878 *ra = NIOS2_EA_REGNUM; 879 return 1; 880 case MATCH_R1_BRET: 881 *ra = NIOS2_BA_REGNUM; 882 return 1; 883 default: 884 return 0; 885 } 886 else 887 switch (op->match) 888 { 889 case MATCH_R2_JMP: 890 *ra = GET_IW_F2I16_A (insn); 891 return 1; 892 case MATCH_R2_JMPR_N: 893 *ra = GET_IW_F1X1_A (insn); 894 return 1; 895 case MATCH_R2_RET: 896 case MATCH_R2_RET_N: 897 *ra = NIOS2_RA_REGNUM; 898 return 1; 899 case MATCH_R2_ERET: 900 *ra = NIOS2_EA_REGNUM; 901 return 1; 902 case MATCH_R2_BRET: 903 *ra = NIOS2_BA_REGNUM; 904 return 1; 905 default: 906 return 0; 907 } 908 return 0; 909} 910 911/* Match and disassemble an indirect call instruction, with a register 912 operand. Returns true on success, and fills in the operand pointer. */ 913 914static int 915nios2_match_callr (uint32_t insn, const struct nios2_opcode *op, 916 unsigned long mach, int *ra) 917{ 918 int is_r2 = (mach == bfd_mach_nios2r2); 919 920 if (!is_r2 && op->match == MATCH_R1_CALLR) 921 { 922 *ra = GET_IW_I_A (insn); 923 return 1; 924 } 925 else if (!is_r2) 926 return 0; 927 else if (op->match == MATCH_R2_CALLR) 928 { 929 *ra = GET_IW_F2I16_A (insn); 930 return 1; 931 } 932 else if (op->match == MATCH_R2_CALLR_N) 933 { 934 *ra = GET_IW_F1X1_A (insn); 935 return 1; 936 } 937 return 0; 938} 939 940/* Match and disassemble a break instruction, with an unsigned operand. 941 Returns true on success, and fills in the operand pointer. */ 942 943static int 944nios2_match_break (uint32_t insn, const struct nios2_opcode *op, 945 unsigned long mach, unsigned int *uimm) 946{ 947 int is_r2 = (mach == bfd_mach_nios2r2); 948 949 if (!is_r2 && op->match == MATCH_R1_BREAK) 950 { 951 *uimm = GET_IW_R_IMM5 (insn); 952 return 1; 953 } 954 else if (!is_r2) 955 return 0; 956 else if (op->match == MATCH_R2_BREAK) 957 { 958 *uimm = GET_IW_F3X6L5_IMM5 (insn); 959 return 1; 960 } 961 else if (op->match == MATCH_R2_BREAK_N) 962 { 963 *uimm = GET_IW_X2L5_IMM5 (insn); 964 return 1; 965 } 966 return 0; 967} 968 969/* Match and disassemble a trap instruction, with an unsigned operand. 970 Returns true on success, and fills in the operand pointer. */ 971 972static int 973nios2_match_trap (uint32_t insn, const struct nios2_opcode *op, 974 unsigned long mach, unsigned int *uimm) 975{ 976 int is_r2 = (mach == bfd_mach_nios2r2); 977 978 if (!is_r2 && op->match == MATCH_R1_TRAP) 979 { 980 *uimm = GET_IW_R_IMM5 (insn); 981 return 1; 982 } 983 else if (!is_r2) 984 return 0; 985 else if (op->match == MATCH_R2_TRAP) 986 { 987 *uimm = GET_IW_F3X6L5_IMM5 (insn); 988 return 1; 989 } 990 else if (op->match == MATCH_R2_TRAP_N) 991 { 992 *uimm = GET_IW_X2L5_IMM5 (insn); 993 return 1; 994 } 995 return 0; 996} 997 998/* Helper function to identify when we're in a function epilogue; 999 that is, the part of the function from the point at which the 1000 stack adjustments are made, to the return or sibcall. 1001 Note that we may have several stack adjustment instructions, and 1002 this function needs to test whether the stack teardown has already 1003 started before current_pc, not whether it has completed. */ 1004 1005static int 1006nios2_in_epilogue_p (struct gdbarch *gdbarch, 1007 CORE_ADDR current_pc, 1008 CORE_ADDR start_pc) 1009{ 1010 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1011 int is_r2 = (mach == bfd_mach_nios2r2); 1012 /* Maximum number of possibly-epilogue instructions to check. 1013 Note that this number should not be too large, else we can 1014 potentially end up iterating through unmapped memory. */ 1015 int ninsns, max_insns = 5; 1016 unsigned int insn; 1017 const struct nios2_opcode *op = NULL; 1018 unsigned int uimm; 1019 int imm; 1020 int wb, id, ret; 1021 int ra, rb, rc; 1022 enum branch_condition cond; 1023 CORE_ADDR pc; 1024 1025 /* There has to be a previous instruction in the function. */ 1026 if (current_pc <= start_pc) 1027 return 0; 1028 1029 /* Find the previous instruction before current_pc. For R2, it might 1030 be either a 16-bit or 32-bit instruction; the only way to know for 1031 sure is to scan through from the beginning of the function, 1032 disassembling as we go. */ 1033 if (is_r2) 1034 for (pc = start_pc; ; ) 1035 { 1036 op = nios2_fetch_insn (gdbarch, pc, &insn); 1037 if (op == NULL) 1038 return 0; 1039 if (pc + op->size < current_pc) 1040 pc += op->size; 1041 else 1042 break; 1043 /* We can skip over insns to a forward branch target. Since 1044 the branch offset is relative to the next instruction, 1045 it's correct to do this after incrementing the pc above. */ 1046 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond) 1047 && imm > 0 1048 && pc + imm < current_pc) 1049 pc += imm; 1050 } 1051 /* Otherwise just go back to the previous 32-bit insn. */ 1052 else 1053 pc = current_pc - NIOS2_OPCODE_SIZE; 1054 1055 /* Beginning with the previous instruction we just located, check whether 1056 we are in a sequence of at least one stack adjustment instruction. 1057 Possible instructions here include: 1058 ADDI sp, sp, n 1059 ADD sp, sp, rn 1060 LDW sp, n(sp) 1061 SPINCI.N n 1062 LDWSP.N sp, n(sp) 1063 LDWM {reglist}, (sp)++, wb */ 1064 for (ninsns = 0; ninsns < max_insns; ninsns++) 1065 { 1066 int ok = 0; 1067 1068 /* Fetch the insn at pc. */ 1069 op = nios2_fetch_insn (gdbarch, pc, &insn); 1070 if (op == NULL) 1071 return 0; 1072 pc += op->size; 1073 1074 /* Was it a stack adjustment? */ 1075 if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) 1076 ok = (rb == NIOS2_SP_REGNUM); 1077 else if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) 1078 ok = (rc == NIOS2_SP_REGNUM); 1079 else if (nios2_match_ldw (insn, op, mach, &ra, &rb, &imm)) 1080 ok = (rb == NIOS2_SP_REGNUM); 1081 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, 1082 &imm, &wb, &ret, &id)) 1083 ok = (ra == NIOS2_SP_REGNUM && wb && id); 1084 if (!ok) 1085 break; 1086 } 1087 1088 /* No stack adjustments found. */ 1089 if (ninsns == 0) 1090 return 0; 1091 1092 /* We found more stack adjustments than we expect GCC to be generating. 1093 Since it looks like a stack unwind might be in progress tell GDB to 1094 treat it as such. */ 1095 if (ninsns == max_insns) 1096 return 1; 1097 1098 /* The next instruction following the stack adjustments must be a 1099 return, jump, or unconditional branch, or a CDX pop.n or ldwm 1100 that does an implicit return. */ 1101 if (nios2_match_jmpr (insn, op, mach, &ra) 1102 || nios2_match_jmpi (insn, op, mach, &uimm) 1103 || (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret) 1104 && ret) 1105 || (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond) 1106 && cond == branch_none)) 1107 return 1; 1108 1109 return 0; 1110} 1111 1112/* Implement the stack_frame_destroyed_p gdbarch method. */ 1113 1114static int 1115nios2_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 1116{ 1117 CORE_ADDR func_addr; 1118 1119 if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) 1120 return nios2_in_epilogue_p (gdbarch, pc, func_addr); 1121 1122 return 0; 1123} 1124 1125/* Do prologue analysis, returning the PC of the first instruction 1126 after the function prologue. Assumes CACHE has already been 1127 initialized. THIS_FRAME can be null, in which case we are only 1128 interested in skipping the prologue. Otherwise CACHE is filled in 1129 from the frame information. 1130 1131 The prologue may consist of the following parts: 1132 1) Profiling instrumentation. For non-PIC code it looks like: 1133 mov r8, ra 1134 call mcount 1135 mov ra, r8 1136 1137 2) A stack adjustment and save of R4-R7 for varargs functions. 1138 For R2 CDX this is typically handled with a STWM, otherwise 1139 this is typically merged with item 3. 1140 1141 3) A stack adjustment and save of the callee-saved registers. 1142 For R2 CDX these are typically handled with a PUSH.N or STWM, 1143 otherwise as an explicit SP decrement and individual register 1144 saves. 1145 1146 There may also be a stack switch here in an exception handler 1147 in place of a stack adjustment. It looks like: 1148 movhi rx, %hiadj(newstack) 1149 addhi rx, rx, %lo(newstack) 1150 stw sp, constant(rx) 1151 mov sp, rx 1152 1153 4) A frame pointer save, which can be either a MOV or ADDI. 1154 1155 5) A further stack pointer adjustment. This is normally included 1156 adjustment in step 3 unless the total adjustment is too large 1157 to be done in one step. 1158 1159 7) A stack overflow check, which can take either of these forms: 1160 bgeu sp, rx, +8 1161 trap 3 1162 or 1163 bltu sp, rx, .Lstack_overflow 1164 ... 1165 .Lstack_overflow: 1166 trap 3 1167 1168 Older versions of GCC emitted "break 3" instead of "trap 3" here, 1169 so we check for both cases. 1170 1171 Older GCC versions emitted stack overflow checks after the SP 1172 adjustments in both steps 3 and 4. Starting with GCC 6, there is 1173 at most one overflow check, which is placed before the first 1174 stack adjustment for R2 CDX and after the first stack adjustment 1175 otherwise. 1176 1177 The prologue instructions may be combined or interleaved with other 1178 instructions. 1179 1180 To cope with all this variability we decode all the instructions 1181 from the start of the prologue until we hit an instruction that 1182 cannot possibly be a prologue instruction, such as a branch, call, 1183 return, or epilogue instruction. The prologue is considered to end 1184 at the last instruction that can definitely be considered a 1185 prologue instruction. */ 1186 1187static CORE_ADDR 1188nios2_analyze_prologue (struct gdbarch *gdbarch, const CORE_ADDR start_pc, 1189 const CORE_ADDR current_pc, 1190 struct nios2_unwind_cache *cache, 1191 struct frame_info *this_frame) 1192{ 1193 /* Maximum number of possibly-prologue instructions to check. 1194 Note that this number should not be too large, else we can 1195 potentially end up iterating through unmapped memory. */ 1196 int ninsns, max_insns = 50; 1197 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1198 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1199 1200 /* Does the frame set up the FP register? */ 1201 int base_reg = 0; 1202 1203 struct reg_value *value = cache->reg_value; 1204 struct reg_value temp_value[NIOS2_NUM_REGS]; 1205 1206 int i; 1207 1208 /* Save the starting PC so we can correct the pc after running 1209 through the prolog, using symbol info. */ 1210 CORE_ADDR pc = start_pc; 1211 1212 /* Is this an exception handler? */ 1213 int exception_handler = 0; 1214 1215 /* What was the original value of SP (or fake original value for 1216 functions which switch stacks? */ 1217 CORE_ADDR frame_high; 1218 1219 /* The last definitely-prologue instruction seen. */ 1220 CORE_ADDR prologue_end; 1221 1222 /* Is this the innermost function? */ 1223 int innermost = (this_frame ? (frame_relative_level (this_frame) == 0) : 1); 1224 1225 if (nios2_debug) 1226 fprintf_unfiltered (gdb_stdlog, 1227 "{ nios2_analyze_prologue start=%s, current=%s ", 1228 paddress (gdbarch, start_pc), 1229 paddress (gdbarch, current_pc)); 1230 1231 /* Set up the default values of the registers. */ 1232 nios2_setup_default (cache); 1233 1234 /* Find the prologue instructions. */ 1235 prologue_end = start_pc; 1236 for (ninsns = 0; ninsns < max_insns; ninsns++) 1237 { 1238 /* Present instruction. */ 1239 uint32_t insn; 1240 const struct nios2_opcode *op; 1241 int ra, rb, rc, imm; 1242 unsigned int uimm; 1243 unsigned int reglist; 1244 int wb, id, ret; 1245 enum branch_condition cond; 1246 1247 if (pc == current_pc) 1248 { 1249 /* When we reach the current PC we must save the current 1250 register state (for the backtrace) but keep analysing 1251 because there might be more to find out (eg. is this an 1252 exception handler). */ 1253 memcpy (temp_value, value, sizeof (temp_value)); 1254 value = temp_value; 1255 if (nios2_debug) 1256 fprintf_unfiltered (gdb_stdlog, "*"); 1257 } 1258 1259 op = nios2_fetch_insn (gdbarch, pc, &insn); 1260 1261 /* Unknown opcode? Stop scanning. */ 1262 if (op == NULL) 1263 break; 1264 pc += op->size; 1265 1266 if (nios2_debug) 1267 { 1268 if (op->size == 2) 1269 fprintf_unfiltered (gdb_stdlog, "[%04X]", insn & 0xffff); 1270 else 1271 fprintf_unfiltered (gdb_stdlog, "[%08X]", insn); 1272 } 1273 1274 /* The following instructions can appear in the prologue. */ 1275 1276 if (nios2_match_add (insn, op, mach, &ra, &rb, &rc)) 1277 { 1278 /* ADD rc, ra, rb (also used for MOV) */ 1279 if (rc == NIOS2_SP_REGNUM 1280 && rb == 0 1281 && value[ra].reg == cache->reg_saved[NIOS2_SP_REGNUM].basereg) 1282 { 1283 /* If the previous value of SP is available somewhere 1284 near the new stack pointer value then this is a 1285 stack switch. */ 1286 1287 /* If any registers were saved on the stack before then 1288 we can't backtrace into them now. */ 1289 for (i = 0 ; i < NIOS2_NUM_REGS ; i++) 1290 { 1291 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) 1292 cache->reg_saved[i].basereg = -1; 1293 if (value[i].reg == NIOS2_SP_REGNUM) 1294 value[i].reg = -1; 1295 } 1296 1297 /* Create a fake "high water mark" 4 bytes above where SP 1298 was stored and fake up the registers to be consistent 1299 with that. */ 1300 value[NIOS2_SP_REGNUM].reg = NIOS2_SP_REGNUM; 1301 value[NIOS2_SP_REGNUM].offset 1302 = (value[ra].offset 1303 - cache->reg_saved[NIOS2_SP_REGNUM].addr 1304 - 4); 1305 cache->reg_saved[NIOS2_SP_REGNUM].basereg = NIOS2_SP_REGNUM; 1306 cache->reg_saved[NIOS2_SP_REGNUM].addr = -4; 1307 } 1308 1309 else if (rc == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) 1310 /* This is setting SP from FP. This only happens in the 1311 function epilogue. */ 1312 break; 1313 1314 else if (rc != 0) 1315 { 1316 if (value[rb].reg == 0) 1317 value[rc].reg = value[ra].reg; 1318 else if (value[ra].reg == 0) 1319 value[rc].reg = value[rb].reg; 1320 else 1321 value[rc].reg = -1; 1322 value[rc].offset = value[ra].offset + value[rb].offset; 1323 } 1324 1325 /* The add/move is only considered a prologue instruction 1326 if the destination is SP or FP. */ 1327 if (rc == NIOS2_SP_REGNUM || rc == NIOS2_FP_REGNUM) 1328 prologue_end = pc; 1329 } 1330 1331 else if (nios2_match_sub (insn, op, mach, &ra, &rb, &rc)) 1332 { 1333 /* SUB rc, ra, rb */ 1334 if (rc == NIOS2_SP_REGNUM && rb == NIOS2_SP_REGNUM 1335 && value[rc].reg != 0) 1336 /* If we are decrementing the SP by a non-constant amount, 1337 this is alloca, not part of the prologue. */ 1338 break; 1339 else if (rc != 0) 1340 { 1341 if (value[rb].reg == 0) 1342 value[rc].reg = value[ra].reg; 1343 else 1344 value[rc].reg = -1; 1345 value[rc].offset = value[ra].offset - value[rb].offset; 1346 } 1347 } 1348 1349 else if (nios2_match_addi (insn, op, mach, &ra, &rb, &imm)) 1350 { 1351 /* ADDI rb, ra, imm */ 1352 1353 /* A positive stack adjustment has to be part of the epilogue. */ 1354 if (rb == NIOS2_SP_REGNUM 1355 && (imm > 0 || value[ra].reg != NIOS2_SP_REGNUM)) 1356 break; 1357 1358 /* Likewise restoring SP from FP. */ 1359 else if (rb == NIOS2_SP_REGNUM && ra == NIOS2_FP_REGNUM) 1360 break; 1361 1362 if (rb != 0) 1363 { 1364 value[rb].reg = value[ra].reg; 1365 value[rb].offset = value[ra].offset + imm; 1366 } 1367 1368 /* The add is only considered a prologue instruction 1369 if the destination is SP or FP. */ 1370 if (rb == NIOS2_SP_REGNUM || rb == NIOS2_FP_REGNUM) 1371 prologue_end = pc; 1372 } 1373 1374 else if (nios2_match_orhi (insn, op, mach, &ra, &rb, &uimm)) 1375 { 1376 /* ORHI rb, ra, uimm (also used for MOVHI) */ 1377 if (rb != 0) 1378 { 1379 value[rb].reg = (value[ra].reg == 0) ? 0 : -1; 1380 value[rb].offset = value[ra].offset | (uimm << 16); 1381 } 1382 } 1383 1384 else if (nios2_match_stw (insn, op, mach, &ra, &rb, &imm)) 1385 { 1386 /* STW rb, imm(ra) */ 1387 1388 /* Are we storing the original value of a register to the stack? 1389 For exception handlers the value of EA-4 (return 1390 address from interrupts etc) is sometimes stored. */ 1391 int orig = value[rb].reg; 1392 if (orig > 0 1393 && (value[rb].offset == 0 1394 || (orig == NIOS2_EA_REGNUM && value[rb].offset == -4)) 1395 && value[ra].reg == NIOS2_SP_REGNUM) 1396 { 1397 if (pc < current_pc) 1398 { 1399 /* Save off callee saved registers. */ 1400 cache->reg_saved[orig].basereg = value[ra].reg; 1401 cache->reg_saved[orig].addr = value[ra].offset + imm; 1402 } 1403 1404 prologue_end = pc; 1405 1406 if (orig == NIOS2_EA_REGNUM || orig == NIOS2_ESTATUS_REGNUM) 1407 exception_handler = 1; 1408 } 1409 else 1410 /* Non-stack memory writes cannot appear in the prologue. */ 1411 break; 1412 } 1413 1414 else if (nios2_match_stwm (insn, op, mach, 1415 ®list, &ra, &imm, &wb, &id)) 1416 { 1417 /* PUSH.N {reglist}, adjust 1418 or 1419 STWM {reglist}, --(SP)[, writeback] */ 1420 int i; 1421 int off = 0; 1422 1423 if (ra != NIOS2_SP_REGNUM || id != 0) 1424 /* This is a non-stack-push memory write and cannot be 1425 part of the prologue. */ 1426 break; 1427 1428 for (i = 31; i >= 0; i--) 1429 if (reglist & (1 << i)) 1430 { 1431 int orig = value[i].reg; 1432 1433 off += 4; 1434 if (orig > 0 && value[i].offset == 0 && pc < current_pc) 1435 { 1436 cache->reg_saved[orig].basereg 1437 = value[NIOS2_SP_REGNUM].reg; 1438 cache->reg_saved[orig].addr 1439 = value[NIOS2_SP_REGNUM].offset - off; 1440 } 1441 } 1442 1443 if (wb) 1444 value[NIOS2_SP_REGNUM].offset -= off; 1445 value[NIOS2_SP_REGNUM].offset -= imm; 1446 1447 prologue_end = pc; 1448 } 1449 1450 else if (nios2_match_rdctl (insn, op, mach, &ra, &rc)) 1451 { 1452 /* RDCTL rC, ctlN 1453 This can appear in exception handlers in combination with 1454 a subsequent save to the stack frame. */ 1455 if (rc != 0) 1456 { 1457 value[rc].reg = NIOS2_STATUS_REGNUM + ra; 1458 value[rc].offset = 0; 1459 } 1460 } 1461 1462 else if (nios2_match_calli (insn, op, mach, &uimm)) 1463 { 1464 if (value[8].reg == NIOS2_RA_REGNUM 1465 && value[8].offset == 0 1466 && value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM 1467 && value[NIOS2_SP_REGNUM].offset == 0) 1468 { 1469 /* A CALL instruction. This is treated as a call to mcount 1470 if ra has been stored into r8 beforehand and if it's 1471 before the stack adjust. 1472 Note mcount corrupts r2-r3, r9-r15 & ra. */ 1473 for (i = 2 ; i <= 3 ; i++) 1474 value[i].reg = -1; 1475 for (i = 9 ; i <= 15 ; i++) 1476 value[i].reg = -1; 1477 value[NIOS2_RA_REGNUM].reg = -1; 1478 1479 prologue_end = pc; 1480 } 1481 1482 /* Other calls are not part of the prologue. */ 1483 else 1484 break; 1485 } 1486 1487 else if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) 1488 { 1489 /* Branches not involving a stack overflow check aren't part of 1490 the prologue. */ 1491 if (ra != NIOS2_SP_REGNUM) 1492 break; 1493 else if (cond == branch_geu) 1494 { 1495 /* BGEU sp, rx, +8 1496 TRAP 3 (or BREAK 3) 1497 This instruction sequence is used in stack checking; 1498 we can ignore it. */ 1499 unsigned int next_insn; 1500 const struct nios2_opcode *next_op 1501 = nios2_fetch_insn (gdbarch, pc, &next_insn); 1502 if (next_op != NULL 1503 && (nios2_match_trap (next_insn, op, mach, &uimm) 1504 || nios2_match_break (next_insn, op, mach, &uimm))) 1505 pc += next_op->size; 1506 else 1507 break; 1508 } 1509 else if (cond == branch_ltu) 1510 { 1511 /* BLTU sp, rx, .Lstackoverflow 1512 If the location branched to holds a TRAP or BREAK 1513 instruction then this is also stack overflow detection. */ 1514 unsigned int next_insn; 1515 const struct nios2_opcode *next_op 1516 = nios2_fetch_insn (gdbarch, pc + imm, &next_insn); 1517 if (next_op != NULL 1518 && (nios2_match_trap (next_insn, op, mach, &uimm) 1519 || nios2_match_break (next_insn, op, mach, &uimm))) 1520 ; 1521 else 1522 break; 1523 } 1524 else 1525 break; 1526 } 1527 1528 /* All other calls, jumps, returns, TRAPs, or BREAKs terminate 1529 the prologue. */ 1530 else if (nios2_match_callr (insn, op, mach, &ra) 1531 || nios2_match_jmpr (insn, op, mach, &ra) 1532 || nios2_match_jmpi (insn, op, mach, &uimm) 1533 || (nios2_match_ldwm (insn, op, mach, ®list, &ra, 1534 &imm, &wb, &id, &ret) 1535 && ret) 1536 || nios2_match_trap (insn, op, mach, &uimm) 1537 || nios2_match_break (insn, op, mach, &uimm)) 1538 break; 1539 } 1540 1541 /* If THIS_FRAME is NULL, we are being called from skip_prologue 1542 and are only interested in the PROLOGUE_END value, so just 1543 return that now and skip over the cache updates, which depend 1544 on having frame information. */ 1545 if (this_frame == NULL) 1546 return prologue_end; 1547 1548 /* If we are in the function epilogue and have already popped 1549 registers off the stack in preparation for returning, then we 1550 want to go back to the original register values. */ 1551 if (innermost && nios2_in_epilogue_p (gdbarch, current_pc, start_pc)) 1552 nios2_setup_default (cache); 1553 1554 /* Exception handlers use a different return address register. */ 1555 if (exception_handler) 1556 cache->return_regnum = NIOS2_EA_REGNUM; 1557 1558 if (nios2_debug) 1559 fprintf_unfiltered (gdb_stdlog, "\n-> retreg=%d, ", cache->return_regnum); 1560 1561 if (cache->reg_value[NIOS2_FP_REGNUM].reg == NIOS2_SP_REGNUM) 1562 /* If the FP now holds an offset from the CFA then this is a 1563 normal frame which uses the frame pointer. */ 1564 base_reg = NIOS2_FP_REGNUM; 1565 else if (cache->reg_value[NIOS2_SP_REGNUM].reg == NIOS2_SP_REGNUM) 1566 /* FP doesn't hold an offset from the CFA. If SP still holds an 1567 offset from the CFA then we might be in a function which omits 1568 the frame pointer, or we might be partway through the prologue. 1569 In both cases we can find the CFA using SP. */ 1570 base_reg = NIOS2_SP_REGNUM; 1571 else 1572 { 1573 /* Somehow the stack pointer has been corrupted. 1574 We can't return. */ 1575 if (nios2_debug) 1576 fprintf_unfiltered (gdb_stdlog, "<can't reach cfa> }\n"); 1577 return 0; 1578 } 1579 1580 if (cache->reg_value[base_reg].offset == 0 1581 || cache->reg_saved[NIOS2_RA_REGNUM].basereg != NIOS2_SP_REGNUM 1582 || cache->reg_saved[cache->return_regnum].basereg != NIOS2_SP_REGNUM) 1583 { 1584 /* If the frame didn't adjust the stack, didn't save RA or 1585 didn't save EA in an exception handler then it must either 1586 be a leaf function (doesn't call any other functions) or it 1587 can't return. If it has called another function then it 1588 can't be a leaf, so set base == 0 to indicate that we can't 1589 backtrace past it. */ 1590 1591 if (!innermost) 1592 { 1593 /* If it isn't the innermost function then it can't be a 1594 leaf, unless it was interrupted. Check whether RA for 1595 this frame is the same as PC. If so then it probably 1596 wasn't interrupted. */ 1597 CORE_ADDR ra 1598 = get_frame_register_unsigned (this_frame, NIOS2_RA_REGNUM); 1599 1600 if (ra == current_pc) 1601 { 1602 if (nios2_debug) 1603 fprintf_unfiltered 1604 (gdb_stdlog, 1605 "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n", 1606 paddress (gdbarch, cache->reg_value[base_reg].offset), 1607 cache->reg_saved[NIOS2_RA_REGNUM].basereg, 1608 cache->return_regnum, 1609 cache->reg_saved[cache->return_regnum].basereg); 1610 return 0; 1611 } 1612 } 1613 } 1614 1615 /* Get the value of whichever register we are using for the 1616 base. */ 1617 cache->base = get_frame_register_unsigned (this_frame, base_reg); 1618 1619 /* What was the value of SP at the start of this function (or just 1620 after the stack switch). */ 1621 frame_high = cache->base - cache->reg_value[base_reg].offset; 1622 1623 /* Adjust all the saved registers such that they contain addresses 1624 instead of offsets. */ 1625 for (i = 0; i < NIOS2_NUM_REGS; i++) 1626 if (cache->reg_saved[i].basereg == NIOS2_SP_REGNUM) 1627 { 1628 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; 1629 cache->reg_saved[i].addr += frame_high; 1630 } 1631 1632 for (i = 0; i < NIOS2_NUM_REGS; i++) 1633 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) 1634 { 1635 CORE_ADDR gp = get_frame_register_unsigned (this_frame, 1636 NIOS2_GP_REGNUM); 1637 1638 for ( ; i < NIOS2_NUM_REGS; i++) 1639 if (cache->reg_saved[i].basereg == NIOS2_GP_REGNUM) 1640 { 1641 cache->reg_saved[i].basereg = NIOS2_Z_REGNUM; 1642 cache->reg_saved[i].addr += gp; 1643 } 1644 } 1645 1646 /* Work out what the value of SP was on the first instruction of 1647 this function. If we didn't switch stacks then this can be 1648 trivially computed from the base address. */ 1649 if (cache->reg_saved[NIOS2_SP_REGNUM].basereg == NIOS2_Z_REGNUM) 1650 cache->cfa 1651 = read_memory_unsigned_integer (cache->reg_saved[NIOS2_SP_REGNUM].addr, 1652 4, byte_order); 1653 else 1654 cache->cfa = frame_high; 1655 1656 /* Exception handlers restore ESTATUS into STATUS. */ 1657 if (exception_handler) 1658 { 1659 cache->reg_saved[NIOS2_STATUS_REGNUM] 1660 = cache->reg_saved[NIOS2_ESTATUS_REGNUM]; 1661 cache->reg_saved[NIOS2_ESTATUS_REGNUM].basereg = -1; 1662 } 1663 1664 if (nios2_debug) 1665 fprintf_unfiltered (gdb_stdlog, "cfa=%s }\n", 1666 paddress (gdbarch, cache->cfa)); 1667 1668 return prologue_end; 1669} 1670 1671/* Implement the skip_prologue gdbarch hook. */ 1672 1673static CORE_ADDR 1674nios2_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) 1675{ 1676 CORE_ADDR func_addr; 1677 1678 struct nios2_unwind_cache cache; 1679 1680 /* See if we can determine the end of the prologue via the symbol 1681 table. If so, then return either PC, or the PC after the 1682 prologue, whichever is greater. */ 1683 if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) 1684 { 1685 CORE_ADDR post_prologue_pc 1686 = skip_prologue_using_sal (gdbarch, func_addr); 1687 1688 if (post_prologue_pc != 0) 1689 return std::max (start_pc, post_prologue_pc); 1690 } 1691 1692 /* Prologue analysis does the rest.... */ 1693 nios2_init_cache (&cache, start_pc); 1694 return nios2_analyze_prologue (gdbarch, start_pc, start_pc, &cache, NULL); 1695} 1696 1697/* Implement the breakpoint_kind_from_pc gdbarch method. */ 1698 1699static int 1700nios2_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 1701{ 1702 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1703 1704 if (mach == bfd_mach_nios2r2) 1705 { 1706 unsigned int insn; 1707 const struct nios2_opcode *op 1708 = nios2_fetch_insn (gdbarch, *pcptr, &insn); 1709 1710 if (op && op->size == NIOS2_CDX_OPCODE_SIZE) 1711 return NIOS2_CDX_OPCODE_SIZE; 1712 else 1713 return NIOS2_OPCODE_SIZE; 1714 } 1715 else 1716 return NIOS2_OPCODE_SIZE; 1717} 1718 1719/* Implement the sw_breakpoint_from_kind gdbarch method. */ 1720 1721static const gdb_byte * 1722nios2_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 1723{ 1724/* The Nios II ABI for Linux says: "Userspace programs should not use 1725 the break instruction and userspace debuggers should not insert 1726 one." and "Userspace breakpoints are accomplished using the trap 1727 instruction with immediate operand 31 (all ones)." 1728 1729 So, we use "trap 31" consistently as the breakpoint on bare-metal 1730 as well as Linux targets. */ 1731 1732 /* R2 trap encoding: 1733 ((0x2d << 26) | (0x1f << 21) | (0x1d << 16) | (0x20 << 0)) 1734 0xb7fd0020 1735 CDX trap.n encoding: 1736 ((0xd << 12) | (0x1f << 6) | (0x9 << 0)) 1737 0xd7c9 1738 Note that code is always little-endian on R2. */ 1739 *size = kind; 1740 1741 if (kind == NIOS2_CDX_OPCODE_SIZE) 1742 { 1743 static const gdb_byte cdx_breakpoint_le[] = {0xc9, 0xd7}; 1744 1745 return cdx_breakpoint_le; 1746 } 1747 else 1748 { 1749 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 1750 1751 if (mach == bfd_mach_nios2r2) 1752 { 1753 static const gdb_byte r2_breakpoint_le[] = {0x20, 0x00, 0xfd, 0xb7}; 1754 1755 return r2_breakpoint_le; 1756 } 1757 else 1758 { 1759 enum bfd_endian byte_order_for_code 1760 = gdbarch_byte_order_for_code (gdbarch); 1761 /* R1 trap encoding: 1762 ((0x1d << 17) | (0x2d << 11) | (0x1f << 6) | (0x3a << 0)) 1763 0x003b6ffa */ 1764 static const gdb_byte r1_breakpoint_le[] = {0xfa, 0x6f, 0x3b, 0x0}; 1765 static const gdb_byte r1_breakpoint_be[] = {0x0, 0x3b, 0x6f, 0xfa}; 1766 1767 if (byte_order_for_code == BFD_ENDIAN_BIG) 1768 return r1_breakpoint_be; 1769 else 1770 return r1_breakpoint_le; 1771 } 1772 } 1773} 1774 1775/* Implement the print_insn gdbarch method. */ 1776 1777static int 1778nios2_print_insn (bfd_vma memaddr, disassemble_info *info) 1779{ 1780 if (info->endian == BFD_ENDIAN_BIG) 1781 return print_insn_big_nios2 (memaddr, info); 1782 else 1783 return print_insn_little_nios2 (memaddr, info); 1784} 1785 1786 1787/* Implement the frame_align gdbarch method. */ 1788 1789static CORE_ADDR 1790nios2_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 1791{ 1792 return align_down (addr, 4); 1793} 1794 1795 1796/* Implement the return_value gdbarch method. */ 1797 1798static enum return_value_convention 1799nios2_return_value (struct gdbarch *gdbarch, struct value *function, 1800 struct type *type, struct regcache *regcache, 1801 gdb_byte *readbuf, const gdb_byte *writebuf) 1802{ 1803 if (TYPE_LENGTH (type) > 8) 1804 return RETURN_VALUE_STRUCT_CONVENTION; 1805 1806 if (readbuf) 1807 nios2_extract_return_value (gdbarch, type, regcache, readbuf); 1808 if (writebuf) 1809 nios2_store_return_value (gdbarch, type, regcache, writebuf); 1810 1811 return RETURN_VALUE_REGISTER_CONVENTION; 1812} 1813 1814/* Implement the dummy_id gdbarch method. */ 1815 1816static struct frame_id 1817nios2_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1818{ 1819 return frame_id_build 1820 (get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM), 1821 get_frame_pc (this_frame)); 1822} 1823 1824/* Implement the push_dummy_call gdbarch method. */ 1825 1826static CORE_ADDR 1827nios2_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1828 struct regcache *regcache, CORE_ADDR bp_addr, 1829 int nargs, struct value **args, CORE_ADDR sp, 1830 int struct_return, CORE_ADDR struct_addr) 1831{ 1832 int argreg; 1833 int float_argreg; 1834 int argnum; 1835 int len = 0; 1836 int stack_offset = 0; 1837 CORE_ADDR func_addr = find_function_addr (function, NULL); 1838 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1839 1840 /* Set the return address register to point to the entry point of 1841 the program, where a breakpoint lies in wait. */ 1842 regcache_cooked_write_signed (regcache, NIOS2_RA_REGNUM, bp_addr); 1843 1844 /* Now make space on the stack for the args. */ 1845 for (argnum = 0; argnum < nargs; argnum++) 1846 len += align_up (TYPE_LENGTH (value_type (args[argnum])), 4); 1847 sp -= len; 1848 1849 /* Initialize the register pointer. */ 1850 argreg = NIOS2_FIRST_ARGREG; 1851 1852 /* The struct_return pointer occupies the first parameter-passing 1853 register. */ 1854 if (struct_return) 1855 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 1856 1857 /* Now load as many as possible of the first arguments into 1858 registers, and push the rest onto the stack. Loop through args 1859 from first to last. */ 1860 for (argnum = 0; argnum < nargs; argnum++) 1861 { 1862 const gdb_byte *val; 1863 struct value *arg = args[argnum]; 1864 struct type *arg_type = check_typedef (value_type (arg)); 1865 int len = TYPE_LENGTH (arg_type); 1866 1867 val = value_contents (arg); 1868 1869 /* Copy the argument to general registers or the stack in 1870 register-sized pieces. Large arguments are split between 1871 registers and stack. */ 1872 while (len > 0) 1873 { 1874 int partial_len = (len < 4 ? len : 4); 1875 1876 if (argreg <= NIOS2_LAST_ARGREG) 1877 { 1878 /* The argument is being passed in a register. */ 1879 CORE_ADDR regval = extract_unsigned_integer (val, partial_len, 1880 byte_order); 1881 1882 regcache_cooked_write_unsigned (regcache, argreg, regval); 1883 argreg++; 1884 } 1885 else 1886 { 1887 /* The argument is being passed on the stack. */ 1888 CORE_ADDR addr = sp + stack_offset; 1889 1890 write_memory (addr, val, partial_len); 1891 stack_offset += align_up (partial_len, 4); 1892 } 1893 1894 len -= partial_len; 1895 val += partial_len; 1896 } 1897 } 1898 1899 regcache_cooked_write_signed (regcache, NIOS2_SP_REGNUM, sp); 1900 1901 /* Return adjusted stack pointer. */ 1902 return sp; 1903} 1904 1905/* Implement the unwind_pc gdbarch method. */ 1906 1907static CORE_ADDR 1908nios2_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1909{ 1910 gdb_byte buf[4]; 1911 1912 frame_unwind_register (next_frame, NIOS2_PC_REGNUM, buf); 1913 return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); 1914} 1915 1916/* Implement the unwind_sp gdbarch method. */ 1917 1918static CORE_ADDR 1919nios2_unwind_sp (struct gdbarch *gdbarch, struct frame_info *this_frame) 1920{ 1921 return frame_unwind_register_unsigned (this_frame, NIOS2_SP_REGNUM); 1922} 1923 1924/* Use prologue analysis to fill in the register cache 1925 *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes 1926 *THIS_PROLOGUE_CACHE first. */ 1927 1928static struct nios2_unwind_cache * 1929nios2_frame_unwind_cache (struct frame_info *this_frame, 1930 void **this_prologue_cache) 1931{ 1932 struct gdbarch *gdbarch = get_frame_arch (this_frame); 1933 CORE_ADDR current_pc; 1934 struct nios2_unwind_cache *cache; 1935 1936 if (*this_prologue_cache) 1937 return (struct nios2_unwind_cache *) *this_prologue_cache; 1938 1939 cache = FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache); 1940 *this_prologue_cache = cache; 1941 1942 /* Zero all fields. */ 1943 nios2_init_cache (cache, get_frame_func (this_frame)); 1944 1945 /* Prologue analysis does the rest... */ 1946 current_pc = get_frame_pc (this_frame); 1947 if (cache->pc != 0) 1948 nios2_analyze_prologue (gdbarch, cache->pc, current_pc, cache, this_frame); 1949 1950 return cache; 1951} 1952 1953/* Implement the this_id function for the normal unwinder. */ 1954 1955static void 1956nios2_frame_this_id (struct frame_info *this_frame, void **this_cache, 1957 struct frame_id *this_id) 1958{ 1959 struct nios2_unwind_cache *cache = 1960 nios2_frame_unwind_cache (this_frame, this_cache); 1961 1962 /* This marks the outermost frame. */ 1963 if (cache->base == 0) 1964 return; 1965 1966 *this_id = frame_id_build (cache->cfa, cache->pc); 1967} 1968 1969/* Implement the prev_register function for the normal unwinder. */ 1970 1971static struct value * 1972nios2_frame_prev_register (struct frame_info *this_frame, void **this_cache, 1973 int regnum) 1974{ 1975 struct nios2_unwind_cache *cache = 1976 nios2_frame_unwind_cache (this_frame, this_cache); 1977 1978 gdb_assert (regnum >= 0 && regnum < NIOS2_NUM_REGS); 1979 1980 /* The PC of the previous frame is stored in the RA register of 1981 the current frame. Frob regnum so that we pull the value from 1982 the correct place. */ 1983 if (regnum == NIOS2_PC_REGNUM) 1984 regnum = cache->return_regnum; 1985 1986 if (regnum == NIOS2_SP_REGNUM && cache->cfa) 1987 return frame_unwind_got_constant (this_frame, regnum, cache->cfa); 1988 1989 /* If we've worked out where a register is stored then load it from 1990 there. */ 1991 if (cache->reg_saved[regnum].basereg == NIOS2_Z_REGNUM) 1992 return frame_unwind_got_memory (this_frame, regnum, 1993 cache->reg_saved[regnum].addr); 1994 1995 return frame_unwind_got_register (this_frame, regnum, regnum); 1996} 1997 1998/* Implement the this_base, this_locals, and this_args hooks 1999 for the normal unwinder. */ 2000 2001static CORE_ADDR 2002nios2_frame_base_address (struct frame_info *this_frame, void **this_cache) 2003{ 2004 struct nios2_unwind_cache *info 2005 = nios2_frame_unwind_cache (this_frame, this_cache); 2006 2007 return info->base; 2008} 2009 2010/* Data structures for the normal prologue-analysis-based 2011 unwinder. */ 2012 2013static const struct frame_unwind nios2_frame_unwind = 2014{ 2015 NORMAL_FRAME, 2016 default_frame_unwind_stop_reason, 2017 nios2_frame_this_id, 2018 nios2_frame_prev_register, 2019 NULL, 2020 default_frame_sniffer 2021}; 2022 2023static const struct frame_base nios2_frame_base = 2024{ 2025 &nios2_frame_unwind, 2026 nios2_frame_base_address, 2027 nios2_frame_base_address, 2028 nios2_frame_base_address 2029}; 2030 2031/* Fill in the register cache *THIS_CACHE for THIS_FRAME for use 2032 in the stub unwinder. */ 2033 2034static struct trad_frame_cache * 2035nios2_stub_frame_cache (struct frame_info *this_frame, void **this_cache) 2036{ 2037 CORE_ADDR pc; 2038 CORE_ADDR start_addr; 2039 CORE_ADDR stack_addr; 2040 struct trad_frame_cache *this_trad_cache; 2041 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2042 2043 if (*this_cache != NULL) 2044 return (struct trad_frame_cache *) *this_cache; 2045 this_trad_cache = trad_frame_cache_zalloc (this_frame); 2046 *this_cache = this_trad_cache; 2047 2048 /* The return address is in the link register. */ 2049 trad_frame_set_reg_realreg (this_trad_cache, 2050 gdbarch_pc_regnum (gdbarch), 2051 NIOS2_RA_REGNUM); 2052 2053 /* Frame ID, since it's a frameless / stackless function, no stack 2054 space is allocated and SP on entry is the current SP. */ 2055 pc = get_frame_pc (this_frame); 2056 find_pc_partial_function (pc, NULL, &start_addr, NULL); 2057 stack_addr = get_frame_register_unsigned (this_frame, NIOS2_SP_REGNUM); 2058 trad_frame_set_id (this_trad_cache, frame_id_build (start_addr, stack_addr)); 2059 /* Assume that the frame's base is the same as the stack pointer. */ 2060 trad_frame_set_this_base (this_trad_cache, stack_addr); 2061 2062 return this_trad_cache; 2063} 2064 2065/* Implement the this_id function for the stub unwinder. */ 2066 2067static void 2068nios2_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, 2069 struct frame_id *this_id) 2070{ 2071 struct trad_frame_cache *this_trad_cache 2072 = nios2_stub_frame_cache (this_frame, this_cache); 2073 2074 trad_frame_get_id (this_trad_cache, this_id); 2075} 2076 2077/* Implement the prev_register function for the stub unwinder. */ 2078 2079static struct value * 2080nios2_stub_frame_prev_register (struct frame_info *this_frame, 2081 void **this_cache, int regnum) 2082{ 2083 struct trad_frame_cache *this_trad_cache 2084 = nios2_stub_frame_cache (this_frame, this_cache); 2085 2086 return trad_frame_get_register (this_trad_cache, this_frame, regnum); 2087} 2088 2089/* Implement the sniffer function for the stub unwinder. 2090 This unwinder is used for cases where the normal 2091 prologue-analysis-based unwinder can't work, 2092 such as PLT stubs. */ 2093 2094static int 2095nios2_stub_frame_sniffer (const struct frame_unwind *self, 2096 struct frame_info *this_frame, void **cache) 2097{ 2098 gdb_byte dummy[4]; 2099 CORE_ADDR pc = get_frame_address_in_block (this_frame); 2100 2101 /* Use the stub unwinder for unreadable code. */ 2102 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) 2103 return 1; 2104 2105 if (in_plt_section (pc)) 2106 return 1; 2107 2108 return 0; 2109} 2110 2111/* Define the data structures for the stub unwinder. */ 2112 2113static const struct frame_unwind nios2_stub_frame_unwind = 2114{ 2115 NORMAL_FRAME, 2116 default_frame_unwind_stop_reason, 2117 nios2_stub_frame_this_id, 2118 nios2_stub_frame_prev_register, 2119 NULL, 2120 nios2_stub_frame_sniffer 2121}; 2122 2123 2124 2125/* Determine where to set a single step breakpoint while considering 2126 branch prediction. */ 2127 2128static CORE_ADDR 2129nios2_get_next_pc (struct regcache *regcache, CORE_ADDR pc) 2130{ 2131 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2132 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2133 unsigned long mach = gdbarch_bfd_arch_info (gdbarch)->mach; 2134 unsigned int insn; 2135 const struct nios2_opcode *op = nios2_fetch_insn (gdbarch, pc, &insn); 2136 int ra; 2137 int rb; 2138 int imm; 2139 unsigned int uimm; 2140 int wb, id, ret; 2141 enum branch_condition cond; 2142 2143 /* Do something stupid if we can't disassemble the insn at pc. */ 2144 if (op == NULL) 2145 return pc + NIOS2_OPCODE_SIZE; 2146 2147 if (nios2_match_branch (insn, op, mach, &ra, &rb, &imm, &cond)) 2148 { 2149 int ras = regcache_raw_get_signed (regcache, ra); 2150 int rbs = regcache_raw_get_signed (regcache, rb); 2151 unsigned int rau = regcache_raw_get_unsigned (regcache, ra); 2152 unsigned int rbu = regcache_raw_get_unsigned (regcache, rb); 2153 2154 pc += op->size; 2155 switch (cond) 2156 { 2157 case branch_none: 2158 pc += imm; 2159 break; 2160 case branch_eq: 2161 if (ras == rbs) 2162 pc += imm; 2163 break; 2164 case branch_ne: 2165 if (ras != rbs) 2166 pc += imm; 2167 break; 2168 case branch_ge: 2169 if (ras >= rbs) 2170 pc += imm; 2171 break; 2172 case branch_geu: 2173 if (rau >= rbu) 2174 pc += imm; 2175 break; 2176 case branch_lt: 2177 if (ras < rbs) 2178 pc += imm; 2179 break; 2180 case branch_ltu: 2181 if (rau < rbu) 2182 pc += imm; 2183 break; 2184 default: 2185 break; 2186 } 2187 } 2188 2189 else if (nios2_match_jmpi (insn, op, mach, &uimm) 2190 || nios2_match_calli (insn, op, mach, &uimm)) 2191 pc = (pc & 0xf0000000) | uimm; 2192 2193 else if (nios2_match_jmpr (insn, op, mach, &ra) 2194 || nios2_match_callr (insn, op, mach, &ra)) 2195 pc = regcache_raw_get_unsigned (regcache, ra); 2196 2197 else if (nios2_match_ldwm (insn, op, mach, &uimm, &ra, &imm, &wb, &id, &ret) 2198 && ret) 2199 { 2200 /* If ra is in the reglist, we have to use the value saved in the 2201 stack frame rather than the current value. */ 2202 if (uimm & (1 << NIOS2_RA_REGNUM)) 2203 pc = nios2_unwind_pc (gdbarch, get_current_frame ()); 2204 else 2205 pc = regcache_raw_get_unsigned (regcache, NIOS2_RA_REGNUM); 2206 } 2207 2208 else if (nios2_match_trap (insn, op, mach, &uimm) && uimm == 0) 2209 { 2210 if (tdep->syscall_next_pc != NULL) 2211 return tdep->syscall_next_pc (get_current_frame (), op); 2212 } 2213 2214 else 2215 pc += op->size; 2216 2217 return pc; 2218} 2219 2220/* Implement the software_single_step gdbarch method. */ 2221 2222static VEC (CORE_ADDR) * 2223nios2_software_single_step (struct regcache *regcache) 2224{ 2225 struct gdbarch *gdbarch = get_regcache_arch (regcache); 2226 CORE_ADDR next_pc = nios2_get_next_pc (regcache, regcache_read_pc (regcache)); 2227 VEC (CORE_ADDR) *next_pcs = NULL; 2228 2229 VEC_safe_push (CORE_ADDR, next_pcs, next_pc); 2230 2231 return next_pcs; 2232} 2233 2234/* Implement the get_longjump_target gdbarch method. */ 2235 2236static int 2237nios2_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) 2238{ 2239 struct gdbarch *gdbarch = get_frame_arch (frame); 2240 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2241 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2242 CORE_ADDR jb_addr = get_frame_register_unsigned (frame, NIOS2_R4_REGNUM); 2243 gdb_byte buf[4]; 2244 2245 if (target_read_memory (jb_addr + (tdep->jb_pc * 4), buf, 4)) 2246 return 0; 2247 2248 *pc = extract_unsigned_integer (buf, 4, byte_order); 2249 return 1; 2250} 2251 2252/* Initialize the Nios II gdbarch. */ 2253 2254static struct gdbarch * 2255nios2_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2256{ 2257 struct gdbarch *gdbarch; 2258 struct gdbarch_tdep *tdep; 2259 int i; 2260 struct tdesc_arch_data *tdesc_data = NULL; 2261 const struct target_desc *tdesc = info.target_desc; 2262 2263 if (!tdesc_has_registers (tdesc)) 2264 /* Pick a default target description. */ 2265 tdesc = tdesc_nios2; 2266 2267 /* Check any target description for validity. */ 2268 if (tdesc_has_registers (tdesc)) 2269 { 2270 const struct tdesc_feature *feature; 2271 int valid_p; 2272 2273 feature = tdesc_find_feature (tdesc, "org.gnu.gdb.nios2.cpu"); 2274 if (feature == NULL) 2275 return NULL; 2276 2277 tdesc_data = tdesc_data_alloc (); 2278 2279 valid_p = 1; 2280 2281 for (i = 0; i < NIOS2_NUM_REGS; i++) 2282 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, 2283 nios2_reg_names[i]); 2284 2285 if (!valid_p) 2286 { 2287 tdesc_data_cleanup (tdesc_data); 2288 return NULL; 2289 } 2290 } 2291 2292 /* Find a candidate among the list of pre-declared architectures. */ 2293 arches = gdbarch_list_lookup_by_info (arches, &info); 2294 if (arches != NULL) 2295 return arches->gdbarch; 2296 2297 /* None found, create a new architecture from the information 2298 provided. */ 2299 tdep = XCNEW (struct gdbarch_tdep); 2300 gdbarch = gdbarch_alloc (&info, tdep); 2301 2302 /* longjmp support not enabled by default. */ 2303 tdep->jb_pc = -1; 2304 2305 /* Data type sizes. */ 2306 set_gdbarch_ptr_bit (gdbarch, 32); 2307 set_gdbarch_addr_bit (gdbarch, 32); 2308 set_gdbarch_short_bit (gdbarch, 16); 2309 set_gdbarch_int_bit (gdbarch, 32); 2310 set_gdbarch_long_bit (gdbarch, 32); 2311 set_gdbarch_long_long_bit (gdbarch, 64); 2312 set_gdbarch_float_bit (gdbarch, 32); 2313 set_gdbarch_double_bit (gdbarch, 64); 2314 2315 set_gdbarch_float_format (gdbarch, floatformats_ieee_single); 2316 set_gdbarch_double_format (gdbarch, floatformats_ieee_double); 2317 2318 /* The register set. */ 2319 set_gdbarch_num_regs (gdbarch, NIOS2_NUM_REGS); 2320 set_gdbarch_sp_regnum (gdbarch, NIOS2_SP_REGNUM); 2321 set_gdbarch_pc_regnum (gdbarch, NIOS2_PC_REGNUM); /* Pseudo register PC */ 2322 2323 set_gdbarch_register_name (gdbarch, nios2_register_name); 2324 set_gdbarch_register_type (gdbarch, nios2_register_type); 2325 2326 /* Provide register mappings for stabs and dwarf2. */ 2327 set_gdbarch_stab_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); 2328 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, nios2_dwarf_reg_to_regnum); 2329 2330 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2331 2332 /* Call dummy code. */ 2333 set_gdbarch_frame_align (gdbarch, nios2_frame_align); 2334 2335 set_gdbarch_return_value (gdbarch, nios2_return_value); 2336 2337 set_gdbarch_skip_prologue (gdbarch, nios2_skip_prologue); 2338 set_gdbarch_stack_frame_destroyed_p (gdbarch, nios2_stack_frame_destroyed_p); 2339 set_gdbarch_breakpoint_kind_from_pc (gdbarch, nios2_breakpoint_kind_from_pc); 2340 set_gdbarch_sw_breakpoint_from_kind (gdbarch, nios2_sw_breakpoint_from_kind); 2341 2342 set_gdbarch_dummy_id (gdbarch, nios2_dummy_id); 2343 set_gdbarch_unwind_pc (gdbarch, nios2_unwind_pc); 2344 set_gdbarch_unwind_sp (gdbarch, nios2_unwind_sp); 2345 2346 /* The dwarf2 unwinder will normally produce the best results if 2347 the debug information is available, so register it first. */ 2348 dwarf2_append_unwinders (gdbarch); 2349 frame_unwind_append_unwinder (gdbarch, &nios2_stub_frame_unwind); 2350 frame_unwind_append_unwinder (gdbarch, &nios2_frame_unwind); 2351 2352 /* Single stepping. */ 2353 set_gdbarch_software_single_step (gdbarch, nios2_software_single_step); 2354 2355 /* Hook in ABI-specific overrides, if they have been registered. */ 2356 gdbarch_init_osabi (info, gdbarch); 2357 2358 if (tdep->jb_pc >= 0) 2359 set_gdbarch_get_longjmp_target (gdbarch, nios2_get_longjmp_target); 2360 2361 frame_base_set_default (gdbarch, &nios2_frame_base); 2362 2363 set_gdbarch_print_insn (gdbarch, nios2_print_insn); 2364 2365 /* Enable inferior call support. */ 2366 set_gdbarch_push_dummy_call (gdbarch, nios2_push_dummy_call); 2367 2368 if (tdesc_data) 2369 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 2370 2371 return gdbarch; 2372} 2373 2374extern initialize_file_ftype _initialize_nios2_tdep; /* -Wmissing-prototypes */ 2375 2376void 2377_initialize_nios2_tdep (void) 2378{ 2379 gdbarch_register (bfd_arch_nios2, nios2_gdbarch_init, NULL); 2380 initialize_tdesc_nios2 (); 2381 2382 /* Allow debugging this file's internals. */ 2383 add_setshow_boolean_cmd ("nios2", class_maintenance, &nios2_debug, 2384 _("Set Nios II debugging."), 2385 _("Show Nios II debugging."), 2386 _("When on, Nios II specific debugging is enabled."), 2387 NULL, 2388 NULL, 2389 &setdebuglist, &showdebuglist); 2390} 2391