x86-dregs.c revision 1.1
1/* Debug register code for x86 (i386 and x86-64). 2 3 Copyright (C) 2001-2015 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20#include "common-defs.h" 21#include "x86-dregs.h" 22#include "break-common.h" 23 24/* Support for hardware watchpoints and breakpoints using the x86 25 debug registers. 26 27 This provides several functions for inserting and removing 28 hardware-assisted breakpoints and watchpoints, testing if one or 29 more of the watchpoints triggered and at what address, checking 30 whether a given region can be watched, etc. 31 32 The functions below implement debug registers sharing by reference 33 counts, and allow to watch regions up to 16 bytes long. */ 34 35/* Accessor macros for low-level function vector. */ 36 37/* Can we update the inferior's debug registers? */ 38#define x86_dr_low_can_set_addr() (x86_dr_low.set_addr != NULL) 39 40/* Update the inferior's debug register REGNUM from STATE. */ 41#define x86_dr_low_set_addr(new_state, i) \ 42 (x86_dr_low.set_addr ((i), (new_state)->dr_mirror[(i)])) 43 44/* Return the inferior's debug register REGNUM. */ 45#define x86_dr_low_get_addr(i) (x86_dr_low.get_addr ((i))) 46 47/* Can we update the inferior's DR7 control register? */ 48#define x86_dr_low_can_set_control() (x86_dr_low.set_control != NULL) 49 50/* Update the inferior's DR7 debug control register from STATE. */ 51#define x86_dr_low_set_control(new_state) \ 52 (x86_dr_low.set_control ((new_state)->dr_control_mirror)) 53 54/* Return the value of the inferior's DR7 debug control register. */ 55#define x86_dr_low_get_control() (x86_dr_low.get_control ()) 56 57/* Return the value of the inferior's DR6 debug status register. */ 58#define x86_dr_low_get_status() (x86_dr_low.get_status ()) 59 60/* Return the debug register size, in bytes. */ 61#define x86_get_debug_register_length() \ 62 (x86_dr_low.debug_register_length) 63 64/* Support for 8-byte wide hw watchpoints. */ 65#define TARGET_HAS_DR_LEN_8 (x86_get_debug_register_length () == 8) 66 67/* DR7 Debug Control register fields. */ 68 69/* How many bits to skip in DR7 to get to R/W and LEN fields. */ 70#define DR_CONTROL_SHIFT 16 71/* How many bits in DR7 per R/W and LEN field for each watchpoint. */ 72#define DR_CONTROL_SIZE 4 73 74/* Watchpoint/breakpoint read/write fields in DR7. */ 75#define DR_RW_EXECUTE (0x0) /* Break on instruction execution. */ 76#define DR_RW_WRITE (0x1) /* Break on data writes. */ 77#define DR_RW_READ (0x3) /* Break on data reads or writes. */ 78 79/* This is here for completeness. No platform supports this 80 functionality yet (as of March 2001). Note that the DE flag in the 81 CR4 register needs to be set to support this. */ 82#ifndef DR_RW_IORW 83#define DR_RW_IORW (0x2) /* Break on I/O reads or writes. */ 84#endif 85 86/* Watchpoint/breakpoint length fields in DR7. The 2-bit left shift 87 is so we could OR this with the read/write field defined above. */ 88#define DR_LEN_1 (0x0 << 2) /* 1-byte region watch or breakpoint. */ 89#define DR_LEN_2 (0x1 << 2) /* 2-byte region watch. */ 90#define DR_LEN_4 (0x3 << 2) /* 4-byte region watch. */ 91#define DR_LEN_8 (0x2 << 2) /* 8-byte region watch (AMD64). */ 92 93/* Local and Global Enable flags in DR7. 94 95 When the Local Enable flag is set, the breakpoint/watchpoint is 96 enabled only for the current task; the processor automatically 97 clears this flag on every task switch. When the Global Enable flag 98 is set, the breakpoint/watchpoint is enabled for all tasks; the 99 processor never clears this flag. 100 101 Currently, all watchpoint are locally enabled. If you need to 102 enable them globally, read the comment which pertains to this in 103 x86_insert_aligned_watchpoint below. */ 104#define DR_LOCAL_ENABLE_SHIFT 0 /* Extra shift to the local enable bit. */ 105#define DR_GLOBAL_ENABLE_SHIFT 1 /* Extra shift to the global enable bit. */ 106#define DR_ENABLE_SIZE 2 /* Two enable bits per debug register. */ 107 108/* Local and global exact breakpoint enable flags (a.k.a. slowdown 109 flags). These are only required on i386, to allow detection of the 110 exact instruction which caused a watchpoint to break; i486 and 111 later processors do that automatically. We set these flags for 112 backwards compatibility. */ 113#define DR_LOCAL_SLOWDOWN (0x100) 114#define DR_GLOBAL_SLOWDOWN (0x200) 115 116/* Fields reserved by Intel. This includes the GD (General Detect 117 Enable) flag, which causes a debug exception to be generated when a 118 MOV instruction accesses one of the debug registers. 119 120 FIXME: My Intel manual says we should use 0xF800, not 0xFC00. */ 121#define DR_CONTROL_RESERVED (0xFC00) 122 123/* Auxiliary helper macros. */ 124 125/* A value that masks all fields in DR7 that are reserved by Intel. */ 126#define X86_DR_CONTROL_MASK (~DR_CONTROL_RESERVED) 127 128/* The I'th debug register is vacant if its Local and Global Enable 129 bits are reset in the Debug Control register. */ 130#define X86_DR_VACANT(state, i) \ 131 (((state)->dr_control_mirror & (3 << (DR_ENABLE_SIZE * (i)))) == 0) 132 133/* Locally enable the break/watchpoint in the I'th debug register. */ 134#define X86_DR_LOCAL_ENABLE(state, i) \ 135 do { \ 136 (state)->dr_control_mirror |= \ 137 (1 << (DR_LOCAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ 138 } while (0) 139 140/* Globally enable the break/watchpoint in the I'th debug register. */ 141#define X86_DR_GLOBAL_ENABLE(state, i) \ 142 do { \ 143 (state)->dr_control_mirror |= \ 144 (1 << (DR_GLOBAL_ENABLE_SHIFT + DR_ENABLE_SIZE * (i))); \ 145 } while (0) 146 147/* Disable the break/watchpoint in the I'th debug register. */ 148#define X86_DR_DISABLE(state, i) \ 149 do { \ 150 (state)->dr_control_mirror &= \ 151 ~(3 << (DR_ENABLE_SIZE * (i))); \ 152 } while (0) 153 154/* Set in DR7 the RW and LEN fields for the I'th debug register. */ 155#define X86_DR_SET_RW_LEN(state, i, rwlen) \ 156 do { \ 157 (state)->dr_control_mirror &= \ 158 ~(0x0f << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ 159 (state)->dr_control_mirror |= \ 160 ((rwlen) << (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))); \ 161 } while (0) 162 163/* Get from DR7 the RW and LEN fields for the I'th debug register. */ 164#define X86_DR_GET_RW_LEN(dr7, i) \ 165 (((dr7) \ 166 >> (DR_CONTROL_SHIFT + DR_CONTROL_SIZE * (i))) & 0x0f) 167 168/* Did the watchpoint whose address is in the I'th register break? */ 169#define X86_DR_WATCH_HIT(dr6, i) ((dr6) & (1 << (i))) 170 171/* Types of operations supported by x86_handle_nonaligned_watchpoint. */ 172typedef enum { WP_INSERT, WP_REMOVE, WP_COUNT } x86_wp_op_t; 173 174/* Print the values of the mirrored debug registers. */ 175 176static void 177x86_show_dr (struct x86_debug_reg_state *state, 178 const char *func, CORE_ADDR addr, 179 int len, enum target_hw_bp_type type) 180{ 181 int i; 182 183 debug_printf ("%s", func); 184 if (addr || len) 185 debug_printf (" (addr=%s, len=%d, type=%s)", 186 phex (addr, 8), len, 187 type == hw_write ? "data-write" 188 : (type == hw_read ? "data-read" 189 : (type == hw_access ? "data-read/write" 190 : (type == hw_execute ? "instruction-execute" 191 /* FIXME: if/when I/O read/write 192 watchpoints are supported, add them 193 here. */ 194 : "??unknown??")))); 195 debug_printf (":\n"); 196 debug_printf ("\tCONTROL (DR7): %s STATUS (DR6): %s\n", 197 phex (state->dr_control_mirror, 8), 198 phex (state->dr_status_mirror, 8)); 199 ALL_DEBUG_ADDRESS_REGISTERS (i) 200 { 201 debug_printf ("\ 202\tDR%d: addr=0x%s, ref.count=%d DR%d: addr=0x%s, ref.count=%d\n", 203 i, phex (state->dr_mirror[i], 204 x86_get_debug_register_length ()), 205 state->dr_ref_count[i], 206 i + 1, phex (state->dr_mirror[i + 1], 207 x86_get_debug_register_length ()), 208 state->dr_ref_count[i + 1]); 209 i++; 210 } 211} 212 213/* Return the value of a 4-bit field for DR7 suitable for watching a 214 region of LEN bytes for accesses of type TYPE. LEN is assumed to 215 have the value of 1, 2, or 4. */ 216 217static unsigned 218x86_length_and_rw_bits (int len, enum target_hw_bp_type type) 219{ 220 unsigned rw; 221 222 switch (type) 223 { 224 case hw_execute: 225 rw = DR_RW_EXECUTE; 226 break; 227 case hw_write: 228 rw = DR_RW_WRITE; 229 break; 230 case hw_read: 231 internal_error (__FILE__, __LINE__, 232 _("The i386 doesn't support " 233 "data-read watchpoints.\n")); 234 case hw_access: 235 rw = DR_RW_READ; 236 break; 237#if 0 238 /* Not yet supported. */ 239 case hw_io_access: 240 rw = DR_RW_IORW; 241 break; 242#endif 243 default: 244 internal_error (__FILE__, __LINE__, _("\ 245Invalid hardware breakpoint type %d in x86_length_and_rw_bits.\n"), 246 (int) type); 247 } 248 249 switch (len) 250 { 251 case 1: 252 return (DR_LEN_1 | rw); 253 case 2: 254 return (DR_LEN_2 | rw); 255 case 4: 256 return (DR_LEN_4 | rw); 257 case 8: 258 if (TARGET_HAS_DR_LEN_8) 259 return (DR_LEN_8 | rw); 260 /* ELSE FALL THROUGH */ 261 default: 262 internal_error (__FILE__, __LINE__, _("\ 263Invalid hardware breakpoint length %d in x86_length_and_rw_bits.\n"), len); 264 } 265} 266 267/* Insert a watchpoint at address ADDR, which is assumed to be aligned 268 according to the length of the region to watch. LEN_RW_BITS is the 269 value of the bits from DR7 which describes the length and access 270 type of the region to be watched by this watchpoint. Return 0 on 271 success, -1 on failure. */ 272 273static int 274x86_insert_aligned_watchpoint (struct x86_debug_reg_state *state, 275 CORE_ADDR addr, unsigned len_rw_bits) 276{ 277 int i; 278 279 if (!x86_dr_low_can_set_addr () || !x86_dr_low_can_set_control ()) 280 return -1; 281 282 /* First, look for an occupied debug register with the same address 283 and the same RW and LEN definitions. If we find one, we can 284 reuse it for this watchpoint as well (and save a register). */ 285 ALL_DEBUG_ADDRESS_REGISTERS (i) 286 { 287 if (!X86_DR_VACANT (state, i) 288 && state->dr_mirror[i] == addr 289 && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) 290 { 291 state->dr_ref_count[i]++; 292 return 0; 293 } 294 } 295 296 /* Next, look for a vacant debug register. */ 297 ALL_DEBUG_ADDRESS_REGISTERS (i) 298 { 299 if (X86_DR_VACANT (state, i)) 300 break; 301 } 302 303 /* No more debug registers! */ 304 if (i >= DR_NADDR) 305 return -1; 306 307 /* Now set up the register I to watch our region. */ 308 309 /* Record the info in our local mirrored array. */ 310 state->dr_mirror[i] = addr; 311 state->dr_ref_count[i] = 1; 312 X86_DR_SET_RW_LEN (state, i, len_rw_bits); 313 /* Note: we only enable the watchpoint locally, i.e. in the current 314 task. Currently, no x86 target allows or supports global 315 watchpoints; however, if any target would want that in the 316 future, GDB should probably provide a command to control whether 317 to enable watchpoints globally or locally, and the code below 318 should use global or local enable and slow-down flags as 319 appropriate. */ 320 X86_DR_LOCAL_ENABLE (state, i); 321 state->dr_control_mirror |= DR_LOCAL_SLOWDOWN; 322 state->dr_control_mirror &= X86_DR_CONTROL_MASK; 323 324 return 0; 325} 326 327/* Remove a watchpoint at address ADDR, which is assumed to be aligned 328 according to the length of the region to watch. LEN_RW_BITS is the 329 value of the bits from DR7 which describes the length and access 330 type of the region watched by this watchpoint. Return 0 on 331 success, -1 on failure. */ 332 333static int 334x86_remove_aligned_watchpoint (struct x86_debug_reg_state *state, 335 CORE_ADDR addr, unsigned len_rw_bits) 336{ 337 int i, retval = -1; 338 int all_vacant = 1; 339 340 ALL_DEBUG_ADDRESS_REGISTERS (i) 341 { 342 if (!X86_DR_VACANT (state, i) 343 && state->dr_mirror[i] == addr 344 && X86_DR_GET_RW_LEN (state->dr_control_mirror, i) == len_rw_bits) 345 { 346 if (--state->dr_ref_count[i] == 0) /* No longer in use? */ 347 { 348 /* Reset our mirror. */ 349 state->dr_mirror[i] = 0; 350 X86_DR_DISABLE (state, i); 351 /* Even though not strictly necessary, clear out all 352 bits in DR_CONTROL related to this debug register. 353 Debug output is clearer when we don't have stale bits 354 in place. This also allows the assertion below. */ 355 X86_DR_SET_RW_LEN (state, i, 0); 356 } 357 retval = 0; 358 } 359 360 if (!X86_DR_VACANT (state, i)) 361 all_vacant = 0; 362 } 363 364 if (all_vacant) 365 { 366 /* Even though not strictly necessary, clear out all of 367 DR_CONTROL, so that when we have no debug registers in use, 368 we end up with DR_CONTROL == 0. The Linux support relies on 369 this for an optimization. Plus, it makes for clearer debug 370 output. */ 371 state->dr_control_mirror &= ~DR_LOCAL_SLOWDOWN; 372 373 gdb_assert (state->dr_control_mirror == 0); 374 } 375 return retval; 376} 377 378/* Insert or remove a (possibly non-aligned) watchpoint, or count the 379 number of debug registers required to watch a region at address 380 ADDR whose length is LEN for accesses of type TYPE. Return 0 on 381 successful insertion or removal, a positive number when queried 382 about the number of registers, or -1 on failure. If WHAT is not a 383 valid value, bombs through internal_error. */ 384 385static int 386x86_handle_nonaligned_watchpoint (struct x86_debug_reg_state *state, 387 x86_wp_op_t what, CORE_ADDR addr, int len, 388 enum target_hw_bp_type type) 389{ 390 int retval = 0; 391 int max_wp_len = TARGET_HAS_DR_LEN_8 ? 8 : 4; 392 393 static const int size_try_array[8][8] = 394 { 395 {1, 1, 1, 1, 1, 1, 1, 1}, /* Trying size one. */ 396 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size two. */ 397 {2, 1, 2, 1, 2, 1, 2, 1}, /* Trying size three. */ 398 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size four. */ 399 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size five. */ 400 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size six. */ 401 {4, 1, 2, 1, 4, 1, 2, 1}, /* Trying size seven. */ 402 {8, 1, 2, 1, 4, 1, 2, 1}, /* Trying size eight. */ 403 }; 404 405 while (len > 0) 406 { 407 int align = addr % max_wp_len; 408 /* Four (eight on AMD64) is the maximum length a debug register 409 can watch. */ 410 int try = (len > max_wp_len ? (max_wp_len - 1) : len - 1); 411 int size = size_try_array[try][align]; 412 413 if (what == WP_COUNT) 414 { 415 /* size_try_array[] is defined such that each iteration 416 through the loop is guaranteed to produce an address and a 417 size that can be watched with a single debug register. 418 Thus, for counting the registers required to watch a 419 region, we simply need to increment the count on each 420 iteration. */ 421 retval++; 422 } 423 else 424 { 425 unsigned len_rw = x86_length_and_rw_bits (size, type); 426 427 if (what == WP_INSERT) 428 retval = x86_insert_aligned_watchpoint (state, addr, len_rw); 429 else if (what == WP_REMOVE) 430 retval = x86_remove_aligned_watchpoint (state, addr, len_rw); 431 else 432 internal_error (__FILE__, __LINE__, _("\ 433Invalid value %d of operation in x86_handle_nonaligned_watchpoint.\n"), 434 (int) what); 435 if (retval) 436 break; 437 } 438 439 addr += size; 440 len -= size; 441 } 442 443 return retval; 444} 445 446/* Update the inferior debug registers state, in STATE, with the 447 new debug registers state, in NEW_STATE. */ 448 449static void 450x86_update_inferior_debug_regs (struct x86_debug_reg_state *state, 451 struct x86_debug_reg_state *new_state) 452{ 453 int i; 454 455 ALL_DEBUG_ADDRESS_REGISTERS (i) 456 { 457 if (X86_DR_VACANT (new_state, i) != X86_DR_VACANT (state, i)) 458 x86_dr_low_set_addr (new_state, i); 459 else 460 gdb_assert (new_state->dr_mirror[i] == state->dr_mirror[i]); 461 } 462 463 if (new_state->dr_control_mirror != state->dr_control_mirror) 464 x86_dr_low_set_control (new_state); 465 466 *state = *new_state; 467} 468 469/* Insert a watchpoint to watch a memory region which starts at 470 address ADDR and whose length is LEN bytes. Watch memory accesses 471 of the type TYPE. Return 0 on success, -1 on failure. */ 472 473int 474x86_dr_insert_watchpoint (struct x86_debug_reg_state *state, 475 enum target_hw_bp_type type, 476 CORE_ADDR addr, int len) 477{ 478 int retval; 479 /* Work on a local copy of the debug registers, and on success, 480 commit the change back to the inferior. */ 481 struct x86_debug_reg_state local_state = *state; 482 483 if (type == hw_read) 484 return 1; /* unsupported */ 485 486 if (((len != 1 && len != 2 && len != 4) 487 && !(TARGET_HAS_DR_LEN_8 && len == 8)) 488 || addr % len != 0) 489 { 490 retval = x86_handle_nonaligned_watchpoint (&local_state, 491 WP_INSERT, 492 addr, len, type); 493 } 494 else 495 { 496 unsigned len_rw = x86_length_and_rw_bits (len, type); 497 498 retval = x86_insert_aligned_watchpoint (&local_state, 499 addr, len_rw); 500 } 501 502 if (retval == 0) 503 x86_update_inferior_debug_regs (state, &local_state); 504 505 if (show_debug_regs) 506 x86_show_dr (state, "insert_watchpoint", addr, len, type); 507 508 return retval; 509} 510 511/* Remove a watchpoint that watched the memory region which starts at 512 address ADDR, whose length is LEN bytes, and for accesses of the 513 type TYPE. Return 0 on success, -1 on failure. */ 514 515int 516x86_dr_remove_watchpoint (struct x86_debug_reg_state *state, 517 enum target_hw_bp_type type, 518 CORE_ADDR addr, int len) 519{ 520 int retval; 521 /* Work on a local copy of the debug registers, and on success, 522 commit the change back to the inferior. */ 523 struct x86_debug_reg_state local_state = *state; 524 525 if (((len != 1 && len != 2 && len != 4) 526 && !(TARGET_HAS_DR_LEN_8 && len == 8)) 527 || addr % len != 0) 528 { 529 retval = x86_handle_nonaligned_watchpoint (&local_state, 530 WP_REMOVE, 531 addr, len, type); 532 } 533 else 534 { 535 unsigned len_rw = x86_length_and_rw_bits (len, type); 536 537 retval = x86_remove_aligned_watchpoint (&local_state, 538 addr, len_rw); 539 } 540 541 if (retval == 0) 542 x86_update_inferior_debug_regs (state, &local_state); 543 544 if (show_debug_regs) 545 x86_show_dr (state, "remove_watchpoint", addr, len, type); 546 547 return retval; 548} 549 550/* Return non-zero if we can watch a memory region that starts at 551 address ADDR and whose length is LEN bytes. */ 552 553int 554x86_dr_region_ok_for_watchpoint (struct x86_debug_reg_state *state, 555 CORE_ADDR addr, int len) 556{ 557 int nregs; 558 559 /* Compute how many aligned watchpoints we would need to cover this 560 region. */ 561 nregs = x86_handle_nonaligned_watchpoint (state, WP_COUNT, 562 addr, len, hw_write); 563 return nregs <= DR_NADDR ? 1 : 0; 564} 565 566/* If the inferior has some break/watchpoint that triggered, set the 567 address associated with that break/watchpoint and return non-zero. 568 Otherwise, return zero. */ 569 570int 571x86_dr_stopped_data_address (struct x86_debug_reg_state *state, 572 CORE_ADDR *addr_p) 573{ 574 CORE_ADDR addr = 0; 575 int i; 576 int rc = 0; 577 /* The current thread's DR_STATUS. We always need to read this to 578 check whether some watchpoint caused the trap. */ 579 unsigned status; 580 /* We need DR_CONTROL as well, but only iff DR_STATUS indicates a 581 data breakpoint trap. Only fetch it when necessary, to avoid an 582 unnecessary extra syscall when no watchpoint triggered. */ 583 int control_p = 0; 584 unsigned control = 0; 585 586 /* In non-stop/async, threads can be running while we change the 587 global dr_mirror (and friends). Say, we set a watchpoint, and 588 let threads resume. Now, say you delete the watchpoint, or 589 add/remove watchpoints such that dr_mirror changes while threads 590 are running. On targets that support non-stop, 591 inserting/deleting watchpoints updates the global dr_mirror only. 592 It does not update the real thread's debug registers; that's only 593 done prior to resume. Instead, if threads are running when the 594 mirror changes, a temporary and transparent stop on all threads 595 is forced so they can get their copy of the debug registers 596 updated on re-resume. Now, say, a thread hit a watchpoint before 597 having been updated with the new dr_mirror contents, and we 598 haven't yet handled the corresponding SIGTRAP. If we trusted 599 dr_mirror below, we'd mistake the real trapped address (from the 600 last time we had updated debug registers in the thread) with 601 whatever was currently in dr_mirror. So to fix this, dr_mirror 602 always represents intention, what we _want_ threads to have in 603 debug registers. To get at the address and cause of the trap, we 604 need to read the state the thread still has in its debug 605 registers. 606 607 In sum, always get the current debug register values the current 608 thread has, instead of trusting the global mirror. If the thread 609 was running when we last changed watchpoints, the mirror no 610 longer represents what was set in this thread's debug 611 registers. */ 612 status = x86_dr_low_get_status (); 613 614 ALL_DEBUG_ADDRESS_REGISTERS (i) 615 { 616 if (!X86_DR_WATCH_HIT (status, i)) 617 continue; 618 619 if (!control_p) 620 { 621 control = x86_dr_low_get_control (); 622 control_p = 1; 623 } 624 625 /* This second condition makes sure DRi is set up for a data 626 watchpoint, not a hardware breakpoint. The reason is that 627 GDB doesn't call the target_stopped_data_address method 628 except for data watchpoints. In other words, I'm being 629 paranoiac. */ 630 if (X86_DR_GET_RW_LEN (control, i) != 0) 631 { 632 addr = x86_dr_low_get_addr (i); 633 rc = 1; 634 if (show_debug_regs) 635 x86_show_dr (state, "watchpoint_hit", addr, -1, hw_write); 636 } 637 } 638 639 if (show_debug_regs && addr == 0) 640 x86_show_dr (state, "stopped_data_addr", 0, 0, hw_write); 641 642 if (rc) 643 *addr_p = addr; 644 return rc; 645} 646 647/* Return non-zero if the inferior has some watchpoint that triggered. 648 Otherwise return zero. */ 649 650int 651x86_dr_stopped_by_watchpoint (struct x86_debug_reg_state *state) 652{ 653 CORE_ADDR addr = 0; 654 return x86_dr_stopped_data_address (state, &addr); 655} 656