tc-ia64.c revision 1.1.1.1
1/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. 2 Copyright (C) 1998-2020 Free Software Foundation, Inc. 3 Contributed by David Mosberger-Tang <davidm@hpl.hp.com> 4 5 This file is part of GAS, the GNU Assembler. 6 7 GAS is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GAS is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to 19 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 20 Boston, MA 02110-1301, USA. */ 21 22/* 23 TODO: 24 25 - optional operands 26 - directives: 27 .eb 28 .estate 29 .lb 30 .popsection 31 .previous 32 .psr 33 .pushsection 34 - labels are wrong if automatic alignment is introduced 35 (e.g., checkout the second real10 definition in test-data.s) 36 - DV-related stuff: 37 <reg>.safe_across_calls and any other DV-related directives I don't 38 have documentation for. 39 verify mod-sched-brs reads/writes are checked/marked (and other 40 notes) 41 42 */ 43 44#include "as.h" 45#include "safe-ctype.h" 46#include "dwarf2dbg.h" 47#include "subsegs.h" 48 49#include "opcode/ia64.h" 50 51#include "elf/ia64.h" 52#include "bfdver.h" 53#include <time.h> 54 55#ifdef HAVE_LIMITS_H 56#include <limits.h> 57#endif 58 59#define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) 60 61/* Some systems define MIN in, e.g., param.h. */ 62#undef MIN 63#define MIN(a,b) ((a) < (b) ? (a) : (b)) 64 65#define NUM_SLOTS 4 66#define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] 67#define CURR_SLOT md.slot[md.curr_slot] 68 69#define O_pseudo_fixup (O_max + 1) 70 71enum special_section 72 { 73 /* IA-64 ABI section pseudo-ops. */ 74 SPECIAL_SECTION_BSS = 0, 75 SPECIAL_SECTION_SBSS, 76 SPECIAL_SECTION_SDATA, 77 SPECIAL_SECTION_RODATA, 78 SPECIAL_SECTION_COMMENT, 79 SPECIAL_SECTION_UNWIND, 80 SPECIAL_SECTION_UNWIND_INFO, 81 /* HPUX specific section pseudo-ops. */ 82 SPECIAL_SECTION_INIT_ARRAY, 83 SPECIAL_SECTION_FINI_ARRAY, 84 }; 85 86enum reloc_func 87 { 88 FUNC_DTP_MODULE, 89 FUNC_DTP_RELATIVE, 90 FUNC_FPTR_RELATIVE, 91 FUNC_GP_RELATIVE, 92 FUNC_LT_RELATIVE, 93 FUNC_LT_RELATIVE_X, 94 FUNC_PC_RELATIVE, 95 FUNC_PLT_RELATIVE, 96 FUNC_SEC_RELATIVE, 97 FUNC_SEG_RELATIVE, 98 FUNC_TP_RELATIVE, 99 FUNC_LTV_RELATIVE, 100 FUNC_LT_FPTR_RELATIVE, 101 FUNC_LT_DTP_MODULE, 102 FUNC_LT_DTP_RELATIVE, 103 FUNC_LT_TP_RELATIVE, 104 FUNC_IPLT_RELOC, 105#ifdef TE_VMS 106 FUNC_SLOTCOUNT_RELOC, 107#endif 108 }; 109 110enum reg_symbol 111 { 112 REG_GR = 0, 113 REG_FR = (REG_GR + 128), 114 REG_AR = (REG_FR + 128), 115 REG_CR = (REG_AR + 128), 116 REG_DAHR = (REG_CR + 128), 117 REG_P = (REG_DAHR + 8), 118 REG_BR = (REG_P + 64), 119 REG_IP = (REG_BR + 8), 120 REG_CFM, 121 REG_PR, 122 REG_PR_ROT, 123 REG_PSR, 124 REG_PSR_L, 125 REG_PSR_UM, 126 /* The following are pseudo-registers for use by gas only. */ 127 IND_CPUID, 128 IND_DBR, 129 IND_DTR, 130 IND_ITR, 131 IND_IBR, 132 IND_MSR, 133 IND_PKR, 134 IND_PMC, 135 IND_PMD, 136 IND_DAHR, 137 IND_RR, 138 /* The following pseudo-registers are used for unwind directives only: */ 139 REG_PSP, 140 REG_PRIUNAT, 141 REG_NUM 142 }; 143 144enum dynreg_type 145 { 146 DYNREG_GR = 0, /* dynamic general purpose register */ 147 DYNREG_FR, /* dynamic floating point register */ 148 DYNREG_PR, /* dynamic predicate register */ 149 DYNREG_NUM_TYPES 150 }; 151 152enum operand_match_result 153 { 154 OPERAND_MATCH, 155 OPERAND_OUT_OF_RANGE, 156 OPERAND_MISMATCH 157 }; 158 159/* On the ia64, we can't know the address of a text label until the 160 instructions are packed into a bundle. To handle this, we keep 161 track of the list of labels that appear in front of each 162 instruction. */ 163struct label_fix 164{ 165 struct label_fix *next; 166 struct symbol *sym; 167 bfd_boolean dw2_mark_labels; 168}; 169 170#ifdef TE_VMS 171/* An internally used relocation. */ 172#define DUMMY_RELOC_IA64_SLOTCOUNT (BFD_RELOC_UNUSED + 1) 173#endif 174 175/* This is the endianness of the current section. */ 176extern int target_big_endian; 177 178/* This is the default endianness. */ 179static int default_big_endian = TARGET_BYTES_BIG_ENDIAN; 180 181void (*ia64_number_to_chars) (char *, valueT, int); 182 183static void ia64_float_to_chars_bigendian (char *, LITTLENUM_TYPE *, int); 184static void ia64_float_to_chars_littleendian (char *, LITTLENUM_TYPE *, int); 185 186static void (*ia64_float_to_chars) (char *, LITTLENUM_TYPE *, int); 187 188static htab_t alias_hash; 189static htab_t alias_name_hash; 190static htab_t secalias_hash; 191static htab_t secalias_name_hash; 192 193/* List of chars besides those in app.c:symbol_chars that can start an 194 operand. Used to prevent the scrubber eating vital white-space. */ 195const char ia64_symbol_chars[] = "@?"; 196 197/* Characters which always start a comment. */ 198const char comment_chars[] = ""; 199 200/* Characters which start a comment at the beginning of a line. */ 201const char line_comment_chars[] = "#"; 202 203/* Characters which may be used to separate multiple commands on a 204 single line. */ 205const char line_separator_chars[] = ";{}"; 206 207/* Characters which are used to indicate an exponent in a floating 208 point number. */ 209const char EXP_CHARS[] = "eE"; 210 211/* Characters which mean that a number is a floating point constant, 212 as in 0d1.0. */ 213const char FLT_CHARS[] = "rRsSfFdDxXpP"; 214 215/* ia64-specific option processing: */ 216 217const char *md_shortopts = "m:N:x::"; 218 219struct option md_longopts[] = 220 { 221#define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) 222 {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, 223#define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) 224 {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} 225 }; 226 227size_t md_longopts_size = sizeof (md_longopts); 228 229static struct 230 { 231 htab_t pseudo_hash; /* pseudo opcode hash table */ 232 htab_t reg_hash; /* register name hash table */ 233 htab_t dynreg_hash; /* dynamic register hash table */ 234 htab_t const_hash; /* constant hash table */ 235 htab_t entry_hash; /* code entry hint hash table */ 236 237 /* If X_op is != O_absent, the register name for the instruction's 238 qualifying predicate. If NULL, p0 is assumed for instructions 239 that are predictable. */ 240 expressionS qp; 241 242 /* Optimize for which CPU. */ 243 enum 244 { 245 itanium1, 246 itanium2 247 } tune; 248 249 /* What to do when hint.b is used. */ 250 enum 251 { 252 hint_b_error, 253 hint_b_warning, 254 hint_b_ok 255 } hint_b; 256 257 unsigned int 258 manual_bundling : 1, 259 debug_dv: 1, 260 detect_dv: 1, 261 explicit_mode : 1, /* which mode we're in */ 262 default_explicit_mode : 1, /* which mode is the default */ 263 mode_explicitly_set : 1, /* was the current mode explicitly set? */ 264 auto_align : 1, 265 keep_pending_output : 1; 266 267 /* What to do when something is wrong with unwind directives. */ 268 enum 269 { 270 unwind_check_warning, 271 unwind_check_error 272 } unwind_check; 273 274 /* Each bundle consists of up to three instructions. We keep 275 track of four most recent instructions so we can correctly set 276 the end_of_insn_group for the last instruction in a bundle. */ 277 int curr_slot; 278 int num_slots_in_use; 279 struct slot 280 { 281 unsigned int 282 end_of_insn_group : 1, 283 manual_bundling_on : 1, 284 manual_bundling_off : 1, 285 loc_directive_seen : 1; 286 signed char user_template; /* user-selected template, if any */ 287 unsigned char qp_regno; /* qualifying predicate */ 288 /* This duplicates a good fraction of "struct fix" but we 289 can't use a "struct fix" instead since we can't call 290 fix_new_exp() until we know the address of the instruction. */ 291 int num_fixups; 292 struct insn_fix 293 { 294 bfd_reloc_code_real_type code; 295 enum ia64_opnd opnd; /* type of operand in need of fix */ 296 unsigned int is_pcrel : 1; /* is operand pc-relative? */ 297 expressionS expr; /* the value to be inserted */ 298 } 299 fixup[2]; /* at most two fixups per insn */ 300 struct ia64_opcode *idesc; 301 struct label_fix *label_fixups; 302 struct label_fix *tag_fixups; 303 struct unw_rec_list *unwind_record; /* Unwind directive. */ 304 expressionS opnd[6]; 305 const char *src_file; 306 unsigned int src_line; 307 struct dwarf2_line_info debug_line; 308 } 309 slot[NUM_SLOTS]; 310 311 segT last_text_seg; 312 313 struct dynreg 314 { 315 struct dynreg *next; /* next dynamic register */ 316 const char *name; 317 unsigned short base; /* the base register number */ 318 unsigned short num_regs; /* # of registers in this set */ 319 } 320 *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; 321 322 flagword flags; /* ELF-header flags */ 323 324 struct mem_offset { 325 unsigned hint:1; /* is this hint currently valid? */ 326 bfd_vma offset; /* mem.offset offset */ 327 bfd_vma base; /* mem.offset base */ 328 } mem_offset; 329 330 int path; /* number of alt. entry points seen */ 331 const char **entry_labels; /* labels of all alternate paths in 332 the current DV-checking block. */ 333 int maxpaths; /* size currently allocated for 334 entry_labels */ 335 336 int pointer_size; /* size in bytes of a pointer */ 337 int pointer_size_shift; /* shift size of a pointer for alignment */ 338 339 symbolS *indregsym[IND_RR - IND_CPUID + 1]; 340 } 341md; 342 343/* These are not const, because they are modified to MMI for non-itanium1 344 targets below. */ 345/* MFI bundle of nops. */ 346static unsigned char le_nop[16] = 347{ 348 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 349 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00 350}; 351/* MFI bundle of nops with stop-bit. */ 352static unsigned char le_nop_stop[16] = 353{ 354 0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 355 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00 356}; 357 358/* application registers: */ 359 360#define AR_K0 0 361#define AR_K7 7 362#define AR_RSC 16 363#define AR_BSP 17 364#define AR_BSPSTORE 18 365#define AR_RNAT 19 366#define AR_FCR 21 367#define AR_EFLAG 24 368#define AR_CSD 25 369#define AR_SSD 26 370#define AR_CFLG 27 371#define AR_FSR 28 372#define AR_FIR 29 373#define AR_FDR 30 374#define AR_CCV 32 375#define AR_UNAT 36 376#define AR_FPSR 40 377#define AR_ITC 44 378#define AR_RUC 45 379#define AR_PFS 64 380#define AR_LC 65 381#define AR_EC 66 382 383static const struct 384 { 385 const char *name; 386 unsigned int regnum; 387 } 388ar[] = 389 { 390 {"ar.k0", AR_K0}, {"ar.k1", AR_K0 + 1}, 391 {"ar.k2", AR_K0 + 2}, {"ar.k3", AR_K0 + 3}, 392 {"ar.k4", AR_K0 + 4}, {"ar.k5", AR_K0 + 5}, 393 {"ar.k6", AR_K0 + 6}, {"ar.k7", AR_K7}, 394 {"ar.rsc", AR_RSC}, {"ar.bsp", AR_BSP}, 395 {"ar.bspstore", AR_BSPSTORE}, {"ar.rnat", AR_RNAT}, 396 {"ar.fcr", AR_FCR}, {"ar.eflag", AR_EFLAG}, 397 {"ar.csd", AR_CSD}, {"ar.ssd", AR_SSD}, 398 {"ar.cflg", AR_CFLG}, {"ar.fsr", AR_FSR}, 399 {"ar.fir", AR_FIR}, {"ar.fdr", AR_FDR}, 400 {"ar.ccv", AR_CCV}, {"ar.unat", AR_UNAT}, 401 {"ar.fpsr", AR_FPSR}, {"ar.itc", AR_ITC}, 402 {"ar.ruc", AR_RUC}, {"ar.pfs", AR_PFS}, 403 {"ar.lc", AR_LC}, {"ar.ec", AR_EC}, 404 }; 405 406/* control registers: */ 407 408#define CR_DCR 0 409#define CR_ITM 1 410#define CR_IVA 2 411#define CR_PTA 8 412#define CR_GPTA 9 413#define CR_IPSR 16 414#define CR_ISR 17 415#define CR_IIP 19 416#define CR_IFA 20 417#define CR_ITIR 21 418#define CR_IIPA 22 419#define CR_IFS 23 420#define CR_IIM 24 421#define CR_IHA 25 422#define CR_IIB0 26 423#define CR_IIB1 27 424#define CR_LID 64 425#define CR_IVR 65 426#define CR_TPR 66 427#define CR_EOI 67 428#define CR_IRR0 68 429#define CR_IRR3 71 430#define CR_ITV 72 431#define CR_PMV 73 432#define CR_CMCV 74 433#define CR_LRR0 80 434#define CR_LRR1 81 435 436static const struct 437 { 438 const char *name; 439 unsigned int regnum; 440 } 441cr[] = 442 { 443 {"cr.dcr", CR_DCR}, 444 {"cr.itm", CR_ITM}, 445 {"cr.iva", CR_IVA}, 446 {"cr.pta", CR_PTA}, 447 {"cr.gpta", CR_GPTA}, 448 {"cr.ipsr", CR_IPSR}, 449 {"cr.isr", CR_ISR}, 450 {"cr.iip", CR_IIP}, 451 {"cr.ifa", CR_IFA}, 452 {"cr.itir", CR_ITIR}, 453 {"cr.iipa", CR_IIPA}, 454 {"cr.ifs", CR_IFS}, 455 {"cr.iim", CR_IIM}, 456 {"cr.iha", CR_IHA}, 457 {"cr.iib0", CR_IIB0}, 458 {"cr.iib1", CR_IIB1}, 459 {"cr.lid", CR_LID}, 460 {"cr.ivr", CR_IVR}, 461 {"cr.tpr", CR_TPR}, 462 {"cr.eoi", CR_EOI}, 463 {"cr.irr0", CR_IRR0}, 464 {"cr.irr1", CR_IRR0 + 1}, 465 {"cr.irr2", CR_IRR0 + 2}, 466 {"cr.irr3", CR_IRR3}, 467 {"cr.itv", CR_ITV}, 468 {"cr.pmv", CR_PMV}, 469 {"cr.cmcv", CR_CMCV}, 470 {"cr.lrr0", CR_LRR0}, 471 {"cr.lrr1", CR_LRR1} 472 }; 473 474#define PSR_MFL 4 475#define PSR_IC 13 476#define PSR_DFL 18 477#define PSR_CPL 32 478 479static const struct const_desc 480 { 481 const char *name; 482 valueT value; 483 } 484const_bits[] = 485 { 486 /* PSR constant masks: */ 487 488 /* 0: reserved */ 489 {"psr.be", ((valueT) 1) << 1}, 490 {"psr.up", ((valueT) 1) << 2}, 491 {"psr.ac", ((valueT) 1) << 3}, 492 {"psr.mfl", ((valueT) 1) << 4}, 493 {"psr.mfh", ((valueT) 1) << 5}, 494 /* 6-12: reserved */ 495 {"psr.ic", ((valueT) 1) << 13}, 496 {"psr.i", ((valueT) 1) << 14}, 497 {"psr.pk", ((valueT) 1) << 15}, 498 /* 16: reserved */ 499 {"psr.dt", ((valueT) 1) << 17}, 500 {"psr.dfl", ((valueT) 1) << 18}, 501 {"psr.dfh", ((valueT) 1) << 19}, 502 {"psr.sp", ((valueT) 1) << 20}, 503 {"psr.pp", ((valueT) 1) << 21}, 504 {"psr.di", ((valueT) 1) << 22}, 505 {"psr.si", ((valueT) 1) << 23}, 506 {"psr.db", ((valueT) 1) << 24}, 507 {"psr.lp", ((valueT) 1) << 25}, 508 {"psr.tb", ((valueT) 1) << 26}, 509 {"psr.rt", ((valueT) 1) << 27}, 510 /* 28-31: reserved */ 511 /* 32-33: cpl (current privilege level) */ 512 {"psr.is", ((valueT) 1) << 34}, 513 {"psr.mc", ((valueT) 1) << 35}, 514 {"psr.it", ((valueT) 1) << 36}, 515 {"psr.id", ((valueT) 1) << 37}, 516 {"psr.da", ((valueT) 1) << 38}, 517 {"psr.dd", ((valueT) 1) << 39}, 518 {"psr.ss", ((valueT) 1) << 40}, 519 /* 41-42: ri (restart instruction) */ 520 {"psr.ed", ((valueT) 1) << 43}, 521 {"psr.bn", ((valueT) 1) << 44}, 522 }; 523 524/* indirect register-sets/memory: */ 525 526static const struct 527 { 528 const char *name; 529 unsigned int regnum; 530 } 531indirect_reg[] = 532 { 533 { "CPUID", IND_CPUID }, 534 { "cpuid", IND_CPUID }, 535 { "dbr", IND_DBR }, 536 { "dtr", IND_DTR }, 537 { "itr", IND_ITR }, 538 { "ibr", IND_IBR }, 539 { "msr", IND_MSR }, 540 { "pkr", IND_PKR }, 541 { "pmc", IND_PMC }, 542 { "pmd", IND_PMD }, 543 { "dahr", IND_DAHR }, 544 { "rr", IND_RR }, 545 }; 546 547/* Pseudo functions used to indicate relocation types (these functions 548 start with an at sign (@). */ 549static struct 550 { 551 const char *name; 552 enum pseudo_type 553 { 554 PSEUDO_FUNC_NONE, 555 PSEUDO_FUNC_RELOC, 556 PSEUDO_FUNC_CONST, 557 PSEUDO_FUNC_REG, 558 PSEUDO_FUNC_FLOAT 559 } 560 type; 561 union 562 { 563 unsigned long ival; 564 symbolS *sym; 565 } 566 u; 567 } 568pseudo_func[] = 569 { 570 /* reloc pseudo functions (these must come first!): */ 571 { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } }, 572 { "dtprel", PSEUDO_FUNC_RELOC, { 0 } }, 573 { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, 574 { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, 575 { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, 576 { "ltoffx", PSEUDO_FUNC_RELOC, { 0 } }, 577 { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, 578 { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, 579 { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, 580 { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, 581 { "tprel", PSEUDO_FUNC_RELOC, { 0 } }, 582 { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, 583 { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ 584 { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */ 585 { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */ 586 { NULL, 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */ 587 { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, 588#ifdef TE_VMS 589 { "slotcount", PSEUDO_FUNC_RELOC, { 0 } }, 590#endif 591 592 /* mbtype4 constants: */ 593 { "alt", PSEUDO_FUNC_CONST, { 0xa } }, 594 { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, 595 { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, 596 { "rev", PSEUDO_FUNC_CONST, { 0xb } }, 597 { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, 598 599 /* fclass constants: */ 600 { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, 601 { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, 602 { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, 603 { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, 604 { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, 605 { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, 606 { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, 607 { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, 608 { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, 609 610 { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ 611 612 /* hint constants: */ 613 { "pause", PSEUDO_FUNC_CONST, { 0x0 } }, 614 { "priority", PSEUDO_FUNC_CONST, { 0x1 } }, 615 616 /* tf constants: */ 617 { "clz", PSEUDO_FUNC_CONST, { 32 } }, 618 { "mpy", PSEUDO_FUNC_CONST, { 33 } }, 619 { "datahints", PSEUDO_FUNC_CONST, { 34 } }, 620 621 /* unwind-related constants: */ 622 { "svr4", PSEUDO_FUNC_CONST, { ELFOSABI_NONE } }, 623 { "hpux", PSEUDO_FUNC_CONST, { ELFOSABI_HPUX } }, 624 { "nt", PSEUDO_FUNC_CONST, { 2 } }, /* conflicts w/ELFOSABI_NETBSD */ 625 { "linux", PSEUDO_FUNC_CONST, { ELFOSABI_GNU } }, 626 { "freebsd", PSEUDO_FUNC_CONST, { ELFOSABI_FREEBSD } }, 627 { "openvms", PSEUDO_FUNC_CONST, { ELFOSABI_OPENVMS } }, 628 { "nsk", PSEUDO_FUNC_CONST, { ELFOSABI_NSK } }, 629 630 /* unwind-related registers: */ 631 { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } 632 }; 633 634/* 41-bit nop opcodes (one per unit): */ 635static const bfd_vma nop[IA64_NUM_UNITS] = 636 { 637 0x0000000000LL, /* NIL => break 0 */ 638 0x0008000000LL, /* I-unit nop */ 639 0x0008000000LL, /* M-unit nop */ 640 0x4000000000LL, /* B-unit nop */ 641 0x0008000000LL, /* F-unit nop */ 642 0x0000000000LL, /* L-"unit" nop immediate */ 643 0x0008000000LL, /* X-unit nop */ 644 }; 645 646/* Can't be `const' as it's passed to input routines (which have the 647 habit of setting temporary sentinels. */ 648static char special_section_name[][20] = 649 { 650 {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, 651 {".IA_64.unwind"}, {".IA_64.unwind_info"}, 652 {".init_array"}, {".fini_array"} 653 }; 654 655/* The best template for a particular sequence of up to three 656 instructions: */ 657#define N IA64_NUM_TYPES 658static unsigned char best_template[N][N][N]; 659#undef N 660 661/* Resource dependencies currently in effect */ 662static struct rsrc { 663 int depind; /* dependency index */ 664 const struct ia64_dependency *dependency; /* actual dependency */ 665 unsigned specific:1, /* is this a specific bit/regno? */ 666 link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ 667 int index; /* specific regno/bit within dependency */ 668 int note; /* optional qualifying note (0 if none) */ 669#define STATE_NONE 0 670#define STATE_STOP 1 671#define STATE_SRLZ 2 672 int insn_srlz; /* current insn serialization state */ 673 int data_srlz; /* current data serialization state */ 674 int qp_regno; /* qualifying predicate for this usage */ 675 const char *file; /* what file marked this dependency */ 676 unsigned int line; /* what line marked this dependency */ 677 struct mem_offset mem_offset; /* optional memory offset hint */ 678 enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ 679 int path; /* corresponding code entry index */ 680} *regdeps = NULL; 681static int regdepslen = 0; 682static int regdepstotlen = 0; 683static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; 684static const char *dv_sem[] = { "none", "implied", "impliedf", 685 "data", "instr", "specific", "stop", "other" }; 686static const char *dv_cmp_type[] = { "none", "OR", "AND" }; 687 688/* Current state of PR mutexation */ 689static struct qpmutex { 690 valueT prmask; 691 int path; 692} *qp_mutexes = NULL; /* QP mutex bitmasks */ 693static int qp_mutexeslen = 0; 694static int qp_mutexestotlen = 0; 695static valueT qp_safe_across_calls = 0; 696 697/* Current state of PR implications */ 698static struct qp_imply { 699 unsigned p1:6; 700 unsigned p2:6; 701 unsigned p2_branched:1; 702 int path; 703} *qp_implies = NULL; 704static int qp_implieslen = 0; 705static int qp_impliestotlen = 0; 706 707/* Keep track of static GR values so that indirect register usage can 708 sometimes be tracked. */ 709static struct gr { 710 unsigned known:1; 711 int path; 712 valueT value; 713} gr_values[128] = { 714 { 715 1, 716#ifdef INT_MAX 717 INT_MAX, 718#else 719 (((1 << (8 * sizeof(gr_values->path) - 2)) - 1) << 1) + 1, 720#endif 721 0 722 } 723}; 724 725/* Remember the alignment frag. */ 726static fragS *align_frag; 727 728/* These are the routines required to output the various types of 729 unwind records. */ 730 731/* A slot_number is a frag address plus the slot index (0-2). We use the 732 frag address here so that if there is a section switch in the middle of 733 a function, then instructions emitted to a different section are not 734 counted. Since there may be more than one frag for a function, this 735 means we also need to keep track of which frag this address belongs to 736 so we can compute inter-frag distances. This also nicely solves the 737 problem with nops emitted for align directives, which can't easily be 738 counted, but can easily be derived from frag sizes. */ 739 740typedef struct unw_rec_list { 741 unwind_record r; 742 unsigned long slot_number; 743 fragS *slot_frag; 744 struct unw_rec_list *next; 745} unw_rec_list; 746 747#define SLOT_NUM_NOT_SET (unsigned)-1 748 749/* Linked list of saved prologue counts. A very poor 750 implementation of a map from label numbers to prologue counts. */ 751typedef struct label_prologue_count 752{ 753 struct label_prologue_count *next; 754 unsigned long label_number; 755 unsigned int prologue_count; 756} label_prologue_count; 757 758typedef struct proc_pending 759{ 760 symbolS *sym; 761 struct proc_pending *next; 762} proc_pending; 763 764static struct 765{ 766 /* Maintain a list of unwind entries for the current function. */ 767 unw_rec_list *list; 768 unw_rec_list *tail; 769 770 /* Any unwind entries that should be attached to the current slot 771 that an insn is being constructed for. */ 772 unw_rec_list *current_entry; 773 774 /* These are used to create the unwind table entry for this function. */ 775 proc_pending proc_pending; 776 symbolS *info; /* pointer to unwind info */ 777 symbolS *personality_routine; 778 segT saved_text_seg; 779 subsegT saved_text_subseg; 780 unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ 781 782 /* TRUE if processing unwind directives in a prologue region. */ 783 unsigned int prologue : 1; 784 unsigned int prologue_mask : 4; 785 unsigned int prologue_gr : 7; 786 unsigned int body : 1; 787 unsigned int insn : 1; 788 unsigned int prologue_count; /* number of .prologues seen so far */ 789 /* Prologue counts at previous .label_state directives. */ 790 struct label_prologue_count * saved_prologue_counts; 791 792 /* List of split up .save-s. */ 793 unw_p_record *pending_saves; 794} unwind; 795 796/* The input value is a negated offset from psp, and specifies an address 797 psp - offset. The encoded value is psp + 16 - (4 * offset). Thus we 798 must add 16 and divide by 4 to get the encoded value. */ 799 800#define ENCODED_PSP_OFFSET(OFFSET) (((OFFSET) + 16) / 4) 801 802typedef void (*vbyte_func) (int, char *, char *); 803 804/* Forward declarations: */ 805static void dot_alias (int); 806static int parse_operand_and_eval (expressionS *, int); 807static void emit_one_bundle (void); 808static bfd_reloc_code_real_type ia64_gen_real_reloc_type (struct symbol *, 809 bfd_reloc_code_real_type); 810static void insn_group_break (int, int, int); 811static void add_qp_mutex (valueT); 812static void add_qp_imply (int, int); 813static void clear_qp_mutex (valueT); 814static void clear_qp_implies (valueT, valueT); 815static void print_dependency (const char *, int); 816static void instruction_serialization (void); 817static void data_serialization (void); 818static void output_R3_format (vbyte_func, unw_record_type, unsigned long); 819static void output_B3_format (vbyte_func, unsigned long, unsigned long); 820static void output_B4_format (vbyte_func, unw_record_type, unsigned long); 821static void free_saved_prologue_counts (void); 822 823/* Determine if application register REGNUM resides only in the integer 824 unit (as opposed to the memory unit). */ 825static int 826ar_is_only_in_integer_unit (int reg) 827{ 828 reg -= REG_AR; 829 return reg >= 64 && reg <= 111; 830} 831 832/* Determine if application register REGNUM resides only in the memory 833 unit (as opposed to the integer unit). */ 834static int 835ar_is_only_in_memory_unit (int reg) 836{ 837 reg -= REG_AR; 838 return reg >= 0 && reg <= 47; 839} 840 841/* Switch to section NAME and create section if necessary. It's 842 rather ugly that we have to manipulate input_line_pointer but I 843 don't see any other way to accomplish the same thing without 844 changing obj-elf.c (which may be the Right Thing, in the end). */ 845static void 846set_section (char *name) 847{ 848 char *saved_input_line_pointer; 849 850 saved_input_line_pointer = input_line_pointer; 851 input_line_pointer = name; 852 obj_elf_section (0); 853 input_line_pointer = saved_input_line_pointer; 854} 855 856/* Map 's' to SHF_IA_64_SHORT. */ 857 858bfd_vma 859ia64_elf_section_letter (int letter, const char **ptr_msg) 860{ 861 if (letter == 's') 862 return SHF_IA_64_SHORT; 863 else if (letter == 'o') 864 return SHF_LINK_ORDER; 865#ifdef TE_VMS 866 else if (letter == 'O') 867 return SHF_IA_64_VMS_OVERLAID; 868 else if (letter == 'g') 869 return SHF_IA_64_VMS_GLOBAL; 870#endif 871 872 *ptr_msg = _("bad .section directive: want a,o,s,w,x,M,S,G,T in string"); 873 return -1; 874} 875 876/* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ 877 878flagword 879ia64_elf_section_flags (flagword flags, 880 bfd_vma attr, 881 int type ATTRIBUTE_UNUSED) 882{ 883 if (attr & SHF_IA_64_SHORT) 884 flags |= SEC_SMALL_DATA; 885 return flags; 886} 887 888int 889ia64_elf_section_type (const char *str, size_t len) 890{ 891#define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0)) 892 893 if (STREQ (ELF_STRING_ia64_unwind_info)) 894 return SHT_PROGBITS; 895 896 if (STREQ (ELF_STRING_ia64_unwind_info_once)) 897 return SHT_PROGBITS; 898 899 if (STREQ (ELF_STRING_ia64_unwind)) 900 return SHT_IA_64_UNWIND; 901 902 if (STREQ (ELF_STRING_ia64_unwind_once)) 903 return SHT_IA_64_UNWIND; 904 905 if (STREQ ("unwind")) 906 return SHT_IA_64_UNWIND; 907 908 return -1; 909#undef STREQ 910} 911 912static unsigned int 913set_regstack (unsigned int ins, 914 unsigned int locs, 915 unsigned int outs, 916 unsigned int rots) 917{ 918 /* Size of frame. */ 919 unsigned int sof; 920 921 sof = ins + locs + outs; 922 if (sof > 96) 923 { 924 as_bad (_("Size of frame exceeds maximum of 96 registers")); 925 return 0; 926 } 927 if (rots > sof) 928 { 929 as_warn (_("Size of rotating registers exceeds frame size")); 930 return 0; 931 } 932 md.in.base = REG_GR + 32; 933 md.loc.base = md.in.base + ins; 934 md.out.base = md.loc.base + locs; 935 936 md.in.num_regs = ins; 937 md.loc.num_regs = locs; 938 md.out.num_regs = outs; 939 md.rot.num_regs = rots; 940 return sof; 941} 942 943void 944ia64_flush_insns (void) 945{ 946 struct label_fix *lfix; 947 segT saved_seg; 948 subsegT saved_subseg; 949 unw_rec_list *ptr; 950 bfd_boolean mark; 951 952 if (!md.last_text_seg) 953 return; 954 955 saved_seg = now_seg; 956 saved_subseg = now_subseg; 957 958 subseg_set (md.last_text_seg, 0); 959 960 while (md.num_slots_in_use > 0) 961 emit_one_bundle (); /* force out queued instructions */ 962 963 /* In case there are labels following the last instruction, resolve 964 those now. */ 965 mark = FALSE; 966 for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) 967 { 968 symbol_set_value_now (lfix->sym); 969 mark |= lfix->dw2_mark_labels; 970 } 971 if (mark) 972 { 973 dwarf2_where (&CURR_SLOT.debug_line); 974 CURR_SLOT.debug_line.flags |= DWARF2_FLAG_BASIC_BLOCK; 975 dwarf2_gen_line_info (frag_now_fix (), &CURR_SLOT.debug_line); 976 dwarf2_consume_line_info (); 977 } 978 CURR_SLOT.label_fixups = 0; 979 980 for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) 981 symbol_set_value_now (lfix->sym); 982 CURR_SLOT.tag_fixups = 0; 983 984 /* In case there are unwind directives following the last instruction, 985 resolve those now. We only handle prologue, body, and endp directives 986 here. Give an error for others. */ 987 for (ptr = unwind.current_entry; ptr; ptr = ptr->next) 988 { 989 switch (ptr->r.type) 990 { 991 case prologue: 992 case prologue_gr: 993 case body: 994 case endp: 995 ptr->slot_number = (unsigned long) frag_more (0); 996 ptr->slot_frag = frag_now; 997 break; 998 999 /* Allow any record which doesn't have a "t" field (i.e., 1000 doesn't relate to a particular instruction). */ 1001 case unwabi: 1002 case br_gr: 1003 case copy_state: 1004 case fr_mem: 1005 case frgr_mem: 1006 case gr_gr: 1007 case gr_mem: 1008 case label_state: 1009 case rp_br: 1010 case spill_base: 1011 case spill_mask: 1012 /* nothing */ 1013 break; 1014 1015 default: 1016 as_bad (_("Unwind directive not followed by an instruction.")); 1017 break; 1018 } 1019 } 1020 unwind.current_entry = NULL; 1021 1022 subseg_set (saved_seg, saved_subseg); 1023 1024 if (md.qp.X_op == O_register) 1025 as_bad (_("qualifying predicate not followed by instruction")); 1026} 1027 1028void 1029ia64_cons_align (int nbytes) 1030{ 1031 if (md.auto_align) 1032 { 1033 int log; 1034 for (log = 0; (nbytes & 1) != 1; nbytes >>= 1) 1035 log++; 1036 1037 do_align (log, NULL, 0, 0); 1038 } 1039} 1040 1041#ifdef TE_VMS 1042 1043/* .vms_common section, symbol, size, alignment */ 1044 1045static void 1046obj_elf_vms_common (int ignore ATTRIBUTE_UNUSED) 1047{ 1048 const char *sec_name; 1049 char *sym_name; 1050 char c; 1051 offsetT size; 1052 offsetT cur_size; 1053 offsetT temp; 1054 symbolS *symbolP; 1055 segT current_seg = now_seg; 1056 subsegT current_subseg = now_subseg; 1057 offsetT log_align; 1058 1059 /* Section name. */ 1060 sec_name = obj_elf_section_name (); 1061 if (sec_name == NULL) 1062 return; 1063 1064 /* Symbol name. */ 1065 SKIP_WHITESPACE (); 1066 if (*input_line_pointer == ',') 1067 { 1068 input_line_pointer++; 1069 SKIP_WHITESPACE (); 1070 } 1071 else 1072 { 1073 as_bad (_("expected ',' after section name")); 1074 ignore_rest_of_line (); 1075 return; 1076 } 1077 1078 c = get_symbol_name (&sym_name); 1079 1080 if (input_line_pointer == sym_name) 1081 { 1082 (void) restore_line_pointer (c); 1083 as_bad (_("expected symbol name")); 1084 ignore_rest_of_line (); 1085 return; 1086 } 1087 1088 symbolP = symbol_find_or_make (sym_name); 1089 (void) restore_line_pointer (c); 1090 1091 if ((S_IS_DEFINED (symbolP) || symbol_equated_p (symbolP)) 1092 && !S_IS_COMMON (symbolP)) 1093 { 1094 as_bad (_("Ignoring attempt to re-define symbol")); 1095 ignore_rest_of_line (); 1096 return; 1097 } 1098 1099 /* Symbol size. */ 1100 SKIP_WHITESPACE (); 1101 if (*input_line_pointer == ',') 1102 { 1103 input_line_pointer++; 1104 SKIP_WHITESPACE (); 1105 } 1106 else 1107 { 1108 as_bad (_("expected ',' after symbol name")); 1109 ignore_rest_of_line (); 1110 return; 1111 } 1112 1113 temp = get_absolute_expression (); 1114 size = temp; 1115 size &= ((offsetT) 2 << (stdoutput->arch_info->bits_per_address - 1)) - 1; 1116 if (temp != size) 1117 { 1118 as_warn (_("size (%ld) out of range, ignored"), (long) temp); 1119 ignore_rest_of_line (); 1120 return; 1121 } 1122 1123 /* Alignment. */ 1124 SKIP_WHITESPACE (); 1125 if (*input_line_pointer == ',') 1126 { 1127 input_line_pointer++; 1128 SKIP_WHITESPACE (); 1129 } 1130 else 1131 { 1132 as_bad (_("expected ',' after symbol size")); 1133 ignore_rest_of_line (); 1134 return; 1135 } 1136 1137 log_align = get_absolute_expression (); 1138 1139 demand_empty_rest_of_line (); 1140 1141 obj_elf_change_section 1142 (sec_name, SHT_NOBITS, 1143 SHF_ALLOC | SHF_WRITE | SHF_IA_64_VMS_OVERLAID | SHF_IA_64_VMS_GLOBAL, 1144 0, NULL, 1, 0); 1145 1146 S_SET_VALUE (symbolP, 0); 1147 S_SET_SIZE (symbolP, size); 1148 S_SET_EXTERNAL (symbolP); 1149 S_SET_SEGMENT (symbolP, now_seg); 1150 1151 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 1152 1153 record_alignment (now_seg, log_align); 1154 1155 cur_size = bfd_section_size (now_seg); 1156 if ((int) size > cur_size) 1157 { 1158 char *pfrag 1159 = frag_var (rs_fill, 1, 1, (relax_substateT)0, NULL, 1160 (valueT)size - (valueT)cur_size, NULL); 1161 *pfrag = 0; 1162 bfd_set_section_size (now_seg, size); 1163 } 1164 1165 /* Switch back to current segment. */ 1166 subseg_set (current_seg, current_subseg); 1167 1168#ifdef md_elf_section_change_hook 1169 md_elf_section_change_hook (); 1170#endif 1171} 1172 1173#endif /* TE_VMS */ 1174 1175/* Output COUNT bytes to a memory location. */ 1176static char *vbyte_mem_ptr = NULL; 1177 1178static void 1179output_vbyte_mem (int count, char *ptr, char *comment ATTRIBUTE_UNUSED) 1180{ 1181 int x; 1182 if (vbyte_mem_ptr == NULL) 1183 abort (); 1184 1185 if (count == 0) 1186 return; 1187 for (x = 0; x < count; x++) 1188 *(vbyte_mem_ptr++) = ptr[x]; 1189} 1190 1191/* Count the number of bytes required for records. */ 1192static int vbyte_count = 0; 1193static void 1194count_output (int count, 1195 char *ptr ATTRIBUTE_UNUSED, 1196 char *comment ATTRIBUTE_UNUSED) 1197{ 1198 vbyte_count += count; 1199} 1200 1201static void 1202output_R1_format (vbyte_func f, unw_record_type rtype, int rlen) 1203{ 1204 int r = 0; 1205 char byte; 1206 if (rlen > 0x1f) 1207 { 1208 output_R3_format (f, rtype, rlen); 1209 return; 1210 } 1211 1212 if (rtype == body) 1213 r = 1; 1214 else if (rtype != prologue) 1215 as_bad (_("record type is not valid")); 1216 1217 byte = UNW_R1 | (r << 5) | (rlen & 0x1f); 1218 (*f) (1, &byte, NULL); 1219} 1220 1221static void 1222output_R2_format (vbyte_func f, int mask, int grsave, unsigned long rlen) 1223{ 1224 char bytes[20]; 1225 int count = 2; 1226 mask = (mask & 0x0f); 1227 grsave = (grsave & 0x7f); 1228 1229 bytes[0] = (UNW_R2 | (mask >> 1)); 1230 bytes[1] = (((mask & 0x01) << 7) | grsave); 1231 count += output_leb128 (bytes + 2, rlen, 0); 1232 (*f) (count, bytes, NULL); 1233} 1234 1235static void 1236output_R3_format (vbyte_func f, unw_record_type rtype, unsigned long rlen) 1237{ 1238 int r = 0, count; 1239 char bytes[20]; 1240 if (rlen <= 0x1f) 1241 { 1242 output_R1_format (f, rtype, rlen); 1243 return; 1244 } 1245 1246 if (rtype == body) 1247 r = 1; 1248 else if (rtype != prologue) 1249 as_bad (_("record type is not valid")); 1250 bytes[0] = (UNW_R3 | r); 1251 count = output_leb128 (bytes + 1, rlen, 0); 1252 (*f) (count + 1, bytes, NULL); 1253} 1254 1255static void 1256output_P1_format (vbyte_func f, int brmask) 1257{ 1258 char byte; 1259 byte = UNW_P1 | (brmask & 0x1f); 1260 (*f) (1, &byte, NULL); 1261} 1262 1263static void 1264output_P2_format (vbyte_func f, int brmask, int gr) 1265{ 1266 char bytes[2]; 1267 brmask = (brmask & 0x1f); 1268 bytes[0] = UNW_P2 | (brmask >> 1); 1269 bytes[1] = (((brmask & 1) << 7) | gr); 1270 (*f) (2, bytes, NULL); 1271} 1272 1273static void 1274output_P3_format (vbyte_func f, unw_record_type rtype, int reg) 1275{ 1276 char bytes[2]; 1277 int r = 0; 1278 reg = (reg & 0x7f); 1279 switch (rtype) 1280 { 1281 case psp_gr: 1282 r = 0; 1283 break; 1284 case rp_gr: 1285 r = 1; 1286 break; 1287 case pfs_gr: 1288 r = 2; 1289 break; 1290 case preds_gr: 1291 r = 3; 1292 break; 1293 case unat_gr: 1294 r = 4; 1295 break; 1296 case lc_gr: 1297 r = 5; 1298 break; 1299 case rp_br: 1300 r = 6; 1301 break; 1302 case rnat_gr: 1303 r = 7; 1304 break; 1305 case bsp_gr: 1306 r = 8; 1307 break; 1308 case bspstore_gr: 1309 r = 9; 1310 break; 1311 case fpsr_gr: 1312 r = 10; 1313 break; 1314 case priunat_gr: 1315 r = 11; 1316 break; 1317 default: 1318 as_bad (_("Invalid record type for P3 format.")); 1319 } 1320 bytes[0] = (UNW_P3 | (r >> 1)); 1321 bytes[1] = (((r & 1) << 7) | reg); 1322 (*f) (2, bytes, NULL); 1323} 1324 1325static void 1326output_P4_format (vbyte_func f, unsigned char *imask, unsigned long imask_size) 1327{ 1328 imask[0] = UNW_P4; 1329 (*f) (imask_size, (char *) imask, NULL); 1330} 1331 1332static void 1333output_P5_format (vbyte_func f, int grmask, unsigned long frmask) 1334{ 1335 char bytes[4]; 1336 grmask = (grmask & 0x0f); 1337 1338 bytes[0] = UNW_P5; 1339 bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); 1340 bytes[2] = ((frmask & 0x0000ff00) >> 8); 1341 bytes[3] = (frmask & 0x000000ff); 1342 (*f) (4, bytes, NULL); 1343} 1344 1345static void 1346output_P6_format (vbyte_func f, unw_record_type rtype, int rmask) 1347{ 1348 char byte; 1349 int r = 0; 1350 1351 if (rtype == gr_mem) 1352 r = 1; 1353 else if (rtype != fr_mem) 1354 as_bad (_("Invalid record type for format P6")); 1355 byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); 1356 (*f) (1, &byte, NULL); 1357} 1358 1359static void 1360output_P7_format (vbyte_func f, 1361 unw_record_type rtype, 1362 unsigned long w1, 1363 unsigned long w2) 1364{ 1365 char bytes[20]; 1366 int count = 1; 1367 int r = 0; 1368 count += output_leb128 (bytes + 1, w1, 0); 1369 switch (rtype) 1370 { 1371 case mem_stack_f: 1372 r = 0; 1373 count += output_leb128 (bytes + count, w2 >> 4, 0); 1374 break; 1375 case mem_stack_v: 1376 r = 1; 1377 break; 1378 case spill_base: 1379 r = 2; 1380 break; 1381 case psp_sprel: 1382 r = 3; 1383 break; 1384 case rp_when: 1385 r = 4; 1386 break; 1387 case rp_psprel: 1388 r = 5; 1389 break; 1390 case pfs_when: 1391 r = 6; 1392 break; 1393 case pfs_psprel: 1394 r = 7; 1395 break; 1396 case preds_when: 1397 r = 8; 1398 break; 1399 case preds_psprel: 1400 r = 9; 1401 break; 1402 case lc_when: 1403 r = 10; 1404 break; 1405 case lc_psprel: 1406 r = 11; 1407 break; 1408 case unat_when: 1409 r = 12; 1410 break; 1411 case unat_psprel: 1412 r = 13; 1413 break; 1414 case fpsr_when: 1415 r = 14; 1416 break; 1417 case fpsr_psprel: 1418 r = 15; 1419 break; 1420 default: 1421 break; 1422 } 1423 bytes[0] = (UNW_P7 | r); 1424 (*f) (count, bytes, NULL); 1425} 1426 1427static void 1428output_P8_format (vbyte_func f, unw_record_type rtype, unsigned long t) 1429{ 1430 char bytes[20]; 1431 int r = 0; 1432 int count = 2; 1433 bytes[0] = UNW_P8; 1434 switch (rtype) 1435 { 1436 case rp_sprel: 1437 r = 1; 1438 break; 1439 case pfs_sprel: 1440 r = 2; 1441 break; 1442 case preds_sprel: 1443 r = 3; 1444 break; 1445 case lc_sprel: 1446 r = 4; 1447 break; 1448 case unat_sprel: 1449 r = 5; 1450 break; 1451 case fpsr_sprel: 1452 r = 6; 1453 break; 1454 case bsp_when: 1455 r = 7; 1456 break; 1457 case bsp_psprel: 1458 r = 8; 1459 break; 1460 case bsp_sprel: 1461 r = 9; 1462 break; 1463 case bspstore_when: 1464 r = 10; 1465 break; 1466 case bspstore_psprel: 1467 r = 11; 1468 break; 1469 case bspstore_sprel: 1470 r = 12; 1471 break; 1472 case rnat_when: 1473 r = 13; 1474 break; 1475 case rnat_psprel: 1476 r = 14; 1477 break; 1478 case rnat_sprel: 1479 r = 15; 1480 break; 1481 case priunat_when_gr: 1482 r = 16; 1483 break; 1484 case priunat_psprel: 1485 r = 17; 1486 break; 1487 case priunat_sprel: 1488 r = 18; 1489 break; 1490 case priunat_when_mem: 1491 r = 19; 1492 break; 1493 default: 1494 break; 1495 } 1496 bytes[1] = r; 1497 count += output_leb128 (bytes + 2, t, 0); 1498 (*f) (count, bytes, NULL); 1499} 1500 1501static void 1502output_P9_format (vbyte_func f, int grmask, int gr) 1503{ 1504 char bytes[3]; 1505 bytes[0] = UNW_P9; 1506 bytes[1] = (grmask & 0x0f); 1507 bytes[2] = (gr & 0x7f); 1508 (*f) (3, bytes, NULL); 1509} 1510 1511static void 1512output_P10_format (vbyte_func f, int abi, int context) 1513{ 1514 char bytes[3]; 1515 bytes[0] = UNW_P10; 1516 bytes[1] = (abi & 0xff); 1517 bytes[2] = (context & 0xff); 1518 (*f) (3, bytes, NULL); 1519} 1520 1521static void 1522output_B1_format (vbyte_func f, unw_record_type rtype, unsigned long label) 1523{ 1524 char byte; 1525 int r = 0; 1526 if (label > 0x1f) 1527 { 1528 output_B4_format (f, rtype, label); 1529 return; 1530 } 1531 if (rtype == copy_state) 1532 r = 1; 1533 else if (rtype != label_state) 1534 as_bad (_("Invalid record type for format B1")); 1535 1536 byte = (UNW_B1 | (r << 5) | (label & 0x1f)); 1537 (*f) (1, &byte, NULL); 1538} 1539 1540static void 1541output_B2_format (vbyte_func f, unsigned long ecount, unsigned long t) 1542{ 1543 char bytes[20]; 1544 int count = 1; 1545 if (ecount > 0x1f) 1546 { 1547 output_B3_format (f, ecount, t); 1548 return; 1549 } 1550 bytes[0] = (UNW_B2 | (ecount & 0x1f)); 1551 count += output_leb128 (bytes + 1, t, 0); 1552 (*f) (count, bytes, NULL); 1553} 1554 1555static void 1556output_B3_format (vbyte_func f, unsigned long ecount, unsigned long t) 1557{ 1558 char bytes[20]; 1559 int count = 1; 1560 if (ecount <= 0x1f) 1561 { 1562 output_B2_format (f, ecount, t); 1563 return; 1564 } 1565 bytes[0] = UNW_B3; 1566 count += output_leb128 (bytes + 1, t, 0); 1567 count += output_leb128 (bytes + count, ecount, 0); 1568 (*f) (count, bytes, NULL); 1569} 1570 1571static void 1572output_B4_format (vbyte_func f, unw_record_type rtype, unsigned long label) 1573{ 1574 char bytes[20]; 1575 int r = 0; 1576 int count = 1; 1577 if (label <= 0x1f) 1578 { 1579 output_B1_format (f, rtype, label); 1580 return; 1581 } 1582 1583 if (rtype == copy_state) 1584 r = 1; 1585 else if (rtype != label_state) 1586 as_bad (_("Invalid record type for format B1")); 1587 1588 bytes[0] = (UNW_B4 | (r << 3)); 1589 count += output_leb128 (bytes + 1, label, 0); 1590 (*f) (count, bytes, NULL); 1591} 1592 1593static char 1594format_ab_reg (int ab, int reg) 1595{ 1596 int ret; 1597 ab = (ab & 3); 1598 reg = (reg & 0x1f); 1599 ret = (ab << 5) | reg; 1600 return ret; 1601} 1602 1603static void 1604output_X1_format (vbyte_func f, 1605 unw_record_type rtype, 1606 int ab, 1607 int reg, 1608 unsigned long t, 1609 unsigned long w1) 1610{ 1611 char bytes[20]; 1612 int r = 0; 1613 int count = 2; 1614 bytes[0] = UNW_X1; 1615 1616 if (rtype == spill_sprel) 1617 r = 1; 1618 else if (rtype != spill_psprel) 1619 as_bad (_("Invalid record type for format X1")); 1620 bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); 1621 count += output_leb128 (bytes + 2, t, 0); 1622 count += output_leb128 (bytes + count, w1, 0); 1623 (*f) (count, bytes, NULL); 1624} 1625 1626static void 1627output_X2_format (vbyte_func f, 1628 int ab, 1629 int reg, 1630 int x, 1631 int y, 1632 int treg, 1633 unsigned long t) 1634{ 1635 char bytes[20]; 1636 int count = 3; 1637 bytes[0] = UNW_X2; 1638 bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1639 bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); 1640 count += output_leb128 (bytes + 3, t, 0); 1641 (*f) (count, bytes, NULL); 1642} 1643 1644static void 1645output_X3_format (vbyte_func f, 1646 unw_record_type rtype, 1647 int qp, 1648 int ab, 1649 int reg, 1650 unsigned long t, 1651 unsigned long w1) 1652{ 1653 char bytes[20]; 1654 int r = 0; 1655 int count = 3; 1656 bytes[0] = UNW_X3; 1657 1658 if (rtype == spill_sprel_p) 1659 r = 1; 1660 else if (rtype != spill_psprel_p) 1661 as_bad (_("Invalid record type for format X3")); 1662 bytes[1] = ((r << 7) | (qp & 0x3f)); 1663 bytes[2] = format_ab_reg (ab, reg); 1664 count += output_leb128 (bytes + 3, t, 0); 1665 count += output_leb128 (bytes + count, w1, 0); 1666 (*f) (count, bytes, NULL); 1667} 1668 1669static void 1670output_X4_format (vbyte_func f, 1671 int qp, 1672 int ab, 1673 int reg, 1674 int x, 1675 int y, 1676 int treg, 1677 unsigned long t) 1678{ 1679 char bytes[20]; 1680 int count = 4; 1681 bytes[0] = UNW_X4; 1682 bytes[1] = (qp & 0x3f); 1683 bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); 1684 bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); 1685 count += output_leb128 (bytes + 4, t, 0); 1686 (*f) (count, bytes, NULL); 1687} 1688 1689/* This function checks whether there are any outstanding .save-s and 1690 discards them if so. */ 1691 1692static void 1693check_pending_save (void) 1694{ 1695 if (unwind.pending_saves) 1696 { 1697 unw_rec_list *cur, *prev; 1698 1699 as_warn (_("Previous .save incomplete")); 1700 for (cur = unwind.list, prev = NULL; cur; ) 1701 if (&cur->r.record.p == unwind.pending_saves) 1702 { 1703 if (prev) 1704 prev->next = cur->next; 1705 else 1706 unwind.list = cur->next; 1707 if (cur == unwind.tail) 1708 unwind.tail = prev; 1709 if (cur == unwind.current_entry) 1710 unwind.current_entry = cur->next; 1711 /* Don't free the first discarded record, it's being used as 1712 terminator for (currently) br_gr and gr_gr processing, and 1713 also prevents leaving a dangling pointer to it in its 1714 predecessor. */ 1715 cur->r.record.p.grmask = 0; 1716 cur->r.record.p.brmask = 0; 1717 cur->r.record.p.frmask = 0; 1718 prev = cur->r.record.p.next; 1719 cur->r.record.p.next = NULL; 1720 cur = prev; 1721 break; 1722 } 1723 else 1724 { 1725 prev = cur; 1726 cur = cur->next; 1727 } 1728 while (cur) 1729 { 1730 prev = cur; 1731 cur = cur->r.record.p.next; 1732 free (prev); 1733 } 1734 unwind.pending_saves = NULL; 1735 } 1736} 1737 1738/* This function allocates a record list structure, and initializes fields. */ 1739 1740static unw_rec_list * 1741alloc_record (unw_record_type t) 1742{ 1743 unw_rec_list *ptr; 1744 ptr = XNEW (unw_rec_list); 1745 memset (ptr, 0, sizeof (*ptr)); 1746 ptr->slot_number = SLOT_NUM_NOT_SET; 1747 ptr->r.type = t; 1748 return ptr; 1749} 1750 1751/* Dummy unwind record used for calculating the length of the last prologue or 1752 body region. */ 1753 1754static unw_rec_list * 1755output_endp (void) 1756{ 1757 unw_rec_list *ptr = alloc_record (endp); 1758 return ptr; 1759} 1760 1761static unw_rec_list * 1762output_prologue (void) 1763{ 1764 unw_rec_list *ptr = alloc_record (prologue); 1765 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1766 return ptr; 1767} 1768 1769static unw_rec_list * 1770output_prologue_gr (unsigned int saved_mask, unsigned int reg) 1771{ 1772 unw_rec_list *ptr = alloc_record (prologue_gr); 1773 memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); 1774 ptr->r.record.r.grmask = saved_mask; 1775 ptr->r.record.r.grsave = reg; 1776 return ptr; 1777} 1778 1779static unw_rec_list * 1780output_body (void) 1781{ 1782 unw_rec_list *ptr = alloc_record (body); 1783 return ptr; 1784} 1785 1786static unw_rec_list * 1787output_mem_stack_f (unsigned int size) 1788{ 1789 unw_rec_list *ptr = alloc_record (mem_stack_f); 1790 ptr->r.record.p.size = size; 1791 return ptr; 1792} 1793 1794static unw_rec_list * 1795output_mem_stack_v (void) 1796{ 1797 unw_rec_list *ptr = alloc_record (mem_stack_v); 1798 return ptr; 1799} 1800 1801static unw_rec_list * 1802output_psp_gr (unsigned int gr) 1803{ 1804 unw_rec_list *ptr = alloc_record (psp_gr); 1805 ptr->r.record.p.r.gr = gr; 1806 return ptr; 1807} 1808 1809static unw_rec_list * 1810output_psp_sprel (unsigned int offset) 1811{ 1812 unw_rec_list *ptr = alloc_record (psp_sprel); 1813 ptr->r.record.p.off.sp = offset / 4; 1814 return ptr; 1815} 1816 1817static unw_rec_list * 1818output_rp_when (void) 1819{ 1820 unw_rec_list *ptr = alloc_record (rp_when); 1821 return ptr; 1822} 1823 1824static unw_rec_list * 1825output_rp_gr (unsigned int gr) 1826{ 1827 unw_rec_list *ptr = alloc_record (rp_gr); 1828 ptr->r.record.p.r.gr = gr; 1829 return ptr; 1830} 1831 1832static unw_rec_list * 1833output_rp_br (unsigned int br) 1834{ 1835 unw_rec_list *ptr = alloc_record (rp_br); 1836 ptr->r.record.p.r.br = br; 1837 return ptr; 1838} 1839 1840static unw_rec_list * 1841output_rp_psprel (unsigned int offset) 1842{ 1843 unw_rec_list *ptr = alloc_record (rp_psprel); 1844 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 1845 return ptr; 1846} 1847 1848static unw_rec_list * 1849output_rp_sprel (unsigned int offset) 1850{ 1851 unw_rec_list *ptr = alloc_record (rp_sprel); 1852 ptr->r.record.p.off.sp = offset / 4; 1853 return ptr; 1854} 1855 1856static unw_rec_list * 1857output_pfs_when (void) 1858{ 1859 unw_rec_list *ptr = alloc_record (pfs_when); 1860 return ptr; 1861} 1862 1863static unw_rec_list * 1864output_pfs_gr (unsigned int gr) 1865{ 1866 unw_rec_list *ptr = alloc_record (pfs_gr); 1867 ptr->r.record.p.r.gr = gr; 1868 return ptr; 1869} 1870 1871static unw_rec_list * 1872output_pfs_psprel (unsigned int offset) 1873{ 1874 unw_rec_list *ptr = alloc_record (pfs_psprel); 1875 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 1876 return ptr; 1877} 1878 1879static unw_rec_list * 1880output_pfs_sprel (unsigned int offset) 1881{ 1882 unw_rec_list *ptr = alloc_record (pfs_sprel); 1883 ptr->r.record.p.off.sp = offset / 4; 1884 return ptr; 1885} 1886 1887static unw_rec_list * 1888output_preds_when (void) 1889{ 1890 unw_rec_list *ptr = alloc_record (preds_when); 1891 return ptr; 1892} 1893 1894static unw_rec_list * 1895output_preds_gr (unsigned int gr) 1896{ 1897 unw_rec_list *ptr = alloc_record (preds_gr); 1898 ptr->r.record.p.r.gr = gr; 1899 return ptr; 1900} 1901 1902static unw_rec_list * 1903output_preds_psprel (unsigned int offset) 1904{ 1905 unw_rec_list *ptr = alloc_record (preds_psprel); 1906 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 1907 return ptr; 1908} 1909 1910static unw_rec_list * 1911output_preds_sprel (unsigned int offset) 1912{ 1913 unw_rec_list *ptr = alloc_record (preds_sprel); 1914 ptr->r.record.p.off.sp = offset / 4; 1915 return ptr; 1916} 1917 1918static unw_rec_list * 1919output_fr_mem (unsigned int mask) 1920{ 1921 unw_rec_list *ptr = alloc_record (fr_mem); 1922 unw_rec_list *cur = ptr; 1923 1924 ptr->r.record.p.frmask = mask; 1925 unwind.pending_saves = &ptr->r.record.p; 1926 for (;;) 1927 { 1928 unw_rec_list *prev = cur; 1929 1930 /* Clear least significant set bit. */ 1931 mask &= ~(mask & (~mask + 1)); 1932 if (!mask) 1933 return ptr; 1934 cur = alloc_record (fr_mem); 1935 cur->r.record.p.frmask = mask; 1936 /* Retain only least significant bit. */ 1937 prev->r.record.p.frmask ^= mask; 1938 prev->r.record.p.next = cur; 1939 } 1940} 1941 1942static unw_rec_list * 1943output_frgr_mem (unsigned int gr_mask, unsigned int fr_mask) 1944{ 1945 unw_rec_list *ptr = alloc_record (frgr_mem); 1946 unw_rec_list *cur = ptr; 1947 1948 unwind.pending_saves = &cur->r.record.p; 1949 cur->r.record.p.frmask = fr_mask; 1950 while (fr_mask) 1951 { 1952 unw_rec_list *prev = cur; 1953 1954 /* Clear least significant set bit. */ 1955 fr_mask &= ~(fr_mask & (~fr_mask + 1)); 1956 if (!gr_mask && !fr_mask) 1957 return ptr; 1958 cur = alloc_record (frgr_mem); 1959 cur->r.record.p.frmask = fr_mask; 1960 /* Retain only least significant bit. */ 1961 prev->r.record.p.frmask ^= fr_mask; 1962 prev->r.record.p.next = cur; 1963 } 1964 cur->r.record.p.grmask = gr_mask; 1965 for (;;) 1966 { 1967 unw_rec_list *prev = cur; 1968 1969 /* Clear least significant set bit. */ 1970 gr_mask &= ~(gr_mask & (~gr_mask + 1)); 1971 if (!gr_mask) 1972 return ptr; 1973 cur = alloc_record (frgr_mem); 1974 cur->r.record.p.grmask = gr_mask; 1975 /* Retain only least significant bit. */ 1976 prev->r.record.p.grmask ^= gr_mask; 1977 prev->r.record.p.next = cur; 1978 } 1979} 1980 1981static unw_rec_list * 1982output_gr_gr (unsigned int mask, unsigned int reg) 1983{ 1984 unw_rec_list *ptr = alloc_record (gr_gr); 1985 unw_rec_list *cur = ptr; 1986 1987 ptr->r.record.p.grmask = mask; 1988 ptr->r.record.p.r.gr = reg; 1989 unwind.pending_saves = &ptr->r.record.p; 1990 for (;;) 1991 { 1992 unw_rec_list *prev = cur; 1993 1994 /* Clear least significant set bit. */ 1995 mask &= ~(mask & (~mask + 1)); 1996 if (!mask) 1997 return ptr; 1998 cur = alloc_record (gr_gr); 1999 cur->r.record.p.grmask = mask; 2000 /* Indicate this record shouldn't be output. */ 2001 cur->r.record.p.r.gr = REG_NUM; 2002 /* Retain only least significant bit. */ 2003 prev->r.record.p.grmask ^= mask; 2004 prev->r.record.p.next = cur; 2005 } 2006} 2007 2008static unw_rec_list * 2009output_gr_mem (unsigned int mask) 2010{ 2011 unw_rec_list *ptr = alloc_record (gr_mem); 2012 unw_rec_list *cur = ptr; 2013 2014 ptr->r.record.p.grmask = mask; 2015 unwind.pending_saves = &ptr->r.record.p; 2016 for (;;) 2017 { 2018 unw_rec_list *prev = cur; 2019 2020 /* Clear least significant set bit. */ 2021 mask &= ~(mask & (~mask + 1)); 2022 if (!mask) 2023 return ptr; 2024 cur = alloc_record (gr_mem); 2025 cur->r.record.p.grmask = mask; 2026 /* Retain only least significant bit. */ 2027 prev->r.record.p.grmask ^= mask; 2028 prev->r.record.p.next = cur; 2029 } 2030} 2031 2032static unw_rec_list * 2033output_br_mem (unsigned int mask) 2034{ 2035 unw_rec_list *ptr = alloc_record (br_mem); 2036 unw_rec_list *cur = ptr; 2037 2038 ptr->r.record.p.brmask = mask; 2039 unwind.pending_saves = &ptr->r.record.p; 2040 for (;;) 2041 { 2042 unw_rec_list *prev = cur; 2043 2044 /* Clear least significant set bit. */ 2045 mask &= ~(mask & (~mask + 1)); 2046 if (!mask) 2047 return ptr; 2048 cur = alloc_record (br_mem); 2049 cur->r.record.p.brmask = mask; 2050 /* Retain only least significant bit. */ 2051 prev->r.record.p.brmask ^= mask; 2052 prev->r.record.p.next = cur; 2053 } 2054} 2055 2056static unw_rec_list * 2057output_br_gr (unsigned int mask, unsigned int reg) 2058{ 2059 unw_rec_list *ptr = alloc_record (br_gr); 2060 unw_rec_list *cur = ptr; 2061 2062 ptr->r.record.p.brmask = mask; 2063 ptr->r.record.p.r.gr = reg; 2064 unwind.pending_saves = &ptr->r.record.p; 2065 for (;;) 2066 { 2067 unw_rec_list *prev = cur; 2068 2069 /* Clear least significant set bit. */ 2070 mask &= ~(mask & (~mask + 1)); 2071 if (!mask) 2072 return ptr; 2073 cur = alloc_record (br_gr); 2074 cur->r.record.p.brmask = mask; 2075 /* Indicate this record shouldn't be output. */ 2076 cur->r.record.p.r.gr = REG_NUM; 2077 /* Retain only least significant bit. */ 2078 prev->r.record.p.brmask ^= mask; 2079 prev->r.record.p.next = cur; 2080 } 2081} 2082 2083static unw_rec_list * 2084output_spill_base (unsigned int offset) 2085{ 2086 unw_rec_list *ptr = alloc_record (spill_base); 2087 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2088 return ptr; 2089} 2090 2091static unw_rec_list * 2092output_unat_when (void) 2093{ 2094 unw_rec_list *ptr = alloc_record (unat_when); 2095 return ptr; 2096} 2097 2098static unw_rec_list * 2099output_unat_gr (unsigned int gr) 2100{ 2101 unw_rec_list *ptr = alloc_record (unat_gr); 2102 ptr->r.record.p.r.gr = gr; 2103 return ptr; 2104} 2105 2106static unw_rec_list * 2107output_unat_psprel (unsigned int offset) 2108{ 2109 unw_rec_list *ptr = alloc_record (unat_psprel); 2110 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2111 return ptr; 2112} 2113 2114static unw_rec_list * 2115output_unat_sprel (unsigned int offset) 2116{ 2117 unw_rec_list *ptr = alloc_record (unat_sprel); 2118 ptr->r.record.p.off.sp = offset / 4; 2119 return ptr; 2120} 2121 2122static unw_rec_list * 2123output_lc_when (void) 2124{ 2125 unw_rec_list *ptr = alloc_record (lc_when); 2126 return ptr; 2127} 2128 2129static unw_rec_list * 2130output_lc_gr (unsigned int gr) 2131{ 2132 unw_rec_list *ptr = alloc_record (lc_gr); 2133 ptr->r.record.p.r.gr = gr; 2134 return ptr; 2135} 2136 2137static unw_rec_list * 2138output_lc_psprel (unsigned int offset) 2139{ 2140 unw_rec_list *ptr = alloc_record (lc_psprel); 2141 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2142 return ptr; 2143} 2144 2145static unw_rec_list * 2146output_lc_sprel (unsigned int offset) 2147{ 2148 unw_rec_list *ptr = alloc_record (lc_sprel); 2149 ptr->r.record.p.off.sp = offset / 4; 2150 return ptr; 2151} 2152 2153static unw_rec_list * 2154output_fpsr_when (void) 2155{ 2156 unw_rec_list *ptr = alloc_record (fpsr_when); 2157 return ptr; 2158} 2159 2160static unw_rec_list * 2161output_fpsr_gr (unsigned int gr) 2162{ 2163 unw_rec_list *ptr = alloc_record (fpsr_gr); 2164 ptr->r.record.p.r.gr = gr; 2165 return ptr; 2166} 2167 2168static unw_rec_list * 2169output_fpsr_psprel (unsigned int offset) 2170{ 2171 unw_rec_list *ptr = alloc_record (fpsr_psprel); 2172 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2173 return ptr; 2174} 2175 2176static unw_rec_list * 2177output_fpsr_sprel (unsigned int offset) 2178{ 2179 unw_rec_list *ptr = alloc_record (fpsr_sprel); 2180 ptr->r.record.p.off.sp = offset / 4; 2181 return ptr; 2182} 2183 2184static unw_rec_list * 2185output_priunat_when_gr (void) 2186{ 2187 unw_rec_list *ptr = alloc_record (priunat_when_gr); 2188 return ptr; 2189} 2190 2191static unw_rec_list * 2192output_priunat_when_mem (void) 2193{ 2194 unw_rec_list *ptr = alloc_record (priunat_when_mem); 2195 return ptr; 2196} 2197 2198static unw_rec_list * 2199output_priunat_gr (unsigned int gr) 2200{ 2201 unw_rec_list *ptr = alloc_record (priunat_gr); 2202 ptr->r.record.p.r.gr = gr; 2203 return ptr; 2204} 2205 2206static unw_rec_list * 2207output_priunat_psprel (unsigned int offset) 2208{ 2209 unw_rec_list *ptr = alloc_record (priunat_psprel); 2210 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2211 return ptr; 2212} 2213 2214static unw_rec_list * 2215output_priunat_sprel (unsigned int offset) 2216{ 2217 unw_rec_list *ptr = alloc_record (priunat_sprel); 2218 ptr->r.record.p.off.sp = offset / 4; 2219 return ptr; 2220} 2221 2222static unw_rec_list * 2223output_bsp_when (void) 2224{ 2225 unw_rec_list *ptr = alloc_record (bsp_when); 2226 return ptr; 2227} 2228 2229static unw_rec_list * 2230output_bsp_gr (unsigned int gr) 2231{ 2232 unw_rec_list *ptr = alloc_record (bsp_gr); 2233 ptr->r.record.p.r.gr = gr; 2234 return ptr; 2235} 2236 2237static unw_rec_list * 2238output_bsp_psprel (unsigned int offset) 2239{ 2240 unw_rec_list *ptr = alloc_record (bsp_psprel); 2241 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2242 return ptr; 2243} 2244 2245static unw_rec_list * 2246output_bsp_sprel (unsigned int offset) 2247{ 2248 unw_rec_list *ptr = alloc_record (bsp_sprel); 2249 ptr->r.record.p.off.sp = offset / 4; 2250 return ptr; 2251} 2252 2253static unw_rec_list * 2254output_bspstore_when (void) 2255{ 2256 unw_rec_list *ptr = alloc_record (bspstore_when); 2257 return ptr; 2258} 2259 2260static unw_rec_list * 2261output_bspstore_gr (unsigned int gr) 2262{ 2263 unw_rec_list *ptr = alloc_record (bspstore_gr); 2264 ptr->r.record.p.r.gr = gr; 2265 return ptr; 2266} 2267 2268static unw_rec_list * 2269output_bspstore_psprel (unsigned int offset) 2270{ 2271 unw_rec_list *ptr = alloc_record (bspstore_psprel); 2272 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2273 return ptr; 2274} 2275 2276static unw_rec_list * 2277output_bspstore_sprel (unsigned int offset) 2278{ 2279 unw_rec_list *ptr = alloc_record (bspstore_sprel); 2280 ptr->r.record.p.off.sp = offset / 4; 2281 return ptr; 2282} 2283 2284static unw_rec_list * 2285output_rnat_when (void) 2286{ 2287 unw_rec_list *ptr = alloc_record (rnat_when); 2288 return ptr; 2289} 2290 2291static unw_rec_list * 2292output_rnat_gr (unsigned int gr) 2293{ 2294 unw_rec_list *ptr = alloc_record (rnat_gr); 2295 ptr->r.record.p.r.gr = gr; 2296 return ptr; 2297} 2298 2299static unw_rec_list * 2300output_rnat_psprel (unsigned int offset) 2301{ 2302 unw_rec_list *ptr = alloc_record (rnat_psprel); 2303 ptr->r.record.p.off.psp = ENCODED_PSP_OFFSET (offset); 2304 return ptr; 2305} 2306 2307static unw_rec_list * 2308output_rnat_sprel (unsigned int offset) 2309{ 2310 unw_rec_list *ptr = alloc_record (rnat_sprel); 2311 ptr->r.record.p.off.sp = offset / 4; 2312 return ptr; 2313} 2314 2315static unw_rec_list * 2316output_unwabi (unsigned long abi, unsigned long context) 2317{ 2318 unw_rec_list *ptr = alloc_record (unwabi); 2319 ptr->r.record.p.abi = abi; 2320 ptr->r.record.p.context = context; 2321 return ptr; 2322} 2323 2324static unw_rec_list * 2325output_epilogue (unsigned long ecount) 2326{ 2327 unw_rec_list *ptr = alloc_record (epilogue); 2328 ptr->r.record.b.ecount = ecount; 2329 return ptr; 2330} 2331 2332static unw_rec_list * 2333output_label_state (unsigned long label) 2334{ 2335 unw_rec_list *ptr = alloc_record (label_state); 2336 ptr->r.record.b.label = label; 2337 return ptr; 2338} 2339 2340static unw_rec_list * 2341output_copy_state (unsigned long label) 2342{ 2343 unw_rec_list *ptr = alloc_record (copy_state); 2344 ptr->r.record.b.label = label; 2345 return ptr; 2346} 2347 2348static unw_rec_list * 2349output_spill_psprel (unsigned int ab, 2350 unsigned int reg, 2351 unsigned int offset, 2352 unsigned int predicate) 2353{ 2354 unw_rec_list *ptr = alloc_record (predicate ? spill_psprel_p : spill_psprel); 2355 ptr->r.record.x.ab = ab; 2356 ptr->r.record.x.reg = reg; 2357 ptr->r.record.x.where.pspoff = ENCODED_PSP_OFFSET (offset); 2358 ptr->r.record.x.qp = predicate; 2359 return ptr; 2360} 2361 2362static unw_rec_list * 2363output_spill_sprel (unsigned int ab, 2364 unsigned int reg, 2365 unsigned int offset, 2366 unsigned int predicate) 2367{ 2368 unw_rec_list *ptr = alloc_record (predicate ? spill_sprel_p : spill_sprel); 2369 ptr->r.record.x.ab = ab; 2370 ptr->r.record.x.reg = reg; 2371 ptr->r.record.x.where.spoff = offset / 4; 2372 ptr->r.record.x.qp = predicate; 2373 return ptr; 2374} 2375 2376static unw_rec_list * 2377output_spill_reg (unsigned int ab, 2378 unsigned int reg, 2379 unsigned int targ_reg, 2380 unsigned int xy, 2381 unsigned int predicate) 2382{ 2383 unw_rec_list *ptr = alloc_record (predicate ? spill_reg_p : spill_reg); 2384 ptr->r.record.x.ab = ab; 2385 ptr->r.record.x.reg = reg; 2386 ptr->r.record.x.where.reg = targ_reg; 2387 ptr->r.record.x.xy = xy; 2388 ptr->r.record.x.qp = predicate; 2389 return ptr; 2390} 2391 2392/* Given a unw_rec_list process the correct format with the 2393 specified function. */ 2394 2395static void 2396process_one_record (unw_rec_list *ptr, vbyte_func f) 2397{ 2398 unsigned int fr_mask, gr_mask; 2399 2400 switch (ptr->r.type) 2401 { 2402 /* This is a dummy record that takes up no space in the output. */ 2403 case endp: 2404 break; 2405 2406 case gr_mem: 2407 case fr_mem: 2408 case br_mem: 2409 case frgr_mem: 2410 /* These are taken care of by prologue/prologue_gr. */ 2411 break; 2412 2413 case prologue_gr: 2414 case prologue: 2415 if (ptr->r.type == prologue_gr) 2416 output_R2_format (f, ptr->r.record.r.grmask, 2417 ptr->r.record.r.grsave, ptr->r.record.r.rlen); 2418 else 2419 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2420 2421 /* Output descriptor(s) for union of register spills (if any). */ 2422 gr_mask = ptr->r.record.r.mask.gr_mem; 2423 fr_mask = ptr->r.record.r.mask.fr_mem; 2424 if (fr_mask) 2425 { 2426 if ((fr_mask & ~0xfUL) == 0) 2427 output_P6_format (f, fr_mem, fr_mask); 2428 else 2429 { 2430 output_P5_format (f, gr_mask, fr_mask); 2431 gr_mask = 0; 2432 } 2433 } 2434 if (gr_mask) 2435 output_P6_format (f, gr_mem, gr_mask); 2436 if (ptr->r.record.r.mask.br_mem) 2437 output_P1_format (f, ptr->r.record.r.mask.br_mem); 2438 2439 /* output imask descriptor if necessary: */ 2440 if (ptr->r.record.r.mask.i) 2441 output_P4_format (f, ptr->r.record.r.mask.i, 2442 ptr->r.record.r.imask_size); 2443 break; 2444 2445 case body: 2446 output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); 2447 break; 2448 case mem_stack_f: 2449 case mem_stack_v: 2450 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 2451 ptr->r.record.p.size); 2452 break; 2453 case psp_gr: 2454 case rp_gr: 2455 case pfs_gr: 2456 case preds_gr: 2457 case unat_gr: 2458 case lc_gr: 2459 case fpsr_gr: 2460 case priunat_gr: 2461 case bsp_gr: 2462 case bspstore_gr: 2463 case rnat_gr: 2464 output_P3_format (f, ptr->r.type, ptr->r.record.p.r.gr); 2465 break; 2466 case rp_br: 2467 output_P3_format (f, rp_br, ptr->r.record.p.r.br); 2468 break; 2469 case psp_sprel: 2470 output_P7_format (f, psp_sprel, ptr->r.record.p.off.sp, 0); 2471 break; 2472 case rp_when: 2473 case pfs_when: 2474 case preds_when: 2475 case unat_when: 2476 case lc_when: 2477 case fpsr_when: 2478 output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); 2479 break; 2480 case rp_psprel: 2481 case pfs_psprel: 2482 case preds_psprel: 2483 case unat_psprel: 2484 case lc_psprel: 2485 case fpsr_psprel: 2486 case spill_base: 2487 output_P7_format (f, ptr->r.type, ptr->r.record.p.off.psp, 0); 2488 break; 2489 case rp_sprel: 2490 case pfs_sprel: 2491 case preds_sprel: 2492 case unat_sprel: 2493 case lc_sprel: 2494 case fpsr_sprel: 2495 case priunat_sprel: 2496 case bsp_sprel: 2497 case bspstore_sprel: 2498 case rnat_sprel: 2499 output_P8_format (f, ptr->r.type, ptr->r.record.p.off.sp); 2500 break; 2501 case gr_gr: 2502 if (ptr->r.record.p.r.gr < REG_NUM) 2503 { 2504 const unw_rec_list *cur = ptr; 2505 2506 gr_mask = cur->r.record.p.grmask; 2507 while ((cur = cur->r.record.p.next) != NULL) 2508 gr_mask |= cur->r.record.p.grmask; 2509 output_P9_format (f, gr_mask, ptr->r.record.p.r.gr); 2510 } 2511 break; 2512 case br_gr: 2513 if (ptr->r.record.p.r.gr < REG_NUM) 2514 { 2515 const unw_rec_list *cur = ptr; 2516 2517 gr_mask = cur->r.record.p.brmask; 2518 while ((cur = cur->r.record.p.next) != NULL) 2519 gr_mask |= cur->r.record.p.brmask; 2520 output_P2_format (f, gr_mask, ptr->r.record.p.r.gr); 2521 } 2522 break; 2523 case spill_mask: 2524 as_bad (_("spill_mask record unimplemented.")); 2525 break; 2526 case priunat_when_gr: 2527 case priunat_when_mem: 2528 case bsp_when: 2529 case bspstore_when: 2530 case rnat_when: 2531 output_P8_format (f, ptr->r.type, ptr->r.record.p.t); 2532 break; 2533 case priunat_psprel: 2534 case bsp_psprel: 2535 case bspstore_psprel: 2536 case rnat_psprel: 2537 output_P8_format (f, ptr->r.type, ptr->r.record.p.off.psp); 2538 break; 2539 case unwabi: 2540 output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); 2541 break; 2542 case epilogue: 2543 output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); 2544 break; 2545 case label_state: 2546 case copy_state: 2547 output_B4_format (f, ptr->r.type, ptr->r.record.b.label); 2548 break; 2549 case spill_psprel: 2550 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2551 ptr->r.record.x.reg, ptr->r.record.x.t, 2552 ptr->r.record.x.where.pspoff); 2553 break; 2554 case spill_sprel: 2555 output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, 2556 ptr->r.record.x.reg, ptr->r.record.x.t, 2557 ptr->r.record.x.where.spoff); 2558 break; 2559 case spill_reg: 2560 output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, 2561 ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, 2562 ptr->r.record.x.where.reg, ptr->r.record.x.t); 2563 break; 2564 case spill_psprel_p: 2565 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2566 ptr->r.record.x.ab, ptr->r.record.x.reg, 2567 ptr->r.record.x.t, ptr->r.record.x.where.pspoff); 2568 break; 2569 case spill_sprel_p: 2570 output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, 2571 ptr->r.record.x.ab, ptr->r.record.x.reg, 2572 ptr->r.record.x.t, ptr->r.record.x.where.spoff); 2573 break; 2574 case spill_reg_p: 2575 output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, 2576 ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, 2577 ptr->r.record.x.xy, ptr->r.record.x.where.reg, 2578 ptr->r.record.x.t); 2579 break; 2580 default: 2581 as_bad (_("record_type_not_valid")); 2582 break; 2583 } 2584} 2585 2586/* Given a unw_rec_list list, process all the records with 2587 the specified function. */ 2588static void 2589process_unw_records (unw_rec_list *list, vbyte_func f) 2590{ 2591 unw_rec_list *ptr; 2592 for (ptr = list; ptr; ptr = ptr->next) 2593 process_one_record (ptr, f); 2594} 2595 2596/* Determine the size of a record list in bytes. */ 2597static int 2598calc_record_size (unw_rec_list *list) 2599{ 2600 vbyte_count = 0; 2601 process_unw_records (list, count_output); 2602 return vbyte_count; 2603} 2604 2605/* Return the number of bits set in the input value. 2606 Perhaps this has a better place... */ 2607#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4) 2608# define popcount __builtin_popcount 2609#else 2610static int 2611popcount (unsigned x) 2612{ 2613 static const unsigned char popcnt[16] = 2614 { 2615 0, 1, 1, 2, 2616 1, 2, 2, 3, 2617 1, 2, 2, 3, 2618 2, 3, 3, 4 2619 }; 2620 2621 if (x < NELEMS (popcnt)) 2622 return popcnt[x]; 2623 return popcnt[x % NELEMS (popcnt)] + popcount (x / NELEMS (popcnt)); 2624} 2625#endif 2626 2627/* Update IMASK bitmask to reflect the fact that one or more registers 2628 of type TYPE are saved starting at instruction with index T. If N 2629 bits are set in REGMASK, it is assumed that instructions T through 2630 T+N-1 save these registers. 2631 2632 TYPE values: 2633 0: no save 2634 1: instruction saves next fp reg 2635 2: instruction saves next general reg 2636 3: instruction saves next branch reg */ 2637static void 2638set_imask (unw_rec_list *region, 2639 unsigned long regmask, 2640 unsigned long t, 2641 unsigned int type) 2642{ 2643 unsigned char *imask; 2644 unsigned long imask_size; 2645 unsigned int i; 2646 int pos; 2647 2648 imask = region->r.record.r.mask.i; 2649 imask_size = region->r.record.r.imask_size; 2650 if (!imask) 2651 { 2652 imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; 2653 imask = XCNEWVEC (unsigned char, imask_size); 2654 2655 region->r.record.r.imask_size = imask_size; 2656 region->r.record.r.mask.i = imask; 2657 } 2658 2659 i = (t / 4) + 1; 2660 pos = 2 * (3 - t % 4); 2661 while (regmask) 2662 { 2663 if (i >= imask_size) 2664 { 2665 as_bad (_("Ignoring attempt to spill beyond end of region")); 2666 return; 2667 } 2668 2669 imask[i] |= (type & 0x3) << pos; 2670 2671 regmask &= (regmask - 1); 2672 pos -= 2; 2673 if (pos < 0) 2674 { 2675 pos = 0; 2676 ++i; 2677 } 2678 } 2679} 2680 2681/* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. 2682 SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag 2683 containing FIRST_ADDR. If BEFORE_RELAX, then we use worst-case estimates 2684 for frag sizes. */ 2685 2686static unsigned long 2687slot_index (unsigned long slot_addr, 2688 fragS *slot_frag, 2689 unsigned long first_addr, 2690 fragS *first_frag, 2691 int before_relax) 2692{ 2693 unsigned long s_index = 0; 2694 2695 /* First time we are called, the initial address and frag are invalid. */ 2696 if (first_addr == 0) 2697 return 0; 2698 2699 /* If the two addresses are in different frags, then we need to add in 2700 the remaining size of this frag, and then the entire size of intermediate 2701 frags. */ 2702 while (slot_frag != first_frag) 2703 { 2704 unsigned long start_addr = (unsigned long) &first_frag->fr_literal; 2705 2706 if (! before_relax) 2707 { 2708 /* We can get the final addresses only during and after 2709 relaxation. */ 2710 if (first_frag->fr_next && first_frag->fr_next->fr_address) 2711 s_index += 3 * ((first_frag->fr_next->fr_address 2712 - first_frag->fr_address 2713 - first_frag->fr_fix) >> 4); 2714 } 2715 else 2716 /* We don't know what the final addresses will be. We try our 2717 best to estimate. */ 2718 switch (first_frag->fr_type) 2719 { 2720 default: 2721 break; 2722 2723 case rs_space: 2724 as_fatal (_("Only constant space allocation is supported")); 2725 break; 2726 2727 case rs_align: 2728 case rs_align_code: 2729 case rs_align_test: 2730 /* Take alignment into account. Assume the worst case 2731 before relaxation. */ 2732 s_index += 3 * ((1 << first_frag->fr_offset) >> 4); 2733 break; 2734 2735 case rs_org: 2736 if (first_frag->fr_symbol) 2737 { 2738 as_fatal (_("Only constant offsets are supported")); 2739 break; 2740 } 2741 /* Fall through. */ 2742 case rs_fill: 2743 s_index += 3 * (first_frag->fr_offset >> 4); 2744 break; 2745 } 2746 2747 /* Add in the full size of the frag converted to instruction slots. */ 2748 s_index += 3 * (first_frag->fr_fix >> 4); 2749 /* Subtract away the initial part before first_addr. */ 2750 s_index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) 2751 + ((first_addr & 0x3) - (start_addr & 0x3))); 2752 2753 /* Move to the beginning of the next frag. */ 2754 first_frag = first_frag->fr_next; 2755 first_addr = (unsigned long) &first_frag->fr_literal; 2756 2757 /* This can happen if there is section switching in the middle of a 2758 function, causing the frag chain for the function to be broken. 2759 It is too difficult to recover safely from this problem, so we just 2760 exit with an error. */ 2761 if (first_frag == NULL) 2762 as_fatal (_("Section switching in code is not supported.")); 2763 } 2764 2765 /* Add in the used part of the last frag. */ 2766 s_index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) 2767 + ((slot_addr & 0x3) - (first_addr & 0x3))); 2768 return s_index; 2769} 2770 2771/* Optimize unwind record directives. */ 2772 2773static unw_rec_list * 2774optimize_unw_records (unw_rec_list *list) 2775{ 2776 if (!list) 2777 return NULL; 2778 2779 /* If the only unwind record is ".prologue" or ".prologue" followed 2780 by ".body", then we can optimize the unwind directives away. */ 2781 if (list->r.type == prologue 2782 && (list->next->r.type == endp 2783 || (list->next->r.type == body && list->next->next->r.type == endp))) 2784 return NULL; 2785 2786 return list; 2787} 2788 2789/* Given a complete record list, process any records which have 2790 unresolved fields, (ie length counts for a prologue). After 2791 this has been run, all necessary information should be available 2792 within each record to generate an image. */ 2793 2794static void 2795fixup_unw_records (unw_rec_list *list, int before_relax) 2796{ 2797 unw_rec_list *ptr, *region = 0; 2798 unsigned long first_addr = 0, rlen = 0, t; 2799 fragS *first_frag = 0; 2800 2801 for (ptr = list; ptr; ptr = ptr->next) 2802 { 2803 if (ptr->slot_number == SLOT_NUM_NOT_SET) 2804 as_bad (_("Insn slot not set in unwind record.")); 2805 t = slot_index (ptr->slot_number, ptr->slot_frag, 2806 first_addr, first_frag, before_relax); 2807 switch (ptr->r.type) 2808 { 2809 case prologue: 2810 case prologue_gr: 2811 case body: 2812 { 2813 unw_rec_list *last; 2814 int size; 2815 unsigned long last_addr = 0; 2816 fragS *last_frag = NULL; 2817 2818 first_addr = ptr->slot_number; 2819 first_frag = ptr->slot_frag; 2820 /* Find either the next body/prologue start, or the end of 2821 the function, and determine the size of the region. */ 2822 for (last = ptr->next; last != NULL; last = last->next) 2823 if (last->r.type == prologue || last->r.type == prologue_gr 2824 || last->r.type == body || last->r.type == endp) 2825 { 2826 last_addr = last->slot_number; 2827 last_frag = last->slot_frag; 2828 break; 2829 } 2830 size = slot_index (last_addr, last_frag, first_addr, first_frag, 2831 before_relax); 2832 rlen = ptr->r.record.r.rlen = size; 2833 if (ptr->r.type == body) 2834 /* End of region. */ 2835 region = 0; 2836 else 2837 region = ptr; 2838 break; 2839 } 2840 case epilogue: 2841 if (t < rlen) 2842 ptr->r.record.b.t = rlen - 1 - t; 2843 else 2844 /* This happens when a memory-stack-less procedure uses a 2845 ".restore sp" directive at the end of a region to pop 2846 the frame state. */ 2847 ptr->r.record.b.t = 0; 2848 break; 2849 2850 case mem_stack_f: 2851 case mem_stack_v: 2852 case rp_when: 2853 case pfs_when: 2854 case preds_when: 2855 case unat_when: 2856 case lc_when: 2857 case fpsr_when: 2858 case priunat_when_gr: 2859 case priunat_when_mem: 2860 case bsp_when: 2861 case bspstore_when: 2862 case rnat_when: 2863 ptr->r.record.p.t = t; 2864 break; 2865 2866 case spill_reg: 2867 case spill_sprel: 2868 case spill_psprel: 2869 case spill_reg_p: 2870 case spill_sprel_p: 2871 case spill_psprel_p: 2872 ptr->r.record.x.t = t; 2873 break; 2874 2875 case frgr_mem: 2876 if (!region) 2877 { 2878 as_bad (_("frgr_mem record before region record!")); 2879 return; 2880 } 2881 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; 2882 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; 2883 set_imask (region, ptr->r.record.p.frmask, t, 1); 2884 set_imask (region, ptr->r.record.p.grmask, t, 2); 2885 break; 2886 case fr_mem: 2887 if (!region) 2888 { 2889 as_bad (_("fr_mem record before region record!")); 2890 return; 2891 } 2892 region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; 2893 set_imask (region, ptr->r.record.p.frmask, t, 1); 2894 break; 2895 case gr_mem: 2896 if (!region) 2897 { 2898 as_bad (_("gr_mem record before region record!")); 2899 return; 2900 } 2901 region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; 2902 set_imask (region, ptr->r.record.p.grmask, t, 2); 2903 break; 2904 case br_mem: 2905 if (!region) 2906 { 2907 as_bad (_("br_mem record before region record!")); 2908 return; 2909 } 2910 region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; 2911 set_imask (region, ptr->r.record.p.brmask, t, 3); 2912 break; 2913 2914 case gr_gr: 2915 if (!region) 2916 { 2917 as_bad (_("gr_gr record before region record!")); 2918 return; 2919 } 2920 set_imask (region, ptr->r.record.p.grmask, t, 2); 2921 break; 2922 case br_gr: 2923 if (!region) 2924 { 2925 as_bad (_("br_gr record before region record!")); 2926 return; 2927 } 2928 set_imask (region, ptr->r.record.p.brmask, t, 3); 2929 break; 2930 2931 default: 2932 break; 2933 } 2934 } 2935} 2936 2937/* Estimate the size of a frag before relaxing. We only have one type of frag 2938 to handle here, which is the unwind info frag. */ 2939 2940int 2941ia64_estimate_size_before_relax (fragS *frag, 2942 asection *segtype ATTRIBUTE_UNUSED) 2943{ 2944 unw_rec_list *list; 2945 int len, size, pad; 2946 2947 /* ??? This code is identical to the first part of ia64_convert_frag. */ 2948 list = (unw_rec_list *) frag->fr_opcode; 2949 fixup_unw_records (list, 0); 2950 2951 len = calc_record_size (list); 2952 /* pad to pointer-size boundary. */ 2953 pad = len % md.pointer_size; 2954 if (pad != 0) 2955 len += md.pointer_size - pad; 2956 /* Add 8 for the header. */ 2957 size = len + 8; 2958 /* Add a pointer for the personality offset. */ 2959 if (frag->fr_offset) 2960 size += md.pointer_size; 2961 2962 /* fr_var carries the max_chars that we created the fragment with. 2963 We must, of course, have allocated enough memory earlier. */ 2964 gas_assert (frag->fr_var >= size); 2965 2966 return frag->fr_fix + size; 2967} 2968 2969/* This function converts a rs_machine_dependent variant frag into a 2970 normal fill frag with the unwind image from the record list. */ 2971void 2972ia64_convert_frag (fragS *frag) 2973{ 2974 unw_rec_list *list; 2975 int len, size, pad; 2976 valueT flag_value; 2977 2978 /* ??? This code is identical to ia64_estimate_size_before_relax. */ 2979 list = (unw_rec_list *) frag->fr_opcode; 2980 fixup_unw_records (list, 0); 2981 2982 len = calc_record_size (list); 2983 /* pad to pointer-size boundary. */ 2984 pad = len % md.pointer_size; 2985 if (pad != 0) 2986 len += md.pointer_size - pad; 2987 /* Add 8 for the header. */ 2988 size = len + 8; 2989 /* Add a pointer for the personality offset. */ 2990 if (frag->fr_offset) 2991 size += md.pointer_size; 2992 2993 /* fr_var carries the max_chars that we created the fragment with. 2994 We must, of course, have allocated enough memory earlier. */ 2995 gas_assert (frag->fr_var >= size); 2996 2997 /* Initialize the header area. fr_offset is initialized with 2998 unwind.personality_routine. */ 2999 if (frag->fr_offset) 3000 { 3001 if (md.flags & EF_IA_64_ABI64) 3002 flag_value = (bfd_vma) 3 << 32; 3003 else 3004 /* 32-bit unwind info block. */ 3005 flag_value = (bfd_vma) 0x1003 << 32; 3006 } 3007 else 3008 flag_value = 0; 3009 3010 md_number_to_chars (frag->fr_literal, 3011 (((bfd_vma) 1 << 48) /* Version. */ 3012 | flag_value /* U & E handler flags. */ 3013 | (len / md.pointer_size)), /* Length. */ 3014 8); 3015 3016 /* Skip the header. */ 3017 vbyte_mem_ptr = frag->fr_literal + 8; 3018 process_unw_records (list, output_vbyte_mem); 3019 3020 /* Fill the padding bytes with zeros. */ 3021 if (pad != 0) 3022 md_number_to_chars (frag->fr_literal + len + 8 - md.pointer_size + pad, 0, 3023 md.pointer_size - pad); 3024 /* Fill the unwind personality with zeros. */ 3025 if (frag->fr_offset) 3026 md_number_to_chars (frag->fr_literal + size - md.pointer_size, 0, 3027 md.pointer_size); 3028 3029 frag->fr_fix += size; 3030 frag->fr_type = rs_fill; 3031 frag->fr_var = 0; 3032 frag->fr_offset = 0; 3033} 3034 3035static int 3036parse_predicate_and_operand (expressionS *e, unsigned *qp, const char *po) 3037{ 3038 int sep = parse_operand_and_eval (e, ','); 3039 3040 *qp = e->X_add_number - REG_P; 3041 if (e->X_op != O_register || *qp > 63) 3042 { 3043 as_bad (_("First operand to .%s must be a predicate"), po); 3044 *qp = 0; 3045 } 3046 else if (*qp == 0) 3047 as_warn (_("Pointless use of p0 as first operand to .%s"), po); 3048 if (sep == ',') 3049 sep = parse_operand_and_eval (e, ','); 3050 else 3051 e->X_op = O_absent; 3052 return sep; 3053} 3054 3055static void 3056convert_expr_to_ab_reg (const expressionS *e, 3057 unsigned int *ab, 3058 unsigned int *regp, 3059 const char *po, 3060 int n) 3061{ 3062 unsigned int reg = e->X_add_number; 3063 3064 *ab = *regp = 0; /* Anything valid is good here. */ 3065 3066 if (e->X_op != O_register) 3067 reg = REG_GR; /* Anything invalid is good here. */ 3068 3069 if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) 3070 { 3071 *ab = 0; 3072 *regp = reg - REG_GR; 3073 } 3074 else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) 3075 || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) 3076 { 3077 *ab = 1; 3078 *regp = reg - REG_FR; 3079 } 3080 else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) 3081 { 3082 *ab = 2; 3083 *regp = reg - REG_BR; 3084 } 3085 else 3086 { 3087 *ab = 3; 3088 switch (reg) 3089 { 3090 case REG_PR: *regp = 0; break; 3091 case REG_PSP: *regp = 1; break; 3092 case REG_PRIUNAT: *regp = 2; break; 3093 case REG_BR + 0: *regp = 3; break; 3094 case REG_AR + AR_BSP: *regp = 4; break; 3095 case REG_AR + AR_BSPSTORE: *regp = 5; break; 3096 case REG_AR + AR_RNAT: *regp = 6; break; 3097 case REG_AR + AR_UNAT: *regp = 7; break; 3098 case REG_AR + AR_FPSR: *regp = 8; break; 3099 case REG_AR + AR_PFS: *regp = 9; break; 3100 case REG_AR + AR_LC: *regp = 10; break; 3101 3102 default: 3103 as_bad (_("Operand %d to .%s must be a preserved register"), n, po); 3104 break; 3105 } 3106 } 3107} 3108 3109static void 3110convert_expr_to_xy_reg (const expressionS *e, 3111 unsigned int *xy, 3112 unsigned int *regp, 3113 const char *po, 3114 int n) 3115{ 3116 unsigned int reg = e->X_add_number; 3117 3118 *xy = *regp = 0; /* Anything valid is good here. */ 3119 3120 if (e->X_op != O_register) 3121 reg = REG_GR; /* Anything invalid is good here. */ 3122 3123 if (reg >= (REG_GR + 1) && reg <= (REG_GR + 127)) 3124 { 3125 *xy = 0; 3126 *regp = reg - REG_GR; 3127 } 3128 else if (reg >= (REG_FR + 2) && reg <= (REG_FR + 127)) 3129 { 3130 *xy = 1; 3131 *regp = reg - REG_FR; 3132 } 3133 else if (reg >= REG_BR && reg <= (REG_BR + 7)) 3134 { 3135 *xy = 2; 3136 *regp = reg - REG_BR; 3137 } 3138 else 3139 as_bad (_("Operand %d to .%s must be a writable register"), n, po); 3140} 3141 3142static void 3143dot_align (int arg) 3144{ 3145 /* The current frag is an alignment frag. */ 3146 align_frag = frag_now; 3147 s_align_bytes (arg); 3148} 3149 3150static void 3151dot_radix (int dummy ATTRIBUTE_UNUSED) 3152{ 3153 char *radix; 3154 int ch; 3155 3156 SKIP_WHITESPACE (); 3157 3158 if (is_it_end_of_statement ()) 3159 return; 3160 ch = get_symbol_name (&radix); 3161 ia64_canonicalize_symbol_name (radix); 3162 if (strcasecmp (radix, "C")) 3163 as_bad (_("Radix `%s' unsupported or invalid"), radix); 3164 (void) restore_line_pointer (ch); 3165 demand_empty_rest_of_line (); 3166} 3167 3168/* Helper function for .loc directives. If the assembler is not generating 3169 line number info, then we need to remember which instructions have a .loc 3170 directive, and only call dwarf2_gen_line_info for those instructions. */ 3171 3172static void 3173dot_loc (int x) 3174{ 3175 CURR_SLOT.loc_directive_seen = 1; 3176 dwarf2_directive_loc (x); 3177} 3178 3179/* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ 3180static void 3181dot_special_section (int which) 3182{ 3183 set_section ((char *) special_section_name[which]); 3184} 3185 3186/* Return -1 for warning and 0 for error. */ 3187 3188static int 3189unwind_diagnostic (const char * region, const char *directive) 3190{ 3191 if (md.unwind_check == unwind_check_warning) 3192 { 3193 as_warn (_(".%s outside of %s"), directive, region); 3194 return -1; 3195 } 3196 else 3197 { 3198 as_bad (_(".%s outside of %s"), directive, region); 3199 ignore_rest_of_line (); 3200 return 0; 3201 } 3202} 3203 3204/* Return 1 if a directive is in a procedure, -1 if a directive isn't in 3205 a procedure but the unwind directive check is set to warning, 0 if 3206 a directive isn't in a procedure and the unwind directive check is set 3207 to error. */ 3208 3209static int 3210in_procedure (const char *directive) 3211{ 3212 if (unwind.proc_pending.sym 3213 && (!unwind.saved_text_seg || strcmp (directive, "endp") == 0)) 3214 return 1; 3215 return unwind_diagnostic ("procedure", directive); 3216} 3217 3218/* Return 1 if a directive is in a prologue, -1 if a directive isn't in 3219 a prologue but the unwind directive check is set to warning, 0 if 3220 a directive isn't in a prologue and the unwind directive check is set 3221 to error. */ 3222 3223static int 3224in_prologue (const char *directive) 3225{ 3226 int in = in_procedure (directive); 3227 3228 if (in > 0 && !unwind.prologue) 3229 in = unwind_diagnostic ("prologue", directive); 3230 check_pending_save (); 3231 return in; 3232} 3233 3234/* Return 1 if a directive is in a body, -1 if a directive isn't in 3235 a body but the unwind directive check is set to warning, 0 if 3236 a directive isn't in a body and the unwind directive check is set 3237 to error. */ 3238 3239static int 3240in_body (const char *directive) 3241{ 3242 int in = in_procedure (directive); 3243 3244 if (in > 0 && !unwind.body) 3245 in = unwind_diagnostic ("body region", directive); 3246 return in; 3247} 3248 3249static void 3250add_unwind_entry (unw_rec_list *ptr, int sep) 3251{ 3252 if (ptr) 3253 { 3254 if (unwind.tail) 3255 unwind.tail->next = ptr; 3256 else 3257 unwind.list = ptr; 3258 unwind.tail = ptr; 3259 3260 /* The current entry can in fact be a chain of unwind entries. */ 3261 if (unwind.current_entry == NULL) 3262 unwind.current_entry = ptr; 3263 } 3264 3265 /* The current entry can in fact be a chain of unwind entries. */ 3266 if (unwind.current_entry == NULL) 3267 unwind.current_entry = ptr; 3268 3269 if (sep == ',') 3270 { 3271 char *name; 3272 /* Parse a tag permitted for the current directive. */ 3273 int ch; 3274 3275 SKIP_WHITESPACE (); 3276 ch = get_symbol_name (&name); 3277 /* FIXME: For now, just issue a warning that this isn't implemented. */ 3278 { 3279 static int warned; 3280 3281 if (!warned) 3282 { 3283 warned = 1; 3284 as_warn (_("Tags on unwind pseudo-ops aren't supported, yet")); 3285 } 3286 } 3287 (void) restore_line_pointer (ch); 3288 } 3289 if (sep != NOT_A_CHAR) 3290 demand_empty_rest_of_line (); 3291} 3292 3293static void 3294dot_fframe (int dummy ATTRIBUTE_UNUSED) 3295{ 3296 expressionS e; 3297 int sep; 3298 3299 if (!in_prologue ("fframe")) 3300 return; 3301 3302 sep = parse_operand_and_eval (&e, ','); 3303 3304 if (e.X_op != O_constant) 3305 { 3306 as_bad (_("First operand to .fframe must be a constant")); 3307 e.X_add_number = 0; 3308 } 3309 add_unwind_entry (output_mem_stack_f (e.X_add_number), sep); 3310} 3311 3312static void 3313dot_vframe (int dummy ATTRIBUTE_UNUSED) 3314{ 3315 expressionS e; 3316 unsigned reg; 3317 int sep; 3318 3319 if (!in_prologue ("vframe")) 3320 return; 3321 3322 sep = parse_operand_and_eval (&e, ','); 3323 reg = e.X_add_number - REG_GR; 3324 if (e.X_op != O_register || reg > 127) 3325 { 3326 as_bad (_("First operand to .vframe must be a general register")); 3327 reg = 0; 3328 } 3329 add_unwind_entry (output_mem_stack_v (), sep); 3330 if (! (unwind.prologue_mask & 2)) 3331 add_unwind_entry (output_psp_gr (reg), NOT_A_CHAR); 3332 else if (reg != unwind.prologue_gr 3333 + (unsigned) popcount (unwind.prologue_mask & -(2 << 1))) 3334 as_warn (_("Operand of .vframe contradicts .prologue")); 3335} 3336 3337static void 3338dot_vframesp (int psp) 3339{ 3340 expressionS e; 3341 int sep; 3342 3343 if (psp) 3344 as_warn (_(".vframepsp is meaningless, assuming .vframesp was meant")); 3345 3346 if (!in_prologue ("vframesp")) 3347 return; 3348 3349 sep = parse_operand_and_eval (&e, ','); 3350 if (e.X_op != O_constant) 3351 { 3352 as_bad (_("Operand to .vframesp must be a constant (sp-relative offset)")); 3353 e.X_add_number = 0; 3354 } 3355 add_unwind_entry (output_mem_stack_v (), sep); 3356 add_unwind_entry (output_psp_sprel (e.X_add_number), NOT_A_CHAR); 3357} 3358 3359static void 3360dot_save (int dummy ATTRIBUTE_UNUSED) 3361{ 3362 expressionS e1, e2; 3363 unsigned reg1, reg2; 3364 int sep; 3365 3366 if (!in_prologue ("save")) 3367 return; 3368 3369 sep = parse_operand_and_eval (&e1, ','); 3370 if (sep == ',') 3371 sep = parse_operand_and_eval (&e2, ','); 3372 else 3373 e2.X_op = O_absent; 3374 3375 reg1 = e1.X_add_number; 3376 /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3377 if (e1.X_op != O_register) 3378 { 3379 as_bad (_("First operand to .save not a register")); 3380 reg1 = REG_PR; /* Anything valid is good here. */ 3381 } 3382 reg2 = e2.X_add_number - REG_GR; 3383 if (e2.X_op != O_register || reg2 > 127) 3384 { 3385 as_bad (_("Second operand to .save not a valid register")); 3386 reg2 = 0; 3387 } 3388 switch (reg1) 3389 { 3390 case REG_AR + AR_BSP: 3391 add_unwind_entry (output_bsp_when (), sep); 3392 add_unwind_entry (output_bsp_gr (reg2), NOT_A_CHAR); 3393 break; 3394 case REG_AR + AR_BSPSTORE: 3395 add_unwind_entry (output_bspstore_when (), sep); 3396 add_unwind_entry (output_bspstore_gr (reg2), NOT_A_CHAR); 3397 break; 3398 case REG_AR + AR_RNAT: 3399 add_unwind_entry (output_rnat_when (), sep); 3400 add_unwind_entry (output_rnat_gr (reg2), NOT_A_CHAR); 3401 break; 3402 case REG_AR + AR_UNAT: 3403 add_unwind_entry (output_unat_when (), sep); 3404 add_unwind_entry (output_unat_gr (reg2), NOT_A_CHAR); 3405 break; 3406 case REG_AR + AR_FPSR: 3407 add_unwind_entry (output_fpsr_when (), sep); 3408 add_unwind_entry (output_fpsr_gr (reg2), NOT_A_CHAR); 3409 break; 3410 case REG_AR + AR_PFS: 3411 add_unwind_entry (output_pfs_when (), sep); 3412 if (! (unwind.prologue_mask & 4)) 3413 add_unwind_entry (output_pfs_gr (reg2), NOT_A_CHAR); 3414 else if (reg2 != unwind.prologue_gr 3415 + (unsigned) popcount (unwind.prologue_mask & -(4 << 1))) 3416 as_warn (_("Second operand of .save contradicts .prologue")); 3417 break; 3418 case REG_AR + AR_LC: 3419 add_unwind_entry (output_lc_when (), sep); 3420 add_unwind_entry (output_lc_gr (reg2), NOT_A_CHAR); 3421 break; 3422 case REG_BR: 3423 add_unwind_entry (output_rp_when (), sep); 3424 if (! (unwind.prologue_mask & 8)) 3425 add_unwind_entry (output_rp_gr (reg2), NOT_A_CHAR); 3426 else if (reg2 != unwind.prologue_gr) 3427 as_warn (_("Second operand of .save contradicts .prologue")); 3428 break; 3429 case REG_PR: 3430 add_unwind_entry (output_preds_when (), sep); 3431 if (! (unwind.prologue_mask & 1)) 3432 add_unwind_entry (output_preds_gr (reg2), NOT_A_CHAR); 3433 else if (reg2 != unwind.prologue_gr 3434 + (unsigned) popcount (unwind.prologue_mask & -(1 << 1))) 3435 as_warn (_("Second operand of .save contradicts .prologue")); 3436 break; 3437 case REG_PRIUNAT: 3438 add_unwind_entry (output_priunat_when_gr (), sep); 3439 add_unwind_entry (output_priunat_gr (reg2), NOT_A_CHAR); 3440 break; 3441 default: 3442 as_bad (_("First operand to .save not a valid register")); 3443 add_unwind_entry (NULL, sep); 3444 break; 3445 } 3446} 3447 3448static void 3449dot_restore (int dummy ATTRIBUTE_UNUSED) 3450{ 3451 expressionS e1; 3452 unsigned long ecount; /* # of _additional_ regions to pop */ 3453 int sep; 3454 3455 if (!in_body ("restore")) 3456 return; 3457 3458 sep = parse_operand_and_eval (&e1, ','); 3459 if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) 3460 as_bad (_("First operand to .restore must be stack pointer (sp)")); 3461 3462 if (sep == ',') 3463 { 3464 expressionS e2; 3465 3466 sep = parse_operand_and_eval (&e2, ','); 3467 if (e2.X_op != O_constant || e2.X_add_number < 0) 3468 { 3469 as_bad (_("Second operand to .restore must be a constant >= 0")); 3470 e2.X_add_number = 0; 3471 } 3472 ecount = e2.X_add_number; 3473 } 3474 else 3475 ecount = unwind.prologue_count - 1; 3476 3477 if (ecount >= unwind.prologue_count) 3478 { 3479 as_bad (_("Epilogue count of %lu exceeds number of nested prologues (%u)"), 3480 ecount + 1, unwind.prologue_count); 3481 ecount = 0; 3482 } 3483 3484 add_unwind_entry (output_epilogue (ecount), sep); 3485 3486 if (ecount < unwind.prologue_count) 3487 unwind.prologue_count -= ecount + 1; 3488 else 3489 unwind.prologue_count = 0; 3490} 3491 3492static void 3493dot_restorereg (int pred) 3494{ 3495 unsigned int qp, ab, reg; 3496 expressionS e; 3497 int sep; 3498 const char * const po = pred ? "restorereg.p" : "restorereg"; 3499 3500 if (!in_procedure (po)) 3501 return; 3502 3503 if (pred) 3504 sep = parse_predicate_and_operand (&e, &qp, po); 3505 else 3506 { 3507 sep = parse_operand_and_eval (&e, ','); 3508 qp = 0; 3509 } 3510 convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); 3511 3512 add_unwind_entry (output_spill_reg (ab, reg, 0, 0, qp), sep); 3513} 3514 3515static const char *special_linkonce_name[] = 3516 { 3517 ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." 3518 }; 3519 3520static void 3521start_unwind_section (const segT text_seg, int sec_index) 3522{ 3523 /* 3524 Use a slightly ugly scheme to derive the unwind section names from 3525 the text section name: 3526 3527 text sect. unwind table sect. 3528 name: name: comments: 3529 ---------- ----------------- -------------------------------- 3530 .text .IA_64.unwind 3531 .text.foo .IA_64.unwind.text.foo 3532 .foo .IA_64.unwind.foo 3533 .gnu.linkonce.t.foo 3534 .gnu.linkonce.ia64unw.foo 3535 _info .IA_64.unwind_info gas issues error message (ditto) 3536 _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) 3537 3538 This mapping is done so that: 3539 3540 (a) An object file with unwind info only in .text will use 3541 unwind section names .IA_64.unwind and .IA_64.unwind_info. 3542 This follows the letter of the ABI and also ensures backwards 3543 compatibility with older toolchains. 3544 3545 (b) An object file with unwind info in multiple text sections 3546 will use separate unwind sections for each text section. 3547 This allows us to properly set the "sh_info" and "sh_link" 3548 fields in SHT_IA_64_UNWIND as required by the ABI and also 3549 lets GNU ld support programs with multiple segments 3550 containing unwind info (as might be the case for certain 3551 embedded applications). 3552 3553 (c) An error is issued if there would be a name clash. 3554 */ 3555 3556 const char *text_name, *sec_text_name; 3557 char *sec_name; 3558 const char *prefix = special_section_name [sec_index]; 3559 const char *suffix; 3560 3561 sec_text_name = segment_name (text_seg); 3562 text_name = sec_text_name; 3563 if (strncmp (text_name, "_info", 5) == 0) 3564 { 3565 as_bad (_("Illegal section name `%s' (causes unwind section name clash)"), 3566 text_name); 3567 ignore_rest_of_line (); 3568 return; 3569 } 3570 if (strcmp (text_name, ".text") == 0) 3571 text_name = ""; 3572 3573 /* Build the unwind section name by appending the (possibly stripped) 3574 text section name to the unwind prefix. */ 3575 suffix = text_name; 3576 if (strncmp (text_name, ".gnu.linkonce.t.", 3577 sizeof (".gnu.linkonce.t.") - 1) == 0) 3578 { 3579 prefix = special_linkonce_name [sec_index - SPECIAL_SECTION_UNWIND]; 3580 suffix += sizeof (".gnu.linkonce.t.") - 1; 3581 } 3582 3583 sec_name = concat (prefix, suffix, NULL); 3584 3585 /* Handle COMDAT group. */ 3586 if ((text_seg->flags & SEC_LINK_ONCE) != 0 3587 && (elf_section_flags (text_seg) & SHF_GROUP) != 0) 3588 { 3589 char *section; 3590 const char *group_name = elf_group_name (text_seg); 3591 3592 if (group_name == NULL) 3593 { 3594 as_bad (_("Group section `%s' has no group signature"), 3595 sec_text_name); 3596 ignore_rest_of_line (); 3597 free (sec_name); 3598 return; 3599 } 3600 3601 /* We have to construct a fake section directive. */ 3602 section = concat (sec_name, ",\"aG\",@progbits,", group_name, ",comdat", NULL); 3603 set_section (section); 3604 free (section); 3605 } 3606 else 3607 { 3608 set_section (sec_name); 3609 bfd_set_section_flags (now_seg, SEC_LOAD | SEC_ALLOC | SEC_READONLY); 3610 } 3611 3612 elf_linked_to_section (now_seg) = text_seg; 3613 free (sec_name); 3614} 3615 3616static void 3617generate_unwind_image (const segT text_seg) 3618{ 3619 int size, pad; 3620 unw_rec_list *list; 3621 3622 /* Mark the end of the unwind info, so that we can compute the size of the 3623 last unwind region. */ 3624 add_unwind_entry (output_endp (), NOT_A_CHAR); 3625 3626 /* Force out pending instructions, to make sure all unwind records have 3627 a valid slot_number field. */ 3628 ia64_flush_insns (); 3629 3630 /* Generate the unwind record. */ 3631 list = optimize_unw_records (unwind.list); 3632 fixup_unw_records (list, 1); 3633 size = calc_record_size (list); 3634 3635 if (size > 0 || unwind.force_unwind_entry) 3636 { 3637 unwind.force_unwind_entry = 0; 3638 /* pad to pointer-size boundary. */ 3639 pad = size % md.pointer_size; 3640 if (pad != 0) 3641 size += md.pointer_size - pad; 3642 /* Add 8 for the header. */ 3643 size += 8; 3644 /* Add a pointer for the personality offset. */ 3645 if (unwind.personality_routine) 3646 size += md.pointer_size; 3647 } 3648 3649 /* If there are unwind records, switch sections, and output the info. */ 3650 if (size != 0) 3651 { 3652 expressionS exp; 3653 bfd_reloc_code_real_type reloc; 3654 3655 start_unwind_section (text_seg, SPECIAL_SECTION_UNWIND_INFO); 3656 3657 /* Make sure the section has 4 byte alignment for ILP32 and 3658 8 byte alignment for LP64. */ 3659 frag_align (md.pointer_size_shift, 0, 0); 3660 record_alignment (now_seg, md.pointer_size_shift); 3661 3662 /* Set expression which points to start of unwind descriptor area. */ 3663 unwind.info = expr_build_dot (); 3664 3665 frag_var (rs_machine_dependent, size, size, 0, 0, 3666 (offsetT) (long) unwind.personality_routine, 3667 (char *) list); 3668 3669 /* Add the personality address to the image. */ 3670 if (unwind.personality_routine != 0) 3671 { 3672 exp.X_op = O_symbol; 3673 exp.X_add_symbol = unwind.personality_routine; 3674 exp.X_add_number = 0; 3675 3676 if (md.flags & EF_IA_64_BE) 3677 { 3678 if (md.flags & EF_IA_64_ABI64) 3679 reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB; 3680 else 3681 reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB; 3682 } 3683 else 3684 { 3685 if (md.flags & EF_IA_64_ABI64) 3686 reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB; 3687 else 3688 reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB; 3689 } 3690 3691 fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, 3692 md.pointer_size, &exp, 0, reloc); 3693 unwind.personality_routine = 0; 3694 } 3695 } 3696 3697 free_saved_prologue_counts (); 3698 unwind.list = unwind.tail = unwind.current_entry = NULL; 3699} 3700 3701static void 3702dot_handlerdata (int dummy ATTRIBUTE_UNUSED) 3703{ 3704 if (!in_procedure ("handlerdata")) 3705 return; 3706 unwind.force_unwind_entry = 1; 3707 3708 /* Remember which segment we're in so we can switch back after .endp */ 3709 unwind.saved_text_seg = now_seg; 3710 unwind.saved_text_subseg = now_subseg; 3711 3712 /* Generate unwind info into unwind-info section and then leave that 3713 section as the currently active one so dataXX directives go into 3714 the language specific data area of the unwind info block. */ 3715 generate_unwind_image (now_seg); 3716 demand_empty_rest_of_line (); 3717} 3718 3719static void 3720dot_unwentry (int dummy ATTRIBUTE_UNUSED) 3721{ 3722 if (!in_procedure ("unwentry")) 3723 return; 3724 unwind.force_unwind_entry = 1; 3725 demand_empty_rest_of_line (); 3726} 3727 3728static void 3729dot_altrp (int dummy ATTRIBUTE_UNUSED) 3730{ 3731 expressionS e; 3732 unsigned reg; 3733 3734 if (!in_prologue ("altrp")) 3735 return; 3736 3737 parse_operand_and_eval (&e, 0); 3738 reg = e.X_add_number - REG_BR; 3739 if (e.X_op != O_register || reg > 7) 3740 { 3741 as_bad (_("First operand to .altrp not a valid branch register")); 3742 reg = 0; 3743 } 3744 add_unwind_entry (output_rp_br (reg), 0); 3745} 3746 3747static void 3748dot_savemem (int psprel) 3749{ 3750 expressionS e1, e2; 3751 int sep; 3752 int reg1, val; 3753 const char * const po = psprel ? "savepsp" : "savesp"; 3754 3755 if (!in_prologue (po)) 3756 return; 3757 3758 sep = parse_operand_and_eval (&e1, ','); 3759 if (sep == ',') 3760 sep = parse_operand_and_eval (&e2, ','); 3761 else 3762 e2.X_op = O_absent; 3763 3764 reg1 = e1.X_add_number; 3765 val = e2.X_add_number; 3766 3767 /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */ 3768 if (e1.X_op != O_register) 3769 { 3770 as_bad (_("First operand to .%s not a register"), po); 3771 reg1 = REG_PR; /* Anything valid is good here. */ 3772 } 3773 if (e2.X_op != O_constant) 3774 { 3775 as_bad (_("Second operand to .%s not a constant"), po); 3776 val = 0; 3777 } 3778 3779 switch (reg1) 3780 { 3781 case REG_AR + AR_BSP: 3782 add_unwind_entry (output_bsp_when (), sep); 3783 add_unwind_entry ((psprel 3784 ? output_bsp_psprel 3785 : output_bsp_sprel) (val), NOT_A_CHAR); 3786 break; 3787 case REG_AR + AR_BSPSTORE: 3788 add_unwind_entry (output_bspstore_when (), sep); 3789 add_unwind_entry ((psprel 3790 ? output_bspstore_psprel 3791 : output_bspstore_sprel) (val), NOT_A_CHAR); 3792 break; 3793 case REG_AR + AR_RNAT: 3794 add_unwind_entry (output_rnat_when (), sep); 3795 add_unwind_entry ((psprel 3796 ? output_rnat_psprel 3797 : output_rnat_sprel) (val), NOT_A_CHAR); 3798 break; 3799 case REG_AR + AR_UNAT: 3800 add_unwind_entry (output_unat_when (), sep); 3801 add_unwind_entry ((psprel 3802 ? output_unat_psprel 3803 : output_unat_sprel) (val), NOT_A_CHAR); 3804 break; 3805 case REG_AR + AR_FPSR: 3806 add_unwind_entry (output_fpsr_when (), sep); 3807 add_unwind_entry ((psprel 3808 ? output_fpsr_psprel 3809 : output_fpsr_sprel) (val), NOT_A_CHAR); 3810 break; 3811 case REG_AR + AR_PFS: 3812 add_unwind_entry (output_pfs_when (), sep); 3813 add_unwind_entry ((psprel 3814 ? output_pfs_psprel 3815 : output_pfs_sprel) (val), NOT_A_CHAR); 3816 break; 3817 case REG_AR + AR_LC: 3818 add_unwind_entry (output_lc_when (), sep); 3819 add_unwind_entry ((psprel 3820 ? output_lc_psprel 3821 : output_lc_sprel) (val), NOT_A_CHAR); 3822 break; 3823 case REG_BR: 3824 add_unwind_entry (output_rp_when (), sep); 3825 add_unwind_entry ((psprel 3826 ? output_rp_psprel 3827 : output_rp_sprel) (val), NOT_A_CHAR); 3828 break; 3829 case REG_PR: 3830 add_unwind_entry (output_preds_when (), sep); 3831 add_unwind_entry ((psprel 3832 ? output_preds_psprel 3833 : output_preds_sprel) (val), NOT_A_CHAR); 3834 break; 3835 case REG_PRIUNAT: 3836 add_unwind_entry (output_priunat_when_mem (), sep); 3837 add_unwind_entry ((psprel 3838 ? output_priunat_psprel 3839 : output_priunat_sprel) (val), NOT_A_CHAR); 3840 break; 3841 default: 3842 as_bad (_("First operand to .%s not a valid register"), po); 3843 add_unwind_entry (NULL, sep); 3844 break; 3845 } 3846} 3847 3848static void 3849dot_saveg (int dummy ATTRIBUTE_UNUSED) 3850{ 3851 expressionS e; 3852 unsigned grmask; 3853 int sep; 3854 3855 if (!in_prologue ("save.g")) 3856 return; 3857 3858 sep = parse_operand_and_eval (&e, ','); 3859 3860 grmask = e.X_add_number; 3861 if (e.X_op != O_constant 3862 || e.X_add_number <= 0 3863 || e.X_add_number > 0xf) 3864 { 3865 as_bad (_("First operand to .save.g must be a positive 4-bit constant")); 3866 grmask = 0; 3867 } 3868 3869 if (sep == ',') 3870 { 3871 unsigned reg; 3872 int n = popcount (grmask); 3873 3874 parse_operand_and_eval (&e, 0); 3875 reg = e.X_add_number - REG_GR; 3876 if (e.X_op != O_register || reg > 127) 3877 { 3878 as_bad (_("Second operand to .save.g must be a general register")); 3879 reg = 0; 3880 } 3881 else if (reg > 128U - n) 3882 { 3883 as_bad (_("Second operand to .save.g must be the first of %d general registers"), n); 3884 reg = 0; 3885 } 3886 add_unwind_entry (output_gr_gr (grmask, reg), 0); 3887 } 3888 else 3889 add_unwind_entry (output_gr_mem (grmask), 0); 3890} 3891 3892static void 3893dot_savef (int dummy ATTRIBUTE_UNUSED) 3894{ 3895 expressionS e; 3896 3897 if (!in_prologue ("save.f")) 3898 return; 3899 3900 parse_operand_and_eval (&e, 0); 3901 3902 if (e.X_op != O_constant 3903 || e.X_add_number <= 0 3904 || e.X_add_number > 0xfffff) 3905 { 3906 as_bad (_("Operand to .save.f must be a positive 20-bit constant")); 3907 e.X_add_number = 0; 3908 } 3909 add_unwind_entry (output_fr_mem (e.X_add_number), 0); 3910} 3911 3912static void 3913dot_saveb (int dummy ATTRIBUTE_UNUSED) 3914{ 3915 expressionS e; 3916 unsigned brmask; 3917 int sep; 3918 3919 if (!in_prologue ("save.b")) 3920 return; 3921 3922 sep = parse_operand_and_eval (&e, ','); 3923 3924 brmask = e.X_add_number; 3925 if (e.X_op != O_constant 3926 || e.X_add_number <= 0 3927 || e.X_add_number > 0x1f) 3928 { 3929 as_bad (_("First operand to .save.b must be a positive 5-bit constant")); 3930 brmask = 0; 3931 } 3932 3933 if (sep == ',') 3934 { 3935 unsigned reg; 3936 int n = popcount (brmask); 3937 3938 parse_operand_and_eval (&e, 0); 3939 reg = e.X_add_number - REG_GR; 3940 if (e.X_op != O_register || reg > 127) 3941 { 3942 as_bad (_("Second operand to .save.b must be a general register")); 3943 reg = 0; 3944 } 3945 else if (reg > 128U - n) 3946 { 3947 as_bad (_("Second operand to .save.b must be the first of %d general registers"), n); 3948 reg = 0; 3949 } 3950 add_unwind_entry (output_br_gr (brmask, reg), 0); 3951 } 3952 else 3953 add_unwind_entry (output_br_mem (brmask), 0); 3954} 3955 3956static void 3957dot_savegf (int dummy ATTRIBUTE_UNUSED) 3958{ 3959 expressionS e1, e2; 3960 3961 if (!in_prologue ("save.gf")) 3962 return; 3963 3964 if (parse_operand_and_eval (&e1, ',') == ',') 3965 parse_operand_and_eval (&e2, 0); 3966 else 3967 e2.X_op = O_absent; 3968 3969 if (e1.X_op != O_constant 3970 || e1.X_add_number < 0 3971 || e1.X_add_number > 0xf) 3972 { 3973 as_bad (_("First operand to .save.gf must be a non-negative 4-bit constant")); 3974 e1.X_op = O_absent; 3975 e1.X_add_number = 0; 3976 } 3977 if (e2.X_op != O_constant 3978 || e2.X_add_number < 0 3979 || e2.X_add_number > 0xfffff) 3980 { 3981 as_bad (_("Second operand to .save.gf must be a non-negative 20-bit constant")); 3982 e2.X_op = O_absent; 3983 e2.X_add_number = 0; 3984 } 3985 if (e1.X_op == O_constant 3986 && e2.X_op == O_constant 3987 && e1.X_add_number == 0 3988 && e2.X_add_number == 0) 3989 as_bad (_("Operands to .save.gf may not be both zero")); 3990 3991 add_unwind_entry (output_frgr_mem (e1.X_add_number, e2.X_add_number), 0); 3992} 3993 3994static void 3995dot_spill (int dummy ATTRIBUTE_UNUSED) 3996{ 3997 expressionS e; 3998 3999 if (!in_prologue ("spill")) 4000 return; 4001 4002 parse_operand_and_eval (&e, 0); 4003 4004 if (e.X_op != O_constant) 4005 { 4006 as_bad (_("Operand to .spill must be a constant")); 4007 e.X_add_number = 0; 4008 } 4009 add_unwind_entry (output_spill_base (e.X_add_number), 0); 4010} 4011 4012static void 4013dot_spillreg (int pred) 4014{ 4015 int sep; 4016 unsigned int qp, ab, xy, reg, treg; 4017 expressionS e; 4018 const char * const po = pred ? "spillreg.p" : "spillreg"; 4019 4020 if (!in_procedure (po)) 4021 return; 4022 4023 if (pred) 4024 sep = parse_predicate_and_operand (&e, &qp, po); 4025 else 4026 { 4027 sep = parse_operand_and_eval (&e, ','); 4028 qp = 0; 4029 } 4030 convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); 4031 4032 if (sep == ',') 4033 sep = parse_operand_and_eval (&e, ','); 4034 else 4035 e.X_op = O_absent; 4036 convert_expr_to_xy_reg (&e, &xy, &treg, po, 2 + pred); 4037 4038 add_unwind_entry (output_spill_reg (ab, reg, treg, xy, qp), sep); 4039} 4040 4041static void 4042dot_spillmem (int psprel) 4043{ 4044 expressionS e; 4045 int pred = (psprel < 0), sep; 4046 unsigned int qp, ab, reg; 4047 const char * po; 4048 4049 if (pred) 4050 { 4051 psprel = ~psprel; 4052 po = psprel ? "spillpsp.p" : "spillsp.p"; 4053 } 4054 else 4055 po = psprel ? "spillpsp" : "spillsp"; 4056 4057 if (!in_procedure (po)) 4058 return; 4059 4060 if (pred) 4061 sep = parse_predicate_and_operand (&e, &qp, po); 4062 else 4063 { 4064 sep = parse_operand_and_eval (&e, ','); 4065 qp = 0; 4066 } 4067 convert_expr_to_ab_reg (&e, &ab, ®, po, 1 + pred); 4068 4069 if (sep == ',') 4070 sep = parse_operand_and_eval (&e, ','); 4071 else 4072 e.X_op = O_absent; 4073 if (e.X_op != O_constant) 4074 { 4075 as_bad (_("Operand %d to .%s must be a constant"), 2 + pred, po); 4076 e.X_add_number = 0; 4077 } 4078 4079 if (psprel) 4080 add_unwind_entry (output_spill_psprel (ab, reg, e.X_add_number, qp), sep); 4081 else 4082 add_unwind_entry (output_spill_sprel (ab, reg, e.X_add_number, qp), sep); 4083} 4084 4085static unsigned int 4086get_saved_prologue_count (unsigned long lbl) 4087{ 4088 label_prologue_count *lpc = unwind.saved_prologue_counts; 4089 4090 while (lpc != NULL && lpc->label_number != lbl) 4091 lpc = lpc->next; 4092 4093 if (lpc != NULL) 4094 return lpc->prologue_count; 4095 4096 as_bad (_("Missing .label_state %ld"), lbl); 4097 return 1; 4098} 4099 4100static void 4101save_prologue_count (unsigned long lbl, unsigned int count) 4102{ 4103 label_prologue_count *lpc = unwind.saved_prologue_counts; 4104 4105 while (lpc != NULL && lpc->label_number != lbl) 4106 lpc = lpc->next; 4107 4108 if (lpc != NULL) 4109 lpc->prologue_count = count; 4110 else 4111 { 4112 label_prologue_count *new_lpc = XNEW (label_prologue_count); 4113 4114 new_lpc->next = unwind.saved_prologue_counts; 4115 new_lpc->label_number = lbl; 4116 new_lpc->prologue_count = count; 4117 unwind.saved_prologue_counts = new_lpc; 4118 } 4119} 4120 4121static void 4122free_saved_prologue_counts (void) 4123{ 4124 label_prologue_count *lpc = unwind.saved_prologue_counts; 4125 label_prologue_count *next; 4126 4127 while (lpc != NULL) 4128 { 4129 next = lpc->next; 4130 free (lpc); 4131 lpc = next; 4132 } 4133 4134 unwind.saved_prologue_counts = NULL; 4135} 4136 4137static void 4138dot_label_state (int dummy ATTRIBUTE_UNUSED) 4139{ 4140 expressionS e; 4141 4142 if (!in_body ("label_state")) 4143 return; 4144 4145 parse_operand_and_eval (&e, 0); 4146 if (e.X_op == O_constant) 4147 save_prologue_count (e.X_add_number, unwind.prologue_count); 4148 else 4149 { 4150 as_bad (_("Operand to .label_state must be a constant")); 4151 e.X_add_number = 0; 4152 } 4153 add_unwind_entry (output_label_state (e.X_add_number), 0); 4154} 4155 4156static void 4157dot_copy_state (int dummy ATTRIBUTE_UNUSED) 4158{ 4159 expressionS e; 4160 4161 if (!in_body ("copy_state")) 4162 return; 4163 4164 parse_operand_and_eval (&e, 0); 4165 if (e.X_op == O_constant) 4166 unwind.prologue_count = get_saved_prologue_count (e.X_add_number); 4167 else 4168 { 4169 as_bad (_("Operand to .copy_state must be a constant")); 4170 e.X_add_number = 0; 4171 } 4172 add_unwind_entry (output_copy_state (e.X_add_number), 0); 4173} 4174 4175static void 4176dot_unwabi (int dummy ATTRIBUTE_UNUSED) 4177{ 4178 expressionS e1, e2; 4179 unsigned char sep; 4180 4181 if (!in_prologue ("unwabi")) 4182 return; 4183 4184 sep = parse_operand_and_eval (&e1, ','); 4185 if (sep == ',') 4186 parse_operand_and_eval (&e2, 0); 4187 else 4188 e2.X_op = O_absent; 4189 4190 if (e1.X_op != O_constant) 4191 { 4192 as_bad (_("First operand to .unwabi must be a constant")); 4193 e1.X_add_number = 0; 4194 } 4195 4196 if (e2.X_op != O_constant) 4197 { 4198 as_bad (_("Second operand to .unwabi must be a constant")); 4199 e2.X_add_number = 0; 4200 } 4201 4202 add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number), 0); 4203} 4204 4205static void 4206dot_personality (int dummy ATTRIBUTE_UNUSED) 4207{ 4208 char *name, *p, c; 4209 4210 if (!in_procedure ("personality")) 4211 return; 4212 SKIP_WHITESPACE (); 4213 c = get_symbol_name (&name); 4214 p = input_line_pointer; 4215 unwind.personality_routine = symbol_find_or_make (name); 4216 unwind.force_unwind_entry = 1; 4217 *p = c; 4218 SKIP_WHITESPACE_AFTER_NAME (); 4219 demand_empty_rest_of_line (); 4220} 4221 4222static void 4223dot_proc (int dummy ATTRIBUTE_UNUSED) 4224{ 4225 char *name, *p, c; 4226 symbolS *sym; 4227 proc_pending *pending, *last_pending; 4228 4229 if (unwind.proc_pending.sym) 4230 { 4231 (md.unwind_check == unwind_check_warning 4232 ? as_warn 4233 : as_bad) (_("Missing .endp after previous .proc")); 4234 while (unwind.proc_pending.next) 4235 { 4236 pending = unwind.proc_pending.next; 4237 unwind.proc_pending.next = pending->next; 4238 free (pending); 4239 } 4240 } 4241 last_pending = NULL; 4242 4243 /* Parse names of main and alternate entry points and mark them as 4244 function symbols: */ 4245 while (1) 4246 { 4247 SKIP_WHITESPACE (); 4248 c = get_symbol_name (&name); 4249 p = input_line_pointer; 4250 if (!*name) 4251 as_bad (_("Empty argument of .proc")); 4252 else 4253 { 4254 sym = symbol_find_or_make (name); 4255 if (S_IS_DEFINED (sym)) 4256 as_bad (_("`%s' was already defined"), name); 4257 else if (!last_pending) 4258 { 4259 unwind.proc_pending.sym = sym; 4260 last_pending = &unwind.proc_pending; 4261 } 4262 else 4263 { 4264 pending = XNEW (proc_pending); 4265 pending->sym = sym; 4266 last_pending = last_pending->next = pending; 4267 } 4268 symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; 4269 } 4270 *p = c; 4271 SKIP_WHITESPACE_AFTER_NAME (); 4272 if (*input_line_pointer != ',') 4273 break; 4274 ++input_line_pointer; 4275 } 4276 if (!last_pending) 4277 { 4278 unwind.proc_pending.sym = expr_build_dot (); 4279 last_pending = &unwind.proc_pending; 4280 } 4281 last_pending->next = NULL; 4282 demand_empty_rest_of_line (); 4283 do_align (4, NULL, 0, 0); 4284 4285 unwind.prologue = 0; 4286 unwind.prologue_count = 0; 4287 unwind.body = 0; 4288 unwind.insn = 0; 4289 unwind.list = unwind.tail = unwind.current_entry = NULL; 4290 unwind.personality_routine = 0; 4291} 4292 4293static void 4294dot_body (int dummy ATTRIBUTE_UNUSED) 4295{ 4296 if (!in_procedure ("body")) 4297 return; 4298 if (!unwind.prologue && !unwind.body && unwind.insn) 4299 as_warn (_("Initial .body should precede any instructions")); 4300 check_pending_save (); 4301 4302 unwind.prologue = 0; 4303 unwind.prologue_mask = 0; 4304 unwind.body = 1; 4305 4306 add_unwind_entry (output_body (), 0); 4307} 4308 4309static void 4310dot_prologue (int dummy ATTRIBUTE_UNUSED) 4311{ 4312 unsigned mask = 0, grsave = 0; 4313 4314 if (!in_procedure ("prologue")) 4315 return; 4316 if (unwind.prologue) 4317 { 4318 as_bad (_(".prologue within prologue")); 4319 ignore_rest_of_line (); 4320 return; 4321 } 4322 if (!unwind.body && unwind.insn) 4323 as_warn (_("Initial .prologue should precede any instructions")); 4324 4325 if (!is_it_end_of_statement ()) 4326 { 4327 expressionS e; 4328 int n, sep = parse_operand_and_eval (&e, ','); 4329 4330 if (e.X_op != O_constant 4331 || e.X_add_number < 0 4332 || e.X_add_number > 0xf) 4333 as_bad (_("First operand to .prologue must be a positive 4-bit constant")); 4334 else if (e.X_add_number == 0) 4335 as_warn (_("Pointless use of zero first operand to .prologue")); 4336 else 4337 mask = e.X_add_number; 4338 4339 n = popcount (mask); 4340 4341 if (sep == ',') 4342 parse_operand_and_eval (&e, 0); 4343 else 4344 e.X_op = O_absent; 4345 4346 if (e.X_op == O_constant 4347 && e.X_add_number >= 0 4348 && e.X_add_number < 128) 4349 { 4350 if (md.unwind_check == unwind_check_error) 4351 as_warn (_("Using a constant as second operand to .prologue is deprecated")); 4352 grsave = e.X_add_number; 4353 } 4354 else if (e.X_op != O_register 4355 || (grsave = e.X_add_number - REG_GR) > 127) 4356 { 4357 as_bad (_("Second operand to .prologue must be a general register")); 4358 grsave = 0; 4359 } 4360 else if (grsave > 128U - n) 4361 { 4362 as_bad (_("Second operand to .prologue must be the first of %d general registers"), n); 4363 grsave = 0; 4364 } 4365 } 4366 4367 if (mask) 4368 add_unwind_entry (output_prologue_gr (mask, grsave), 0); 4369 else 4370 add_unwind_entry (output_prologue (), 0); 4371 4372 unwind.prologue = 1; 4373 unwind.prologue_mask = mask; 4374 unwind.prologue_gr = grsave; 4375 unwind.body = 0; 4376 ++unwind.prologue_count; 4377} 4378 4379static void 4380dot_endp (int dummy ATTRIBUTE_UNUSED) 4381{ 4382 expressionS e; 4383 int bytes_per_address; 4384 long where; 4385 segT saved_seg; 4386 subsegT saved_subseg; 4387 proc_pending *pending; 4388 int unwind_check = md.unwind_check; 4389 4390 md.unwind_check = unwind_check_error; 4391 if (!in_procedure ("endp")) 4392 return; 4393 md.unwind_check = unwind_check; 4394 4395 if (unwind.saved_text_seg) 4396 { 4397 saved_seg = unwind.saved_text_seg; 4398 saved_subseg = unwind.saved_text_subseg; 4399 unwind.saved_text_seg = NULL; 4400 } 4401 else 4402 { 4403 saved_seg = now_seg; 4404 saved_subseg = now_subseg; 4405 } 4406 4407 insn_group_break (1, 0, 0); 4408 4409 /* If there wasn't a .handlerdata, we haven't generated an image yet. */ 4410 if (!unwind.info) 4411 generate_unwind_image (saved_seg); 4412 4413 if (unwind.info || unwind.force_unwind_entry) 4414 { 4415 symbolS *proc_end; 4416 4417 subseg_set (md.last_text_seg, 0); 4418 proc_end = expr_build_dot (); 4419 4420 start_unwind_section (saved_seg, SPECIAL_SECTION_UNWIND); 4421 4422 /* Make sure that section has 4 byte alignment for ILP32 and 4423 8 byte alignment for LP64. */ 4424 record_alignment (now_seg, md.pointer_size_shift); 4425 4426 /* Need space for 3 pointers for procedure start, procedure end, 4427 and unwind info. */ 4428 memset (frag_more (3 * md.pointer_size), 0, 3 * md.pointer_size); 4429 where = frag_now_fix () - (3 * md.pointer_size); 4430 bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; 4431 4432 /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ 4433 e.X_op = O_pseudo_fixup; 4434 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4435 e.X_add_number = 0; 4436 if (!S_IS_LOCAL (unwind.proc_pending.sym) 4437 && S_IS_DEFINED (unwind.proc_pending.sym)) 4438 e.X_add_symbol 4439 = symbol_temp_new (S_GET_SEGMENT (unwind.proc_pending.sym), 4440 symbol_get_frag (unwind.proc_pending.sym), 4441 S_GET_VALUE (unwind.proc_pending.sym)); 4442 else 4443 e.X_add_symbol = unwind.proc_pending.sym; 4444 ia64_cons_fix_new (frag_now, where, bytes_per_address, &e, 4445 BFD_RELOC_NONE); 4446 4447 e.X_op = O_pseudo_fixup; 4448 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4449 e.X_add_number = 0; 4450 e.X_add_symbol = proc_end; 4451 ia64_cons_fix_new (frag_now, where + bytes_per_address, 4452 bytes_per_address, &e, BFD_RELOC_NONE); 4453 4454 if (unwind.info) 4455 { 4456 e.X_op = O_pseudo_fixup; 4457 e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; 4458 e.X_add_number = 0; 4459 e.X_add_symbol = unwind.info; 4460 ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), 4461 bytes_per_address, &e, BFD_RELOC_NONE); 4462 } 4463 } 4464 subseg_set (saved_seg, saved_subseg); 4465 4466 /* Set symbol sizes. */ 4467 pending = &unwind.proc_pending; 4468 if (S_GET_NAME (pending->sym)) 4469 { 4470 do 4471 { 4472 symbolS *sym = pending->sym; 4473 4474 if (!S_IS_DEFINED (sym)) 4475 as_bad (_("`%s' was not defined within procedure"), S_GET_NAME (sym)); 4476 else if (S_GET_SIZE (sym) == 0 4477 && symbol_get_obj (sym)->size == NULL) 4478 { 4479 fragS *frag = symbol_get_frag (sym); 4480 4481 if (frag) 4482 { 4483 if (frag == frag_now && SEG_NORMAL (now_seg)) 4484 S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); 4485 else 4486 { 4487 symbol_get_obj (sym)->size = XNEW (expressionS); 4488 symbol_get_obj (sym)->size->X_op = O_subtract; 4489 symbol_get_obj (sym)->size->X_add_symbol 4490 = symbol_new (FAKE_LABEL_NAME, now_seg, 4491 frag_now, frag_now_fix ()); 4492 symbol_get_obj (sym)->size->X_op_symbol = sym; 4493 symbol_get_obj (sym)->size->X_add_number = 0; 4494 } 4495 } 4496 } 4497 } while ((pending = pending->next) != NULL); 4498 } 4499 4500 /* Parse names of main and alternate entry points. */ 4501 while (1) 4502 { 4503 char *name, *p, c; 4504 4505 SKIP_WHITESPACE (); 4506 c = get_symbol_name (&name); 4507 p = input_line_pointer; 4508 if (!*name) 4509 (md.unwind_check == unwind_check_warning 4510 ? as_warn 4511 : as_bad) (_("Empty argument of .endp")); 4512 else 4513 { 4514 symbolS *sym = symbol_find (name); 4515 4516 for (pending = &unwind.proc_pending; pending; pending = pending->next) 4517 { 4518 if (sym == pending->sym) 4519 { 4520 pending->sym = NULL; 4521 break; 4522 } 4523 } 4524 if (!sym || !pending) 4525 as_warn (_("`%s' was not specified with previous .proc"), name); 4526 } 4527 *p = c; 4528 SKIP_WHITESPACE_AFTER_NAME (); 4529 if (*input_line_pointer != ',') 4530 break; 4531 ++input_line_pointer; 4532 } 4533 demand_empty_rest_of_line (); 4534 4535 /* Deliberately only checking for the main entry point here; the 4536 language spec even says all arguments to .endp are ignored. */ 4537 if (unwind.proc_pending.sym 4538 && S_GET_NAME (unwind.proc_pending.sym) 4539 && strcmp (S_GET_NAME (unwind.proc_pending.sym), FAKE_LABEL_NAME)) 4540 as_warn (_("`%s' should be an operand to this .endp"), 4541 S_GET_NAME (unwind.proc_pending.sym)); 4542 while (unwind.proc_pending.next) 4543 { 4544 pending = unwind.proc_pending.next; 4545 unwind.proc_pending.next = pending->next; 4546 free (pending); 4547 } 4548 unwind.proc_pending.sym = unwind.info = NULL; 4549} 4550 4551static void 4552dot_template (int template_val) 4553{ 4554 CURR_SLOT.user_template = template_val; 4555} 4556 4557static void 4558dot_regstk (int dummy ATTRIBUTE_UNUSED) 4559{ 4560 int ins, locs, outs, rots; 4561 4562 if (is_it_end_of_statement ()) 4563 ins = locs = outs = rots = 0; 4564 else 4565 { 4566 ins = get_absolute_expression (); 4567 if (*input_line_pointer++ != ',') 4568 goto err; 4569 locs = get_absolute_expression (); 4570 if (*input_line_pointer++ != ',') 4571 goto err; 4572 outs = get_absolute_expression (); 4573 if (*input_line_pointer++ != ',') 4574 goto err; 4575 rots = get_absolute_expression (); 4576 } 4577 set_regstack (ins, locs, outs, rots); 4578 return; 4579 4580 err: 4581 as_bad (_("Comma expected")); 4582 ignore_rest_of_line (); 4583} 4584 4585static void 4586dot_rot (int type) 4587{ 4588 offsetT num_regs; 4589 valueT num_alloced = 0; 4590 struct dynreg **drpp, *dr; 4591 int ch, base_reg = 0; 4592 char *name, *start; 4593 size_t len; 4594 4595 switch (type) 4596 { 4597 case DYNREG_GR: base_reg = REG_GR + 32; break; 4598 case DYNREG_FR: base_reg = REG_FR + 32; break; 4599 case DYNREG_PR: base_reg = REG_P + 16; break; 4600 default: break; 4601 } 4602 4603 /* First, remove existing names from hash table. */ 4604 for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) 4605 { 4606 str_hash_delete (md.dynreg_hash, dr->name); 4607 /* FIXME: Free dr->name. */ 4608 dr->num_regs = 0; 4609 } 4610 4611 drpp = &md.dynreg[type]; 4612 while (1) 4613 { 4614 ch = get_symbol_name (&start); 4615 len = strlen (ia64_canonicalize_symbol_name (start)); 4616 *input_line_pointer = ch; 4617 4618 SKIP_WHITESPACE_AFTER_NAME (); 4619 if (*input_line_pointer != '[') 4620 { 4621 as_bad (_("Expected '['")); 4622 goto err; 4623 } 4624 ++input_line_pointer; /* skip '[' */ 4625 4626 num_regs = get_absolute_expression (); 4627 4628 if (*input_line_pointer++ != ']') 4629 { 4630 as_bad (_("Expected ']'")); 4631 goto err; 4632 } 4633 if (num_regs <= 0) 4634 { 4635 as_bad (_("Number of elements must be positive")); 4636 goto err; 4637 } 4638 SKIP_WHITESPACE (); 4639 4640 num_alloced += num_regs; 4641 switch (type) 4642 { 4643 case DYNREG_GR: 4644 if (num_alloced > md.rot.num_regs) 4645 { 4646 as_bad (_("Used more than the declared %d rotating registers"), 4647 md.rot.num_regs); 4648 goto err; 4649 } 4650 break; 4651 case DYNREG_FR: 4652 if (num_alloced > 96) 4653 { 4654 as_bad (_("Used more than the available 96 rotating registers")); 4655 goto err; 4656 } 4657 break; 4658 case DYNREG_PR: 4659 if (num_alloced > 48) 4660 { 4661 as_bad (_("Used more than the available 48 rotating registers")); 4662 goto err; 4663 } 4664 break; 4665 4666 default: 4667 break; 4668 } 4669 4670 if (!*drpp) 4671 { 4672 *drpp = XOBNEW (¬es, struct dynreg); 4673 memset (*drpp, 0, sizeof (*dr)); 4674 } 4675 4676 name = XOBNEWVEC (¬es, char, len + 1); 4677 memcpy (name, start, len); 4678 name[len] = '\0'; 4679 4680 dr = *drpp; 4681 dr->name = name; 4682 dr->num_regs = num_regs; 4683 dr->base = base_reg; 4684 drpp = &dr->next; 4685 base_reg += num_regs; 4686 4687 if (str_hash_insert (md.dynreg_hash, name, dr, 0) != NULL) 4688 { 4689 as_bad (_("Attempt to redefine register set `%s'"), name); 4690 obstack_free (¬es, name); 4691 goto err; 4692 } 4693 4694 if (*input_line_pointer != ',') 4695 break; 4696 ++input_line_pointer; /* skip comma */ 4697 SKIP_WHITESPACE (); 4698 } 4699 demand_empty_rest_of_line (); 4700 return; 4701 4702 err: 4703 ignore_rest_of_line (); 4704} 4705 4706static void 4707dot_byteorder (int byteorder) 4708{ 4709 segment_info_type *seginfo = seg_info (now_seg); 4710 4711 if (byteorder == -1) 4712 { 4713 if (seginfo->tc_segment_info_data.endian == 0) 4714 seginfo->tc_segment_info_data.endian = default_big_endian ? 1 : 2; 4715 byteorder = seginfo->tc_segment_info_data.endian == 1; 4716 } 4717 else 4718 seginfo->tc_segment_info_data.endian = byteorder ? 1 : 2; 4719 4720 if (target_big_endian != byteorder) 4721 { 4722 target_big_endian = byteorder; 4723 if (target_big_endian) 4724 { 4725 ia64_number_to_chars = number_to_chars_bigendian; 4726 ia64_float_to_chars = ia64_float_to_chars_bigendian; 4727 } 4728 else 4729 { 4730 ia64_number_to_chars = number_to_chars_littleendian; 4731 ia64_float_to_chars = ia64_float_to_chars_littleendian; 4732 } 4733 } 4734} 4735 4736static void 4737dot_psr (int dummy ATTRIBUTE_UNUSED) 4738{ 4739 char *option; 4740 int ch; 4741 4742 while (1) 4743 { 4744 ch = get_symbol_name (&option); 4745 if (strcmp (option, "lsb") == 0) 4746 md.flags &= ~EF_IA_64_BE; 4747 else if (strcmp (option, "msb") == 0) 4748 md.flags |= EF_IA_64_BE; 4749 else if (strcmp (option, "abi32") == 0) 4750 md.flags &= ~EF_IA_64_ABI64; 4751 else if (strcmp (option, "abi64") == 0) 4752 md.flags |= EF_IA_64_ABI64; 4753 else 4754 as_bad (_("Unknown psr option `%s'"), option); 4755 *input_line_pointer = ch; 4756 4757 SKIP_WHITESPACE_AFTER_NAME (); 4758 if (*input_line_pointer != ',') 4759 break; 4760 4761 ++input_line_pointer; 4762 SKIP_WHITESPACE (); 4763 } 4764 demand_empty_rest_of_line (); 4765} 4766 4767static void 4768dot_ln (int dummy ATTRIBUTE_UNUSED) 4769{ 4770 new_logical_line (0, get_absolute_expression ()); 4771 demand_empty_rest_of_line (); 4772} 4773 4774static void 4775cross_section (int ref, void (*builder) (int), int ua) 4776{ 4777 char *start, *end; 4778 int saved_auto_align; 4779 unsigned int section_count; 4780 char *name; 4781 char c; 4782 4783 SKIP_WHITESPACE (); 4784 start = input_line_pointer; 4785 c = get_symbol_name (&name); 4786 if (input_line_pointer == start) 4787 { 4788 as_bad (_("Missing section name")); 4789 ignore_rest_of_line (); 4790 return; 4791 } 4792 * input_line_pointer = c; 4793 SKIP_WHITESPACE_AFTER_NAME (); 4794 end = input_line_pointer; 4795 if (*input_line_pointer != ',') 4796 { 4797 as_bad (_("Comma expected after section name")); 4798 ignore_rest_of_line (); 4799 return; 4800 } 4801 *end = '\0'; 4802 end = input_line_pointer + 1; /* skip comma */ 4803 input_line_pointer = start; 4804 md.keep_pending_output = 1; 4805 section_count = bfd_count_sections (stdoutput); 4806 obj_elf_section (0); 4807 if (section_count != bfd_count_sections (stdoutput)) 4808 as_warn (_("Creating sections with .xdataN/.xrealN/.xstringZ is deprecated.")); 4809 input_line_pointer = end; 4810 saved_auto_align = md.auto_align; 4811 if (ua) 4812 md.auto_align = 0; 4813 (*builder) (ref); 4814 if (ua) 4815 md.auto_align = saved_auto_align; 4816 obj_elf_previous (0); 4817 md.keep_pending_output = 0; 4818} 4819 4820static void 4821dot_xdata (int size) 4822{ 4823 cross_section (size, cons, 0); 4824} 4825 4826/* Why doesn't float_cons() call md_cons_align() the way cons() does? */ 4827 4828static void 4829stmt_float_cons (int kind) 4830{ 4831 size_t alignment; 4832 4833 switch (kind) 4834 { 4835 case 'd': 4836 alignment = 3; 4837 break; 4838 4839 case 'x': 4840 case 'X': 4841 alignment = 4; 4842 break; 4843 4844 case 'f': 4845 default: 4846 alignment = 2; 4847 break; 4848 } 4849 do_align (alignment, NULL, 0, 0); 4850 float_cons (kind); 4851} 4852 4853static void 4854stmt_cons_ua (int size) 4855{ 4856 int saved_auto_align = md.auto_align; 4857 4858 md.auto_align = 0; 4859 cons (size); 4860 md.auto_align = saved_auto_align; 4861} 4862 4863static void 4864dot_xfloat_cons (int kind) 4865{ 4866 cross_section (kind, stmt_float_cons, 0); 4867} 4868 4869static void 4870dot_xstringer (int zero) 4871{ 4872 cross_section (zero, stringer, 0); 4873} 4874 4875static void 4876dot_xdata_ua (int size) 4877{ 4878 cross_section (size, cons, 1); 4879} 4880 4881static void 4882dot_xfloat_cons_ua (int kind) 4883{ 4884 cross_section (kind, float_cons, 1); 4885} 4886 4887/* .reg.val <regname>,value */ 4888 4889static void 4890dot_reg_val (int dummy ATTRIBUTE_UNUSED) 4891{ 4892 expressionS reg; 4893 4894 expression_and_evaluate (®); 4895 if (reg.X_op != O_register) 4896 { 4897 as_bad (_("Register name expected")); 4898 ignore_rest_of_line (); 4899 } 4900 else if (*input_line_pointer++ != ',') 4901 { 4902 as_bad (_("Comma expected")); 4903 ignore_rest_of_line (); 4904 } 4905 else 4906 { 4907 valueT value = get_absolute_expression (); 4908 int regno = reg.X_add_number; 4909 if (regno <= REG_GR || regno > REG_GR + 127) 4910 as_warn (_("Register value annotation ignored")); 4911 else 4912 { 4913 gr_values[regno - REG_GR].known = 1; 4914 gr_values[regno - REG_GR].value = value; 4915 gr_values[regno - REG_GR].path = md.path; 4916 } 4917 } 4918 demand_empty_rest_of_line (); 4919} 4920 4921/* 4922 .serialize.data 4923 .serialize.instruction 4924 */ 4925static void 4926dot_serialize (int type) 4927{ 4928 insn_group_break (0, 0, 0); 4929 if (type) 4930 instruction_serialization (); 4931 else 4932 data_serialization (); 4933 insn_group_break (0, 0, 0); 4934 demand_empty_rest_of_line (); 4935} 4936 4937/* select dv checking mode 4938 .auto 4939 .explicit 4940 .default 4941 4942 A stop is inserted when changing modes 4943 */ 4944 4945static void 4946dot_dv_mode (int type) 4947{ 4948 if (md.manual_bundling) 4949 as_warn (_("Directive invalid within a bundle")); 4950 4951 if (type == 'E' || type == 'A') 4952 md.mode_explicitly_set = 0; 4953 else 4954 md.mode_explicitly_set = 1; 4955 4956 md.detect_dv = 1; 4957 switch (type) 4958 { 4959 case 'A': 4960 case 'a': 4961 if (md.explicit_mode) 4962 insn_group_break (1, 0, 0); 4963 md.explicit_mode = 0; 4964 break; 4965 case 'E': 4966 case 'e': 4967 if (!md.explicit_mode) 4968 insn_group_break (1, 0, 0); 4969 md.explicit_mode = 1; 4970 break; 4971 default: 4972 case 'd': 4973 if (md.explicit_mode != md.default_explicit_mode) 4974 insn_group_break (1, 0, 0); 4975 md.explicit_mode = md.default_explicit_mode; 4976 md.mode_explicitly_set = 0; 4977 break; 4978 } 4979} 4980 4981static void 4982print_prmask (valueT mask) 4983{ 4984 int regno; 4985 const char *comma = ""; 4986 for (regno = 0; regno < 64; regno++) 4987 { 4988 if (mask & ((valueT) 1 << regno)) 4989 { 4990 fprintf (stderr, "%s p%d", comma, regno); 4991 comma = ","; 4992 } 4993 } 4994} 4995 4996/* 4997 .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear" or @clear) 4998 .pred.rel.imply p1, p2 (also .pred.rel "imply" or @imply) 4999 .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex" or @mutex) 5000 .pred.safe_across_calls p1 [, p2 [,...]] 5001 */ 5002 5003static void 5004dot_pred_rel (int type) 5005{ 5006 valueT mask = 0; 5007 int count = 0; 5008 int p1 = -1, p2 = -1; 5009 5010 if (type == 0) 5011 { 5012 if (*input_line_pointer == '"') 5013 { 5014 int len; 5015 char *form = demand_copy_C_string (&len); 5016 5017 if (strcmp (form, "mutex") == 0) 5018 type = 'm'; 5019 else if (strcmp (form, "clear") == 0) 5020 type = 'c'; 5021 else if (strcmp (form, "imply") == 0) 5022 type = 'i'; 5023 obstack_free (¬es, form); 5024 } 5025 else if (*input_line_pointer == '@') 5026 { 5027 char *form; 5028 char c; 5029 5030 ++input_line_pointer; 5031 c = get_symbol_name (&form); 5032 5033 if (strcmp (form, "mutex") == 0) 5034 type = 'm'; 5035 else if (strcmp (form, "clear") == 0) 5036 type = 'c'; 5037 else if (strcmp (form, "imply") == 0) 5038 type = 'i'; 5039 (void) restore_line_pointer (c); 5040 } 5041 else 5042 { 5043 as_bad (_("Missing predicate relation type")); 5044 ignore_rest_of_line (); 5045 return; 5046 } 5047 if (type == 0) 5048 { 5049 as_bad (_("Unrecognized predicate relation type")); 5050 ignore_rest_of_line (); 5051 return; 5052 } 5053 if (*input_line_pointer == ',') 5054 ++input_line_pointer; 5055 SKIP_WHITESPACE (); 5056 } 5057 5058 while (1) 5059 { 5060 valueT bits = 1; 5061 int sep, regno; 5062 expressionS pr, *pr1, *pr2; 5063 5064 sep = parse_operand_and_eval (&pr, ','); 5065 if (pr.X_op == O_register 5066 && pr.X_add_number >= REG_P 5067 && pr.X_add_number <= REG_P + 63) 5068 { 5069 regno = pr.X_add_number - REG_P; 5070 bits <<= regno; 5071 count++; 5072 if (p1 == -1) 5073 p1 = regno; 5074 else if (p2 == -1) 5075 p2 = regno; 5076 } 5077 else if (type != 'i' 5078 && pr.X_op == O_subtract 5079 && (pr1 = symbol_get_value_expression (pr.X_add_symbol)) 5080 && pr1->X_op == O_register 5081 && pr1->X_add_number >= REG_P 5082 && pr1->X_add_number <= REG_P + 63 5083 && (pr2 = symbol_get_value_expression (pr.X_op_symbol)) 5084 && pr2->X_op == O_register 5085 && pr2->X_add_number >= REG_P 5086 && pr2->X_add_number <= REG_P + 63) 5087 { 5088 /* It's a range. */ 5089 int stop; 5090 5091 regno = pr1->X_add_number - REG_P; 5092 stop = pr2->X_add_number - REG_P; 5093 if (regno >= stop) 5094 { 5095 as_bad (_("Bad register range")); 5096 ignore_rest_of_line (); 5097 return; 5098 } 5099 bits = ((bits << stop) << 1) - (bits << regno); 5100 count += stop - regno + 1; 5101 } 5102 else 5103 { 5104 as_bad (_("Predicate register expected")); 5105 ignore_rest_of_line (); 5106 return; 5107 } 5108 if (mask & bits) 5109 as_warn (_("Duplicate predicate register ignored")); 5110 mask |= bits; 5111 if (sep != ',') 5112 break; 5113 } 5114 5115 switch (type) 5116 { 5117 case 'c': 5118 if (count == 0) 5119 mask = ~(valueT) 0; 5120 clear_qp_mutex (mask); 5121 clear_qp_implies (mask, (valueT) 0); 5122 break; 5123 case 'i': 5124 if (count != 2 || p1 == -1 || p2 == -1) 5125 as_bad (_("Predicate source and target required")); 5126 else if (p1 == 0 || p2 == 0) 5127 as_bad (_("Use of p0 is not valid in this context")); 5128 else 5129 add_qp_imply (p1, p2); 5130 break; 5131 case 'm': 5132 if (count < 2) 5133 { 5134 as_bad (_("At least two PR arguments expected")); 5135 break; 5136 } 5137 else if (mask & 1) 5138 { 5139 as_bad (_("Use of p0 is not valid in this context")); 5140 break; 5141 } 5142 add_qp_mutex (mask); 5143 break; 5144 case 's': 5145 /* note that we don't override any existing relations */ 5146 if (count == 0) 5147 { 5148 as_bad (_("At least one PR argument expected")); 5149 break; 5150 } 5151 if (md.debug_dv) 5152 { 5153 fprintf (stderr, "Safe across calls: "); 5154 print_prmask (mask); 5155 fprintf (stderr, "\n"); 5156 } 5157 qp_safe_across_calls = mask; 5158 break; 5159 } 5160 demand_empty_rest_of_line (); 5161} 5162 5163/* .entry label [, label [, ...]] 5164 Hint to DV code that the given labels are to be considered entry points. 5165 Otherwise, only global labels are considered entry points. */ 5166 5167static void 5168dot_entry (int dummy ATTRIBUTE_UNUSED) 5169{ 5170 char *name; 5171 int c; 5172 symbolS *symbolP; 5173 5174 do 5175 { 5176 c = get_symbol_name (&name); 5177 symbolP = symbol_find_or_make (name); 5178 5179 if (str_hash_insert (md.entry_hash, S_GET_NAME (symbolP), symbolP, 0)) 5180 as_bad (_("duplicate entry hint %s"), name); 5181 5182 *input_line_pointer = c; 5183 SKIP_WHITESPACE_AFTER_NAME (); 5184 c = *input_line_pointer; 5185 if (c == ',') 5186 { 5187 input_line_pointer++; 5188 SKIP_WHITESPACE (); 5189 if (*input_line_pointer == '\n') 5190 c = '\n'; 5191 } 5192 } 5193 while (c == ','); 5194 5195 demand_empty_rest_of_line (); 5196} 5197 5198/* .mem.offset offset, base 5199 "base" is used to distinguish between offsets from a different base. */ 5200 5201static void 5202dot_mem_offset (int dummy ATTRIBUTE_UNUSED) 5203{ 5204 md.mem_offset.hint = 1; 5205 md.mem_offset.offset = get_absolute_expression (); 5206 if (*input_line_pointer != ',') 5207 { 5208 as_bad (_("Comma expected")); 5209 ignore_rest_of_line (); 5210 return; 5211 } 5212 ++input_line_pointer; 5213 md.mem_offset.base = get_absolute_expression (); 5214 demand_empty_rest_of_line (); 5215} 5216 5217/* ia64-specific pseudo-ops: */ 5218const pseudo_typeS md_pseudo_table[] = 5219 { 5220 { "radix", dot_radix, 0 }, 5221 { "lcomm", s_lcomm_bytes, 1 }, 5222 { "loc", dot_loc, 0 }, 5223 { "bss", dot_special_section, SPECIAL_SECTION_BSS }, 5224 { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, 5225 { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, 5226 { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, 5227 { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, 5228 { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, 5229 { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, 5230 { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, 5231 { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, 5232 { "proc", dot_proc, 0 }, 5233 { "body", dot_body, 0 }, 5234 { "prologue", dot_prologue, 0 }, 5235 { "endp", dot_endp, 0 }, 5236 5237 { "fframe", dot_fframe, 0 }, 5238 { "vframe", dot_vframe, 0 }, 5239 { "vframesp", dot_vframesp, 0 }, 5240 { "vframepsp", dot_vframesp, 1 }, 5241 { "save", dot_save, 0 }, 5242 { "restore", dot_restore, 0 }, 5243 { "restorereg", dot_restorereg, 0 }, 5244 { "restorereg.p", dot_restorereg, 1 }, 5245 { "handlerdata", dot_handlerdata, 0 }, 5246 { "unwentry", dot_unwentry, 0 }, 5247 { "altrp", dot_altrp, 0 }, 5248 { "savesp", dot_savemem, 0 }, 5249 { "savepsp", dot_savemem, 1 }, 5250 { "save.g", dot_saveg, 0 }, 5251 { "save.f", dot_savef, 0 }, 5252 { "save.b", dot_saveb, 0 }, 5253 { "save.gf", dot_savegf, 0 }, 5254 { "spill", dot_spill, 0 }, 5255 { "spillreg", dot_spillreg, 0 }, 5256 { "spillsp", dot_spillmem, 0 }, 5257 { "spillpsp", dot_spillmem, 1 }, 5258 { "spillreg.p", dot_spillreg, 1 }, 5259 { "spillsp.p", dot_spillmem, ~0 }, 5260 { "spillpsp.p", dot_spillmem, ~1 }, 5261 { "label_state", dot_label_state, 0 }, 5262 { "copy_state", dot_copy_state, 0 }, 5263 { "unwabi", dot_unwabi, 0 }, 5264 { "personality", dot_personality, 0 }, 5265 { "mii", dot_template, 0x0 }, 5266 { "mli", dot_template, 0x2 }, /* old format, for compatibility */ 5267 { "mlx", dot_template, 0x2 }, 5268 { "mmi", dot_template, 0x4 }, 5269 { "mfi", dot_template, 0x6 }, 5270 { "mmf", dot_template, 0x7 }, 5271 { "mib", dot_template, 0x8 }, 5272 { "mbb", dot_template, 0x9 }, 5273 { "bbb", dot_template, 0xb }, 5274 { "mmb", dot_template, 0xc }, 5275 { "mfb", dot_template, 0xe }, 5276 { "align", dot_align, 0 }, 5277 { "regstk", dot_regstk, 0 }, 5278 { "rotr", dot_rot, DYNREG_GR }, 5279 { "rotf", dot_rot, DYNREG_FR }, 5280 { "rotp", dot_rot, DYNREG_PR }, 5281 { "lsb", dot_byteorder, 0 }, 5282 { "msb", dot_byteorder, 1 }, 5283 { "psr", dot_psr, 0 }, 5284 { "alias", dot_alias, 0 }, 5285 { "secalias", dot_alias, 1 }, 5286 { "ln", dot_ln, 0 }, /* source line info (for debugging) */ 5287 5288 { "xdata1", dot_xdata, 1 }, 5289 { "xdata2", dot_xdata, 2 }, 5290 { "xdata4", dot_xdata, 4 }, 5291 { "xdata8", dot_xdata, 8 }, 5292 { "xdata16", dot_xdata, 16 }, 5293 { "xreal4", dot_xfloat_cons, 'f' }, 5294 { "xreal8", dot_xfloat_cons, 'd' }, 5295 { "xreal10", dot_xfloat_cons, 'x' }, 5296 { "xreal16", dot_xfloat_cons, 'X' }, 5297 { "xstring", dot_xstringer, 8 + 0 }, 5298 { "xstringz", dot_xstringer, 8 + 1 }, 5299 5300 /* unaligned versions: */ 5301 { "xdata2.ua", dot_xdata_ua, 2 }, 5302 { "xdata4.ua", dot_xdata_ua, 4 }, 5303 { "xdata8.ua", dot_xdata_ua, 8 }, 5304 { "xdata16.ua", dot_xdata_ua, 16 }, 5305 { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, 5306 { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, 5307 { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, 5308 { "xreal16.ua", dot_xfloat_cons_ua, 'X' }, 5309 5310 /* annotations/DV checking support */ 5311 { "entry", dot_entry, 0 }, 5312 { "mem.offset", dot_mem_offset, 0 }, 5313 { "pred.rel", dot_pred_rel, 0 }, 5314 { "pred.rel.clear", dot_pred_rel, 'c' }, 5315 { "pred.rel.imply", dot_pred_rel, 'i' }, 5316 { "pred.rel.mutex", dot_pred_rel, 'm' }, 5317 { "pred.safe_across_calls", dot_pred_rel, 's' }, 5318 { "reg.val", dot_reg_val, 0 }, 5319 { "serialize.data", dot_serialize, 0 }, 5320 { "serialize.instruction", dot_serialize, 1 }, 5321 { "auto", dot_dv_mode, 'a' }, 5322 { "explicit", dot_dv_mode, 'e' }, 5323 { "default", dot_dv_mode, 'd' }, 5324 5325 /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. 5326 IA-64 aligns data allocation pseudo-ops by default, so we have to 5327 tell it that these ones are supposed to be unaligned. Long term, 5328 should rewrite so that only IA-64 specific data allocation pseudo-ops 5329 are aligned by default. */ 5330 {"2byte", stmt_cons_ua, 2}, 5331 {"4byte", stmt_cons_ua, 4}, 5332 {"8byte", stmt_cons_ua, 8}, 5333 5334#ifdef TE_VMS 5335 {"vms_common", obj_elf_vms_common, 0}, 5336#endif 5337 5338 { NULL, 0, 0 } 5339 }; 5340 5341static const struct pseudo_opcode 5342 { 5343 const char *name; 5344 void (*handler) (int); 5345 int arg; 5346 } 5347pseudo_opcode[] = 5348 { 5349 /* these are more like pseudo-ops, but don't start with a dot */ 5350 { "data1", cons, 1 }, 5351 { "data2", cons, 2 }, 5352 { "data4", cons, 4 }, 5353 { "data8", cons, 8 }, 5354 { "data16", cons, 16 }, 5355 { "real4", stmt_float_cons, 'f' }, 5356 { "real8", stmt_float_cons, 'd' }, 5357 { "real10", stmt_float_cons, 'x' }, 5358 { "real16", stmt_float_cons, 'X' }, 5359 { "string", stringer, 8 + 0 }, 5360 { "stringz", stringer, 8 + 1 }, 5361 5362 /* unaligned versions: */ 5363 { "data2.ua", stmt_cons_ua, 2 }, 5364 { "data4.ua", stmt_cons_ua, 4 }, 5365 { "data8.ua", stmt_cons_ua, 8 }, 5366 { "data16.ua", stmt_cons_ua, 16 }, 5367 { "real4.ua", float_cons, 'f' }, 5368 { "real8.ua", float_cons, 'd' }, 5369 { "real10.ua", float_cons, 'x' }, 5370 { "real16.ua", float_cons, 'X' }, 5371 }; 5372 5373/* Declare a register by creating a symbol for it and entering it in 5374 the symbol table. */ 5375 5376static symbolS * 5377declare_register (const char *name, unsigned int regnum) 5378{ 5379 symbolS *sym; 5380 5381 sym = symbol_create (name, reg_section, &zero_address_frag, regnum); 5382 5383 if (str_hash_insert (md.reg_hash, S_GET_NAME (sym), sym, 0) != NULL) 5384 as_fatal (_("duplicate %s"), name); 5385 5386 return sym; 5387} 5388 5389static void 5390declare_register_set (const char *prefix, 5391 unsigned int num_regs, 5392 unsigned int base_regnum) 5393{ 5394 char name[8]; 5395 unsigned int i; 5396 5397 for (i = 0; i < num_regs; ++i) 5398 { 5399 snprintf (name, sizeof (name), "%s%u", prefix, i); 5400 declare_register (name, base_regnum + i); 5401 } 5402} 5403 5404static unsigned int 5405operand_width (enum ia64_opnd opnd) 5406{ 5407 const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; 5408 unsigned int bits = 0; 5409 int i; 5410 5411 bits = 0; 5412 for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) 5413 bits += odesc->field[i].bits; 5414 5415 return bits; 5416} 5417 5418static enum operand_match_result 5419operand_match (const struct ia64_opcode *idesc, int res_index, expressionS *e) 5420{ 5421 enum ia64_opnd opnd = idesc->operands[res_index]; 5422 int bits, relocatable = 0; 5423 struct insn_fix *fix; 5424 bfd_signed_vma val; 5425 5426 switch (opnd) 5427 { 5428 /* constants: */ 5429 5430 case IA64_OPND_AR_CCV: 5431 if (e->X_op == O_register && e->X_add_number == REG_AR + 32) 5432 return OPERAND_MATCH; 5433 break; 5434 5435 case IA64_OPND_AR_CSD: 5436 if (e->X_op == O_register && e->X_add_number == REG_AR + 25) 5437 return OPERAND_MATCH; 5438 break; 5439 5440 case IA64_OPND_AR_PFS: 5441 if (e->X_op == O_register && e->X_add_number == REG_AR + 64) 5442 return OPERAND_MATCH; 5443 break; 5444 5445 case IA64_OPND_GR0: 5446 if (e->X_op == O_register && e->X_add_number == REG_GR + 0) 5447 return OPERAND_MATCH; 5448 break; 5449 5450 case IA64_OPND_IP: 5451 if (e->X_op == O_register && e->X_add_number == REG_IP) 5452 return OPERAND_MATCH; 5453 break; 5454 5455 case IA64_OPND_PR: 5456 if (e->X_op == O_register && e->X_add_number == REG_PR) 5457 return OPERAND_MATCH; 5458 break; 5459 5460 case IA64_OPND_PR_ROT: 5461 if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) 5462 return OPERAND_MATCH; 5463 break; 5464 5465 case IA64_OPND_PSR: 5466 if (e->X_op == O_register && e->X_add_number == REG_PSR) 5467 return OPERAND_MATCH; 5468 break; 5469 5470 case IA64_OPND_PSR_L: 5471 if (e->X_op == O_register && e->X_add_number == REG_PSR_L) 5472 return OPERAND_MATCH; 5473 break; 5474 5475 case IA64_OPND_PSR_UM: 5476 if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) 5477 return OPERAND_MATCH; 5478 break; 5479 5480 case IA64_OPND_C1: 5481 if (e->X_op == O_constant) 5482 { 5483 if (e->X_add_number == 1) 5484 return OPERAND_MATCH; 5485 else 5486 return OPERAND_OUT_OF_RANGE; 5487 } 5488 break; 5489 5490 case IA64_OPND_C8: 5491 if (e->X_op == O_constant) 5492 { 5493 if (e->X_add_number == 8) 5494 return OPERAND_MATCH; 5495 else 5496 return OPERAND_OUT_OF_RANGE; 5497 } 5498 break; 5499 5500 case IA64_OPND_C16: 5501 if (e->X_op == O_constant) 5502 { 5503 if (e->X_add_number == 16) 5504 return OPERAND_MATCH; 5505 else 5506 return OPERAND_OUT_OF_RANGE; 5507 } 5508 break; 5509 5510 /* register operands: */ 5511 5512 case IA64_OPND_AR3: 5513 if (e->X_op == O_register && e->X_add_number >= REG_AR 5514 && e->X_add_number < REG_AR + 128) 5515 return OPERAND_MATCH; 5516 break; 5517 5518 case IA64_OPND_B1: 5519 case IA64_OPND_B2: 5520 if (e->X_op == O_register && e->X_add_number >= REG_BR 5521 && e->X_add_number < REG_BR + 8) 5522 return OPERAND_MATCH; 5523 break; 5524 5525 case IA64_OPND_CR3: 5526 if (e->X_op == O_register && e->X_add_number >= REG_CR 5527 && e->X_add_number < REG_CR + 128) 5528 return OPERAND_MATCH; 5529 break; 5530 5531 case IA64_OPND_DAHR3: 5532 if (e->X_op == O_register && e->X_add_number >= REG_DAHR 5533 && e->X_add_number < REG_DAHR + 8) 5534 return OPERAND_MATCH; 5535 break; 5536 5537 case IA64_OPND_F1: 5538 case IA64_OPND_F2: 5539 case IA64_OPND_F3: 5540 case IA64_OPND_F4: 5541 if (e->X_op == O_register && e->X_add_number >= REG_FR 5542 && e->X_add_number < REG_FR + 128) 5543 return OPERAND_MATCH; 5544 break; 5545 5546 case IA64_OPND_P1: 5547 case IA64_OPND_P2: 5548 if (e->X_op == O_register && e->X_add_number >= REG_P 5549 && e->X_add_number < REG_P + 64) 5550 return OPERAND_MATCH; 5551 break; 5552 5553 case IA64_OPND_R1: 5554 case IA64_OPND_R2: 5555 case IA64_OPND_R3: 5556 if (e->X_op == O_register && e->X_add_number >= REG_GR 5557 && e->X_add_number < REG_GR + 128) 5558 return OPERAND_MATCH; 5559 break; 5560 5561 case IA64_OPND_R3_2: 5562 if (e->X_op == O_register && e->X_add_number >= REG_GR) 5563 { 5564 if (e->X_add_number < REG_GR + 4) 5565 return OPERAND_MATCH; 5566 else if (e->X_add_number < REG_GR + 128) 5567 return OPERAND_OUT_OF_RANGE; 5568 } 5569 break; 5570 5571 /* indirect operands: */ 5572 case IA64_OPND_CPUID_R3: 5573 case IA64_OPND_DBR_R3: 5574 case IA64_OPND_DTR_R3: 5575 case IA64_OPND_ITR_R3: 5576 case IA64_OPND_IBR_R3: 5577 case IA64_OPND_MSR_R3: 5578 case IA64_OPND_PKR_R3: 5579 case IA64_OPND_PMC_R3: 5580 case IA64_OPND_PMD_R3: 5581 case IA64_OPND_DAHR_R3: 5582 case IA64_OPND_RR_R3: 5583 if (e->X_op == O_index && e->X_op_symbol 5584 && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID 5585 == opnd - IA64_OPND_CPUID_R3)) 5586 return OPERAND_MATCH; 5587 break; 5588 5589 case IA64_OPND_MR3: 5590 if (e->X_op == O_index && !e->X_op_symbol) 5591 return OPERAND_MATCH; 5592 break; 5593 5594 /* immediate operands: */ 5595 case IA64_OPND_CNT2a: 5596 case IA64_OPND_LEN4: 5597 case IA64_OPND_LEN6: 5598 bits = operand_width (idesc->operands[res_index]); 5599 if (e->X_op == O_constant) 5600 { 5601 if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) 5602 return OPERAND_MATCH; 5603 else 5604 return OPERAND_OUT_OF_RANGE; 5605 } 5606 break; 5607 5608 case IA64_OPND_CNT2b: 5609 if (e->X_op == O_constant) 5610 { 5611 if ((bfd_vma) (e->X_add_number - 1) < 3) 5612 return OPERAND_MATCH; 5613 else 5614 return OPERAND_OUT_OF_RANGE; 5615 } 5616 break; 5617 5618 case IA64_OPND_CNT2c: 5619 val = e->X_add_number; 5620 if (e->X_op == O_constant) 5621 { 5622 if ((val == 0 || val == 7 || val == 15 || val == 16)) 5623 return OPERAND_MATCH; 5624 else 5625 return OPERAND_OUT_OF_RANGE; 5626 } 5627 break; 5628 5629 case IA64_OPND_SOR: 5630 /* SOR must be an integer multiple of 8 */ 5631 if (e->X_op == O_constant && e->X_add_number & 0x7) 5632 return OPERAND_OUT_OF_RANGE; 5633 /* Fall through. */ 5634 case IA64_OPND_SOF: 5635 case IA64_OPND_SOL: 5636 if (e->X_op == O_constant) 5637 { 5638 if ((bfd_vma) e->X_add_number <= 96) 5639 return OPERAND_MATCH; 5640 else 5641 return OPERAND_OUT_OF_RANGE; 5642 } 5643 break; 5644 5645 case IA64_OPND_IMMU62: 5646 if (e->X_op == O_constant) 5647 { 5648 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) 5649 return OPERAND_MATCH; 5650 else 5651 return OPERAND_OUT_OF_RANGE; 5652 } 5653 else 5654 { 5655 /* FIXME -- need 62-bit relocation type */ 5656 as_bad (_("62-bit relocation not yet implemented")); 5657 } 5658 break; 5659 5660 case IA64_OPND_IMMU64: 5661 if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup 5662 || e->X_op == O_subtract) 5663 { 5664 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5665 fix->code = BFD_RELOC_IA64_IMM64; 5666 if (e->X_op != O_subtract) 5667 { 5668 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5669 if (e->X_op == O_pseudo_fixup) 5670 e->X_op = O_symbol; 5671 } 5672 5673 fix->opnd = idesc->operands[res_index]; 5674 fix->expr = *e; 5675 fix->is_pcrel = 0; 5676 ++CURR_SLOT.num_fixups; 5677 return OPERAND_MATCH; 5678 } 5679 else if (e->X_op == O_constant) 5680 return OPERAND_MATCH; 5681 break; 5682 5683 case IA64_OPND_IMMU5b: 5684 if (e->X_op == O_constant) 5685 { 5686 val = e->X_add_number; 5687 if (val >= 32 && val <= 63) 5688 return OPERAND_MATCH; 5689 else 5690 return OPERAND_OUT_OF_RANGE; 5691 } 5692 break; 5693 5694 case IA64_OPND_CCNT5: 5695 case IA64_OPND_CNT5: 5696 case IA64_OPND_CNT6: 5697 case IA64_OPND_CPOS6a: 5698 case IA64_OPND_CPOS6b: 5699 case IA64_OPND_CPOS6c: 5700 case IA64_OPND_IMMU2: 5701 case IA64_OPND_IMMU7a: 5702 case IA64_OPND_IMMU7b: 5703 case IA64_OPND_IMMU16: 5704 case IA64_OPND_IMMU19: 5705 case IA64_OPND_IMMU21: 5706 case IA64_OPND_IMMU24: 5707 case IA64_OPND_MBTYPE4: 5708 case IA64_OPND_MHTYPE8: 5709 case IA64_OPND_POS6: 5710 bits = operand_width (idesc->operands[res_index]); 5711 if (e->X_op == O_constant) 5712 { 5713 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5714 return OPERAND_MATCH; 5715 else 5716 return OPERAND_OUT_OF_RANGE; 5717 } 5718 break; 5719 5720 case IA64_OPND_IMMU9: 5721 bits = operand_width (idesc->operands[res_index]); 5722 if (e->X_op == O_constant) 5723 { 5724 if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) 5725 { 5726 int lobits = e->X_add_number & 0x3; 5727 if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) 5728 e->X_add_number |= (bfd_vma) 0x3; 5729 return OPERAND_MATCH; 5730 } 5731 else 5732 return OPERAND_OUT_OF_RANGE; 5733 } 5734 break; 5735 5736 case IA64_OPND_IMM44: 5737 /* least 16 bits must be zero */ 5738 if ((e->X_add_number & 0xffff) != 0) 5739 /* XXX technically, this is wrong: we should not be issuing warning 5740 messages until we're sure this instruction pattern is going to 5741 be used! */ 5742 as_warn (_("lower 16 bits of mask ignored")); 5743 5744 if (e->X_op == O_constant) 5745 { 5746 if (((e->X_add_number >= 0 5747 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) 5748 || (e->X_add_number < 0 5749 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) 5750 { 5751 /* sign-extend */ 5752 if (e->X_add_number >= 0 5753 && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) 5754 { 5755 e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); 5756 } 5757 return OPERAND_MATCH; 5758 } 5759 else 5760 return OPERAND_OUT_OF_RANGE; 5761 } 5762 break; 5763 5764 case IA64_OPND_IMM17: 5765 /* bit 0 is a don't care (pr0 is hardwired to 1) */ 5766 if (e->X_op == O_constant) 5767 { 5768 if (((e->X_add_number >= 0 5769 && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) 5770 || (e->X_add_number < 0 5771 && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) 5772 { 5773 /* sign-extend */ 5774 if (e->X_add_number >= 0 5775 && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) 5776 { 5777 e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); 5778 } 5779 return OPERAND_MATCH; 5780 } 5781 else 5782 return OPERAND_OUT_OF_RANGE; 5783 } 5784 break; 5785 5786 case IA64_OPND_IMM14: 5787 case IA64_OPND_IMM22: 5788 relocatable = 1; 5789 /* Fall through. */ 5790 case IA64_OPND_IMM1: 5791 case IA64_OPND_IMM8: 5792 case IA64_OPND_IMM8U4: 5793 case IA64_OPND_IMM8M1: 5794 case IA64_OPND_IMM8M1U4: 5795 case IA64_OPND_IMM8M1U8: 5796 case IA64_OPND_IMM9a: 5797 case IA64_OPND_IMM9b: 5798 bits = operand_width (idesc->operands[res_index]); 5799 if (relocatable && (e->X_op == O_symbol 5800 || e->X_op == O_subtract 5801 || e->X_op == O_pseudo_fixup)) 5802 { 5803 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5804 5805 if (idesc->operands[res_index] == IA64_OPND_IMM14) 5806 fix->code = BFD_RELOC_IA64_IMM14; 5807 else 5808 fix->code = BFD_RELOC_IA64_IMM22; 5809 5810 if (e->X_op != O_subtract) 5811 { 5812 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5813 if (e->X_op == O_pseudo_fixup) 5814 e->X_op = O_symbol; 5815 } 5816 5817 fix->opnd = idesc->operands[res_index]; 5818 fix->expr = *e; 5819 fix->is_pcrel = 0; 5820 ++CURR_SLOT.num_fixups; 5821 return OPERAND_MATCH; 5822 } 5823 else if (e->X_op != O_constant 5824 && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) 5825 return OPERAND_MISMATCH; 5826 5827 if (opnd == IA64_OPND_IMM8M1U4) 5828 { 5829 /* Zero is not valid for unsigned compares that take an adjusted 5830 constant immediate range. */ 5831 if (e->X_add_number == 0) 5832 return OPERAND_OUT_OF_RANGE; 5833 5834 /* Sign-extend 32-bit unsigned numbers, so that the following range 5835 checks will work. */ 5836 val = e->X_add_number; 5837 if ((val & (~(bfd_vma) 0 << 32)) == 0) 5838 val = (val ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); 5839 5840 /* Check for 0x100000000. This is valid because 5841 0x100000000-1 is the same as ((uint32_t) -1). */ 5842 if (val == ((bfd_signed_vma) 1 << 32)) 5843 return OPERAND_MATCH; 5844 5845 val = val - 1; 5846 } 5847 else if (opnd == IA64_OPND_IMM8M1U8) 5848 { 5849 /* Zero is not valid for unsigned compares that take an adjusted 5850 constant immediate range. */ 5851 if (e->X_add_number == 0) 5852 return OPERAND_OUT_OF_RANGE; 5853 5854 /* Check for 0x10000000000000000. */ 5855 if (e->X_op == O_big) 5856 { 5857 if (generic_bignum[0] == 0 5858 && generic_bignum[1] == 0 5859 && generic_bignum[2] == 0 5860 && generic_bignum[3] == 0 5861 && generic_bignum[4] == 1) 5862 return OPERAND_MATCH; 5863 else 5864 return OPERAND_OUT_OF_RANGE; 5865 } 5866 else 5867 val = e->X_add_number - 1; 5868 } 5869 else if (opnd == IA64_OPND_IMM8M1) 5870 val = e->X_add_number - 1; 5871 else if (opnd == IA64_OPND_IMM8U4) 5872 { 5873 /* Sign-extend 32-bit unsigned numbers, so that the following range 5874 checks will work. */ 5875 val = e->X_add_number; 5876 if ((val & (~(bfd_vma) 0 << 32)) == 0) 5877 val = (val ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); 5878 } 5879 else 5880 val = e->X_add_number; 5881 5882 if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) 5883 || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) 5884 return OPERAND_MATCH; 5885 else 5886 return OPERAND_OUT_OF_RANGE; 5887 5888 case IA64_OPND_INC3: 5889 /* +/- 1, 4, 8, 16 */ 5890 val = e->X_add_number; 5891 if (val < 0) 5892 val = -val; 5893 if (e->X_op == O_constant) 5894 { 5895 if ((val == 1 || val == 4 || val == 8 || val == 16)) 5896 return OPERAND_MATCH; 5897 else 5898 return OPERAND_OUT_OF_RANGE; 5899 } 5900 break; 5901 5902 case IA64_OPND_TGT25: 5903 case IA64_OPND_TGT25b: 5904 case IA64_OPND_TGT25c: 5905 case IA64_OPND_TGT64: 5906 if (e->X_op == O_symbol) 5907 { 5908 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5909 if (opnd == IA64_OPND_TGT25) 5910 fix->code = BFD_RELOC_IA64_PCREL21F; 5911 else if (opnd == IA64_OPND_TGT25b) 5912 fix->code = BFD_RELOC_IA64_PCREL21M; 5913 else if (opnd == IA64_OPND_TGT25c) 5914 fix->code = BFD_RELOC_IA64_PCREL21B; 5915 else if (opnd == IA64_OPND_TGT64) 5916 fix->code = BFD_RELOC_IA64_PCREL60B; 5917 else 5918 abort (); 5919 5920 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5921 fix->opnd = idesc->operands[res_index]; 5922 fix->expr = *e; 5923 fix->is_pcrel = 1; 5924 ++CURR_SLOT.num_fixups; 5925 return OPERAND_MATCH; 5926 } 5927 /* Fall through. */ 5928 case IA64_OPND_TAG13: 5929 case IA64_OPND_TAG13b: 5930 switch (e->X_op) 5931 { 5932 case O_constant: 5933 return OPERAND_MATCH; 5934 5935 case O_symbol: 5936 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5937 /* There are no external relocs for TAG13/TAG13b fields, so we 5938 create a dummy reloc. This will not live past md_apply_fix. */ 5939 fix->code = BFD_RELOC_UNUSED; 5940 fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); 5941 fix->opnd = idesc->operands[res_index]; 5942 fix->expr = *e; 5943 fix->is_pcrel = 1; 5944 ++CURR_SLOT.num_fixups; 5945 return OPERAND_MATCH; 5946 5947 default: 5948 break; 5949 } 5950 break; 5951 5952 case IA64_OPND_LDXMOV: 5953 fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; 5954 fix->code = BFD_RELOC_IA64_LDXMOV; 5955 fix->opnd = idesc->operands[res_index]; 5956 fix->expr = *e; 5957 fix->is_pcrel = 0; 5958 ++CURR_SLOT.num_fixups; 5959 return OPERAND_MATCH; 5960 5961 case IA64_OPND_STRD5b: 5962 if (e->X_op == O_constant) 5963 { 5964 /* 5-bit signed scaled by 64 */ 5965 if ((e->X_add_number <= ( 0xf << 6 )) 5966 && (e->X_add_number >= -( 0x10 << 6 ))) 5967 { 5968 5969 /* Must be a multiple of 64 */ 5970 if ((e->X_add_number & 0x3f) != 0) 5971 as_warn (_("stride must be a multiple of 64; lower 6 bits ignored")); 5972 5973 e->X_add_number &= ~ 0x3f; 5974 return OPERAND_MATCH; 5975 } 5976 else 5977 return OPERAND_OUT_OF_RANGE; 5978 } 5979 break; 5980 case IA64_OPND_CNT6a: 5981 if (e->X_op == O_constant) 5982 { 5983 /* 6-bit unsigned biased by 1 -- count 0 is meaningless */ 5984 if ((e->X_add_number <= 64) 5985 && (e->X_add_number > 0) ) 5986 { 5987 return OPERAND_MATCH; 5988 } 5989 else 5990 return OPERAND_OUT_OF_RANGE; 5991 } 5992 break; 5993 5994 default: 5995 break; 5996 } 5997 return OPERAND_MISMATCH; 5998} 5999 6000static int 6001parse_operand (expressionS *e, int more) 6002{ 6003 int sep = '\0'; 6004 6005 memset (e, 0, sizeof (*e)); 6006 e->X_op = O_absent; 6007 SKIP_WHITESPACE (); 6008 expression (e); 6009 sep = *input_line_pointer; 6010 if (more && (sep == ',' || sep == more)) 6011 ++input_line_pointer; 6012 return sep; 6013} 6014 6015static int 6016parse_operand_and_eval (expressionS *e, int more) 6017{ 6018 int sep = parse_operand (e, more); 6019 resolve_expression (e); 6020 return sep; 6021} 6022 6023static int 6024parse_operand_maybe_eval (expressionS *e, int more, enum ia64_opnd op) 6025{ 6026 int sep = parse_operand (e, more); 6027 switch (op) 6028 { 6029 case IA64_OPND_IMM14: 6030 case IA64_OPND_IMM22: 6031 case IA64_OPND_IMMU64: 6032 case IA64_OPND_TGT25: 6033 case IA64_OPND_TGT25b: 6034 case IA64_OPND_TGT25c: 6035 case IA64_OPND_TGT64: 6036 case IA64_OPND_TAG13: 6037 case IA64_OPND_TAG13b: 6038 case IA64_OPND_LDXMOV: 6039 break; 6040 default: 6041 resolve_expression (e); 6042 break; 6043 } 6044 return sep; 6045} 6046 6047/* Returns the next entry in the opcode table that matches the one in 6048 IDESC, and frees the entry in IDESC. If no matching entry is 6049 found, NULL is returned instead. */ 6050 6051static struct ia64_opcode * 6052get_next_opcode (struct ia64_opcode *idesc) 6053{ 6054 struct ia64_opcode *next = ia64_find_next_opcode (idesc); 6055 ia64_free_opcode (idesc); 6056 return next; 6057} 6058 6059/* Parse the operands for the opcode and find the opcode variant that 6060 matches the specified operands, or NULL if no match is possible. */ 6061 6062static struct ia64_opcode * 6063parse_operands (struct ia64_opcode *idesc) 6064{ 6065 int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; 6066 int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; 6067 int reg1, reg2; 6068 char reg_class; 6069 enum ia64_opnd expected_operand = IA64_OPND_NIL; 6070 enum operand_match_result result; 6071 char mnemonic[129]; 6072 char *first_arg = 0, *end, *saved_input_pointer; 6073 unsigned int sof; 6074 6075 gas_assert (strlen (idesc->name) <= 128); 6076 6077 strcpy (mnemonic, idesc->name); 6078 if (idesc->operands[2] == IA64_OPND_SOF 6079 || idesc->operands[1] == IA64_OPND_SOF) 6080 { 6081 /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we 6082 can't parse the first operand until we have parsed the 6083 remaining operands of the "alloc" instruction. */ 6084 SKIP_WHITESPACE (); 6085 first_arg = input_line_pointer; 6086 end = strchr (input_line_pointer, '='); 6087 if (!end) 6088 { 6089 as_bad (_("Expected separator `='")); 6090 return 0; 6091 } 6092 input_line_pointer = end + 1; 6093 ++i; 6094 ++num_outputs; 6095 } 6096 6097 for (; ; ++i) 6098 { 6099 if (i < NELEMS (CURR_SLOT.opnd)) 6100 { 6101 enum ia64_opnd op = IA64_OPND_NIL; 6102 if (i < NELEMS (idesc->operands)) 6103 op = idesc->operands[i]; 6104 sep = parse_operand_maybe_eval (CURR_SLOT.opnd + i, '=', op); 6105 if (CURR_SLOT.opnd[i].X_op == O_absent) 6106 break; 6107 } 6108 else 6109 { 6110 expressionS dummy; 6111 6112 sep = parse_operand (&dummy, '='); 6113 if (dummy.X_op == O_absent) 6114 break; 6115 } 6116 6117 ++num_operands; 6118 6119 if (sep != '=' && sep != ',') 6120 break; 6121 6122 if (sep == '=') 6123 { 6124 if (num_outputs > 0) 6125 as_bad (_("Duplicate equal sign (=) in instruction")); 6126 else 6127 num_outputs = i + 1; 6128 } 6129 } 6130 if (sep != '\0') 6131 { 6132 as_bad (_("Illegal operand separator `%c'"), sep); 6133 return 0; 6134 } 6135 6136 if (idesc->operands[2] == IA64_OPND_SOF 6137 || idesc->operands[1] == IA64_OPND_SOF) 6138 { 6139 /* Map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r. 6140 Note, however, that due to that mapping operand numbers in error 6141 messages for any of the constant operands will not be correct. */ 6142 know (strcmp (idesc->name, "alloc") == 0); 6143 /* The first operand hasn't been parsed/initialized, yet (but 6144 num_operands intentionally doesn't account for that). */ 6145 i = num_operands > 4 ? 2 : 1; 6146#define FORCE_CONST(n) (CURR_SLOT.opnd[n].X_op == O_constant \ 6147 ? CURR_SLOT.opnd[n].X_add_number \ 6148 : 0) 6149 sof = set_regstack (FORCE_CONST(i), 6150 FORCE_CONST(i + 1), 6151 FORCE_CONST(i + 2), 6152 FORCE_CONST(i + 3)); 6153#undef FORCE_CONST 6154 6155 /* now we can parse the first arg: */ 6156 saved_input_pointer = input_line_pointer; 6157 input_line_pointer = first_arg; 6158 sep = parse_operand_maybe_eval (CURR_SLOT.opnd + 0, '=', 6159 idesc->operands[0]); 6160 if (sep != '=') 6161 --num_outputs; /* force error */ 6162 input_line_pointer = saved_input_pointer; 6163 6164 CURR_SLOT.opnd[i].X_add_number = sof; 6165 if (CURR_SLOT.opnd[i + 1].X_op == O_constant 6166 && CURR_SLOT.opnd[i + 2].X_op == O_constant) 6167 CURR_SLOT.opnd[i + 1].X_add_number 6168 = sof - CURR_SLOT.opnd[i + 2].X_add_number; 6169 else 6170 CURR_SLOT.opnd[i + 1].X_op = O_illegal; 6171 CURR_SLOT.opnd[i + 2] = CURR_SLOT.opnd[i + 3]; 6172 } 6173 6174 highest_unmatched_operand = -4; 6175 curr_out_of_range_pos = -1; 6176 error_pos = 0; 6177 for (; idesc; idesc = get_next_opcode (idesc)) 6178 { 6179 if (num_outputs != idesc->num_outputs) 6180 continue; /* mismatch in # of outputs */ 6181 if (highest_unmatched_operand < 0) 6182 highest_unmatched_operand |= 1; 6183 if (num_operands > NELEMS (idesc->operands) 6184 || (num_operands < NELEMS (idesc->operands) 6185 && idesc->operands[num_operands]) 6186 || (num_operands > 0 && !idesc->operands[num_operands - 1])) 6187 continue; /* mismatch in number of arguments */ 6188 if (highest_unmatched_operand < 0) 6189 highest_unmatched_operand |= 2; 6190 6191 CURR_SLOT.num_fixups = 0; 6192 6193 /* Try to match all operands. If we see an out-of-range operand, 6194 then continue trying to match the rest of the operands, since if 6195 the rest match, then this idesc will give the best error message. */ 6196 6197 out_of_range_pos = -1; 6198 for (i = 0; i < num_operands && idesc->operands[i]; ++i) 6199 { 6200 result = operand_match (idesc, i, CURR_SLOT.opnd + i); 6201 if (result != OPERAND_MATCH) 6202 { 6203 if (result != OPERAND_OUT_OF_RANGE) 6204 break; 6205 if (out_of_range_pos < 0) 6206 /* remember position of the first out-of-range operand: */ 6207 out_of_range_pos = i; 6208 } 6209 } 6210 6211 /* If we did not match all operands, or if at least one operand was 6212 out-of-range, then this idesc does not match. Keep track of which 6213 idesc matched the most operands before failing. If we have two 6214 idescs that failed at the same position, and one had an out-of-range 6215 operand, then prefer the out-of-range operand. Thus if we have 6216 "add r0=0x1000000,r1" we get an error saying the constant is out 6217 of range instead of an error saying that the constant should have been 6218 a register. */ 6219 6220 if (i != num_operands || out_of_range_pos >= 0) 6221 { 6222 if (i > highest_unmatched_operand 6223 || (i == highest_unmatched_operand 6224 && out_of_range_pos > curr_out_of_range_pos)) 6225 { 6226 highest_unmatched_operand = i; 6227 if (out_of_range_pos >= 0) 6228 { 6229 expected_operand = idesc->operands[out_of_range_pos]; 6230 error_pos = out_of_range_pos; 6231 } 6232 else 6233 { 6234 expected_operand = idesc->operands[i]; 6235 error_pos = i; 6236 } 6237 curr_out_of_range_pos = out_of_range_pos; 6238 } 6239 continue; 6240 } 6241 6242 break; 6243 } 6244 if (!idesc) 6245 { 6246 if (expected_operand) 6247 as_bad (_("Operand %u of `%s' should be %s"), 6248 error_pos + 1, mnemonic, 6249 elf64_ia64_operands[expected_operand].desc); 6250 else if (highest_unmatched_operand < 0 && !(highest_unmatched_operand & 1)) 6251 as_bad (_("Wrong number of output operands")); 6252 else if (highest_unmatched_operand < 0 && !(highest_unmatched_operand & 2)) 6253 as_bad (_("Wrong number of input operands")); 6254 else 6255 as_bad (_("Operand mismatch")); 6256 return 0; 6257 } 6258 6259 /* Check that the instruction doesn't use 6260 - r0, f0, or f1 as output operands 6261 - the same predicate twice as output operands 6262 - r0 as address of a base update load or store 6263 - the same GR as output and address of a base update load 6264 - two even- or two odd-numbered FRs as output operands of a floating 6265 point parallel load. 6266 At most two (conflicting) output (or output-like) operands can exist, 6267 (floating point parallel loads have three outputs, but the base register, 6268 if updated, cannot conflict with the actual outputs). */ 6269 reg2 = reg1 = -1; 6270 for (i = 0; i < num_operands; ++i) 6271 { 6272 int regno = 0; 6273 6274 reg_class = 0; 6275 switch (idesc->operands[i]) 6276 { 6277 case IA64_OPND_R1: 6278 case IA64_OPND_R2: 6279 case IA64_OPND_R3: 6280 if (i < num_outputs) 6281 { 6282 if (CURR_SLOT.opnd[i].X_add_number == REG_GR) 6283 reg_class = 'r'; 6284 else if (reg1 < 0) 6285 reg1 = CURR_SLOT.opnd[i].X_add_number; 6286 else if (reg2 < 0) 6287 reg2 = CURR_SLOT.opnd[i].X_add_number; 6288 } 6289 break; 6290 case IA64_OPND_P1: 6291 case IA64_OPND_P2: 6292 if (i < num_outputs) 6293 { 6294 if (reg1 < 0) 6295 reg1 = CURR_SLOT.opnd[i].X_add_number; 6296 else if (reg2 < 0) 6297 reg2 = CURR_SLOT.opnd[i].X_add_number; 6298 } 6299 break; 6300 case IA64_OPND_F1: 6301 case IA64_OPND_F2: 6302 case IA64_OPND_F3: 6303 case IA64_OPND_F4: 6304 if (i < num_outputs) 6305 { 6306 if (CURR_SLOT.opnd[i].X_add_number >= REG_FR 6307 && CURR_SLOT.opnd[i].X_add_number <= REG_FR + 1) 6308 { 6309 reg_class = 'f'; 6310 regno = CURR_SLOT.opnd[i].X_add_number - REG_FR; 6311 } 6312 else if (reg1 < 0) 6313 reg1 = CURR_SLOT.opnd[i].X_add_number; 6314 else if (reg2 < 0) 6315 reg2 = CURR_SLOT.opnd[i].X_add_number; 6316 } 6317 break; 6318 case IA64_OPND_MR3: 6319 if (idesc->flags & IA64_OPCODE_POSTINC) 6320 { 6321 if (CURR_SLOT.opnd[i].X_add_number == REG_GR) 6322 reg_class = 'm'; 6323 else if (reg1 < 0) 6324 reg1 = CURR_SLOT.opnd[i].X_add_number; 6325 else if (reg2 < 0) 6326 reg2 = CURR_SLOT.opnd[i].X_add_number; 6327 } 6328 break; 6329 default: 6330 break; 6331 } 6332 switch (reg_class) 6333 { 6334 case 0: 6335 break; 6336 default: 6337 as_warn (_("Invalid use of `%c%d' as output operand"), reg_class, regno); 6338 break; 6339 case 'm': 6340 as_warn (_("Invalid use of `r%d' as base update address operand"), regno); 6341 break; 6342 } 6343 } 6344 if (reg1 == reg2) 6345 { 6346 if (reg1 >= REG_GR && reg1 <= REG_GR + 127) 6347 { 6348 reg1 -= REG_GR; 6349 reg_class = 'r'; 6350 } 6351 else if (reg1 >= REG_P && reg1 <= REG_P + 63) 6352 { 6353 reg1 -= REG_P; 6354 reg_class = 'p'; 6355 } 6356 else if (reg1 >= REG_FR && reg1 <= REG_FR + 127) 6357 { 6358 reg1 -= REG_FR; 6359 reg_class = 'f'; 6360 } 6361 else 6362 reg_class = 0; 6363 if (reg_class) 6364 as_warn (_("Invalid duplicate use of `%c%d'"), reg_class, reg1); 6365 } 6366 else if (((reg1 >= REG_FR && reg1 <= REG_FR + 31 6367 && reg2 >= REG_FR && reg2 <= REG_FR + 31) 6368 || (reg1 >= REG_FR + 32 && reg1 <= REG_FR + 127 6369 && reg2 >= REG_FR + 32 && reg2 <= REG_FR + 127)) 6370 && ! ((reg1 ^ reg2) & 1)) 6371 as_warn (_("Invalid simultaneous use of `f%d' and `f%d'"), 6372 reg1 - REG_FR, reg2 - REG_FR); 6373 else if ((reg1 >= REG_FR && reg1 <= REG_FR + 31 6374 && reg2 >= REG_FR + 32 && reg2 <= REG_FR + 127) 6375 || (reg1 >= REG_FR + 32 && reg1 <= REG_FR + 127 6376 && reg2 >= REG_FR && reg2 <= REG_FR + 31)) 6377 as_warn (_("Dangerous simultaneous use of `f%d' and `f%d'"), 6378 reg1 - REG_FR, reg2 - REG_FR); 6379 return idesc; 6380} 6381 6382static void 6383build_insn (struct slot *slot, bfd_vma *insnp) 6384{ 6385 const struct ia64_operand *odesc, *o2desc; 6386 struct ia64_opcode *idesc = slot->idesc; 6387 bfd_vma insn; 6388 bfd_signed_vma val; 6389 const char *err; 6390 int i; 6391 6392 insn = idesc->opcode | slot->qp_regno; 6393 6394 for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) 6395 { 6396 if (slot->opnd[i].X_op == O_register 6397 || slot->opnd[i].X_op == O_constant 6398 || slot->opnd[i].X_op == O_index) 6399 val = slot->opnd[i].X_add_number; 6400 else if (slot->opnd[i].X_op == O_big) 6401 { 6402 /* This must be the value 0x10000000000000000. */ 6403 gas_assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); 6404 val = 0; 6405 } 6406 else 6407 val = 0; 6408 6409 switch (idesc->operands[i]) 6410 { 6411 case IA64_OPND_IMMU64: 6412 *insnp++ = (val >> 22) & 0x1ffffffffffLL; 6413 insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) 6414 | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) 6415 | (((val >> 63) & 0x1) << 36)); 6416 continue; 6417 6418 case IA64_OPND_IMMU62: 6419 val &= 0x3fffffffffffffffULL; 6420 if (val != slot->opnd[i].X_add_number) 6421 as_warn (_("Value truncated to 62 bits")); 6422 *insnp++ = (val >> 21) & 0x1ffffffffffLL; 6423 insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); 6424 continue; 6425 6426 case IA64_OPND_TGT64: 6427 val >>= 4; 6428 *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; 6429 insn |= ((((val >> 59) & 0x1) << 36) 6430 | (((val >> 0) & 0xfffff) << 13)); 6431 continue; 6432 6433 case IA64_OPND_AR3: 6434 val -= REG_AR; 6435 break; 6436 6437 case IA64_OPND_B1: 6438 case IA64_OPND_B2: 6439 val -= REG_BR; 6440 break; 6441 6442 case IA64_OPND_CR3: 6443 val -= REG_CR; 6444 break; 6445 6446 case IA64_OPND_DAHR3: 6447 val -= REG_DAHR; 6448 break; 6449 6450 case IA64_OPND_F1: 6451 case IA64_OPND_F2: 6452 case IA64_OPND_F3: 6453 case IA64_OPND_F4: 6454 val -= REG_FR; 6455 break; 6456 6457 case IA64_OPND_P1: 6458 case IA64_OPND_P2: 6459 val -= REG_P; 6460 break; 6461 6462 case IA64_OPND_R1: 6463 case IA64_OPND_R2: 6464 case IA64_OPND_R3: 6465 case IA64_OPND_R3_2: 6466 case IA64_OPND_CPUID_R3: 6467 case IA64_OPND_DBR_R3: 6468 case IA64_OPND_DTR_R3: 6469 case IA64_OPND_ITR_R3: 6470 case IA64_OPND_IBR_R3: 6471 case IA64_OPND_MR3: 6472 case IA64_OPND_MSR_R3: 6473 case IA64_OPND_PKR_R3: 6474 case IA64_OPND_PMC_R3: 6475 case IA64_OPND_PMD_R3: 6476 case IA64_OPND_DAHR_R3: 6477 case IA64_OPND_RR_R3: 6478 val -= REG_GR; 6479 break; 6480 6481 default: 6482 break; 6483 } 6484 6485 odesc = elf64_ia64_operands + idesc->operands[i]; 6486 err = (*odesc->insert) (odesc, val, &insn); 6487 if (err) 6488 as_bad_where (slot->src_file, slot->src_line, 6489 _("Bad operand value: %s"), err); 6490 if (idesc->flags & IA64_OPCODE_PSEUDO) 6491 { 6492 if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) 6493 && odesc == elf64_ia64_operands + IA64_OPND_F3) 6494 { 6495 o2desc = elf64_ia64_operands + IA64_OPND_F2; 6496 (*o2desc->insert) (o2desc, val, &insn); 6497 } 6498 if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) 6499 && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a 6500 || odesc == elf64_ia64_operands + IA64_OPND_POS6)) 6501 { 6502 o2desc = elf64_ia64_operands + IA64_OPND_LEN6; 6503 (*o2desc->insert) (o2desc, 64 - val, &insn); 6504 } 6505 } 6506 } 6507 *insnp = insn; 6508} 6509 6510static void 6511emit_one_bundle (void) 6512{ 6513 int manual_bundling_off = 0, manual_bundling = 0; 6514 enum ia64_unit required_unit, insn_unit = 0; 6515 enum ia64_insn_type type[3], insn_type; 6516 unsigned int template_val, orig_template; 6517 bfd_vma insn[3] = { -1, -1, -1 }; 6518 struct ia64_opcode *idesc; 6519 int end_of_insn_group = 0, user_template = -1; 6520 int n, i, j, first, curr, last_slot; 6521 bfd_vma t0 = 0, t1 = 0; 6522 struct label_fix *lfix; 6523 bfd_boolean mark_label; 6524 struct insn_fix *ifix; 6525 char mnemonic[16]; 6526 fixS *fix; 6527 char *f; 6528 int addr_mod; 6529 6530 first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; 6531 know (first >= 0 && first < NUM_SLOTS); 6532 n = MIN (3, md.num_slots_in_use); 6533 6534 /* Determine template: user user_template if specified, best match 6535 otherwise: */ 6536 6537 if (md.slot[first].user_template >= 0) 6538 user_template = template_val = md.slot[first].user_template; 6539 else 6540 { 6541 /* Auto select appropriate template. */ 6542 memset (type, 0, sizeof (type)); 6543 curr = first; 6544 for (i = 0; i < n; ++i) 6545 { 6546 if (md.slot[curr].label_fixups && i != 0) 6547 break; 6548 type[i] = md.slot[curr].idesc->type; 6549 curr = (curr + 1) % NUM_SLOTS; 6550 } 6551 template_val = best_template[type[0]][type[1]][type[2]]; 6552 } 6553 6554 /* initialize instructions with appropriate nops: */ 6555 for (i = 0; i < 3; ++i) 6556 insn[i] = nop[ia64_templ_desc[template_val].exec_unit[i]]; 6557 6558 f = frag_more (16); 6559 6560 /* Check to see if this bundle is at an offset that is a multiple of 16-bytes 6561 from the start of the frag. */ 6562 addr_mod = frag_now_fix () & 15; 6563 if (frag_now->has_code && frag_now->insn_addr != addr_mod) 6564 as_bad (_("instruction address is not a multiple of 16")); 6565 frag_now->insn_addr = addr_mod; 6566 frag_now->has_code = 1; 6567 6568 /* now fill in slots with as many insns as possible: */ 6569 curr = first; 6570 idesc = md.slot[curr].idesc; 6571 end_of_insn_group = 0; 6572 last_slot = -1; 6573 for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) 6574 { 6575 /* If we have unwind records, we may need to update some now. */ 6576 unw_rec_list *ptr = md.slot[curr].unwind_record; 6577 unw_rec_list *end_ptr = NULL; 6578 6579 if (ptr) 6580 { 6581 /* Find the last prologue/body record in the list for the current 6582 insn, and set the slot number for all records up to that point. 6583 This needs to be done now, because prologue/body records refer to 6584 the current point, not the point after the instruction has been 6585 issued. This matters because there may have been nops emitted 6586 meanwhile. Any non-prologue non-body record followed by a 6587 prologue/body record must also refer to the current point. */ 6588 unw_rec_list *last_ptr; 6589 6590 for (j = 1; end_ptr == NULL && j < md.num_slots_in_use; ++j) 6591 end_ptr = md.slot[(curr + j) % NUM_SLOTS].unwind_record; 6592 for (last_ptr = NULL; ptr != end_ptr; ptr = ptr->next) 6593 if (ptr->r.type == prologue || ptr->r.type == prologue_gr 6594 || ptr->r.type == body) 6595 last_ptr = ptr; 6596 if (last_ptr) 6597 { 6598 /* Make last_ptr point one after the last prologue/body 6599 record. */ 6600 last_ptr = last_ptr->next; 6601 for (ptr = md.slot[curr].unwind_record; ptr != last_ptr; 6602 ptr = ptr->next) 6603 { 6604 ptr->slot_number = (unsigned long) f + i; 6605 ptr->slot_frag = frag_now; 6606 } 6607 /* Remove the initialized records, so that we won't accidentally 6608 update them again if we insert a nop and continue. */ 6609 md.slot[curr].unwind_record = last_ptr; 6610 } 6611 } 6612 6613 manual_bundling_off = md.slot[curr].manual_bundling_off; 6614 if (md.slot[curr].manual_bundling_on) 6615 { 6616 if (curr == first) 6617 manual_bundling = 1; 6618 else 6619 break; /* Need to start a new bundle. */ 6620 } 6621 6622 /* If this instruction specifies a template, then it must be the first 6623 instruction of a bundle. */ 6624 if (curr != first && md.slot[curr].user_template >= 0) 6625 break; 6626 6627 if (idesc->flags & IA64_OPCODE_SLOT2) 6628 { 6629 if (manual_bundling && !manual_bundling_off) 6630 { 6631 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6632 _("`%s' must be last in bundle"), idesc->name); 6633 if (i < 2) 6634 manual_bundling = -1; /* Suppress meaningless post-loop errors. */ 6635 } 6636 i = 2; 6637 } 6638 if (idesc->flags & IA64_OPCODE_LAST) 6639 { 6640 int required_slot; 6641 unsigned int required_template; 6642 6643 /* If we need a stop bit after an M slot, our only choice is 6644 template 5 (M;;MI). If we need a stop bit after a B 6645 slot, our only choice is to place it at the end of the 6646 bundle, because the only available templates are MIB, 6647 MBB, BBB, MMB, and MFB. We don't handle anything other 6648 than M and B slots because these are the only kind of 6649 instructions that can have the IA64_OPCODE_LAST bit set. */ 6650 required_template = template_val; 6651 switch (idesc->type) 6652 { 6653 case IA64_TYPE_M: 6654 required_slot = 0; 6655 required_template = 5; 6656 break; 6657 6658 case IA64_TYPE_B: 6659 required_slot = 2; 6660 break; 6661 6662 default: 6663 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6664 _("Internal error: don't know how to force %s to end of instruction group"), 6665 idesc->name); 6666 required_slot = i; 6667 break; 6668 } 6669 if (manual_bundling 6670 && (i > required_slot 6671 || (required_slot == 2 && !manual_bundling_off) 6672 || (user_template >= 0 6673 /* Changing from MMI to M;MI is OK. */ 6674 && (template_val ^ required_template) > 1))) 6675 { 6676 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6677 _("`%s' must be last in instruction group"), 6678 idesc->name); 6679 if (i < 2 && required_slot == 2 && !manual_bundling_off) 6680 manual_bundling = -1; /* Suppress meaningless post-loop errors. */ 6681 } 6682 if (required_slot < i) 6683 /* Can't fit this instruction. */ 6684 break; 6685 6686 i = required_slot; 6687 if (required_template != template_val) 6688 { 6689 /* If we switch the template, we need to reset the NOPs 6690 after slot i. The slot-types of the instructions ahead 6691 of i never change, so we don't need to worry about 6692 changing NOPs in front of this slot. */ 6693 for (j = i; j < 3; ++j) 6694 insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; 6695 6696 /* We just picked a template that includes the stop bit in the 6697 middle, so we don't need another one emitted later. */ 6698 md.slot[curr].end_of_insn_group = 0; 6699 } 6700 template_val = required_template; 6701 } 6702 if (curr != first && md.slot[curr].label_fixups) 6703 { 6704 if (manual_bundling) 6705 { 6706 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6707 _("Label must be first in a bundle")); 6708 manual_bundling = -1; /* Suppress meaningless post-loop errors. */ 6709 } 6710 /* This insn must go into the first slot of a bundle. */ 6711 break; 6712 } 6713 6714 if (end_of_insn_group && md.num_slots_in_use >= 1) 6715 { 6716 /* We need an instruction group boundary in the middle of a 6717 bundle. See if we can switch to an other template with 6718 an appropriate boundary. */ 6719 6720 orig_template = template_val; 6721 if (i == 1 && (user_template == 4 6722 || (user_template < 0 6723 && (ia64_templ_desc[template_val].exec_unit[0] 6724 == IA64_UNIT_M)))) 6725 { 6726 template_val = 5; 6727 end_of_insn_group = 0; 6728 } 6729 else if (i == 2 && (user_template == 0 6730 || (user_template < 0 6731 && (ia64_templ_desc[template_val].exec_unit[1] 6732 == IA64_UNIT_I))) 6733 /* This test makes sure we don't switch the template if 6734 the next instruction is one that needs to be first in 6735 an instruction group. Since all those instructions are 6736 in the M group, there is no way such an instruction can 6737 fit in this bundle even if we switch the template. The 6738 reason we have to check for this is that otherwise we 6739 may end up generating "MI;;I M.." which has the deadly 6740 effect that the second M instruction is no longer the 6741 first in the group! --davidm 99/12/16 */ 6742 && (idesc->flags & IA64_OPCODE_FIRST) == 0) 6743 { 6744 template_val = 1; 6745 end_of_insn_group = 0; 6746 } 6747 else if (i == 1 6748 && user_template == 0 6749 && !(idesc->flags & IA64_OPCODE_FIRST)) 6750 /* Use the next slot. */ 6751 continue; 6752 else if (curr != first) 6753 /* can't fit this insn */ 6754 break; 6755 6756 if (template_val != orig_template) 6757 /* if we switch the template, we need to reset the NOPs 6758 after slot i. The slot-types of the instructions ahead 6759 of i never change, so we don't need to worry about 6760 changing NOPs in front of this slot. */ 6761 for (j = i; j < 3; ++j) 6762 insn[j] = nop[ia64_templ_desc[template_val].exec_unit[j]]; 6763 } 6764 required_unit = ia64_templ_desc[template_val].exec_unit[i]; 6765 6766 /* resolve dynamic opcodes such as "break", "hint", and "nop": */ 6767 if (idesc->type == IA64_TYPE_DYN) 6768 { 6769 enum ia64_opnd opnd1, opnd2; 6770 6771 if ((strcmp (idesc->name, "nop") == 0) 6772 || (strcmp (idesc->name, "break") == 0)) 6773 insn_unit = required_unit; 6774 else if (strcmp (idesc->name, "hint") == 0) 6775 { 6776 insn_unit = required_unit; 6777 if (required_unit == IA64_UNIT_B) 6778 { 6779 switch (md.hint_b) 6780 { 6781 case hint_b_ok: 6782 break; 6783 case hint_b_warning: 6784 as_warn (_("hint in B unit may be treated as nop")); 6785 break; 6786 case hint_b_error: 6787 /* When manual bundling is off and there is no 6788 user template, we choose a different unit so 6789 that hint won't go into the current slot. We 6790 will fill the current bundle with nops and 6791 try to put hint into the next bundle. */ 6792 if (!manual_bundling && user_template < 0) 6793 insn_unit = IA64_UNIT_I; 6794 else 6795 as_bad (_("hint in B unit can't be used")); 6796 break; 6797 } 6798 } 6799 } 6800 else if (strcmp (idesc->name, "chk.s") == 0 6801 || strcmp (idesc->name, "mov") == 0) 6802 { 6803 insn_unit = IA64_UNIT_M; 6804 if (required_unit == IA64_UNIT_I 6805 || (required_unit == IA64_UNIT_F && template_val == 6)) 6806 insn_unit = IA64_UNIT_I; 6807 } 6808 else 6809 as_fatal (_("emit_one_bundle: unexpected dynamic op")); 6810 6811 snprintf (mnemonic, sizeof (mnemonic), "%s.%c", 6812 idesc->name, "?imbfxx"[insn_unit]); 6813 opnd1 = idesc->operands[0]; 6814 opnd2 = idesc->operands[1]; 6815 ia64_free_opcode (idesc); 6816 idesc = ia64_find_opcode (mnemonic); 6817 /* moves to/from ARs have collisions */ 6818 if (opnd1 == IA64_OPND_AR3 || opnd2 == IA64_OPND_AR3) 6819 { 6820 while (idesc != NULL 6821 && (idesc->operands[0] != opnd1 6822 || idesc->operands[1] != opnd2)) 6823 idesc = get_next_opcode (idesc); 6824 } 6825 md.slot[curr].idesc = idesc; 6826 } 6827 else 6828 { 6829 insn_type = idesc->type; 6830 insn_unit = IA64_UNIT_NIL; 6831 switch (insn_type) 6832 { 6833 case IA64_TYPE_A: 6834 if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) 6835 insn_unit = required_unit; 6836 break; 6837 case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; 6838 case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; 6839 case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; 6840 case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; 6841 case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; 6842 default: break; 6843 } 6844 } 6845 6846 if (insn_unit != required_unit) 6847 continue; /* Try next slot. */ 6848 6849 /* Now is a good time to fix up the labels for this insn. */ 6850 mark_label = FALSE; 6851 for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) 6852 { 6853 S_SET_VALUE (lfix->sym, frag_now_fix () - 16); 6854 symbol_set_frag (lfix->sym, frag_now); 6855 mark_label |= lfix->dw2_mark_labels; 6856 } 6857 for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) 6858 { 6859 S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); 6860 symbol_set_frag (lfix->sym, frag_now); 6861 } 6862 6863 if (debug_type == DEBUG_DWARF2 6864 || md.slot[curr].loc_directive_seen 6865 || mark_label) 6866 { 6867 bfd_vma addr = frag_now->fr_address + frag_now_fix () - 16 + i; 6868 6869 md.slot[curr].loc_directive_seen = 0; 6870 if (mark_label) 6871 md.slot[curr].debug_line.flags |= DWARF2_FLAG_BASIC_BLOCK; 6872 6873 dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); 6874 } 6875 6876 build_insn (md.slot + curr, insn + i); 6877 6878 ptr = md.slot[curr].unwind_record; 6879 if (ptr) 6880 { 6881 /* Set slot numbers for all remaining unwind records belonging to the 6882 current insn. There can not be any prologue/body unwind records 6883 here. */ 6884 for (; ptr != end_ptr; ptr = ptr->next) 6885 { 6886 ptr->slot_number = (unsigned long) f + i; 6887 ptr->slot_frag = frag_now; 6888 } 6889 md.slot[curr].unwind_record = NULL; 6890 } 6891 6892 for (j = 0; j < md.slot[curr].num_fixups; ++j) 6893 { 6894 ifix = md.slot[curr].fixup + j; 6895 fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, 6896 &ifix->expr, ifix->is_pcrel, ifix->code); 6897 fix->tc_fix_data.opnd = ifix->opnd; 6898 fix->fx_file = md.slot[curr].src_file; 6899 fix->fx_line = md.slot[curr].src_line; 6900 } 6901 6902 end_of_insn_group = md.slot[curr].end_of_insn_group; 6903 6904 /* This adjustment to "i" must occur after the fix, otherwise the fix 6905 is assigned to the wrong slot, and the VMS linker complains. */ 6906 if (required_unit == IA64_UNIT_L) 6907 { 6908 know (i == 1); 6909 /* skip one slot for long/X-unit instructions */ 6910 ++i; 6911 } 6912 --md.num_slots_in_use; 6913 last_slot = i; 6914 6915 /* clear slot: */ 6916 ia64_free_opcode (md.slot[curr].idesc); 6917 memset (md.slot + curr, 0, sizeof (md.slot[curr])); 6918 md.slot[curr].user_template = -1; 6919 6920 if (manual_bundling_off) 6921 { 6922 manual_bundling = 0; 6923 break; 6924 } 6925 curr = (curr + 1) % NUM_SLOTS; 6926 idesc = md.slot[curr].idesc; 6927 } 6928 6929 /* A user template was specified, but the first following instruction did 6930 not fit. This can happen with or without manual bundling. */ 6931 if (md.num_slots_in_use > 0 && last_slot < 0) 6932 { 6933 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6934 _("`%s' does not fit into %s template"), 6935 idesc->name, ia64_templ_desc[template_val].name); 6936 /* Drop first insn so we don't livelock. */ 6937 --md.num_slots_in_use; 6938 know (curr == first); 6939 ia64_free_opcode (md.slot[curr].idesc); 6940 memset (md.slot + curr, 0, sizeof (md.slot[curr])); 6941 md.slot[curr].user_template = -1; 6942 } 6943 else if (manual_bundling > 0) 6944 { 6945 if (md.num_slots_in_use > 0) 6946 { 6947 if (last_slot >= 2) 6948 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6949 _("`%s' does not fit into bundle"), idesc->name); 6950 else 6951 { 6952 const char *where; 6953 6954 if (template_val == 2) 6955 where = "X slot"; 6956 else if (last_slot == 0) 6957 where = "slots 2 or 3"; 6958 else 6959 where = "slot 3"; 6960 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6961 _("`%s' can't go in %s of %s template"), 6962 idesc->name, where, ia64_templ_desc[template_val].name); 6963 } 6964 } 6965 else 6966 as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, 6967 _("Missing '}' at end of file")); 6968 } 6969 6970 know (md.num_slots_in_use < NUM_SLOTS); 6971 6972 t0 = end_of_insn_group | (template_val << 1) | (insn[0] << 5) | (insn[1] << 46); 6973 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 6974 6975 number_to_chars_littleendian (f + 0, t0, 8); 6976 number_to_chars_littleendian (f + 8, t1, 8); 6977} 6978 6979int 6980md_parse_option (int c, const char *arg) 6981{ 6982 6983 switch (c) 6984 { 6985 /* Switches from the Intel assembler. */ 6986 case 'm': 6987 if (strcmp (arg, "ilp64") == 0 6988 || strcmp (arg, "lp64") == 0 6989 || strcmp (arg, "p64") == 0) 6990 { 6991 md.flags |= EF_IA_64_ABI64; 6992 } 6993 else if (strcmp (arg, "ilp32") == 0) 6994 { 6995 md.flags &= ~EF_IA_64_ABI64; 6996 } 6997 else if (strcmp (arg, "le") == 0) 6998 { 6999 md.flags &= ~EF_IA_64_BE; 7000 default_big_endian = 0; 7001 } 7002 else if (strcmp (arg, "be") == 0) 7003 { 7004 md.flags |= EF_IA_64_BE; 7005 default_big_endian = 1; 7006 } 7007 else if (strncmp (arg, "unwind-check=", 13) == 0) 7008 { 7009 arg += 13; 7010 if (strcmp (arg, "warning") == 0) 7011 md.unwind_check = unwind_check_warning; 7012 else if (strcmp (arg, "error") == 0) 7013 md.unwind_check = unwind_check_error; 7014 else 7015 return 0; 7016 } 7017 else if (strncmp (arg, "hint.b=", 7) == 0) 7018 { 7019 arg += 7; 7020 if (strcmp (arg, "ok") == 0) 7021 md.hint_b = hint_b_ok; 7022 else if (strcmp (arg, "warning") == 0) 7023 md.hint_b = hint_b_warning; 7024 else if (strcmp (arg, "error") == 0) 7025 md.hint_b = hint_b_error; 7026 else 7027 return 0; 7028 } 7029 else if (strncmp (arg, "tune=", 5) == 0) 7030 { 7031 arg += 5; 7032 if (strcmp (arg, "itanium1") == 0) 7033 md.tune = itanium1; 7034 else if (strcmp (arg, "itanium2") == 0) 7035 md.tune = itanium2; 7036 else 7037 return 0; 7038 } 7039 else 7040 return 0; 7041 break; 7042 7043 case 'N': 7044 if (strcmp (arg, "so") == 0) 7045 { 7046 /* Suppress signon message. */ 7047 } 7048 else if (strcmp (arg, "pi") == 0) 7049 { 7050 /* Reject privileged instructions. FIXME */ 7051 } 7052 else if (strcmp (arg, "us") == 0) 7053 { 7054 /* Allow union of signed and unsigned range. FIXME */ 7055 } 7056 else if (strcmp (arg, "close_fcalls") == 0) 7057 { 7058 /* Do not resolve global function calls. */ 7059 } 7060 else 7061 return 0; 7062 break; 7063 7064 case 'C': 7065 /* temp[="prefix"] Insert temporary labels into the object file 7066 symbol table prefixed by "prefix". 7067 Default prefix is ":temp:". 7068 */ 7069 break; 7070 7071 case 'a': 7072 /* indirect=<tgt> Assume unannotated indirect branches behavior 7073 according to <tgt> -- 7074 exit: branch out from the current context (default) 7075 labels: all labels in context may be branch targets 7076 */ 7077 if (strncmp (arg, "indirect=", 9) != 0) 7078 return 0; 7079 break; 7080 7081 case 'x': 7082 /* -X conflicts with an ignored option, use -x instead */ 7083 md.detect_dv = 1; 7084 if (!arg || strcmp (arg, "explicit") == 0) 7085 { 7086 /* set default mode to explicit */ 7087 md.default_explicit_mode = 1; 7088 break; 7089 } 7090 else if (strcmp (arg, "auto") == 0) 7091 { 7092 md.default_explicit_mode = 0; 7093 } 7094 else if (strcmp (arg, "none") == 0) 7095 { 7096 md.detect_dv = 0; 7097 } 7098 else if (strcmp (arg, "debug") == 0) 7099 { 7100 md.debug_dv = 1; 7101 } 7102 else if (strcmp (arg, "debugx") == 0) 7103 { 7104 md.default_explicit_mode = 1; 7105 md.debug_dv = 1; 7106 } 7107 else if (strcmp (arg, "debugn") == 0) 7108 { 7109 md.debug_dv = 1; 7110 md.detect_dv = 0; 7111 } 7112 else 7113 { 7114 as_bad (_("Unrecognized option '-x%s'"), arg); 7115 } 7116 break; 7117 7118 case 'S': 7119 /* nops Print nops statistics. */ 7120 break; 7121 7122 /* GNU specific switches for gcc. */ 7123 case OPTION_MCONSTANT_GP: 7124 md.flags |= EF_IA_64_CONS_GP; 7125 break; 7126 7127 case OPTION_MAUTO_PIC: 7128 md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; 7129 break; 7130 7131 default: 7132 return 0; 7133 } 7134 7135 return 1; 7136} 7137 7138void 7139md_show_usage (FILE *stream) 7140{ 7141 fputs (_("\ 7142IA-64 options:\n\ 7143 --mconstant-gp mark output file as using the constant-GP model\n\ 7144 (sets ELF header flag EF_IA_64_CONS_GP)\n\ 7145 --mauto-pic mark output file as using the constant-GP model\n\ 7146 without function descriptors (sets ELF header flag\n\ 7147 EF_IA_64_NOFUNCDESC_CONS_GP)\n\ 7148 -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ 7149 -mle | -mbe select little- or big-endian byte order (default -mle)\n\ 7150 -mtune=[itanium1|itanium2]\n\ 7151 tune for a specific CPU (default -mtune=itanium2)\n\ 7152 -munwind-check=[warning|error]\n\ 7153 unwind directive check (default -munwind-check=warning)\n\ 7154 -mhint.b=[ok|warning|error]\n\ 7155 hint.b check (default -mhint.b=error)\n\ 7156 -x | -xexplicit turn on dependency violation checking\n"), stream); 7157 /* Note for translators: "automagically" can be translated as "automatically" here. */ 7158 fputs (_("\ 7159 -xauto automagically remove dependency violations (default)\n\ 7160 -xnone turn off dependency violation checking\n\ 7161 -xdebug debug dependency violation checker\n\ 7162 -xdebugn debug dependency violation checker but turn off\n\ 7163 dependency violation checking\n\ 7164 -xdebugx debug dependency violation checker and turn on\n\ 7165 dependency violation checking\n"), 7166 stream); 7167} 7168 7169void 7170ia64_after_parse_args (void) 7171{ 7172 if (debug_type == DEBUG_STABS) 7173 as_fatal (_("--gstabs is not supported for ia64")); 7174} 7175 7176/* Return true if TYPE fits in TEMPL at SLOT. */ 7177 7178static int 7179match (int templ, int type, int slot) 7180{ 7181 enum ia64_unit unit; 7182 int result; 7183 7184 unit = ia64_templ_desc[templ].exec_unit[slot]; 7185 switch (type) 7186 { 7187 case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ 7188 case IA64_TYPE_A: 7189 result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); 7190 break; 7191 case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; 7192 case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; 7193 case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; 7194 case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; 7195 case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; 7196 default: result = 0; break; 7197 } 7198 return result; 7199} 7200 7201/* For Itanium 1, add a bit of extra goodness if a nop of type F or B would fit 7202 in TEMPL at SLOT. For Itanium 2, add a bit of extra goodness if a nop of 7203 type M or I would fit in TEMPL at SLOT. */ 7204 7205static inline int 7206extra_goodness (int templ, int slot) 7207{ 7208 switch (md.tune) 7209 { 7210 case itanium1: 7211 if (slot == 1 && match (templ, IA64_TYPE_F, slot)) 7212 return 2; 7213 else if (slot == 2 && match (templ, IA64_TYPE_B, slot)) 7214 return 1; 7215 else 7216 return 0; 7217 break; 7218 case itanium2: 7219 if (match (templ, IA64_TYPE_M, slot) 7220 || match (templ, IA64_TYPE_I, slot)) 7221 /* Favor M- and I-unit NOPs. We definitely want to avoid 7222 F-unit and B-unit may cause split-issue or less-than-optimal 7223 branch-prediction. */ 7224 return 2; 7225 else 7226 return 0; 7227 break; 7228 default: 7229 abort (); 7230 return 0; 7231 } 7232} 7233 7234/* This function is called once, at assembler startup time. It sets 7235 up all the tables, etc. that the MD part of the assembler will need 7236 that can be determined before arguments are parsed. */ 7237void 7238md_begin (void) 7239{ 7240 int i, j, k, t, goodness, best, ok; 7241 7242 md.auto_align = 1; 7243 md.explicit_mode = md.default_explicit_mode; 7244 7245 bfd_set_section_alignment (text_section, 4); 7246 7247 /* Make sure function pointers get initialized. */ 7248 target_big_endian = -1; 7249 dot_byteorder (default_big_endian); 7250 7251 alias_hash = str_htab_create (); 7252 alias_name_hash = str_htab_create (); 7253 secalias_hash = str_htab_create (); 7254 secalias_name_hash = str_htab_create (); 7255 7256 pseudo_func[FUNC_DTP_MODULE].u.sym = 7257 symbol_new (".<dtpmod>", undefined_section, 7258 &zero_address_frag, FUNC_DTP_MODULE); 7259 7260 pseudo_func[FUNC_DTP_RELATIVE].u.sym = 7261 symbol_new (".<dtprel>", undefined_section, 7262 &zero_address_frag, FUNC_DTP_RELATIVE); 7263 7264 pseudo_func[FUNC_FPTR_RELATIVE].u.sym = 7265 symbol_new (".<fptr>", undefined_section, 7266 &zero_address_frag, FUNC_FPTR_RELATIVE); 7267 7268 pseudo_func[FUNC_GP_RELATIVE].u.sym = 7269 symbol_new (".<gprel>", undefined_section, 7270 &zero_address_frag, FUNC_GP_RELATIVE); 7271 7272 pseudo_func[FUNC_LT_RELATIVE].u.sym = 7273 symbol_new (".<ltoff>", undefined_section, 7274 &zero_address_frag, FUNC_LT_RELATIVE); 7275 7276 pseudo_func[FUNC_LT_RELATIVE_X].u.sym = 7277 symbol_new (".<ltoffx>", undefined_section, 7278 &zero_address_frag, FUNC_LT_RELATIVE_X); 7279 7280 pseudo_func[FUNC_PC_RELATIVE].u.sym = 7281 symbol_new (".<pcrel>", undefined_section, 7282 &zero_address_frag, FUNC_PC_RELATIVE); 7283 7284 pseudo_func[FUNC_PLT_RELATIVE].u.sym = 7285 symbol_new (".<pltoff>", undefined_section, 7286 &zero_address_frag, FUNC_PLT_RELATIVE); 7287 7288 pseudo_func[FUNC_SEC_RELATIVE].u.sym = 7289 symbol_new (".<secrel>", undefined_section, 7290 &zero_address_frag, FUNC_SEC_RELATIVE); 7291 7292 pseudo_func[FUNC_SEG_RELATIVE].u.sym = 7293 symbol_new (".<segrel>", undefined_section, 7294 &zero_address_frag, FUNC_SEG_RELATIVE); 7295 7296 pseudo_func[FUNC_TP_RELATIVE].u.sym = 7297 symbol_new (".<tprel>", undefined_section, 7298 &zero_address_frag, FUNC_TP_RELATIVE); 7299 7300 pseudo_func[FUNC_LTV_RELATIVE].u.sym = 7301 symbol_new (".<ltv>", undefined_section, 7302 &zero_address_frag, FUNC_LTV_RELATIVE); 7303 7304 pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = 7305 symbol_new (".<ltoff.fptr>", undefined_section, 7306 &zero_address_frag, FUNC_LT_FPTR_RELATIVE); 7307 7308 pseudo_func[FUNC_LT_DTP_MODULE].u.sym = 7309 symbol_new (".<ltoff.dtpmod>", undefined_section, 7310 &zero_address_frag, FUNC_LT_DTP_MODULE); 7311 7312 pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym = 7313 symbol_new (".<ltoff.dptrel>", undefined_section, 7314 &zero_address_frag, FUNC_LT_DTP_RELATIVE); 7315 7316 pseudo_func[FUNC_LT_TP_RELATIVE].u.sym = 7317 symbol_new (".<ltoff.tprel>", undefined_section, 7318 &zero_address_frag, FUNC_LT_TP_RELATIVE); 7319 7320 pseudo_func[FUNC_IPLT_RELOC].u.sym = 7321 symbol_new (".<iplt>", undefined_section, 7322 &zero_address_frag, FUNC_IPLT_RELOC); 7323 7324#ifdef TE_VMS 7325 pseudo_func[FUNC_SLOTCOUNT_RELOC].u.sym = 7326 symbol_new (".<slotcount>", undefined_section, 7327 &zero_address_frag, FUNC_SLOTCOUNT_RELOC); 7328#endif 7329 7330 if (md.tune != itanium1) 7331 { 7332 /* Convert MFI NOPs bundles into MMI NOPs bundles. */ 7333 le_nop[0] = 0x8; 7334 le_nop_stop[0] = 0x9; 7335 } 7336 7337 /* Compute the table of best templates. We compute goodness as a 7338 base 4 value, in which each match counts for 3. Match-failures 7339 result in NOPs and we use extra_goodness() to pick the execution 7340 units that are best suited for issuing the NOP. */ 7341 for (i = 0; i < IA64_NUM_TYPES; ++i) 7342 for (j = 0; j < IA64_NUM_TYPES; ++j) 7343 for (k = 0; k < IA64_NUM_TYPES; ++k) 7344 { 7345 best = 0; 7346 for (t = 0; t < NELEMS (ia64_templ_desc); ++t) 7347 { 7348 goodness = 0; 7349 if (match (t, i, 0)) 7350 { 7351 if (match (t, j, 1)) 7352 { 7353 if ((t == 2 && j == IA64_TYPE_X) || match (t, k, 2)) 7354 goodness = 3 + 3 + 3; 7355 else 7356 goodness = 3 + 3 + extra_goodness (t, 2); 7357 } 7358 else if (match (t, j, 2)) 7359 goodness = 3 + 3 + extra_goodness (t, 1); 7360 else 7361 { 7362 goodness = 3; 7363 goodness += extra_goodness (t, 1); 7364 goodness += extra_goodness (t, 2); 7365 } 7366 } 7367 else if (match (t, i, 1)) 7368 { 7369 if ((t == 2 && i == IA64_TYPE_X) || match (t, j, 2)) 7370 goodness = 3 + 3; 7371 else 7372 goodness = 3 + extra_goodness (t, 2); 7373 } 7374 else if (match (t, i, 2)) 7375 goodness = 3 + extra_goodness (t, 1); 7376 7377 if (goodness > best) 7378 { 7379 best = goodness; 7380 best_template[i][j][k] = t; 7381 } 7382 } 7383 } 7384 7385#ifdef DEBUG_TEMPLATES 7386 /* For debugging changes to the best_template calculations. We don't care 7387 about combinations with invalid instructions, so start the loops at 1. */ 7388 for (i = 0; i < IA64_NUM_TYPES; ++i) 7389 for (j = 0; j < IA64_NUM_TYPES; ++j) 7390 for (k = 0; k < IA64_NUM_TYPES; ++k) 7391 { 7392 char type_letter[IA64_NUM_TYPES] = { 'n', 'a', 'i', 'm', 'b', 'f', 7393 'x', 'd' }; 7394 fprintf (stderr, "%c%c%c %s\n", type_letter[i], type_letter[j], 7395 type_letter[k], 7396 ia64_templ_desc[best_template[i][j][k]].name); 7397 } 7398#endif 7399 7400 for (i = 0; i < NUM_SLOTS; ++i) 7401 md.slot[i].user_template = -1; 7402 7403 md.pseudo_hash = str_htab_create (); 7404 for (i = 0; i < NELEMS (pseudo_opcode); ++i) 7405 if (str_hash_insert (md.pseudo_hash, pseudo_opcode[i].name, 7406 pseudo_opcode + i, 0) != NULL) 7407 as_fatal (_("duplicate %s"), pseudo_opcode[i].name); 7408 7409 md.reg_hash = str_htab_create (); 7410 md.dynreg_hash = str_htab_create (); 7411 md.const_hash = str_htab_create (); 7412 md.entry_hash = str_htab_create (); 7413 7414 /* general registers: */ 7415 declare_register_set ("r", 128, REG_GR); 7416 declare_register ("gp", REG_GR + 1); 7417 declare_register ("sp", REG_GR + 12); 7418 declare_register ("tp", REG_GR + 13); 7419 declare_register_set ("ret", 4, REG_GR + 8); 7420 7421 /* floating point registers: */ 7422 declare_register_set ("f", 128, REG_FR); 7423 declare_register_set ("farg", 8, REG_FR + 8); 7424 declare_register_set ("fret", 8, REG_FR + 8); 7425 7426 /* branch registers: */ 7427 declare_register_set ("b", 8, REG_BR); 7428 declare_register ("rp", REG_BR + 0); 7429 7430 /* predicate registers: */ 7431 declare_register_set ("p", 64, REG_P); 7432 declare_register ("pr", REG_PR); 7433 declare_register ("pr.rot", REG_PR_ROT); 7434 7435 /* application registers: */ 7436 declare_register_set ("ar", 128, REG_AR); 7437 for (i = 0; i < NELEMS (ar); ++i) 7438 declare_register (ar[i].name, REG_AR + ar[i].regnum); 7439 7440 /* control registers: */ 7441 declare_register_set ("cr", 128, REG_CR); 7442 for (i = 0; i < NELEMS (cr); ++i) 7443 declare_register (cr[i].name, REG_CR + cr[i].regnum); 7444 7445 /* dahr registers: */ 7446 declare_register_set ("dahr", 8, REG_DAHR); 7447 7448 declare_register ("ip", REG_IP); 7449 declare_register ("cfm", REG_CFM); 7450 declare_register ("psr", REG_PSR); 7451 declare_register ("psr.l", REG_PSR_L); 7452 declare_register ("psr.um", REG_PSR_UM); 7453 7454 for (i = 0; i < NELEMS (indirect_reg); ++i) 7455 { 7456 unsigned int regnum = indirect_reg[i].regnum; 7457 7458 md.indregsym[regnum - IND_CPUID] = declare_register (indirect_reg[i].name, regnum); 7459 } 7460 7461 /* pseudo-registers used to specify unwind info: */ 7462 declare_register ("psp", REG_PSP); 7463 7464 for (i = 0; i < NELEMS (const_bits); ++i) 7465 if (str_hash_insert (md.const_hash, const_bits[i].name, const_bits + i, 0)) 7466 as_fatal (_("duplicate %s"), const_bits[i].name); 7467 7468 /* Set the architecture and machine depending on defaults and command line 7469 options. */ 7470 if (md.flags & EF_IA_64_ABI64) 7471 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); 7472 else 7473 ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); 7474 7475 if (! ok) 7476 as_warn (_("Could not set architecture and machine")); 7477 7478 /* Set the pointer size and pointer shift size depending on md.flags */ 7479 7480 if (md.flags & EF_IA_64_ABI64) 7481 { 7482 md.pointer_size = 8; /* pointers are 8 bytes */ 7483 md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */ 7484 } 7485 else 7486 { 7487 md.pointer_size = 4; /* pointers are 4 bytes */ 7488 md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */ 7489 } 7490 7491 md.mem_offset.hint = 0; 7492 md.path = 0; 7493 md.maxpaths = 0; 7494 md.entry_labels = NULL; 7495} 7496 7497/* Set the default options in md. Cannot do this in md_begin because 7498 that is called after md_parse_option which is where we set the 7499 options in md based on command line options. */ 7500 7501void 7502ia64_init (int argc ATTRIBUTE_UNUSED, char **argv ATTRIBUTE_UNUSED) 7503{ 7504 md.flags = MD_FLAGS_DEFAULT; 7505#ifndef TE_VMS 7506 /* Don't turn on dependency checking for VMS, doesn't work. */ 7507 md.detect_dv = 1; 7508#endif 7509 /* FIXME: We should change it to unwind_check_error someday. */ 7510 md.unwind_check = unwind_check_warning; 7511 md.hint_b = hint_b_error; 7512 md.tune = itanium2; 7513} 7514 7515/* Return a string for the target object file format. */ 7516 7517const char * 7518ia64_target_format (void) 7519{ 7520 if (OUTPUT_FLAVOR == bfd_target_elf_flavour) 7521 { 7522 if (md.flags & EF_IA_64_BE) 7523 { 7524 if (md.flags & EF_IA_64_ABI64) 7525#if defined(TE_AIX50) 7526 return "elf64-ia64-aix-big"; 7527#elif defined(TE_HPUX) 7528 return "elf64-ia64-hpux-big"; 7529#else 7530 return "elf64-ia64-big"; 7531#endif 7532 else 7533#if defined(TE_AIX50) 7534 return "elf32-ia64-aix-big"; 7535#elif defined(TE_HPUX) 7536 return "elf32-ia64-hpux-big"; 7537#else 7538 return "elf32-ia64-big"; 7539#endif 7540 } 7541 else 7542 { 7543 if (md.flags & EF_IA_64_ABI64) 7544#if defined (TE_AIX50) 7545 return "elf64-ia64-aix-little"; 7546#elif defined (TE_VMS) 7547 { 7548 md.flags |= EF_IA_64_ARCHVER_1; 7549 return "elf64-ia64-vms"; 7550 } 7551#else 7552 return "elf64-ia64-little"; 7553#endif 7554 else 7555#ifdef TE_AIX50 7556 return "elf32-ia64-aix-little"; 7557#else 7558 return "elf32-ia64-little"; 7559#endif 7560 } 7561 } 7562 else 7563 return "unknown-format"; 7564} 7565 7566void 7567ia64_end_of_source (void) 7568{ 7569 /* terminate insn group upon reaching end of file: */ 7570 insn_group_break (1, 0, 0); 7571 7572 /* emits slots we haven't written yet: */ 7573 ia64_flush_insns (); 7574 7575 bfd_set_private_flags (stdoutput, md.flags); 7576 7577 md.mem_offset.hint = 0; 7578} 7579 7580void 7581ia64_start_line (void) 7582{ 7583 static int first; 7584 7585 if (!first) { 7586 /* Make sure we don't reference input_line_pointer[-1] when that's 7587 not valid. */ 7588 first = 1; 7589 return; 7590 } 7591 7592 if (md.qp.X_op == O_register) 7593 as_bad (_("qualifying predicate not followed by instruction")); 7594 md.qp.X_op = O_absent; 7595 7596 if (ignore_input ()) 7597 return; 7598 7599 if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') 7600 { 7601 if (md.detect_dv && !md.explicit_mode) 7602 { 7603 static int warned; 7604 7605 if (!warned) 7606 { 7607 warned = 1; 7608 as_warn (_("Explicit stops are ignored in auto mode")); 7609 } 7610 } 7611 else 7612 insn_group_break (1, 0, 0); 7613 } 7614 else if (input_line_pointer[-1] == '{') 7615 { 7616 if (md.manual_bundling) 7617 as_warn (_("Found '{' when manual bundling is already turned on")); 7618 else 7619 CURR_SLOT.manual_bundling_on = 1; 7620 md.manual_bundling = 1; 7621 7622 /* Bundling is only acceptable in explicit mode 7623 or when in default automatic mode. */ 7624 if (md.detect_dv && !md.explicit_mode) 7625 { 7626 if (!md.mode_explicitly_set 7627 && !md.default_explicit_mode) 7628 dot_dv_mode ('E'); 7629 else 7630 as_warn (_("Found '{' after explicit switch to automatic mode")); 7631 } 7632 } 7633 else if (input_line_pointer[-1] == '}') 7634 { 7635 if (!md.manual_bundling) 7636 as_warn (_("Found '}' when manual bundling is off")); 7637 else 7638 PREV_SLOT.manual_bundling_off = 1; 7639 md.manual_bundling = 0; 7640 7641 /* switch back to automatic mode, if applicable */ 7642 if (md.detect_dv 7643 && md.explicit_mode 7644 && !md.mode_explicitly_set 7645 && !md.default_explicit_mode) 7646 dot_dv_mode ('A'); 7647 } 7648} 7649 7650/* This is a hook for ia64_frob_label, so that it can distinguish tags from 7651 labels. */ 7652static int defining_tag = 0; 7653 7654int 7655ia64_unrecognized_line (int ch) 7656{ 7657 switch (ch) 7658 { 7659 case '(': 7660 expression_and_evaluate (&md.qp); 7661 if (*input_line_pointer++ != ')') 7662 { 7663 as_bad (_("Expected ')'")); 7664 return 0; 7665 } 7666 if (md.qp.X_op != O_register) 7667 { 7668 as_bad (_("Qualifying predicate expected")); 7669 return 0; 7670 } 7671 if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) 7672 { 7673 as_bad (_("Predicate register expected")); 7674 return 0; 7675 } 7676 return 1; 7677 7678 case '[': 7679 { 7680 char *s; 7681 char c; 7682 symbolS *tag; 7683 int temp; 7684 7685 if (md.qp.X_op == O_register) 7686 { 7687 as_bad (_("Tag must come before qualifying predicate.")); 7688 return 0; 7689 } 7690 7691 /* This implements just enough of read_a_source_file in read.c to 7692 recognize labels. */ 7693 if (is_name_beginner (*input_line_pointer)) 7694 { 7695 c = get_symbol_name (&s); 7696 } 7697 else if (LOCAL_LABELS_FB 7698 && ISDIGIT (*input_line_pointer)) 7699 { 7700 temp = 0; 7701 while (ISDIGIT (*input_line_pointer)) 7702 temp = (temp * 10) + *input_line_pointer++ - '0'; 7703 fb_label_instance_inc (temp); 7704 s = fb_label_name (temp, 0); 7705 c = *input_line_pointer; 7706 } 7707 else 7708 { 7709 s = NULL; 7710 c = '\0'; 7711 } 7712 if (c != ':') 7713 { 7714 /* Put ':' back for error messages' sake. */ 7715 *input_line_pointer++ = ':'; 7716 as_bad (_("Expected ':'")); 7717 return 0; 7718 } 7719 7720 defining_tag = 1; 7721 tag = colon (s); 7722 defining_tag = 0; 7723 /* Put ':' back for error messages' sake. */ 7724 *input_line_pointer++ = ':'; 7725 if (*input_line_pointer++ != ']') 7726 { 7727 as_bad (_("Expected ']'")); 7728 return 0; 7729 } 7730 if (! tag) 7731 { 7732 as_bad (_("Tag name expected")); 7733 return 0; 7734 } 7735 return 1; 7736 } 7737 7738 default: 7739 break; 7740 } 7741 7742 /* Not a valid line. */ 7743 return 0; 7744} 7745 7746void 7747ia64_frob_label (struct symbol *sym) 7748{ 7749 struct label_fix *fix; 7750 7751 /* Tags need special handling since they are not bundle breaks like 7752 labels. */ 7753 if (defining_tag) 7754 { 7755 fix = XOBNEW (¬es, struct label_fix); 7756 fix->sym = sym; 7757 fix->next = CURR_SLOT.tag_fixups; 7758 fix->dw2_mark_labels = FALSE; 7759 CURR_SLOT.tag_fixups = fix; 7760 7761 return; 7762 } 7763 7764 if (bfd_section_flags (now_seg) & SEC_CODE) 7765 { 7766 md.last_text_seg = now_seg; 7767 fix = XOBNEW (¬es, struct label_fix); 7768 fix->sym = sym; 7769 fix->next = CURR_SLOT.label_fixups; 7770 fix->dw2_mark_labels = dwarf2_loc_mark_labels; 7771 CURR_SLOT.label_fixups = fix; 7772 7773 /* Keep track of how many code entry points we've seen. */ 7774 if (md.path == md.maxpaths) 7775 { 7776 md.maxpaths += 20; 7777 md.entry_labels = XRESIZEVEC (const char *, md.entry_labels, 7778 md.maxpaths); 7779 } 7780 md.entry_labels[md.path++] = S_GET_NAME (sym); 7781 } 7782} 7783 7784#ifdef TE_HPUX 7785/* The HP-UX linker will give unresolved symbol errors for symbols 7786 that are declared but unused. This routine removes declared, 7787 unused symbols from an object. */ 7788int 7789ia64_frob_symbol (struct symbol *sym) 7790{ 7791 if ((S_GET_SEGMENT (sym) == bfd_und_section_ptr && ! symbol_used_p (sym) && 7792 ELF_ST_VISIBILITY (S_GET_OTHER (sym)) == STV_DEFAULT) 7793 || (S_GET_SEGMENT (sym) == bfd_abs_section_ptr 7794 && ! S_IS_EXTERNAL (sym))) 7795 return 1; 7796 return 0; 7797} 7798#endif 7799 7800void 7801ia64_flush_pending_output (void) 7802{ 7803 if (!md.keep_pending_output 7804 && bfd_section_flags (now_seg) & SEC_CODE) 7805 { 7806 /* ??? This causes many unnecessary stop bits to be emitted. 7807 Unfortunately, it isn't clear if it is safe to remove this. */ 7808 insn_group_break (1, 0, 0); 7809 ia64_flush_insns (); 7810 } 7811} 7812 7813/* Do ia64-specific expression optimization. All that's done here is 7814 to transform index expressions that are either due to the indexing 7815 of rotating registers or due to the indexing of indirect register 7816 sets. */ 7817int 7818ia64_optimize_expr (expressionS *l, operatorT op, expressionS *r) 7819{ 7820 if (op != O_index) 7821 return 0; 7822 resolve_expression (l); 7823 if (l->X_op == O_register) 7824 { 7825 unsigned num_regs = l->X_add_number >> 16; 7826 7827 resolve_expression (r); 7828 if (num_regs) 7829 { 7830 /* Left side is a .rotX-allocated register. */ 7831 if (r->X_op != O_constant) 7832 { 7833 as_bad (_("Rotating register index must be a non-negative constant")); 7834 r->X_add_number = 0; 7835 } 7836 else if ((valueT) r->X_add_number >= num_regs) 7837 { 7838 as_bad (_("Index out of range 0..%u"), num_regs - 1); 7839 r->X_add_number = 0; 7840 } 7841 l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; 7842 return 1; 7843 } 7844 else if (l->X_add_number >= IND_CPUID && l->X_add_number <= IND_RR) 7845 { 7846 if (r->X_op != O_register 7847 || r->X_add_number < REG_GR 7848 || r->X_add_number > REG_GR + 127) 7849 { 7850 as_bad (_("Indirect register index must be a general register")); 7851 r->X_add_number = REG_GR; 7852 } 7853 l->X_op = O_index; 7854 l->X_op_symbol = md.indregsym[l->X_add_number - IND_CPUID]; 7855 l->X_add_number = r->X_add_number; 7856 return 1; 7857 } 7858 } 7859 as_bad (_("Index can only be applied to rotating or indirect registers")); 7860 /* Fall back to some register use of which has as little as possible 7861 side effects, to minimize subsequent error messages. */ 7862 l->X_op = O_register; 7863 l->X_add_number = REG_GR + 3; 7864 return 1; 7865} 7866 7867int 7868ia64_parse_name (char *name, expressionS *e, char *nextcharP) 7869{ 7870 struct const_desc *cdesc; 7871 struct dynreg *dr = 0; 7872 unsigned int idx; 7873 struct symbol *sym; 7874 char *end; 7875 7876 if (*name == '@') 7877 { 7878 enum pseudo_type pseudo_type = PSEUDO_FUNC_NONE; 7879 7880 /* Find what relocation pseudo-function we're dealing with. */ 7881 for (idx = 0; idx < NELEMS (pseudo_func); ++idx) 7882 if (pseudo_func[idx].name 7883 && pseudo_func[idx].name[0] == name[1] 7884 && strcmp (pseudo_func[idx].name + 1, name + 2) == 0) 7885 { 7886 pseudo_type = pseudo_func[idx].type; 7887 break; 7888 } 7889 switch (pseudo_type) 7890 { 7891 case PSEUDO_FUNC_RELOC: 7892 end = input_line_pointer; 7893 if (*nextcharP != '(') 7894 { 7895 as_bad (_("Expected '('")); 7896 break; 7897 } 7898 /* Skip '('. */ 7899 ++input_line_pointer; 7900 expression (e); 7901 if (*input_line_pointer != ')') 7902 { 7903 as_bad (_("Missing ')'")); 7904 goto done; 7905 } 7906 /* Skip ')'. */ 7907 ++input_line_pointer; 7908#ifdef TE_VMS 7909 if (idx == FUNC_SLOTCOUNT_RELOC) 7910 { 7911 /* @slotcount can accept any expression. Canonicalize. */ 7912 e->X_add_symbol = make_expr_symbol (e); 7913 e->X_op = O_symbol; 7914 e->X_add_number = 0; 7915 } 7916#endif 7917 if (e->X_op != O_symbol) 7918 { 7919 if (e->X_op != O_pseudo_fixup) 7920 { 7921 as_bad (_("Not a symbolic expression")); 7922 goto done; 7923 } 7924 if (idx != FUNC_LT_RELATIVE) 7925 { 7926 as_bad (_("Illegal combination of relocation functions")); 7927 goto done; 7928 } 7929 switch (S_GET_VALUE (e->X_op_symbol)) 7930 { 7931 case FUNC_FPTR_RELATIVE: 7932 idx = FUNC_LT_FPTR_RELATIVE; break; 7933 case FUNC_DTP_MODULE: 7934 idx = FUNC_LT_DTP_MODULE; break; 7935 case FUNC_DTP_RELATIVE: 7936 idx = FUNC_LT_DTP_RELATIVE; break; 7937 case FUNC_TP_RELATIVE: 7938 idx = FUNC_LT_TP_RELATIVE; break; 7939 default: 7940 as_bad (_("Illegal combination of relocation functions")); 7941 goto done; 7942 } 7943 } 7944 /* Make sure gas doesn't get rid of local symbols that are used 7945 in relocs. */ 7946 e->X_op = O_pseudo_fixup; 7947 e->X_op_symbol = pseudo_func[idx].u.sym; 7948 done: 7949 *nextcharP = *input_line_pointer; 7950 break; 7951 7952 case PSEUDO_FUNC_CONST: 7953 e->X_op = O_constant; 7954 e->X_add_number = pseudo_func[idx].u.ival; 7955 break; 7956 7957 case PSEUDO_FUNC_REG: 7958 e->X_op = O_register; 7959 e->X_add_number = pseudo_func[idx].u.ival; 7960 break; 7961 7962 default: 7963 return 0; 7964 } 7965 return 1; 7966 } 7967 7968 /* first see if NAME is a known register name: */ 7969 sym = str_hash_find (md.reg_hash, name); 7970 if (sym) 7971 { 7972 e->X_op = O_register; 7973 e->X_add_number = S_GET_VALUE (sym); 7974 return 1; 7975 } 7976 7977 cdesc = str_hash_find (md.const_hash, name); 7978 if (cdesc) 7979 { 7980 e->X_op = O_constant; 7981 e->X_add_number = cdesc->value; 7982 return 1; 7983 } 7984 7985 /* check for inN, locN, or outN: */ 7986 idx = 0; 7987 switch (name[0]) 7988 { 7989 case 'i': 7990 if (name[1] == 'n' && ISDIGIT (name[2])) 7991 { 7992 dr = &md.in; 7993 idx = 2; 7994 } 7995 break; 7996 7997 case 'l': 7998 if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3])) 7999 { 8000 dr = &md.loc; 8001 idx = 3; 8002 } 8003 break; 8004 8005 case 'o': 8006 if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3])) 8007 { 8008 dr = &md.out; 8009 idx = 3; 8010 } 8011 break; 8012 8013 default: 8014 break; 8015 } 8016 8017 /* Ignore register numbers with leading zeroes, except zero itself. */ 8018 if (dr && (name[idx] != '0' || name[idx + 1] == '\0')) 8019 { 8020 unsigned long regnum; 8021 8022 /* The name is inN, locN, or outN; parse the register number. */ 8023 regnum = strtoul (name + idx, &end, 10); 8024 if (end > name + idx && *end == '\0' && regnum < 96) 8025 { 8026 if (regnum >= dr->num_regs) 8027 { 8028 if (!dr->num_regs) 8029 as_bad (_("No current frame")); 8030 else 8031 as_bad (_("Register number out of range 0..%u"), 8032 dr->num_regs - 1); 8033 regnum = 0; 8034 } 8035 e->X_op = O_register; 8036 e->X_add_number = dr->base + regnum; 8037 return 1; 8038 } 8039 } 8040 8041 end = xstrdup (name); 8042 name = ia64_canonicalize_symbol_name (end); 8043 if ((dr = str_hash_find (md.dynreg_hash, name))) 8044 { 8045 /* We've got ourselves the name of a rotating register set. 8046 Store the base register number in the low 16 bits of 8047 X_add_number and the size of the register set in the top 16 8048 bits. */ 8049 e->X_op = O_register; 8050 e->X_add_number = dr->base | (dr->num_regs << 16); 8051 free (end); 8052 return 1; 8053 } 8054 free (end); 8055 return 0; 8056} 8057 8058/* Remove the '#' suffix that indicates a symbol as opposed to a register. */ 8059 8060char * 8061ia64_canonicalize_symbol_name (char *name) 8062{ 8063 size_t len = strlen (name), full = len; 8064 8065 while (len > 0 && name[len - 1] == '#') 8066 --len; 8067 if (len <= 0) 8068 { 8069 if (full > 0) 8070 as_bad (_("Standalone `#' is illegal")); 8071 } 8072 else if (len < full - 1) 8073 as_warn (_("Redundant `#' suffix operators")); 8074 name[len] = '\0'; 8075 return name; 8076} 8077 8078/* Return true if idesc is a conditional branch instruction. This excludes 8079 the modulo scheduled branches, and br.ia. Mod-sched branches are excluded 8080 because they always read/write resources regardless of the value of the 8081 qualifying predicate. br.ia must always use p0, and hence is always 8082 taken. Thus this function returns true for branches which can fall 8083 through, and which use no resources if they do fall through. */ 8084 8085static int 8086is_conditional_branch (struct ia64_opcode *idesc) 8087{ 8088 /* br is a conditional branch. Everything that starts with br. except 8089 br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch. 8090 Everything that starts with brl is a conditional branch. */ 8091 return (idesc->name[0] == 'b' && idesc->name[1] == 'r' 8092 && (idesc->name[2] == '\0' 8093 || (idesc->name[2] == '.' && idesc->name[3] != 'i' 8094 && idesc->name[3] != 'c' && idesc->name[3] != 'w') 8095 || idesc->name[2] == 'l' 8096 /* br.cond, br.call, br.clr */ 8097 || (idesc->name[2] == '.' && idesc->name[3] == 'c' 8098 && (idesc->name[4] == 'a' || idesc->name[4] == 'o' 8099 || (idesc->name[4] == 'l' && idesc->name[5] == 'r'))))); 8100} 8101 8102/* Return whether the given opcode is a taken branch. If there's any doubt, 8103 returns zero. */ 8104 8105static int 8106is_taken_branch (struct ia64_opcode *idesc) 8107{ 8108 return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) 8109 || strncmp (idesc->name, "br.ia", 5) == 0); 8110} 8111 8112/* Return whether the given opcode is an interruption or rfi. If there's any 8113 doubt, returns zero. */ 8114 8115static int 8116is_interruption_or_rfi (struct ia64_opcode *idesc) 8117{ 8118 if (strcmp (idesc->name, "rfi") == 0) 8119 return 1; 8120 return 0; 8121} 8122 8123/* Returns the index of the given dependency in the opcode's list of chks, or 8124 -1 if there is no dependency. */ 8125 8126static int 8127depends_on (int depind, struct ia64_opcode *idesc) 8128{ 8129 int i; 8130 const struct ia64_opcode_dependency *dep = idesc->dependencies; 8131 for (i = 0; i < dep->nchks; i++) 8132 { 8133 if (depind == DEP (dep->chks[i])) 8134 return i; 8135 } 8136 return -1; 8137} 8138 8139/* Determine a set of specific resources used for a particular resource 8140 class. Returns the number of specific resources identified For those 8141 cases which are not determinable statically, the resource returned is 8142 marked nonspecific. 8143 8144 Meanings of value in 'NOTE': 8145 1) only read/write when the register number is explicitly encoded in the 8146 insn. 8147 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only 8148 accesses CFM when qualifying predicate is in the rotating region. 8149 3) general register value is used to specify an indirect register; not 8150 determinable statically. 8151 4) only read the given resource when bits 7:0 of the indirect index 8152 register value does not match the register number of the resource; not 8153 determinable statically. 8154 5) all rules are implementation specific. 8155 6) only when both the index specified by the reader and the index specified 8156 by the writer have the same value in bits 63:61; not determinable 8157 statically. 8158 7) only access the specified resource when the corresponding mask bit is 8159 set 8160 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is 8161 only read when these insns reference FR2-31 8162 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only 8163 written when these insns write FR32-127 8164 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the 8165 instruction 8166 11) The target predicates are written independently of PR[qp], but source 8167 registers are only read if PR[qp] is true. Since the state of PR[qp] 8168 cannot statically be determined, all source registers are marked used. 8169 12) This insn only reads the specified predicate register when that 8170 register is the PR[qp]. 8171 13) This reference to ld-c only applies to the GR whose value is loaded 8172 with data returned from memory, not the post-incremented address register. 8173 14) The RSE resource includes the implementation-specific RSE internal 8174 state resources. At least one (and possibly more) of these resources are 8175 read by each instruction listed in IC:rse-readers. At least one (and 8176 possibly more) of these resources are written by each insn listed in 8177 IC:rse-writers. 8178 15+16) Represents reserved instructions, which the assembler does not 8179 generate. 8180 17) CR[TPR] has a RAW dependency only between mov-to-CR-TPR and 8181 mov-to-PSR-l or ssm instructions that set PSR.i, PSR.pp or PSR.up. 8182 8183 Memory resources (i.e. locations in memory) are *not* marked or tracked by 8184 this code; there are no dependency violations based on memory access. 8185*/ 8186 8187#define MAX_SPECS 256 8188#define DV_CHK 1 8189#define DV_REG 0 8190 8191static int 8192specify_resource (const struct ia64_dependency *dep, 8193 struct ia64_opcode *idesc, 8194 /* is this a DV chk or a DV reg? */ 8195 int type, 8196 /* returned specific resources */ 8197 struct rsrc specs[MAX_SPECS], 8198 /* resource note for this insn's usage */ 8199 int note, 8200 /* which execution path to examine */ 8201 int path) 8202{ 8203 int count = 0; 8204 int i; 8205 int rsrc_write = 0; 8206 struct rsrc tmpl; 8207 8208 if (dep->mode == IA64_DV_WAW 8209 || (dep->mode == IA64_DV_RAW && type == DV_REG) 8210 || (dep->mode == IA64_DV_WAR && type == DV_CHK)) 8211 rsrc_write = 1; 8212 8213 /* template for any resources we identify */ 8214 tmpl.dependency = dep; 8215 tmpl.note = note; 8216 tmpl.insn_srlz = tmpl.data_srlz = 0; 8217 tmpl.qp_regno = CURR_SLOT.qp_regno; 8218 tmpl.link_to_qp_branch = 1; 8219 tmpl.mem_offset.hint = 0; 8220 tmpl.mem_offset.offset = 0; 8221 tmpl.mem_offset.base = 0; 8222 tmpl.specific = 1; 8223 tmpl.index = -1; 8224 tmpl.cmp_type = CMP_NONE; 8225 tmpl.depind = 0; 8226 tmpl.file = NULL; 8227 tmpl.line = 0; 8228 tmpl.path = 0; 8229 8230#define UNHANDLED \ 8231as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ 8232dep->name, idesc->name, (rsrc_write?"write":"read"), note) 8233#define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) 8234 8235 /* we don't need to track these */ 8236 if (dep->semantics == IA64_DVS_NONE) 8237 return 0; 8238 8239 switch (dep->specifier) 8240 { 8241 case IA64_RS_AR_K: 8242 if (note == 1) 8243 { 8244 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 8245 { 8246 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8247 if (regno >= 0 && regno <= 7) 8248 { 8249 specs[count] = tmpl; 8250 specs[count++].index = regno; 8251 } 8252 } 8253 } 8254 else if (note == 0) 8255 { 8256 for (i = 0; i < 8; i++) 8257 { 8258 specs[count] = tmpl; 8259 specs[count++].index = i; 8260 } 8261 } 8262 else 8263 { 8264 UNHANDLED; 8265 } 8266 break; 8267 8268 case IA64_RS_AR_UNAT: 8269 /* This is a mov =AR or mov AR= instruction. */ 8270 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 8271 { 8272 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8273 if (regno == AR_UNAT) 8274 { 8275 specs[count++] = tmpl; 8276 } 8277 } 8278 else 8279 { 8280 /* This is a spill/fill, or other instruction that modifies the 8281 unat register. */ 8282 8283 /* Unless we can determine the specific bits used, mark the whole 8284 thing; bits 8:3 of the memory address indicate the bit used in 8285 UNAT. The .mem.offset hint may be used to eliminate a small 8286 subset of conflicts. */ 8287 specs[count] = tmpl; 8288 if (md.mem_offset.hint) 8289 { 8290 if (md.debug_dv) 8291 fprintf (stderr, " Using hint for spill/fill\n"); 8292 /* The index isn't actually used, just set it to something 8293 approximating the bit index. */ 8294 specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; 8295 specs[count].mem_offset.hint = 1; 8296 specs[count].mem_offset.offset = md.mem_offset.offset; 8297 specs[count++].mem_offset.base = md.mem_offset.base; 8298 } 8299 else 8300 { 8301 specs[count++].specific = 0; 8302 } 8303 } 8304 break; 8305 8306 case IA64_RS_AR: 8307 if (note == 1) 8308 { 8309 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 8310 { 8311 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8312 if ((regno >= 8 && regno <= 15) 8313 || (regno >= 20 && regno <= 23) 8314 || (regno >= 31 && regno <= 39) 8315 || (regno >= 41 && regno <= 47) 8316 || (regno >= 67 && regno <= 111)) 8317 { 8318 specs[count] = tmpl; 8319 specs[count++].index = regno; 8320 } 8321 } 8322 } 8323 else 8324 { 8325 UNHANDLED; 8326 } 8327 break; 8328 8329 case IA64_RS_ARb: 8330 if (note == 1) 8331 { 8332 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 8333 { 8334 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 8335 if ((regno >= 48 && regno <= 63) 8336 || (regno >= 112 && regno <= 127)) 8337 { 8338 specs[count] = tmpl; 8339 specs[count++].index = regno; 8340 } 8341 } 8342 } 8343 else if (note == 0) 8344 { 8345 for (i = 48; i < 64; i++) 8346 { 8347 specs[count] = tmpl; 8348 specs[count++].index = i; 8349 } 8350 for (i = 112; i < 128; i++) 8351 { 8352 specs[count] = tmpl; 8353 specs[count++].index = i; 8354 } 8355 } 8356 else 8357 { 8358 UNHANDLED; 8359 } 8360 break; 8361 8362 case IA64_RS_BR: 8363 if (note != 1) 8364 { 8365 UNHANDLED; 8366 } 8367 else 8368 { 8369 if (rsrc_write) 8370 { 8371 for (i = 0; i < idesc->num_outputs; i++) 8372 if (idesc->operands[i] == IA64_OPND_B1 8373 || idesc->operands[i] == IA64_OPND_B2) 8374 { 8375 specs[count] = tmpl; 8376 specs[count++].index = 8377 CURR_SLOT.opnd[i].X_add_number - REG_BR; 8378 } 8379 } 8380 else 8381 { 8382 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) 8383 if (idesc->operands[i] == IA64_OPND_B1 8384 || idesc->operands[i] == IA64_OPND_B2) 8385 { 8386 specs[count] = tmpl; 8387 specs[count++].index = 8388 CURR_SLOT.opnd[i].X_add_number - REG_BR; 8389 } 8390 } 8391 } 8392 break; 8393 8394 case IA64_RS_CPUID: /* four or more registers */ 8395 if (note == 3) 8396 { 8397 if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) 8398 { 8399 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 8400 if (regno >= 0 && regno < NELEMS (gr_values) 8401 && KNOWN (regno)) 8402 { 8403 specs[count] = tmpl; 8404 specs[count++].index = gr_values[regno].value & 0xFF; 8405 } 8406 else 8407 { 8408 specs[count] = tmpl; 8409 specs[count++].specific = 0; 8410 } 8411 } 8412 } 8413 else 8414 { 8415 UNHANDLED; 8416 } 8417 break; 8418 8419 case IA64_RS_DBR: /* four or more registers */ 8420 if (note == 3) 8421 { 8422 if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) 8423 { 8424 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 8425 if (regno >= 0 && regno < NELEMS (gr_values) 8426 && KNOWN (regno)) 8427 { 8428 specs[count] = tmpl; 8429 specs[count++].index = gr_values[regno].value & 0xFF; 8430 } 8431 else 8432 { 8433 specs[count] = tmpl; 8434 specs[count++].specific = 0; 8435 } 8436 } 8437 } 8438 else if (note == 0 && !rsrc_write) 8439 { 8440 specs[count] = tmpl; 8441 specs[count++].specific = 0; 8442 } 8443 else 8444 { 8445 UNHANDLED; 8446 } 8447 break; 8448 8449 case IA64_RS_IBR: /* four or more registers */ 8450 if (note == 3) 8451 { 8452 if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) 8453 { 8454 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 8455 if (regno >= 0 && regno < NELEMS (gr_values) 8456 && KNOWN (regno)) 8457 { 8458 specs[count] = tmpl; 8459 specs[count++].index = gr_values[regno].value & 0xFF; 8460 } 8461 else 8462 { 8463 specs[count] = tmpl; 8464 specs[count++].specific = 0; 8465 } 8466 } 8467 } 8468 else 8469 { 8470 UNHANDLED; 8471 } 8472 break; 8473 8474 case IA64_RS_MSR: 8475 if (note == 5) 8476 { 8477 /* These are implementation specific. Force all references to 8478 conflict with all other references. */ 8479 specs[count] = tmpl; 8480 specs[count++].specific = 0; 8481 } 8482 else 8483 { 8484 UNHANDLED; 8485 } 8486 break; 8487 8488 case IA64_RS_PKR: /* 16 or more registers */ 8489 if (note == 3 || note == 4) 8490 { 8491 if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) 8492 { 8493 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 8494 if (regno >= 0 && regno < NELEMS (gr_values) 8495 && KNOWN (regno)) 8496 { 8497 if (note == 3) 8498 { 8499 specs[count] = tmpl; 8500 specs[count++].index = gr_values[regno].value & 0xFF; 8501 } 8502 else 8503 for (i = 0; i < NELEMS (gr_values); i++) 8504 { 8505 /* Uses all registers *except* the one in R3. */ 8506 if ((unsigned)i != (gr_values[regno].value & 0xFF)) 8507 { 8508 specs[count] = tmpl; 8509 specs[count++].index = i; 8510 } 8511 } 8512 } 8513 else 8514 { 8515 specs[count] = tmpl; 8516 specs[count++].specific = 0; 8517 } 8518 } 8519 } 8520 else if (note == 0) 8521 { 8522 /* probe et al. */ 8523 specs[count] = tmpl; 8524 specs[count++].specific = 0; 8525 } 8526 break; 8527 8528 case IA64_RS_PMC: /* four or more registers */ 8529 if (note == 3) 8530 { 8531 if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 8532 || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) 8533 8534 { 8535 int reg_index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) 8536 ? 1 : !rsrc_write); 8537 int regno = CURR_SLOT.opnd[reg_index].X_add_number - REG_GR; 8538 if (regno >= 0 && regno < NELEMS (gr_values) 8539 && KNOWN (regno)) 8540 { 8541 specs[count] = tmpl; 8542 specs[count++].index = gr_values[regno].value & 0xFF; 8543 } 8544 else 8545 { 8546 specs[count] = tmpl; 8547 specs[count++].specific = 0; 8548 } 8549 } 8550 } 8551 else 8552 { 8553 UNHANDLED; 8554 } 8555 break; 8556 8557 case IA64_RS_PMD: /* four or more registers */ 8558 if (note == 3) 8559 { 8560 if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) 8561 { 8562 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 8563 if (regno >= 0 && regno < NELEMS (gr_values) 8564 && KNOWN (regno)) 8565 { 8566 specs[count] = tmpl; 8567 specs[count++].index = gr_values[regno].value & 0xFF; 8568 } 8569 else 8570 { 8571 specs[count] = tmpl; 8572 specs[count++].specific = 0; 8573 } 8574 } 8575 } 8576 else 8577 { 8578 UNHANDLED; 8579 } 8580 break; 8581 8582 case IA64_RS_RR: /* eight registers */ 8583 if (note == 6) 8584 { 8585 if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) 8586 { 8587 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; 8588 if (regno >= 0 && regno < NELEMS (gr_values) 8589 && KNOWN (regno)) 8590 { 8591 specs[count] = tmpl; 8592 specs[count++].index = (gr_values[regno].value >> 61) & 0x7; 8593 } 8594 else 8595 { 8596 specs[count] = tmpl; 8597 specs[count++].specific = 0; 8598 } 8599 } 8600 } 8601 else if (note == 0 && !rsrc_write) 8602 { 8603 specs[count] = tmpl; 8604 specs[count++].specific = 0; 8605 } 8606 else 8607 { 8608 UNHANDLED; 8609 } 8610 break; 8611 8612 case IA64_RS_CR_IRR: 8613 if (note == 0) 8614 { 8615 /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ 8616 int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; 8617 if (rsrc_write 8618 && idesc->operands[1] == IA64_OPND_CR3 8619 && regno == CR_IVR) 8620 { 8621 for (i = 0; i < 4; i++) 8622 { 8623 specs[count] = tmpl; 8624 specs[count++].index = CR_IRR0 + i; 8625 } 8626 } 8627 } 8628 else if (note == 1) 8629 { 8630 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 8631 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 8632 && regno >= CR_IRR0 8633 && regno <= CR_IRR3) 8634 { 8635 specs[count] = tmpl; 8636 specs[count++].index = regno; 8637 } 8638 } 8639 else 8640 { 8641 UNHANDLED; 8642 } 8643 break; 8644 8645 case IA64_RS_CR_IIB: 8646 if (note != 0) 8647 { 8648 UNHANDLED; 8649 } 8650 else 8651 { 8652 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 8653 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 8654 && (regno == CR_IIB0 || regno == CR_IIB1)) 8655 { 8656 specs[count] = tmpl; 8657 specs[count++].index = regno; 8658 } 8659 } 8660 break; 8661 8662 case IA64_RS_CR_LRR: 8663 if (note != 1) 8664 { 8665 UNHANDLED; 8666 } 8667 else 8668 { 8669 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 8670 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 8671 && (regno == CR_LRR0 || regno == CR_LRR1)) 8672 { 8673 specs[count] = tmpl; 8674 specs[count++].index = regno; 8675 } 8676 } 8677 break; 8678 8679 case IA64_RS_CR: 8680 if (note == 1) 8681 { 8682 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 8683 { 8684 specs[count] = tmpl; 8685 specs[count++].index = 8686 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 8687 } 8688 } 8689 else 8690 { 8691 UNHANDLED; 8692 } 8693 break; 8694 8695 case IA64_RS_DAHR: 8696 if (note == 0) 8697 { 8698 if (idesc->operands[!rsrc_write] == IA64_OPND_DAHR3) 8699 { 8700 specs[count] = tmpl; 8701 specs[count++].index = 8702 CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_DAHR; 8703 } 8704 } 8705 else 8706 { 8707 UNHANDLED; 8708 } 8709 break; 8710 8711 case IA64_RS_FR: 8712 case IA64_RS_FRb: 8713 if (note != 1) 8714 { 8715 UNHANDLED; 8716 } 8717 else if (rsrc_write) 8718 { 8719 if (dep->specifier == IA64_RS_FRb 8720 && idesc->operands[0] == IA64_OPND_F1) 8721 { 8722 specs[count] = tmpl; 8723 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; 8724 } 8725 } 8726 else 8727 { 8728 for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) 8729 { 8730 if (idesc->operands[i] == IA64_OPND_F2 8731 || idesc->operands[i] == IA64_OPND_F3 8732 || idesc->operands[i] == IA64_OPND_F4) 8733 { 8734 specs[count] = tmpl; 8735 specs[count++].index = 8736 CURR_SLOT.opnd[i].X_add_number - REG_FR; 8737 } 8738 } 8739 } 8740 break; 8741 8742 case IA64_RS_GR: 8743 if (note == 13) 8744 { 8745 /* This reference applies only to the GR whose value is loaded with 8746 data returned from memory. */ 8747 specs[count] = tmpl; 8748 specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; 8749 } 8750 else if (note == 1) 8751 { 8752 if (rsrc_write) 8753 { 8754 for (i = 0; i < idesc->num_outputs; i++) 8755 if (idesc->operands[i] == IA64_OPND_R1 8756 || idesc->operands[i] == IA64_OPND_R2 8757 || idesc->operands[i] == IA64_OPND_R3) 8758 { 8759 specs[count] = tmpl; 8760 specs[count++].index = 8761 CURR_SLOT.opnd[i].X_add_number - REG_GR; 8762 } 8763 if (idesc->flags & IA64_OPCODE_POSTINC) 8764 for (i = 0; i < NELEMS (idesc->operands); i++) 8765 if (idesc->operands[i] == IA64_OPND_MR3) 8766 { 8767 specs[count] = tmpl; 8768 specs[count++].index = 8769 CURR_SLOT.opnd[i].X_add_number - REG_GR; 8770 } 8771 } 8772 else 8773 { 8774 /* Look for anything that reads a GR. */ 8775 for (i = 0; i < NELEMS (idesc->operands); i++) 8776 { 8777 if (idesc->operands[i] == IA64_OPND_MR3 8778 || idesc->operands[i] == IA64_OPND_CPUID_R3 8779 || idesc->operands[i] == IA64_OPND_DBR_R3 8780 || idesc->operands[i] == IA64_OPND_IBR_R3 8781 || idesc->operands[i] == IA64_OPND_MSR_R3 8782 || idesc->operands[i] == IA64_OPND_PKR_R3 8783 || idesc->operands[i] == IA64_OPND_PMC_R3 8784 || idesc->operands[i] == IA64_OPND_PMD_R3 8785 || idesc->operands[i] == IA64_OPND_DAHR_R3 8786 || idesc->operands[i] == IA64_OPND_RR_R3 8787 || ((i >= idesc->num_outputs) 8788 && (idesc->operands[i] == IA64_OPND_R1 8789 || idesc->operands[i] == IA64_OPND_R2 8790 || idesc->operands[i] == IA64_OPND_R3 8791 /* addl source register. */ 8792 || idesc->operands[i] == IA64_OPND_R3_2))) 8793 { 8794 specs[count] = tmpl; 8795 specs[count++].index = 8796 CURR_SLOT.opnd[i].X_add_number - REG_GR; 8797 } 8798 } 8799 } 8800 } 8801 else 8802 { 8803 UNHANDLED; 8804 } 8805 break; 8806 8807 /* This is the same as IA64_RS_PRr, except that the register range is 8808 from 1 - 15, and there are no rotating register reads/writes here. */ 8809 case IA64_RS_PR: 8810 if (note == 0) 8811 { 8812 for (i = 1; i < 16; i++) 8813 { 8814 specs[count] = tmpl; 8815 specs[count++].index = i; 8816 } 8817 } 8818 else if (note == 7) 8819 { 8820 valueT mask = 0; 8821 /* Mark only those registers indicated by the mask. */ 8822 if (rsrc_write) 8823 { 8824 mask = CURR_SLOT.opnd[2].X_add_number; 8825 for (i = 1; i < 16; i++) 8826 if (mask & ((valueT) 1 << i)) 8827 { 8828 specs[count] = tmpl; 8829 specs[count++].index = i; 8830 } 8831 } 8832 else 8833 { 8834 UNHANDLED; 8835 } 8836 } 8837 else if (note == 11) /* note 11 implies note 1 as well */ 8838 { 8839 if (rsrc_write) 8840 { 8841 for (i = 0; i < idesc->num_outputs; i++) 8842 { 8843 if (idesc->operands[i] == IA64_OPND_P1 8844 || idesc->operands[i] == IA64_OPND_P2) 8845 { 8846 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 8847 if (regno >= 1 && regno < 16) 8848 { 8849 specs[count] = tmpl; 8850 specs[count++].index = regno; 8851 } 8852 } 8853 } 8854 } 8855 else 8856 { 8857 UNHANDLED; 8858 } 8859 } 8860 else if (note == 12) 8861 { 8862 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 8863 { 8864 specs[count] = tmpl; 8865 specs[count++].index = CURR_SLOT.qp_regno; 8866 } 8867 } 8868 else if (note == 1) 8869 { 8870 if (rsrc_write) 8871 { 8872 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8873 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8874 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 8875 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 8876 8877 if ((idesc->operands[0] == IA64_OPND_P1 8878 || idesc->operands[0] == IA64_OPND_P2) 8879 && p1 >= 1 && p1 < 16) 8880 { 8881 specs[count] = tmpl; 8882 specs[count].cmp_type = 8883 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 8884 specs[count++].index = p1; 8885 } 8886 if ((idesc->operands[1] == IA64_OPND_P1 8887 || idesc->operands[1] == IA64_OPND_P2) 8888 && p2 >= 1 && p2 < 16) 8889 { 8890 specs[count] = tmpl; 8891 specs[count].cmp_type = 8892 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 8893 specs[count++].index = p2; 8894 } 8895 } 8896 else 8897 { 8898 if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) 8899 { 8900 specs[count] = tmpl; 8901 specs[count++].index = CURR_SLOT.qp_regno; 8902 } 8903 if (idesc->operands[1] == IA64_OPND_PR) 8904 { 8905 for (i = 1; i < 16; i++) 8906 { 8907 specs[count] = tmpl; 8908 specs[count++].index = i; 8909 } 8910 } 8911 } 8912 } 8913 else 8914 { 8915 UNHANDLED; 8916 } 8917 break; 8918 8919 /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are 8920 simplified cases of this. */ 8921 case IA64_RS_PRr: 8922 if (note == 0) 8923 { 8924 for (i = 16; i < 63; i++) 8925 { 8926 specs[count] = tmpl; 8927 specs[count++].index = i; 8928 } 8929 } 8930 else if (note == 7) 8931 { 8932 valueT mask = 0; 8933 /* Mark only those registers indicated by the mask. */ 8934 if (rsrc_write 8935 && idesc->operands[0] == IA64_OPND_PR) 8936 { 8937 mask = CURR_SLOT.opnd[2].X_add_number; 8938 if (mask & ((valueT) 1 << 16)) 8939 for (i = 16; i < 63; i++) 8940 { 8941 specs[count] = tmpl; 8942 specs[count++].index = i; 8943 } 8944 } 8945 else if (rsrc_write 8946 && idesc->operands[0] == IA64_OPND_PR_ROT) 8947 { 8948 for (i = 16; i < 63; i++) 8949 { 8950 specs[count] = tmpl; 8951 specs[count++].index = i; 8952 } 8953 } 8954 else 8955 { 8956 UNHANDLED; 8957 } 8958 } 8959 else if (note == 11) /* note 11 implies note 1 as well */ 8960 { 8961 if (rsrc_write) 8962 { 8963 for (i = 0; i < idesc->num_outputs; i++) 8964 { 8965 if (idesc->operands[i] == IA64_OPND_P1 8966 || idesc->operands[i] == IA64_OPND_P2) 8967 { 8968 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 8969 if (regno >= 16 && regno < 63) 8970 { 8971 specs[count] = tmpl; 8972 specs[count++].index = regno; 8973 } 8974 } 8975 } 8976 } 8977 else 8978 { 8979 UNHANDLED; 8980 } 8981 } 8982 else if (note == 12) 8983 { 8984 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 8985 { 8986 specs[count] = tmpl; 8987 specs[count++].index = CURR_SLOT.qp_regno; 8988 } 8989 } 8990 else if (note == 1) 8991 { 8992 if (rsrc_write) 8993 { 8994 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 8995 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 8996 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 8997 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 8998 8999 if ((idesc->operands[0] == IA64_OPND_P1 9000 || idesc->operands[0] == IA64_OPND_P2) 9001 && p1 >= 16 && p1 < 63) 9002 { 9003 specs[count] = tmpl; 9004 specs[count].cmp_type = 9005 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 9006 specs[count++].index = p1; 9007 } 9008 if ((idesc->operands[1] == IA64_OPND_P1 9009 || idesc->operands[1] == IA64_OPND_P2) 9010 && p2 >= 16 && p2 < 63) 9011 { 9012 specs[count] = tmpl; 9013 specs[count].cmp_type = 9014 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 9015 specs[count++].index = p2; 9016 } 9017 } 9018 else 9019 { 9020 if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) 9021 { 9022 specs[count] = tmpl; 9023 specs[count++].index = CURR_SLOT.qp_regno; 9024 } 9025 if (idesc->operands[1] == IA64_OPND_PR) 9026 { 9027 for (i = 16; i < 63; i++) 9028 { 9029 specs[count] = tmpl; 9030 specs[count++].index = i; 9031 } 9032 } 9033 } 9034 } 9035 else 9036 { 9037 UNHANDLED; 9038 } 9039 break; 9040 9041 case IA64_RS_PSR: 9042 /* Verify that the instruction is using the PSR bit indicated in 9043 dep->regindex. */ 9044 if (note == 0) 9045 { 9046 if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) 9047 { 9048 if (dep->regindex < 6) 9049 { 9050 specs[count++] = tmpl; 9051 } 9052 } 9053 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) 9054 { 9055 if (dep->regindex < 32 9056 || dep->regindex == 35 9057 || dep->regindex == 36 9058 || (!rsrc_write && dep->regindex == PSR_CPL)) 9059 { 9060 specs[count++] = tmpl; 9061 } 9062 } 9063 else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) 9064 { 9065 if (dep->regindex < 32 9066 || dep->regindex == 35 9067 || dep->regindex == 36 9068 || (rsrc_write && dep->regindex == PSR_CPL)) 9069 { 9070 specs[count++] = tmpl; 9071 } 9072 } 9073 else 9074 { 9075 /* Several PSR bits have very specific dependencies. */ 9076 switch (dep->regindex) 9077 { 9078 default: 9079 specs[count++] = tmpl; 9080 break; 9081 case PSR_IC: 9082 if (rsrc_write) 9083 { 9084 specs[count++] = tmpl; 9085 } 9086 else 9087 { 9088 /* Only certain CR accesses use PSR.ic */ 9089 if (idesc->operands[0] == IA64_OPND_CR3 9090 || idesc->operands[1] == IA64_OPND_CR3) 9091 { 9092 int reg_index = 9093 ((idesc->operands[0] == IA64_OPND_CR3) 9094 ? 0 : 1); 9095 int regno = 9096 CURR_SLOT.opnd[reg_index].X_add_number - REG_CR; 9097 9098 switch (regno) 9099 { 9100 default: 9101 break; 9102 case CR_ITIR: 9103 case CR_IFS: 9104 case CR_IIM: 9105 case CR_IIP: 9106 case CR_IPSR: 9107 case CR_ISR: 9108 case CR_IFA: 9109 case CR_IHA: 9110 case CR_IIB0: 9111 case CR_IIB1: 9112 case CR_IIPA: 9113 specs[count++] = tmpl; 9114 break; 9115 } 9116 } 9117 } 9118 break; 9119 case PSR_CPL: 9120 if (rsrc_write) 9121 { 9122 specs[count++] = tmpl; 9123 } 9124 else 9125 { 9126 /* Only some AR accesses use cpl */ 9127 if (idesc->operands[0] == IA64_OPND_AR3 9128 || idesc->operands[1] == IA64_OPND_AR3) 9129 { 9130 int reg_index = 9131 ((idesc->operands[0] == IA64_OPND_AR3) 9132 ? 0 : 1); 9133 int regno = 9134 CURR_SLOT.opnd[reg_index].X_add_number - REG_AR; 9135 9136 if (regno == AR_ITC 9137 || regno == AR_RUC 9138 || (reg_index == 0 9139 && (regno == AR_RSC 9140 || (regno >= AR_K0 9141 && regno <= AR_K7)))) 9142 { 9143 specs[count++] = tmpl; 9144 } 9145 } 9146 else 9147 { 9148 specs[count++] = tmpl; 9149 } 9150 break; 9151 } 9152 } 9153 } 9154 } 9155 else if (note == 7) 9156 { 9157 valueT mask = 0; 9158 if (idesc->operands[0] == IA64_OPND_IMMU24) 9159 { 9160 mask = CURR_SLOT.opnd[0].X_add_number; 9161 } 9162 else 9163 { 9164 UNHANDLED; 9165 } 9166 if (mask & ((valueT) 1 << dep->regindex)) 9167 { 9168 specs[count++] = tmpl; 9169 } 9170 } 9171 else if (note == 8) 9172 { 9173 int min = dep->regindex == PSR_DFL ? 2 : 32; 9174 int max = dep->regindex == PSR_DFL ? 31 : 127; 9175 /* dfh is read on FR32-127; dfl is read on FR2-31 */ 9176 for (i = 0; i < NELEMS (idesc->operands); i++) 9177 { 9178 if (idesc->operands[i] == IA64_OPND_F1 9179 || idesc->operands[i] == IA64_OPND_F2 9180 || idesc->operands[i] == IA64_OPND_F3 9181 || idesc->operands[i] == IA64_OPND_F4) 9182 { 9183 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 9184 if (reg >= min && reg <= max) 9185 { 9186 specs[count++] = tmpl; 9187 } 9188 } 9189 } 9190 } 9191 else if (note == 9) 9192 { 9193 int min = dep->regindex == PSR_MFL ? 2 : 32; 9194 int max = dep->regindex == PSR_MFL ? 31 : 127; 9195 /* mfh is read on writes to FR32-127; mfl is read on writes to 9196 FR2-31 */ 9197 for (i = 0; i < idesc->num_outputs; i++) 9198 { 9199 if (idesc->operands[i] == IA64_OPND_F1) 9200 { 9201 int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; 9202 if (reg >= min && reg <= max) 9203 { 9204 specs[count++] = tmpl; 9205 } 9206 } 9207 } 9208 } 9209 else if (note == 10) 9210 { 9211 for (i = 0; i < NELEMS (idesc->operands); i++) 9212 { 9213 if (idesc->operands[i] == IA64_OPND_R1 9214 || idesc->operands[i] == IA64_OPND_R2 9215 || idesc->operands[i] == IA64_OPND_R3) 9216 { 9217 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 9218 if (regno >= 16 && regno <= 31) 9219 { 9220 specs[count++] = tmpl; 9221 } 9222 } 9223 } 9224 } 9225 else 9226 { 9227 UNHANDLED; 9228 } 9229 break; 9230 9231 case IA64_RS_AR_FPSR: 9232 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) 9233 { 9234 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 9235 if (regno == AR_FPSR) 9236 { 9237 specs[count++] = tmpl; 9238 } 9239 } 9240 else 9241 { 9242 specs[count++] = tmpl; 9243 } 9244 break; 9245 9246 case IA64_RS_ARX: 9247 /* Handle all AR[REG] resources */ 9248 if (note == 0 || note == 1) 9249 { 9250 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; 9251 if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 9252 && regno == dep->regindex) 9253 { 9254 specs[count++] = tmpl; 9255 } 9256 /* other AR[REG] resources may be affected by AR accesses */ 9257 else if (idesc->operands[0] == IA64_OPND_AR3) 9258 { 9259 /* AR[] writes */ 9260 regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; 9261 switch (dep->regindex) 9262 { 9263 default: 9264 break; 9265 case AR_BSP: 9266 case AR_RNAT: 9267 if (regno == AR_BSPSTORE) 9268 { 9269 specs[count++] = tmpl; 9270 } 9271 /* Fall through. */ 9272 case AR_RSC: 9273 if (!rsrc_write && 9274 (regno == AR_BSPSTORE 9275 || regno == AR_RNAT)) 9276 { 9277 specs[count++] = tmpl; 9278 } 9279 break; 9280 } 9281 } 9282 else if (idesc->operands[1] == IA64_OPND_AR3) 9283 { 9284 /* AR[] reads */ 9285 regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; 9286 switch (dep->regindex) 9287 { 9288 default: 9289 break; 9290 case AR_RSC: 9291 if (regno == AR_BSPSTORE || regno == AR_RNAT) 9292 { 9293 specs[count++] = tmpl; 9294 } 9295 break; 9296 } 9297 } 9298 else 9299 { 9300 specs[count++] = tmpl; 9301 } 9302 } 9303 else 9304 { 9305 UNHANDLED; 9306 } 9307 break; 9308 9309 case IA64_RS_CRX: 9310 /* Handle all CR[REG] resources. 9311 ??? FIXME: The rule 17 isn't really handled correctly. */ 9312 if (note == 0 || note == 1 || note == 17) 9313 { 9314 if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) 9315 { 9316 int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; 9317 if (regno == dep->regindex) 9318 { 9319 specs[count++] = tmpl; 9320 } 9321 else if (!rsrc_write) 9322 { 9323 /* Reads from CR[IVR] affect other resources. */ 9324 if (regno == CR_IVR) 9325 { 9326 if ((dep->regindex >= CR_IRR0 9327 && dep->regindex <= CR_IRR3) 9328 || dep->regindex == CR_TPR) 9329 { 9330 specs[count++] = tmpl; 9331 } 9332 } 9333 } 9334 } 9335 else 9336 { 9337 specs[count++] = tmpl; 9338 } 9339 } 9340 else 9341 { 9342 UNHANDLED; 9343 } 9344 break; 9345 9346 case IA64_RS_INSERVICE: 9347 /* look for write of EOI (67) or read of IVR (65) */ 9348 if ((idesc->operands[0] == IA64_OPND_CR3 9349 && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) 9350 || (idesc->operands[1] == IA64_OPND_CR3 9351 && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) 9352 { 9353 specs[count++] = tmpl; 9354 } 9355 break; 9356 9357 case IA64_RS_GR0: 9358 if (note == 1) 9359 { 9360 specs[count++] = tmpl; 9361 } 9362 else 9363 { 9364 UNHANDLED; 9365 } 9366 break; 9367 9368 case IA64_RS_CFM: 9369 if (note != 2) 9370 { 9371 specs[count++] = tmpl; 9372 } 9373 else 9374 { 9375 /* Check if any of the registers accessed are in the rotating region. 9376 mov to/from pr accesses CFM only when qp_regno is in the rotating 9377 region */ 9378 for (i = 0; i < NELEMS (idesc->operands); i++) 9379 { 9380 if (idesc->operands[i] == IA64_OPND_R1 9381 || idesc->operands[i] == IA64_OPND_R2 9382 || idesc->operands[i] == IA64_OPND_R3) 9383 { 9384 int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; 9385 /* Assumes that md.rot.num_regs is always valid */ 9386 if (md.rot.num_regs > 0 9387 && num > 31 9388 && num < 31 + md.rot.num_regs) 9389 { 9390 specs[count] = tmpl; 9391 specs[count++].specific = 0; 9392 } 9393 } 9394 else if (idesc->operands[i] == IA64_OPND_F1 9395 || idesc->operands[i] == IA64_OPND_F2 9396 || idesc->operands[i] == IA64_OPND_F3 9397 || idesc->operands[i] == IA64_OPND_F4) 9398 { 9399 int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; 9400 if (num > 31) 9401 { 9402 specs[count] = tmpl; 9403 specs[count++].specific = 0; 9404 } 9405 } 9406 else if (idesc->operands[i] == IA64_OPND_P1 9407 || idesc->operands[i] == IA64_OPND_P2) 9408 { 9409 int num = CURR_SLOT.opnd[i].X_add_number - REG_P; 9410 if (num > 15) 9411 { 9412 specs[count] = tmpl; 9413 specs[count++].specific = 0; 9414 } 9415 } 9416 } 9417 if (CURR_SLOT.qp_regno > 15) 9418 { 9419 specs[count] = tmpl; 9420 specs[count++].specific = 0; 9421 } 9422 } 9423 break; 9424 9425 /* This is the same as IA64_RS_PRr, except simplified to account for 9426 the fact that there is only one register. */ 9427 case IA64_RS_PR63: 9428 if (note == 0) 9429 { 9430 specs[count++] = tmpl; 9431 } 9432 else if (note == 7) 9433 { 9434 valueT mask = 0; 9435 if (idesc->operands[2] == IA64_OPND_IMM17) 9436 mask = CURR_SLOT.opnd[2].X_add_number; 9437 if (mask & ((valueT) 1 << 63)) 9438 specs[count++] = tmpl; 9439 } 9440 else if (note == 11) 9441 { 9442 if ((idesc->operands[0] == IA64_OPND_P1 9443 && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) 9444 || (idesc->operands[1] == IA64_OPND_P2 9445 && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) 9446 { 9447 specs[count++] = tmpl; 9448 } 9449 } 9450 else if (note == 12) 9451 { 9452 if (CURR_SLOT.qp_regno == 63) 9453 { 9454 specs[count++] = tmpl; 9455 } 9456 } 9457 else if (note == 1) 9458 { 9459 if (rsrc_write) 9460 { 9461 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 9462 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 9463 int or_andcm = strstr (idesc->name, "or.andcm") != NULL; 9464 int and_orcm = strstr (idesc->name, "and.orcm") != NULL; 9465 9466 if (p1 == 63 9467 && (idesc->operands[0] == IA64_OPND_P1 9468 || idesc->operands[0] == IA64_OPND_P2)) 9469 { 9470 specs[count] = tmpl; 9471 specs[count++].cmp_type = 9472 (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); 9473 } 9474 if (p2 == 63 9475 && (idesc->operands[1] == IA64_OPND_P1 9476 || idesc->operands[1] == IA64_OPND_P2)) 9477 { 9478 specs[count] = tmpl; 9479 specs[count++].cmp_type = 9480 (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); 9481 } 9482 } 9483 else 9484 { 9485 if (CURR_SLOT.qp_regno == 63) 9486 { 9487 specs[count++] = tmpl; 9488 } 9489 } 9490 } 9491 else 9492 { 9493 UNHANDLED; 9494 } 9495 break; 9496 9497 case IA64_RS_RSE: 9498 /* FIXME we can identify some individual RSE written resources, but RSE 9499 read resources have not yet been completely identified, so for now 9500 treat RSE as a single resource */ 9501 if (strncmp (idesc->name, "mov", 3) == 0) 9502 { 9503 if (rsrc_write) 9504 { 9505 if (idesc->operands[0] == IA64_OPND_AR3 9506 && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) 9507 { 9508 specs[count++] = tmpl; 9509 } 9510 } 9511 else 9512 { 9513 if (idesc->operands[0] == IA64_OPND_AR3) 9514 { 9515 if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE 9516 || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) 9517 { 9518 specs[count++] = tmpl; 9519 } 9520 } 9521 else if (idesc->operands[1] == IA64_OPND_AR3) 9522 { 9523 if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP 9524 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE 9525 || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) 9526 { 9527 specs[count++] = tmpl; 9528 } 9529 } 9530 } 9531 } 9532 else 9533 { 9534 specs[count++] = tmpl; 9535 } 9536 break; 9537 9538 case IA64_RS_ANY: 9539 /* FIXME -- do any of these need to be non-specific? */ 9540 specs[count++] = tmpl; 9541 break; 9542 9543 default: 9544 as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); 9545 break; 9546 } 9547 9548 return count; 9549} 9550 9551/* Clear branch flags on marked resources. This breaks the link between the 9552 QP of the marking instruction and a subsequent branch on the same QP. */ 9553 9554static void 9555clear_qp_branch_flag (valueT mask) 9556{ 9557 int i; 9558 for (i = 0; i < regdepslen; i++) 9559 { 9560 valueT bit = ((valueT) 1 << regdeps[i].qp_regno); 9561 if ((bit & mask) != 0) 9562 { 9563 regdeps[i].link_to_qp_branch = 0; 9564 } 9565 } 9566} 9567 9568/* MASK contains 2 and only 2 PRs which are mutually exclusive. Remove 9569 any mutexes which contain one of the PRs and create new ones when 9570 needed. */ 9571 9572static int 9573update_qp_mutex (valueT mask) 9574{ 9575 int i; 9576 int add = 0; 9577 9578 i = 0; 9579 while (i < qp_mutexeslen) 9580 { 9581 if ((qp_mutexes[i].prmask & mask) != 0) 9582 { 9583 /* If it destroys and creates the same mutex, do nothing. */ 9584 if (qp_mutexes[i].prmask == mask 9585 && qp_mutexes[i].path == md.path) 9586 { 9587 i++; 9588 add = -1; 9589 } 9590 else 9591 { 9592 int keep = 0; 9593 9594 if (md.debug_dv) 9595 { 9596 fprintf (stderr, " Clearing mutex relation"); 9597 print_prmask (qp_mutexes[i].prmask); 9598 fprintf (stderr, "\n"); 9599 } 9600 9601 /* Deal with the old mutex with more than 3+ PRs only if 9602 the new mutex on the same execution path with it. 9603 9604 FIXME: The 3+ mutex support is incomplete. 9605 dot_pred_rel () may be a better place to fix it. */ 9606 if (qp_mutexes[i].path == md.path) 9607 { 9608 /* If it is a proper subset of the mutex, create a 9609 new mutex. */ 9610 if (add == 0 9611 && (qp_mutexes[i].prmask & mask) == mask) 9612 add = 1; 9613 9614 qp_mutexes[i].prmask &= ~mask; 9615 if (qp_mutexes[i].prmask & (qp_mutexes[i].prmask - 1)) 9616 { 9617 /* Modify the mutex if there are more than one 9618 PR left. */ 9619 keep = 1; 9620 i++; 9621 } 9622 } 9623 9624 if (keep == 0) 9625 /* Remove the mutex. */ 9626 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; 9627 } 9628 } 9629 else 9630 ++i; 9631 } 9632 9633 if (add == 1) 9634 add_qp_mutex (mask); 9635 9636 return add; 9637} 9638 9639/* Remove any mutexes which contain any of the PRs indicated in the mask. 9640 9641 Any changes to a PR clears the mutex relations which include that PR. */ 9642 9643static void 9644clear_qp_mutex (valueT mask) 9645{ 9646 int i; 9647 9648 i = 0; 9649 while (i < qp_mutexeslen) 9650 { 9651 if ((qp_mutexes[i].prmask & mask) != 0) 9652 { 9653 if (md.debug_dv) 9654 { 9655 fprintf (stderr, " Clearing mutex relation"); 9656 print_prmask (qp_mutexes[i].prmask); 9657 fprintf (stderr, "\n"); 9658 } 9659 qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; 9660 } 9661 else 9662 ++i; 9663 } 9664} 9665 9666/* Clear implies relations which contain PRs in the given masks. 9667 P1_MASK indicates the source of the implies relation, while P2_MASK 9668 indicates the implied PR. */ 9669 9670static void 9671clear_qp_implies (valueT p1_mask, valueT p2_mask) 9672{ 9673 int i; 9674 9675 i = 0; 9676 while (i < qp_implieslen) 9677 { 9678 if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 9679 || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) 9680 { 9681 if (md.debug_dv) 9682 fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", 9683 qp_implies[i].p1, qp_implies[i].p2); 9684 qp_implies[i] = qp_implies[--qp_implieslen]; 9685 } 9686 else 9687 ++i; 9688 } 9689} 9690 9691/* Add the PRs specified to the list of implied relations. */ 9692 9693static void 9694add_qp_imply (int p1, int p2) 9695{ 9696 valueT mask; 9697 valueT bit; 9698 int i; 9699 9700 /* p0 is not meaningful here. */ 9701 if (p1 == 0 || p2 == 0) 9702 abort (); 9703 9704 if (p1 == p2) 9705 return; 9706 9707 /* If it exists already, ignore it. */ 9708 for (i = 0; i < qp_implieslen; i++) 9709 { 9710 if (qp_implies[i].p1 == p1 9711 && qp_implies[i].p2 == p2 9712 && qp_implies[i].path == md.path 9713 && !qp_implies[i].p2_branched) 9714 return; 9715 } 9716 9717 if (qp_implieslen == qp_impliestotlen) 9718 { 9719 qp_impliestotlen += 20; 9720 qp_implies = XRESIZEVEC (struct qp_imply, qp_implies, qp_impliestotlen); 9721 } 9722 if (md.debug_dv) 9723 fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); 9724 qp_implies[qp_implieslen].p1 = p1; 9725 qp_implies[qp_implieslen].p2 = p2; 9726 qp_implies[qp_implieslen].path = md.path; 9727 qp_implies[qp_implieslen++].p2_branched = 0; 9728 9729 /* Add in the implied transitive relations; for everything that p2 implies, 9730 make p1 imply that, too; for everything that implies p1, make it imply p2 9731 as well. */ 9732 for (i = 0; i < qp_implieslen; i++) 9733 { 9734 if (qp_implies[i].p1 == p2) 9735 add_qp_imply (p1, qp_implies[i].p2); 9736 if (qp_implies[i].p2 == p1) 9737 add_qp_imply (qp_implies[i].p1, p2); 9738 } 9739 /* Add in mutex relations implied by this implies relation; for each mutex 9740 relation containing p2, duplicate it and replace p2 with p1. */ 9741 bit = (valueT) 1 << p1; 9742 mask = (valueT) 1 << p2; 9743 for (i = 0; i < qp_mutexeslen; i++) 9744 { 9745 if (qp_mutexes[i].prmask & mask) 9746 add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); 9747 } 9748} 9749 9750/* Add the PRs specified in the mask to the mutex list; this means that only 9751 one of the PRs can be true at any time. PR0 should never be included in 9752 the mask. */ 9753 9754static void 9755add_qp_mutex (valueT mask) 9756{ 9757 if (mask & 0x1) 9758 abort (); 9759 9760 if (qp_mutexeslen == qp_mutexestotlen) 9761 { 9762 qp_mutexestotlen += 20; 9763 qp_mutexes = XRESIZEVEC (struct qpmutex, qp_mutexes, qp_mutexestotlen); 9764 } 9765 if (md.debug_dv) 9766 { 9767 fprintf (stderr, " Registering mutex on"); 9768 print_prmask (mask); 9769 fprintf (stderr, "\n"); 9770 } 9771 qp_mutexes[qp_mutexeslen].path = md.path; 9772 qp_mutexes[qp_mutexeslen++].prmask = mask; 9773} 9774 9775static int 9776has_suffix_p (const char *name, const char *suffix) 9777{ 9778 size_t namelen = strlen (name); 9779 size_t sufflen = strlen (suffix); 9780 9781 if (namelen <= sufflen) 9782 return 0; 9783 return strcmp (name + namelen - sufflen, suffix) == 0; 9784} 9785 9786static void 9787clear_register_values (void) 9788{ 9789 int i; 9790 if (md.debug_dv) 9791 fprintf (stderr, " Clearing register values\n"); 9792 for (i = 1; i < NELEMS (gr_values); i++) 9793 gr_values[i].known = 0; 9794} 9795 9796/* Keep track of register values/changes which affect DV tracking. 9797 9798 optimization note: should add a flag to classes of insns where otherwise we 9799 have to examine a group of strings to identify them. */ 9800 9801static void 9802note_register_values (struct ia64_opcode *idesc) 9803{ 9804 valueT qp_changemask = 0; 9805 int i; 9806 9807 /* Invalidate values for registers being written to. */ 9808 for (i = 0; i < idesc->num_outputs; i++) 9809 { 9810 if (idesc->operands[i] == IA64_OPND_R1 9811 || idesc->operands[i] == IA64_OPND_R2 9812 || idesc->operands[i] == IA64_OPND_R3) 9813 { 9814 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 9815 if (regno > 0 && regno < NELEMS (gr_values)) 9816 gr_values[regno].known = 0; 9817 } 9818 else if (idesc->operands[i] == IA64_OPND_R3_2) 9819 { 9820 int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; 9821 if (regno > 0 && regno < 4) 9822 gr_values[regno].known = 0; 9823 } 9824 else if (idesc->operands[i] == IA64_OPND_P1 9825 || idesc->operands[i] == IA64_OPND_P2) 9826 { 9827 int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; 9828 qp_changemask |= (valueT) 1 << regno; 9829 } 9830 else if (idesc->operands[i] == IA64_OPND_PR) 9831 { 9832 if (idesc->operands[2] & (valueT) 0x10000) 9833 qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; 9834 else 9835 qp_changemask = idesc->operands[2]; 9836 break; 9837 } 9838 else if (idesc->operands[i] == IA64_OPND_PR_ROT) 9839 { 9840 if (idesc->operands[1] & ((valueT) 1 << 43)) 9841 qp_changemask = -((valueT) 1 << 44) | idesc->operands[1]; 9842 else 9843 qp_changemask = idesc->operands[1]; 9844 qp_changemask &= ~(valueT) 0xFFFF; 9845 break; 9846 } 9847 } 9848 9849 /* Always clear qp branch flags on any PR change. */ 9850 /* FIXME there may be exceptions for certain compares. */ 9851 clear_qp_branch_flag (qp_changemask); 9852 9853 /* Invalidate rotating registers on insns which affect RRBs in CFM. */ 9854 if (idesc->flags & IA64_OPCODE_MOD_RRBS) 9855 { 9856 qp_changemask |= ~(valueT) 0xFFFF; 9857 if (strcmp (idesc->name, "clrrrb.pr") != 0) 9858 { 9859 for (i = 32; i < 32 + md.rot.num_regs; i++) 9860 gr_values[i].known = 0; 9861 } 9862 clear_qp_mutex (qp_changemask); 9863 clear_qp_implies (qp_changemask, qp_changemask); 9864 } 9865 /* After a call, all register values are undefined, except those marked 9866 as "safe". */ 9867 else if (strncmp (idesc->name, "br.call", 6) == 0 9868 || strncmp (idesc->name, "brl.call", 7) == 0) 9869 { 9870 /* FIXME keep GR values which are marked as "safe_across_calls" */ 9871 clear_register_values (); 9872 clear_qp_mutex (~qp_safe_across_calls); 9873 clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); 9874 clear_qp_branch_flag (~qp_safe_across_calls); 9875 } 9876 else if (is_interruption_or_rfi (idesc) 9877 || is_taken_branch (idesc)) 9878 { 9879 clear_register_values (); 9880 clear_qp_mutex (~(valueT) 0); 9881 clear_qp_implies (~(valueT) 0, ~(valueT) 0); 9882 } 9883 /* Look for mutex and implies relations. */ 9884 else if ((idesc->operands[0] == IA64_OPND_P1 9885 || idesc->operands[0] == IA64_OPND_P2) 9886 && (idesc->operands[1] == IA64_OPND_P1 9887 || idesc->operands[1] == IA64_OPND_P2)) 9888 { 9889 int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; 9890 int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; 9891 valueT p1mask = (p1 != 0) ? (valueT) 1 << p1 : 0; 9892 valueT p2mask = (p2 != 0) ? (valueT) 1 << p2 : 0; 9893 9894 /* If both PRs are PR0, we can't really do anything. */ 9895 if (p1 == 0 && p2 == 0) 9896 { 9897 if (md.debug_dv) 9898 fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); 9899 } 9900 /* In general, clear mutexes and implies which include P1 or P2, 9901 with the following exceptions. */ 9902 else if (has_suffix_p (idesc->name, ".or.andcm") 9903 || has_suffix_p (idesc->name, ".and.orcm")) 9904 { 9905 clear_qp_implies (p2mask, p1mask); 9906 } 9907 else if (has_suffix_p (idesc->name, ".andcm") 9908 || has_suffix_p (idesc->name, ".and")) 9909 { 9910 clear_qp_implies (0, p1mask | p2mask); 9911 } 9912 else if (has_suffix_p (idesc->name, ".orcm") 9913 || has_suffix_p (idesc->name, ".or")) 9914 { 9915 clear_qp_mutex (p1mask | p2mask); 9916 clear_qp_implies (p1mask | p2mask, 0); 9917 } 9918 else 9919 { 9920 int added = 0; 9921 9922 clear_qp_implies (p1mask | p2mask, p1mask | p2mask); 9923 9924 /* If one of the PRs is PR0, we call clear_qp_mutex. */ 9925 if (p1 == 0 || p2 == 0) 9926 clear_qp_mutex (p1mask | p2mask); 9927 else 9928 added = update_qp_mutex (p1mask | p2mask); 9929 9930 if (CURR_SLOT.qp_regno == 0 9931 || has_suffix_p (idesc->name, ".unc")) 9932 { 9933 if (added == 0 && p1 && p2) 9934 add_qp_mutex (p1mask | p2mask); 9935 if (CURR_SLOT.qp_regno != 0) 9936 { 9937 if (p1) 9938 add_qp_imply (p1, CURR_SLOT.qp_regno); 9939 if (p2) 9940 add_qp_imply (p2, CURR_SLOT.qp_regno); 9941 } 9942 } 9943 } 9944 } 9945 /* Look for mov imm insns into GRs. */ 9946 else if (idesc->operands[0] == IA64_OPND_R1 9947 && (idesc->operands[1] == IA64_OPND_IMM22 9948 || idesc->operands[1] == IA64_OPND_IMMU64) 9949 && CURR_SLOT.opnd[1].X_op == O_constant 9950 && (strcmp (idesc->name, "mov") == 0 9951 || strcmp (idesc->name, "movl") == 0)) 9952 { 9953 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; 9954 if (regno > 0 && regno < NELEMS (gr_values)) 9955 { 9956 gr_values[regno].known = 1; 9957 gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; 9958 gr_values[regno].path = md.path; 9959 if (md.debug_dv) 9960 { 9961 fprintf (stderr, " Know gr%d = ", regno); 9962 fprintf_vma (stderr, gr_values[regno].value); 9963 fputs ("\n", stderr); 9964 } 9965 } 9966 } 9967 /* Look for dep.z imm insns. */ 9968 else if (idesc->operands[0] == IA64_OPND_R1 9969 && idesc->operands[1] == IA64_OPND_IMM8 9970 && strcmp (idesc->name, "dep.z") == 0) 9971 { 9972 int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; 9973 if (regno > 0 && regno < NELEMS (gr_values)) 9974 { 9975 valueT value = CURR_SLOT.opnd[1].X_add_number; 9976 9977 if (CURR_SLOT.opnd[3].X_add_number < 64) 9978 value &= ((valueT)1 << CURR_SLOT.opnd[3].X_add_number) - 1; 9979 value <<= CURR_SLOT.opnd[2].X_add_number; 9980 gr_values[regno].known = 1; 9981 gr_values[regno].value = value; 9982 gr_values[regno].path = md.path; 9983 if (md.debug_dv) 9984 { 9985 fprintf (stderr, " Know gr%d = ", regno); 9986 fprintf_vma (stderr, gr_values[regno].value); 9987 fputs ("\n", stderr); 9988 } 9989 } 9990 } 9991 else 9992 { 9993 clear_qp_mutex (qp_changemask); 9994 clear_qp_implies (qp_changemask, qp_changemask); 9995 } 9996} 9997 9998/* Return whether the given predicate registers are currently mutex. */ 9999 10000static int 10001qp_mutex (int p1, int p2, int path) 10002{ 10003 int i; 10004 valueT mask; 10005 10006 if (p1 != p2) 10007 { 10008 mask = ((valueT) 1 << p1) | (valueT) 1 << p2; 10009 for (i = 0; i < qp_mutexeslen; i++) 10010 { 10011 if (qp_mutexes[i].path >= path 10012 && (qp_mutexes[i].prmask & mask) == mask) 10013 return 1; 10014 } 10015 } 10016 return 0; 10017} 10018 10019/* Return whether the given resource is in the given insn's list of chks 10020 Return 1 if the conflict is absolutely determined, 2 if it's a potential 10021 conflict. */ 10022 10023static int 10024resources_match (struct rsrc *rs, 10025 struct ia64_opcode *idesc, 10026 int note, 10027 int qp_regno, 10028 int path) 10029{ 10030 struct rsrc specs[MAX_SPECS]; 10031 int count; 10032 10033 /* If the marked resource's qp_regno and the given qp_regno are mutex, 10034 we don't need to check. One exception is note 11, which indicates that 10035 target predicates are written regardless of PR[qp]. */ 10036 if (qp_mutex (rs->qp_regno, qp_regno, path) 10037 && note != 11) 10038 return 0; 10039 10040 count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); 10041 while (count-- > 0) 10042 { 10043 /* UNAT checking is a bit more specific than other resources */ 10044 if (rs->dependency->specifier == IA64_RS_AR_UNAT 10045 && specs[count].mem_offset.hint 10046 && rs->mem_offset.hint) 10047 { 10048 if (rs->mem_offset.base == specs[count].mem_offset.base) 10049 { 10050 if (((rs->mem_offset.offset >> 3) & 0x3F) == 10051 ((specs[count].mem_offset.offset >> 3) & 0x3F)) 10052 return 1; 10053 else 10054 continue; 10055 } 10056 } 10057 10058 /* Skip apparent PR write conflicts where both writes are an AND or both 10059 writes are an OR. */ 10060 if (rs->dependency->specifier == IA64_RS_PR 10061 || rs->dependency->specifier == IA64_RS_PRr 10062 || rs->dependency->specifier == IA64_RS_PR63) 10063 { 10064 if (specs[count].cmp_type != CMP_NONE 10065 && specs[count].cmp_type == rs->cmp_type) 10066 { 10067 if (md.debug_dv) 10068 fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", 10069 dv_mode[rs->dependency->mode], 10070 rs->dependency->specifier != IA64_RS_PR63 ? 10071 specs[count].index : 63); 10072 continue; 10073 } 10074 if (md.debug_dv) 10075 fprintf (stderr, 10076 " %s on parallel compare conflict %s vs %s on PR%d\n", 10077 dv_mode[rs->dependency->mode], 10078 dv_cmp_type[rs->cmp_type], 10079 dv_cmp_type[specs[count].cmp_type], 10080 rs->dependency->specifier != IA64_RS_PR63 ? 10081 specs[count].index : 63); 10082 10083 } 10084 10085 /* If either resource is not specific, conservatively assume a conflict 10086 */ 10087 if (!specs[count].specific || !rs->specific) 10088 return 2; 10089 else if (specs[count].index == rs->index) 10090 return 1; 10091 } 10092 10093 return 0; 10094} 10095 10096/* Indicate an instruction group break; if INSERT_STOP is non-zero, then 10097 insert a stop to create the break. Update all resource dependencies 10098 appropriately. If QP_REGNO is non-zero, only apply the break to resources 10099 which use the same QP_REGNO and have the link_to_qp_branch flag set. 10100 If SAVE_CURRENT is non-zero, don't affect resources marked by the current 10101 instruction. */ 10102 10103static void 10104insn_group_break (int insert_stop, int qp_regno, int save_current) 10105{ 10106 int i; 10107 10108 if (insert_stop && md.num_slots_in_use > 0) 10109 PREV_SLOT.end_of_insn_group = 1; 10110 10111 if (md.debug_dv) 10112 { 10113 fprintf (stderr, " Insn group break%s", 10114 (insert_stop ? " (w/stop)" : "")); 10115 if (qp_regno != 0) 10116 fprintf (stderr, " effective for QP=%d", qp_regno); 10117 fprintf (stderr, "\n"); 10118 } 10119 10120 i = 0; 10121 while (i < regdepslen) 10122 { 10123 const struct ia64_dependency *dep = regdeps[i].dependency; 10124 10125 if (qp_regno != 0 10126 && regdeps[i].qp_regno != qp_regno) 10127 { 10128 ++i; 10129 continue; 10130 } 10131 10132 if (save_current 10133 && CURR_SLOT.src_file == regdeps[i].file 10134 && CURR_SLOT.src_line == regdeps[i].line) 10135 { 10136 ++i; 10137 continue; 10138 } 10139 10140 /* clear dependencies which are automatically cleared by a stop, or 10141 those that have reached the appropriate state of insn serialization */ 10142 if (dep->semantics == IA64_DVS_IMPLIED 10143 || dep->semantics == IA64_DVS_IMPLIEDF 10144 || regdeps[i].insn_srlz == STATE_SRLZ) 10145 { 10146 print_dependency ("Removing", i); 10147 regdeps[i] = regdeps[--regdepslen]; 10148 } 10149 else 10150 { 10151 if (dep->semantics == IA64_DVS_DATA 10152 || dep->semantics == IA64_DVS_INSTR 10153 || dep->semantics == IA64_DVS_SPECIFIC) 10154 { 10155 if (regdeps[i].insn_srlz == STATE_NONE) 10156 regdeps[i].insn_srlz = STATE_STOP; 10157 if (regdeps[i].data_srlz == STATE_NONE) 10158 regdeps[i].data_srlz = STATE_STOP; 10159 } 10160 ++i; 10161 } 10162 } 10163} 10164 10165/* Add the given resource usage spec to the list of active dependencies. */ 10166 10167static void 10168mark_resource (struct ia64_opcode *idesc ATTRIBUTE_UNUSED, 10169 const struct ia64_dependency *dep ATTRIBUTE_UNUSED, 10170 struct rsrc *spec, 10171 int depind, 10172 int path) 10173{ 10174 if (regdepslen == regdepstotlen) 10175 { 10176 regdepstotlen += 20; 10177 regdeps = XRESIZEVEC (struct rsrc, regdeps, regdepstotlen); 10178 } 10179 10180 regdeps[regdepslen] = *spec; 10181 regdeps[regdepslen].depind = depind; 10182 regdeps[regdepslen].path = path; 10183 regdeps[regdepslen].file = CURR_SLOT.src_file; 10184 regdeps[regdepslen].line = CURR_SLOT.src_line; 10185 10186 print_dependency ("Adding", regdepslen); 10187 10188 ++regdepslen; 10189} 10190 10191static void 10192print_dependency (const char *action, int depind) 10193{ 10194 if (md.debug_dv) 10195 { 10196 fprintf (stderr, " %s %s '%s'", 10197 action, dv_mode[(regdeps[depind].dependency)->mode], 10198 (regdeps[depind].dependency)->name); 10199 if (regdeps[depind].specific && regdeps[depind].index >= 0) 10200 fprintf (stderr, " (%d)", regdeps[depind].index); 10201 if (regdeps[depind].mem_offset.hint) 10202 { 10203 fputs (" ", stderr); 10204 fprintf_vma (stderr, regdeps[depind].mem_offset.base); 10205 fputs ("+", stderr); 10206 fprintf_vma (stderr, regdeps[depind].mem_offset.offset); 10207 } 10208 fprintf (stderr, "\n"); 10209 } 10210} 10211 10212static void 10213instruction_serialization (void) 10214{ 10215 int i; 10216 if (md.debug_dv) 10217 fprintf (stderr, " Instruction serialization\n"); 10218 for (i = 0; i < regdepslen; i++) 10219 if (regdeps[i].insn_srlz == STATE_STOP) 10220 regdeps[i].insn_srlz = STATE_SRLZ; 10221} 10222 10223static void 10224data_serialization (void) 10225{ 10226 int i = 0; 10227 if (md.debug_dv) 10228 fprintf (stderr, " Data serialization\n"); 10229 while (i < regdepslen) 10230 { 10231 if (regdeps[i].data_srlz == STATE_STOP 10232 /* Note: as of 991210, all "other" dependencies are cleared by a 10233 data serialization. This might change with new tables */ 10234 || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) 10235 { 10236 print_dependency ("Removing", i); 10237 regdeps[i] = regdeps[--regdepslen]; 10238 } 10239 else 10240 ++i; 10241 } 10242} 10243 10244/* Insert stops and serializations as needed to avoid DVs. */ 10245 10246static void 10247remove_marked_resource (struct rsrc *rs) 10248{ 10249 switch (rs->dependency->semantics) 10250 { 10251 case IA64_DVS_SPECIFIC: 10252 if (md.debug_dv) 10253 fprintf (stderr, "Implementation-specific, assume worst case...\n"); 10254 /* Fall through. */ 10255 case IA64_DVS_INSTR: 10256 if (md.debug_dv) 10257 fprintf (stderr, "Inserting instr serialization\n"); 10258 if (rs->insn_srlz < STATE_STOP) 10259 insn_group_break (1, 0, 0); 10260 if (rs->insn_srlz < STATE_SRLZ) 10261 { 10262 struct slot oldslot = CURR_SLOT; 10263 /* Manually jam a srlz.i insn into the stream */ 10264 memset (&CURR_SLOT, 0, sizeof (CURR_SLOT)); 10265 CURR_SLOT.user_template = -1; 10266 CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); 10267 instruction_serialization (); 10268 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 10269 if (++md.num_slots_in_use >= NUM_SLOTS) 10270 emit_one_bundle (); 10271 CURR_SLOT = oldslot; 10272 } 10273 insn_group_break (1, 0, 0); 10274 break; 10275 case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all 10276 "other" types of DV are eliminated 10277 by a data serialization */ 10278 case IA64_DVS_DATA: 10279 if (md.debug_dv) 10280 fprintf (stderr, "Inserting data serialization\n"); 10281 if (rs->data_srlz < STATE_STOP) 10282 insn_group_break (1, 0, 0); 10283 { 10284 struct slot oldslot = CURR_SLOT; 10285 /* Manually jam a srlz.d insn into the stream */ 10286 memset (&CURR_SLOT, 0, sizeof (CURR_SLOT)); 10287 CURR_SLOT.user_template = -1; 10288 CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); 10289 data_serialization (); 10290 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 10291 if (++md.num_slots_in_use >= NUM_SLOTS) 10292 emit_one_bundle (); 10293 CURR_SLOT = oldslot; 10294 } 10295 break; 10296 case IA64_DVS_IMPLIED: 10297 case IA64_DVS_IMPLIEDF: 10298 if (md.debug_dv) 10299 fprintf (stderr, "Inserting stop\n"); 10300 insn_group_break (1, 0, 0); 10301 break; 10302 default: 10303 break; 10304 } 10305} 10306 10307/* Check the resources used by the given opcode against the current dependency 10308 list. 10309 10310 The check is run once for each execution path encountered. In this case, 10311 a unique execution path is the sequence of instructions following a code 10312 entry point, e.g. the following has three execution paths, one starting 10313 at L0, one at L1, and one at L2. 10314 10315 L0: nop 10316 L1: add 10317 L2: add 10318 br.ret 10319*/ 10320 10321static void 10322check_dependencies (struct ia64_opcode *idesc) 10323{ 10324 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 10325 int path; 10326 int i; 10327 10328 /* Note that the number of marked resources may change within the 10329 loop if in auto mode. */ 10330 i = 0; 10331 while (i < regdepslen) 10332 { 10333 struct rsrc *rs = ®deps[i]; 10334 const struct ia64_dependency *dep = rs->dependency; 10335 int chkind; 10336 int note; 10337 int start_over = 0; 10338 10339 if (dep->semantics == IA64_DVS_NONE 10340 || (chkind = depends_on (rs->depind, idesc)) == -1) 10341 { 10342 ++i; 10343 continue; 10344 } 10345 10346 note = NOTE (opdeps->chks[chkind]); 10347 10348 /* Check this resource against each execution path seen thus far. */ 10349 for (path = 0; path <= md.path; path++) 10350 { 10351 int matchtype; 10352 10353 /* If the dependency wasn't on the path being checked, ignore it. */ 10354 if (rs->path < path) 10355 continue; 10356 10357 /* If the QP for this insn implies a QP which has branched, don't 10358 bother checking. Ed. NOTE: I don't think this check is terribly 10359 useful; what's the point of generating code which will only be 10360 reached if its QP is zero? 10361 This code was specifically inserted to handle the following code, 10362 based on notes from Intel's DV checking code, where p1 implies p2. 10363 10364 mov r4 = 2 10365 (p2) br.cond L 10366 (p1) mov r4 = 7 10367 */ 10368 if (CURR_SLOT.qp_regno != 0) 10369 { 10370 int skip = 0; 10371 int implies; 10372 for (implies = 0; implies < qp_implieslen; implies++) 10373 { 10374 if (qp_implies[implies].path >= path 10375 && qp_implies[implies].p1 == CURR_SLOT.qp_regno 10376 && qp_implies[implies].p2_branched) 10377 { 10378 skip = 1; 10379 break; 10380 } 10381 } 10382 if (skip) 10383 continue; 10384 } 10385 10386 if ((matchtype = resources_match (rs, idesc, note, 10387 CURR_SLOT.qp_regno, path)) != 0) 10388 { 10389 char msg[1024]; 10390 char pathmsg[256] = ""; 10391 char indexmsg[256] = ""; 10392 int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); 10393 10394 if (path != 0) 10395 snprintf (pathmsg, sizeof (pathmsg), 10396 " when entry is at label '%s'", 10397 md.entry_labels[path - 1]); 10398 if (matchtype == 1 && rs->index >= 0) 10399 snprintf (indexmsg, sizeof (indexmsg), 10400 ", specific resource number is %d", 10401 rs->index); 10402 snprintf (msg, sizeof (msg), 10403 "Use of '%s' %s %s dependency '%s' (%s)%s%s", 10404 idesc->name, 10405 (certain ? "violates" : "may violate"), 10406 dv_mode[dep->mode], dep->name, 10407 dv_sem[dep->semantics], 10408 pathmsg, indexmsg); 10409 10410 if (md.explicit_mode) 10411 { 10412 as_warn ("%s", msg); 10413 if (path < md.path) 10414 as_warn (_("Only the first path encountering the conflict is reported")); 10415 as_warn_where (rs->file, rs->line, 10416 _("This is the location of the conflicting usage")); 10417 /* Don't bother checking other paths, to avoid duplicating 10418 the same warning */ 10419 break; 10420 } 10421 else 10422 { 10423 if (md.debug_dv) 10424 fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); 10425 10426 remove_marked_resource (rs); 10427 10428 /* since the set of dependencies has changed, start over */ 10429 /* FIXME -- since we're removing dvs as we go, we 10430 probably don't really need to start over... */ 10431 start_over = 1; 10432 break; 10433 } 10434 } 10435 } 10436 if (start_over) 10437 i = 0; 10438 else 10439 ++i; 10440 } 10441} 10442 10443/* Register new dependencies based on the given opcode. */ 10444 10445static void 10446mark_resources (struct ia64_opcode *idesc) 10447{ 10448 int i; 10449 const struct ia64_opcode_dependency *opdeps = idesc->dependencies; 10450 int add_only_qp_reads = 0; 10451 10452 /* A conditional branch only uses its resources if it is taken; if it is 10453 taken, we stop following that path. The other branch types effectively 10454 *always* write their resources. If it's not taken, register only QP 10455 reads. */ 10456 if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) 10457 { 10458 add_only_qp_reads = 1; 10459 } 10460 10461 if (md.debug_dv) 10462 fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); 10463 10464 for (i = 0; i < opdeps->nregs; i++) 10465 { 10466 const struct ia64_dependency *dep; 10467 struct rsrc specs[MAX_SPECS]; 10468 int note; 10469 int path; 10470 int count; 10471 10472 dep = ia64_find_dependency (opdeps->regs[i]); 10473 note = NOTE (opdeps->regs[i]); 10474 10475 if (add_only_qp_reads 10476 && !(dep->mode == IA64_DV_WAR 10477 && (dep->specifier == IA64_RS_PR 10478 || dep->specifier == IA64_RS_PRr 10479 || dep->specifier == IA64_RS_PR63))) 10480 continue; 10481 10482 count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); 10483 10484 while (count-- > 0) 10485 { 10486 mark_resource (idesc, dep, &specs[count], 10487 DEP (opdeps->regs[i]), md.path); 10488 } 10489 10490 /* The execution path may affect register values, which may in turn 10491 affect which indirect-access resources are accessed. */ 10492 switch (dep->specifier) 10493 { 10494 default: 10495 break; 10496 case IA64_RS_CPUID: 10497 case IA64_RS_DBR: 10498 case IA64_RS_IBR: 10499 case IA64_RS_MSR: 10500 case IA64_RS_PKR: 10501 case IA64_RS_PMC: 10502 case IA64_RS_PMD: 10503 case IA64_RS_RR: 10504 for (path = 0; path < md.path; path++) 10505 { 10506 count = specify_resource (dep, idesc, DV_REG, specs, note, path); 10507 while (count-- > 0) 10508 mark_resource (idesc, dep, &specs[count], 10509 DEP (opdeps->regs[i]), path); 10510 } 10511 break; 10512 } 10513 } 10514} 10515 10516/* Remove dependencies when they no longer apply. */ 10517 10518static void 10519update_dependencies (struct ia64_opcode *idesc) 10520{ 10521 int i; 10522 10523 if (strcmp (idesc->name, "srlz.i") == 0) 10524 { 10525 instruction_serialization (); 10526 } 10527 else if (strcmp (idesc->name, "srlz.d") == 0) 10528 { 10529 data_serialization (); 10530 } 10531 else if (is_interruption_or_rfi (idesc) 10532 || is_taken_branch (idesc)) 10533 { 10534 /* Although technically the taken branch doesn't clear dependencies 10535 which require a srlz.[id], we don't follow the branch; the next 10536 instruction is assumed to start with a clean slate. */ 10537 regdepslen = 0; 10538 md.path = 0; 10539 } 10540 else if (is_conditional_branch (idesc) 10541 && CURR_SLOT.qp_regno != 0) 10542 { 10543 int is_call = strstr (idesc->name, ".call") != NULL; 10544 10545 for (i = 0; i < qp_implieslen; i++) 10546 { 10547 /* If the conditional branch's predicate is implied by the predicate 10548 in an existing dependency, remove that dependency. */ 10549 if (qp_implies[i].p2 == CURR_SLOT.qp_regno) 10550 { 10551 int depind = 0; 10552 /* Note that this implied predicate takes a branch so that if 10553 a later insn generates a DV but its predicate implies this 10554 one, we can avoid the false DV warning. */ 10555 qp_implies[i].p2_branched = 1; 10556 while (depind < regdepslen) 10557 { 10558 if (regdeps[depind].qp_regno == qp_implies[i].p1) 10559 { 10560 print_dependency ("Removing", depind); 10561 regdeps[depind] = regdeps[--regdepslen]; 10562 } 10563 else 10564 ++depind; 10565 } 10566 } 10567 } 10568 /* Any marked resources which have this same predicate should be 10569 cleared, provided that the QP hasn't been modified between the 10570 marking instruction and the branch. */ 10571 if (is_call) 10572 { 10573 insn_group_break (0, CURR_SLOT.qp_regno, 1); 10574 } 10575 else 10576 { 10577 i = 0; 10578 while (i < regdepslen) 10579 { 10580 if (regdeps[i].qp_regno == CURR_SLOT.qp_regno 10581 && regdeps[i].link_to_qp_branch 10582 && (regdeps[i].file != CURR_SLOT.src_file 10583 || regdeps[i].line != CURR_SLOT.src_line)) 10584 { 10585 /* Treat like a taken branch */ 10586 print_dependency ("Removing", i); 10587 regdeps[i] = regdeps[--regdepslen]; 10588 } 10589 else 10590 ++i; 10591 } 10592 } 10593 } 10594} 10595 10596/* Examine the current instruction for dependency violations. */ 10597 10598static int 10599check_dv (struct ia64_opcode *idesc) 10600{ 10601 if (md.debug_dv) 10602 { 10603 fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", 10604 idesc->name, CURR_SLOT.src_line, 10605 idesc->dependencies->nchks, 10606 idesc->dependencies->nregs); 10607 } 10608 10609 /* Look through the list of currently marked resources; if the current 10610 instruction has the dependency in its chks list which uses that resource, 10611 check against the specific resources used. */ 10612 check_dependencies (idesc); 10613 10614 /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), 10615 then add them to the list of marked resources. */ 10616 mark_resources (idesc); 10617 10618 /* There are several types of dependency semantics, and each has its own 10619 requirements for being cleared 10620 10621 Instruction serialization (insns separated by interruption, rfi, or 10622 writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. 10623 10624 Data serialization (instruction serialization, or writer + srlz.d + 10625 reader, where writer and srlz.d are in separate groups) clears 10626 DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to 10627 always be the case). 10628 10629 Instruction group break (groups separated by stop, taken branch, 10630 interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. 10631 */ 10632 update_dependencies (idesc); 10633 10634 /* Sometimes, knowing a register value allows us to avoid giving a false DV 10635 warning. Keep track of as many as possible that are useful. */ 10636 note_register_values (idesc); 10637 10638 /* We don't need or want this anymore. */ 10639 md.mem_offset.hint = 0; 10640 10641 return 0; 10642} 10643 10644/* Translate one line of assembly. Pseudo ops and labels do not show 10645 here. */ 10646void 10647md_assemble (char *str) 10648{ 10649 char *saved_input_line_pointer, *temp; 10650 const char *mnemonic; 10651 const struct pseudo_opcode *pdesc; 10652 struct ia64_opcode *idesc; 10653 unsigned char qp_regno; 10654 unsigned int flags; 10655 int ch; 10656 10657 saved_input_line_pointer = input_line_pointer; 10658 input_line_pointer = str; 10659 10660 /* extract the opcode (mnemonic): */ 10661 10662 ch = get_symbol_name (&temp); 10663 mnemonic = temp; 10664 pdesc = (struct pseudo_opcode *) str_hash_find (md.pseudo_hash, mnemonic); 10665 if (pdesc) 10666 { 10667 (void) restore_line_pointer (ch); 10668 (*pdesc->handler) (pdesc->arg); 10669 goto done; 10670 } 10671 10672 /* Find the instruction descriptor matching the arguments. */ 10673 10674 idesc = ia64_find_opcode (mnemonic); 10675 (void) restore_line_pointer (ch); 10676 if (!idesc) 10677 { 10678 as_bad (_("Unknown opcode `%s'"), mnemonic); 10679 goto done; 10680 } 10681 10682 idesc = parse_operands (idesc); 10683 if (!idesc) 10684 goto done; 10685 10686 /* Handle the dynamic ops we can handle now: */ 10687 if (idesc->type == IA64_TYPE_DYN) 10688 { 10689 if (strcmp (idesc->name, "add") == 0) 10690 { 10691 if (CURR_SLOT.opnd[2].X_op == O_register 10692 && CURR_SLOT.opnd[2].X_add_number < 4) 10693 mnemonic = "addl"; 10694 else 10695 mnemonic = "adds"; 10696 ia64_free_opcode (idesc); 10697 idesc = ia64_find_opcode (mnemonic); 10698 } 10699 else if (strcmp (idesc->name, "mov") == 0) 10700 { 10701 enum ia64_opnd opnd1, opnd2; 10702 int rop; 10703 10704 opnd1 = idesc->operands[0]; 10705 opnd2 = idesc->operands[1]; 10706 if (opnd1 == IA64_OPND_AR3) 10707 rop = 0; 10708 else if (opnd2 == IA64_OPND_AR3) 10709 rop = 1; 10710 else 10711 abort (); 10712 if (CURR_SLOT.opnd[rop].X_op == O_register) 10713 { 10714 if (ar_is_only_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) 10715 mnemonic = "mov.i"; 10716 else if (ar_is_only_in_memory_unit (CURR_SLOT.opnd[rop].X_add_number)) 10717 mnemonic = "mov.m"; 10718 else 10719 rop = -1; 10720 } 10721 else 10722 abort (); 10723 if (rop >= 0) 10724 { 10725 ia64_free_opcode (idesc); 10726 idesc = ia64_find_opcode (mnemonic); 10727 while (idesc != NULL 10728 && (idesc->operands[0] != opnd1 10729 || idesc->operands[1] != opnd2)) 10730 idesc = get_next_opcode (idesc); 10731 } 10732 } 10733 } 10734 else if (strcmp (idesc->name, "mov.i") == 0 10735 || strcmp (idesc->name, "mov.m") == 0) 10736 { 10737 enum ia64_opnd opnd1, opnd2; 10738 int rop; 10739 10740 opnd1 = idesc->operands[0]; 10741 opnd2 = idesc->operands[1]; 10742 if (opnd1 == IA64_OPND_AR3) 10743 rop = 0; 10744 else if (opnd2 == IA64_OPND_AR3) 10745 rop = 1; 10746 else 10747 abort (); 10748 if (CURR_SLOT.opnd[rop].X_op == O_register) 10749 { 10750 char unit = 'a'; 10751 if (ar_is_only_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) 10752 unit = 'i'; 10753 else if (ar_is_only_in_memory_unit (CURR_SLOT.opnd[rop].X_add_number)) 10754 unit = 'm'; 10755 if (unit != 'a' && unit != idesc->name [4]) 10756 as_bad (_("AR %d can only be accessed by %c-unit"), 10757 (int) (CURR_SLOT.opnd[rop].X_add_number - REG_AR), 10758 TOUPPER (unit)); 10759 } 10760 } 10761 else if (strcmp (idesc->name, "hint.b") == 0) 10762 { 10763 switch (md.hint_b) 10764 { 10765 case hint_b_ok: 10766 break; 10767 case hint_b_warning: 10768 as_warn (_("hint.b may be treated as nop")); 10769 break; 10770 case hint_b_error: 10771 as_bad (_("hint.b shouldn't be used")); 10772 break; 10773 } 10774 } 10775 10776 qp_regno = 0; 10777 if (md.qp.X_op == O_register) 10778 { 10779 qp_regno = md.qp.X_add_number - REG_P; 10780 md.qp.X_op = O_absent; 10781 } 10782 10783 flags = idesc->flags; 10784 10785 if ((flags & IA64_OPCODE_FIRST) != 0) 10786 { 10787 /* The alignment frag has to end with a stop bit only if the 10788 next instruction after the alignment directive has to be 10789 the first instruction in an instruction group. */ 10790 if (align_frag) 10791 { 10792 while (align_frag->fr_type != rs_align_code) 10793 { 10794 align_frag = align_frag->fr_next; 10795 if (!align_frag) 10796 break; 10797 } 10798 /* align_frag can be NULL if there are directives in 10799 between. */ 10800 if (align_frag && align_frag->fr_next == frag_now) 10801 align_frag->tc_frag_data = 1; 10802 } 10803 10804 insn_group_break (1, 0, 0); 10805 } 10806 align_frag = NULL; 10807 10808 if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) 10809 { 10810 as_bad (_("`%s' cannot be predicated"), idesc->name); 10811 goto done; 10812 } 10813 10814 /* Build the instruction. */ 10815 CURR_SLOT.qp_regno = qp_regno; 10816 CURR_SLOT.idesc = idesc; 10817 CURR_SLOT.src_file = as_where (&CURR_SLOT.src_line); 10818 dwarf2_where (&CURR_SLOT.debug_line); 10819 dwarf2_consume_line_info (); 10820 10821 /* Add unwind entries, if there are any. */ 10822 if (unwind.current_entry) 10823 { 10824 CURR_SLOT.unwind_record = unwind.current_entry; 10825 unwind.current_entry = NULL; 10826 } 10827 if (unwind.pending_saves) 10828 { 10829 if (unwind.pending_saves->next) 10830 { 10831 /* Attach the next pending save to the next slot so that its 10832 slot number will get set correctly. */ 10833 add_unwind_entry (unwind.pending_saves->next, NOT_A_CHAR); 10834 unwind.pending_saves = &unwind.pending_saves->next->r.record.p; 10835 } 10836 else 10837 unwind.pending_saves = NULL; 10838 } 10839 if (unwind.proc_pending.sym && S_IS_DEFINED (unwind.proc_pending.sym)) 10840 unwind.insn = 1; 10841 10842 /* Check for dependency violations. */ 10843 if (md.detect_dv) 10844 check_dv (idesc); 10845 10846 md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; 10847 if (++md.num_slots_in_use >= NUM_SLOTS) 10848 emit_one_bundle (); 10849 10850 if ((flags & IA64_OPCODE_LAST) != 0) 10851 insn_group_break (1, 0, 0); 10852 10853 md.last_text_seg = now_seg; 10854 10855 done: 10856 input_line_pointer = saved_input_line_pointer; 10857} 10858 10859/* Called when symbol NAME cannot be found in the symbol table. 10860 Should be used for dynamic valued symbols only. */ 10861 10862symbolS * 10863md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 10864{ 10865 return 0; 10866} 10867 10868/* Called for any expression that can not be recognized. When the 10869 function is called, `input_line_pointer' will point to the start of 10870 the expression. */ 10871 10872void 10873md_operand (expressionS *e) 10874{ 10875 switch (*input_line_pointer) 10876 { 10877 case '[': 10878 ++input_line_pointer; 10879 expression_and_evaluate (e); 10880 if (*input_line_pointer != ']') 10881 { 10882 as_bad (_("Closing bracket missing")); 10883 goto err; 10884 } 10885 else 10886 { 10887 if (e->X_op != O_register 10888 || e->X_add_number < REG_GR 10889 || e->X_add_number > REG_GR + 127) 10890 { 10891 as_bad (_("Index must be a general register")); 10892 e->X_add_number = REG_GR; 10893 } 10894 10895 ++input_line_pointer; 10896 e->X_op = O_index; 10897 } 10898 break; 10899 10900 default: 10901 break; 10902 } 10903 return; 10904 10905 err: 10906 ignore_rest_of_line (); 10907} 10908 10909/* Return 1 if it's OK to adjust a reloc by replacing the symbol with 10910 a section symbol plus some offset. For relocs involving @fptr(), 10911 directives we don't want such adjustments since we need to have the 10912 original symbol's name in the reloc. */ 10913int 10914ia64_fix_adjustable (fixS *fix) 10915{ 10916 /* Prevent all adjustments to global symbols */ 10917 if (S_IS_EXTERNAL (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) 10918 return 0; 10919 10920 switch (fix->fx_r_type) 10921 { 10922 case BFD_RELOC_IA64_FPTR64I: 10923 case BFD_RELOC_IA64_FPTR32MSB: 10924 case BFD_RELOC_IA64_FPTR32LSB: 10925 case BFD_RELOC_IA64_FPTR64MSB: 10926 case BFD_RELOC_IA64_FPTR64LSB: 10927 case BFD_RELOC_IA64_LTOFF_FPTR22: 10928 case BFD_RELOC_IA64_LTOFF_FPTR64I: 10929 return 0; 10930 default: 10931 break; 10932 } 10933 10934 return 1; 10935} 10936 10937int 10938ia64_force_relocation (fixS *fix) 10939{ 10940 switch (fix->fx_r_type) 10941 { 10942 case BFD_RELOC_IA64_FPTR64I: 10943 case BFD_RELOC_IA64_FPTR32MSB: 10944 case BFD_RELOC_IA64_FPTR32LSB: 10945 case BFD_RELOC_IA64_FPTR64MSB: 10946 case BFD_RELOC_IA64_FPTR64LSB: 10947 10948 case BFD_RELOC_IA64_LTOFF22: 10949 case BFD_RELOC_IA64_LTOFF64I: 10950 case BFD_RELOC_IA64_LTOFF_FPTR22: 10951 case BFD_RELOC_IA64_LTOFF_FPTR64I: 10952 case BFD_RELOC_IA64_PLTOFF22: 10953 case BFD_RELOC_IA64_PLTOFF64I: 10954 case BFD_RELOC_IA64_PLTOFF64MSB: 10955 case BFD_RELOC_IA64_PLTOFF64LSB: 10956 10957 case BFD_RELOC_IA64_LTOFF22X: 10958 case BFD_RELOC_IA64_LDXMOV: 10959 return 1; 10960 10961 default: 10962 break; 10963 } 10964 10965 return generic_force_reloc (fix); 10966} 10967 10968/* Decide from what point a pc-relative relocation is relative to, 10969 relative to the pc-relative fixup. Er, relatively speaking. */ 10970long 10971ia64_pcrel_from_section (fixS *fix, segT sec) 10972{ 10973 unsigned long off = fix->fx_frag->fr_address + fix->fx_where; 10974 10975 if (bfd_section_flags (sec) & SEC_CODE) 10976 off &= ~0xfUL; 10977 10978 return off; 10979} 10980 10981 10982/* Used to emit section-relative relocs for the dwarf2 debug data. */ 10983void 10984ia64_dwarf2_emit_offset (symbolS *symbol, unsigned int size) 10985{ 10986 expressionS exp; 10987 10988 exp.X_op = O_pseudo_fixup; 10989 exp.X_op_symbol = pseudo_func[FUNC_SEC_RELATIVE].u.sym; 10990 exp.X_add_number = 0; 10991 exp.X_add_symbol = symbol; 10992 emit_expr (&exp, size); 10993} 10994 10995/* This is called whenever some data item (not an instruction) needs a 10996 fixup. We pick the right reloc code depending on the byteorder 10997 currently in effect. */ 10998void 10999ia64_cons_fix_new (fragS *f, int where, int nbytes, expressionS *exp, 11000 bfd_reloc_code_real_type code) 11001{ 11002 fixS *fix; 11003 11004 switch (nbytes) 11005 { 11006 /* There are no reloc for 8 and 16 bit quantities, but we allow 11007 them here since they will work fine as long as the expression 11008 is fully defined at the end of the pass over the source file. */ 11009 case 1: code = BFD_RELOC_8; break; 11010 case 2: code = BFD_RELOC_16; break; 11011 case 4: 11012 if (target_big_endian) 11013 code = BFD_RELOC_IA64_DIR32MSB; 11014 else 11015 code = BFD_RELOC_IA64_DIR32LSB; 11016 break; 11017 11018 case 8: 11019 /* In 32-bit mode, data8 could mean function descriptors too. */ 11020 if (exp->X_op == O_pseudo_fixup 11021 && exp->X_op_symbol 11022 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC 11023 && !(md.flags & EF_IA_64_ABI64)) 11024 { 11025 if (target_big_endian) 11026 code = BFD_RELOC_IA64_IPLTMSB; 11027 else 11028 code = BFD_RELOC_IA64_IPLTLSB; 11029 exp->X_op = O_symbol; 11030 break; 11031 } 11032 else 11033 { 11034 if (target_big_endian) 11035 code = BFD_RELOC_IA64_DIR64MSB; 11036 else 11037 code = BFD_RELOC_IA64_DIR64LSB; 11038 break; 11039 } 11040 11041 case 16: 11042 if (exp->X_op == O_pseudo_fixup 11043 && exp->X_op_symbol 11044 && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC) 11045 { 11046 if (target_big_endian) 11047 code = BFD_RELOC_IA64_IPLTMSB; 11048 else 11049 code = BFD_RELOC_IA64_IPLTLSB; 11050 exp->X_op = O_symbol; 11051 break; 11052 } 11053 /* FALLTHRU */ 11054 11055 default: 11056 as_bad (_("Unsupported fixup size %d"), nbytes); 11057 ignore_rest_of_line (); 11058 return; 11059 } 11060 11061 if (exp->X_op == O_pseudo_fixup) 11062 { 11063 exp->X_op = O_symbol; 11064 code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); 11065 /* ??? If code unchanged, unsupported. */ 11066 } 11067 11068 fix = fix_new_exp (f, where, nbytes, exp, 0, code); 11069 /* We need to store the byte order in effect in case we're going 11070 to fix an 8 or 16 bit relocation (for which there no real 11071 relocs available). See md_apply_fix(). */ 11072 fix->tc_fix_data.bigendian = target_big_endian; 11073} 11074 11075/* Return the actual relocation we wish to associate with the pseudo 11076 reloc described by SYM and R_TYPE. SYM should be one of the 11077 symbols in the pseudo_func array, or NULL. */ 11078 11079static bfd_reloc_code_real_type 11080ia64_gen_real_reloc_type (struct symbol *sym, bfd_reloc_code_real_type r_type) 11081{ 11082 bfd_reloc_code_real_type newr = 0; 11083 const char *type = NULL, *suffix = ""; 11084 11085 if (sym == NULL) 11086 { 11087 return r_type; 11088 } 11089 11090 switch (S_GET_VALUE (sym)) 11091 { 11092 case FUNC_FPTR_RELATIVE: 11093 switch (r_type) 11094 { 11095 case BFD_RELOC_IA64_IMM64: newr = BFD_RELOC_IA64_FPTR64I; break; 11096 case BFD_RELOC_IA64_DIR32MSB: newr = BFD_RELOC_IA64_FPTR32MSB; break; 11097 case BFD_RELOC_IA64_DIR32LSB: newr = BFD_RELOC_IA64_FPTR32LSB; break; 11098 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_FPTR64MSB; break; 11099 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_FPTR64LSB; break; 11100 default: type = "FPTR"; break; 11101 } 11102 break; 11103 11104 case FUNC_GP_RELATIVE: 11105 switch (r_type) 11106 { 11107 case BFD_RELOC_IA64_IMM22: newr = BFD_RELOC_IA64_GPREL22; break; 11108 case BFD_RELOC_IA64_IMM64: newr = BFD_RELOC_IA64_GPREL64I; break; 11109 case BFD_RELOC_IA64_DIR32MSB: newr = BFD_RELOC_IA64_GPREL32MSB; break; 11110 case BFD_RELOC_IA64_DIR32LSB: newr = BFD_RELOC_IA64_GPREL32LSB; break; 11111 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_GPREL64MSB; break; 11112 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_GPREL64LSB; break; 11113 default: type = "GPREL"; break; 11114 } 11115 break; 11116 11117 case FUNC_LT_RELATIVE: 11118 switch (r_type) 11119 { 11120 case BFD_RELOC_IA64_IMM22: newr = BFD_RELOC_IA64_LTOFF22; break; 11121 case BFD_RELOC_IA64_IMM64: newr = BFD_RELOC_IA64_LTOFF64I; break; 11122 default: type = "LTOFF"; break; 11123 } 11124 break; 11125 11126 case FUNC_LT_RELATIVE_X: 11127 switch (r_type) 11128 { 11129 case BFD_RELOC_IA64_IMM22: newr = BFD_RELOC_IA64_LTOFF22X; break; 11130 default: type = "LTOFF"; suffix = "X"; break; 11131 } 11132 break; 11133 11134 case FUNC_PC_RELATIVE: 11135 switch (r_type) 11136 { 11137 case BFD_RELOC_IA64_IMM22: newr = BFD_RELOC_IA64_PCREL22; break; 11138 case BFD_RELOC_IA64_IMM64: newr = BFD_RELOC_IA64_PCREL64I; break; 11139 case BFD_RELOC_IA64_DIR32MSB: newr = BFD_RELOC_IA64_PCREL32MSB; break; 11140 case BFD_RELOC_IA64_DIR32LSB: newr = BFD_RELOC_IA64_PCREL32LSB; break; 11141 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_PCREL64MSB; break; 11142 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_PCREL64LSB; break; 11143 default: type = "PCREL"; break; 11144 } 11145 break; 11146 11147 case FUNC_PLT_RELATIVE: 11148 switch (r_type) 11149 { 11150 case BFD_RELOC_IA64_IMM22: newr = BFD_RELOC_IA64_PLTOFF22; break; 11151 case BFD_RELOC_IA64_IMM64: newr = BFD_RELOC_IA64_PLTOFF64I; break; 11152 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_PLTOFF64MSB;break; 11153 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_PLTOFF64LSB;break; 11154 default: type = "PLTOFF"; break; 11155 } 11156 break; 11157 11158 case FUNC_SEC_RELATIVE: 11159 switch (r_type) 11160 { 11161 case BFD_RELOC_IA64_DIR32MSB: newr = BFD_RELOC_IA64_SECREL32MSB;break; 11162 case BFD_RELOC_IA64_DIR32LSB: newr = BFD_RELOC_IA64_SECREL32LSB;break; 11163 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_SECREL64MSB;break; 11164 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_SECREL64LSB;break; 11165 default: type = "SECREL"; break; 11166 } 11167 break; 11168 11169 case FUNC_SEG_RELATIVE: 11170 switch (r_type) 11171 { 11172 case BFD_RELOC_IA64_DIR32MSB: newr = BFD_RELOC_IA64_SEGREL32MSB;break; 11173 case BFD_RELOC_IA64_DIR32LSB: newr = BFD_RELOC_IA64_SEGREL32LSB;break; 11174 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_SEGREL64MSB;break; 11175 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_SEGREL64LSB;break; 11176 default: type = "SEGREL"; break; 11177 } 11178 break; 11179 11180 case FUNC_LTV_RELATIVE: 11181 switch (r_type) 11182 { 11183 case BFD_RELOC_IA64_DIR32MSB: newr = BFD_RELOC_IA64_LTV32MSB; break; 11184 case BFD_RELOC_IA64_DIR32LSB: newr = BFD_RELOC_IA64_LTV32LSB; break; 11185 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_LTV64MSB; break; 11186 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_LTV64LSB; break; 11187 default: type = "LTV"; break; 11188 } 11189 break; 11190 11191 case FUNC_LT_FPTR_RELATIVE: 11192 switch (r_type) 11193 { 11194 case BFD_RELOC_IA64_IMM22: 11195 newr = BFD_RELOC_IA64_LTOFF_FPTR22; break; 11196 case BFD_RELOC_IA64_IMM64: 11197 newr = BFD_RELOC_IA64_LTOFF_FPTR64I; break; 11198 case BFD_RELOC_IA64_DIR32MSB: 11199 newr = BFD_RELOC_IA64_LTOFF_FPTR32MSB; break; 11200 case BFD_RELOC_IA64_DIR32LSB: 11201 newr = BFD_RELOC_IA64_LTOFF_FPTR32LSB; break; 11202 case BFD_RELOC_IA64_DIR64MSB: 11203 newr = BFD_RELOC_IA64_LTOFF_FPTR64MSB; break; 11204 case BFD_RELOC_IA64_DIR64LSB: 11205 newr = BFD_RELOC_IA64_LTOFF_FPTR64LSB; break; 11206 default: 11207 type = "LTOFF_FPTR"; break; 11208 } 11209 break; 11210 11211 case FUNC_TP_RELATIVE: 11212 switch (r_type) 11213 { 11214 case BFD_RELOC_IA64_IMM14: newr = BFD_RELOC_IA64_TPREL14; break; 11215 case BFD_RELOC_IA64_IMM22: newr = BFD_RELOC_IA64_TPREL22; break; 11216 case BFD_RELOC_IA64_IMM64: newr = BFD_RELOC_IA64_TPREL64I; break; 11217 case BFD_RELOC_IA64_DIR64MSB: newr = BFD_RELOC_IA64_TPREL64MSB; break; 11218 case BFD_RELOC_IA64_DIR64LSB: newr = BFD_RELOC_IA64_TPREL64LSB; break; 11219 default: type = "TPREL"; break; 11220 } 11221 break; 11222 11223 case FUNC_LT_TP_RELATIVE: 11224 switch (r_type) 11225 { 11226 case BFD_RELOC_IA64_IMM22: 11227 newr = BFD_RELOC_IA64_LTOFF_TPREL22; break; 11228 default: 11229 type = "LTOFF_TPREL"; break; 11230 } 11231 break; 11232 11233 case FUNC_DTP_MODULE: 11234 switch (r_type) 11235 { 11236 case BFD_RELOC_IA64_DIR64MSB: 11237 newr = BFD_RELOC_IA64_DTPMOD64MSB; break; 11238 case BFD_RELOC_IA64_DIR64LSB: 11239 newr = BFD_RELOC_IA64_DTPMOD64LSB; break; 11240 default: 11241 type = "DTPMOD"; break; 11242 } 11243 break; 11244 11245 case FUNC_LT_DTP_MODULE: 11246 switch (r_type) 11247 { 11248 case BFD_RELOC_IA64_IMM22: 11249 newr = BFD_RELOC_IA64_LTOFF_DTPMOD22; break; 11250 default: 11251 type = "LTOFF_DTPMOD"; break; 11252 } 11253 break; 11254 11255 case FUNC_DTP_RELATIVE: 11256 switch (r_type) 11257 { 11258 case BFD_RELOC_IA64_DIR32MSB: 11259 newr = BFD_RELOC_IA64_DTPREL32MSB; break; 11260 case BFD_RELOC_IA64_DIR32LSB: 11261 newr = BFD_RELOC_IA64_DTPREL32LSB; break; 11262 case BFD_RELOC_IA64_DIR64MSB: 11263 newr = BFD_RELOC_IA64_DTPREL64MSB; break; 11264 case BFD_RELOC_IA64_DIR64LSB: 11265 newr = BFD_RELOC_IA64_DTPREL64LSB; break; 11266 case BFD_RELOC_IA64_IMM14: 11267 newr = BFD_RELOC_IA64_DTPREL14; break; 11268 case BFD_RELOC_IA64_IMM22: 11269 newr = BFD_RELOC_IA64_DTPREL22; break; 11270 case BFD_RELOC_IA64_IMM64: 11271 newr = BFD_RELOC_IA64_DTPREL64I; break; 11272 default: 11273 type = "DTPREL"; break; 11274 } 11275 break; 11276 11277 case FUNC_LT_DTP_RELATIVE: 11278 switch (r_type) 11279 { 11280 case BFD_RELOC_IA64_IMM22: 11281 newr = BFD_RELOC_IA64_LTOFF_DTPREL22; break; 11282 default: 11283 type = "LTOFF_DTPREL"; break; 11284 } 11285 break; 11286 11287 case FUNC_IPLT_RELOC: 11288 switch (r_type) 11289 { 11290 case BFD_RELOC_IA64_IPLTMSB: return r_type; 11291 case BFD_RELOC_IA64_IPLTLSB: return r_type; 11292 default: type = "IPLT"; break; 11293 } 11294 break; 11295 11296#ifdef TE_VMS 11297 case FUNC_SLOTCOUNT_RELOC: 11298 return DUMMY_RELOC_IA64_SLOTCOUNT; 11299#endif 11300 11301 default: 11302 abort (); 11303 } 11304 11305 if (newr) 11306 return newr; 11307 else 11308 { 11309 int width; 11310 11311 if (!type) 11312 abort (); 11313 switch (r_type) 11314 { 11315 case BFD_RELOC_IA64_DIR32MSB: width = 32; suffix = "MSB"; break; 11316 case BFD_RELOC_IA64_DIR32LSB: width = 32; suffix = "LSB"; break; 11317 case BFD_RELOC_IA64_DIR64MSB: width = 64; suffix = "MSB"; break; 11318 case BFD_RELOC_IA64_DIR64LSB: width = 64; suffix = "LSB"; break; 11319 case BFD_RELOC_UNUSED: width = 13; break; 11320 case BFD_RELOC_IA64_IMM14: width = 14; break; 11321 case BFD_RELOC_IA64_IMM22: width = 22; break; 11322 case BFD_RELOC_IA64_IMM64: width = 64; suffix = "I"; break; 11323 default: abort (); 11324 } 11325 11326 /* This should be an error, but since previously there wasn't any 11327 diagnostic here, don't make it fail because of this for now. */ 11328 as_warn (_("Cannot express %s%d%s relocation"), type, width, suffix); 11329 return r_type; 11330 } 11331} 11332 11333/* Here is where generate the appropriate reloc for pseudo relocation 11334 functions. */ 11335void 11336ia64_validate_fix (fixS *fix) 11337{ 11338 switch (fix->fx_r_type) 11339 { 11340 case BFD_RELOC_IA64_FPTR64I: 11341 case BFD_RELOC_IA64_FPTR32MSB: 11342 case BFD_RELOC_IA64_FPTR64LSB: 11343 case BFD_RELOC_IA64_LTOFF_FPTR22: 11344 case BFD_RELOC_IA64_LTOFF_FPTR64I: 11345 if (fix->fx_offset != 0) 11346 as_bad_where (fix->fx_file, fix->fx_line, 11347 _("No addend allowed in @fptr() relocation")); 11348 break; 11349 default: 11350 break; 11351 } 11352} 11353 11354static void 11355fix_insn (fixS *fix, const struct ia64_operand *odesc, valueT value) 11356{ 11357 bfd_vma insn[3], t0, t1, control_bits; 11358 const char *err; 11359 char *fixpos; 11360 long slot; 11361 11362 slot = fix->fx_where & 0x3; 11363 fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); 11364 11365 /* Bundles are always in little-endian byte order */ 11366 t0 = bfd_getl64 (fixpos); 11367 t1 = bfd_getl64 (fixpos + 8); 11368 control_bits = t0 & 0x1f; 11369 insn[0] = (t0 >> 5) & 0x1ffffffffffLL; 11370 insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); 11371 insn[2] = (t1 >> 23) & 0x1ffffffffffLL; 11372 11373 err = NULL; 11374 if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) 11375 { 11376 insn[1] = (value >> 22) & 0x1ffffffffffLL; 11377 insn[2] |= (((value & 0x7f) << 13) 11378 | (((value >> 7) & 0x1ff) << 27) 11379 | (((value >> 16) & 0x1f) << 22) 11380 | (((value >> 21) & 0x1) << 21) 11381 | (((value >> 63) & 0x1) << 36)); 11382 } 11383 else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) 11384 { 11385 if (value & ~0x3fffffffffffffffULL) 11386 err = _("integer operand out of range"); 11387 insn[1] = (value >> 21) & 0x1ffffffffffLL; 11388 insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); 11389 } 11390 else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) 11391 { 11392 value >>= 4; 11393 insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; 11394 insn[2] |= ((((value >> 59) & 0x1) << 36) 11395 | (((value >> 0) & 0xfffff) << 13)); 11396 } 11397 else 11398 err = (*odesc->insert) (odesc, value, insn + slot); 11399 11400 if (err) 11401 as_bad_where (fix->fx_file, fix->fx_line, "%s", err); 11402 11403 t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); 11404 t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); 11405 number_to_chars_littleendian (fixpos + 0, t0, 8); 11406 number_to_chars_littleendian (fixpos + 8, t1, 8); 11407} 11408 11409/* Attempt to simplify or even eliminate a fixup. The return value is 11410 ignored; perhaps it was once meaningful, but now it is historical. 11411 To indicate that a fixup has been eliminated, set FIXP->FX_DONE. 11412 11413 If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry 11414 (if possible). */ 11415 11416void 11417md_apply_fix (fixS *fix, valueT *valP, segT seg ATTRIBUTE_UNUSED) 11418{ 11419 char *fixpos; 11420 valueT value = *valP; 11421 11422 fixpos = fix->fx_frag->fr_literal + fix->fx_where; 11423 11424 if (fix->fx_pcrel) 11425 { 11426 switch (fix->fx_r_type) 11427 { 11428 case BFD_RELOC_IA64_PCREL21B: break; 11429 case BFD_RELOC_IA64_PCREL21BI: break; 11430 case BFD_RELOC_IA64_PCREL21F: break; 11431 case BFD_RELOC_IA64_PCREL21M: break; 11432 case BFD_RELOC_IA64_PCREL60B: break; 11433 case BFD_RELOC_IA64_PCREL22: break; 11434 case BFD_RELOC_IA64_PCREL64I: break; 11435 case BFD_RELOC_IA64_PCREL32MSB: break; 11436 case BFD_RELOC_IA64_PCREL32LSB: break; 11437 case BFD_RELOC_IA64_PCREL64MSB: break; 11438 case BFD_RELOC_IA64_PCREL64LSB: break; 11439 default: 11440 fix->fx_r_type = ia64_gen_real_reloc_type (pseudo_func[FUNC_PC_RELATIVE].u.sym, 11441 fix->fx_r_type); 11442 break; 11443 } 11444 } 11445 if (fix->fx_addsy) 11446 { 11447 switch ((unsigned) fix->fx_r_type) 11448 { 11449 case BFD_RELOC_UNUSED: 11450 /* This must be a TAG13 or TAG13b operand. There are no external 11451 relocs defined for them, so we must give an error. */ 11452 as_bad_where (fix->fx_file, fix->fx_line, 11453 _("%s must have a constant value"), 11454 elf64_ia64_operands[fix->tc_fix_data.opnd].desc); 11455 fix->fx_done = 1; 11456 return; 11457 11458 case BFD_RELOC_IA64_TPREL14: 11459 case BFD_RELOC_IA64_TPREL22: 11460 case BFD_RELOC_IA64_TPREL64I: 11461 case BFD_RELOC_IA64_LTOFF_TPREL22: 11462 case BFD_RELOC_IA64_LTOFF_DTPMOD22: 11463 case BFD_RELOC_IA64_DTPREL14: 11464 case BFD_RELOC_IA64_DTPREL22: 11465 case BFD_RELOC_IA64_DTPREL64I: 11466 case BFD_RELOC_IA64_LTOFF_DTPREL22: 11467 S_SET_THREAD_LOCAL (fix->fx_addsy); 11468 break; 11469 11470#ifdef TE_VMS 11471 case DUMMY_RELOC_IA64_SLOTCOUNT: 11472 as_bad_where (fix->fx_file, fix->fx_line, 11473 _("cannot resolve @slotcount parameter")); 11474 fix->fx_done = 1; 11475 return; 11476#endif 11477 11478 default: 11479 break; 11480 } 11481 } 11482 else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) 11483 { 11484#ifdef TE_VMS 11485 if (fix->fx_r_type == DUMMY_RELOC_IA64_SLOTCOUNT) 11486 { 11487 /* For @slotcount, convert an addresses difference to a slots 11488 difference. */ 11489 valueT v; 11490 11491 v = (value >> 4) * 3; 11492 switch (value & 0x0f) 11493 { 11494 case 0: 11495 case 1: 11496 case 2: 11497 v += value & 0x0f; 11498 break; 11499 case 0x0f: 11500 v += 2; 11501 break; 11502 case 0x0e: 11503 v += 1; 11504 break; 11505 default: 11506 as_bad (_("invalid @slotcount value")); 11507 } 11508 value = v; 11509 } 11510#endif 11511 11512 if (fix->tc_fix_data.bigendian) 11513 number_to_chars_bigendian (fixpos, value, fix->fx_size); 11514 else 11515 number_to_chars_littleendian (fixpos, value, fix->fx_size); 11516 fix->fx_done = 1; 11517 } 11518 else 11519 { 11520 fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); 11521 fix->fx_done = 1; 11522 } 11523} 11524 11525/* Generate the BFD reloc to be stuck in the object file from the 11526 fixup used internally in the assembler. */ 11527 11528arelent * 11529tc_gen_reloc (asection *sec ATTRIBUTE_UNUSED, fixS *fixp) 11530{ 11531 arelent *reloc; 11532 11533 reloc = XNEW (arelent); 11534 reloc->sym_ptr_ptr = XNEW (asymbol *); 11535 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 11536 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 11537 reloc->addend = fixp->fx_offset; 11538 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 11539 11540 if (!reloc->howto) 11541 { 11542 as_bad_where (fixp->fx_file, fixp->fx_line, 11543 _("Cannot represent %s relocation in object file"), 11544 bfd_get_reloc_code_name (fixp->fx_r_type)); 11545 free (reloc); 11546 return NULL; 11547 } 11548 return reloc; 11549} 11550 11551/* Turn a string in input_line_pointer into a floating point constant 11552 of type TYPE, and store the appropriate bytes in *LIT. The number 11553 of LITTLENUMS emitted is stored in *SIZE. An error message is 11554 returned, or NULL on OK. */ 11555 11556const char * 11557md_atof (int type, char *lit, int *size) 11558{ 11559 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 11560 char *t; 11561 int prec; 11562 11563 switch (type) 11564 { 11565 /* IEEE floats */ 11566 case 'f': 11567 case 'F': 11568 case 's': 11569 case 'S': 11570 prec = 2; 11571 break; 11572 11573 case 'd': 11574 case 'D': 11575 case 'r': 11576 case 'R': 11577 prec = 4; 11578 break; 11579 11580 case 'x': 11581 case 'X': 11582 case 'p': 11583 case 'P': 11584 prec = 5; 11585 break; 11586 11587 default: 11588 *size = 0; 11589 return _("Unrecognized or unsupported floating point constant"); 11590 } 11591 t = atof_ieee (input_line_pointer, type, words); 11592 if (t) 11593 input_line_pointer = t; 11594 11595 (*ia64_float_to_chars) (lit, words, prec); 11596 11597 if (type == 'X') 11598 { 11599 /* It is 10 byte floating point with 6 byte padding. */ 11600 memset (&lit [10], 0, 6); 11601 *size = 8 * sizeof (LITTLENUM_TYPE); 11602 } 11603 else 11604 *size = prec * sizeof (LITTLENUM_TYPE); 11605 11606 return NULL; 11607} 11608 11609/* Handle ia64 specific semantics of the align directive. */ 11610 11611void 11612ia64_md_do_align (int n ATTRIBUTE_UNUSED, 11613 const char *fill ATTRIBUTE_UNUSED, 11614 int len ATTRIBUTE_UNUSED, 11615 int max ATTRIBUTE_UNUSED) 11616{ 11617 if (subseg_text_p (now_seg)) 11618 ia64_flush_insns (); 11619} 11620 11621/* This is called from HANDLE_ALIGN in write.c. Fill in the contents 11622 of an rs_align_code fragment. */ 11623 11624void 11625ia64_handle_align (fragS *fragp) 11626{ 11627 int bytes; 11628 char *p; 11629 const unsigned char *nop_type; 11630 11631 if (fragp->fr_type != rs_align_code) 11632 return; 11633 11634 /* Check if this frag has to end with a stop bit. */ 11635 nop_type = fragp->tc_frag_data ? le_nop_stop : le_nop; 11636 11637 bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 11638 p = fragp->fr_literal + fragp->fr_fix; 11639 11640 /* If no paddings are needed, we check if we need a stop bit. */ 11641 if (!bytes && fragp->tc_frag_data) 11642 { 11643 if (fragp->fr_fix < 16) 11644#if 1 11645 /* FIXME: It won't work with 11646 .align 16 11647 alloc r32=ar.pfs,1,2,4,0 11648 */ 11649 ; 11650#else 11651 as_bad_where (fragp->fr_file, fragp->fr_line, 11652 _("Can't add stop bit to mark end of instruction group")); 11653#endif 11654 else 11655 /* Bundles are always in little-endian byte order. Make sure 11656 the previous bundle has the stop bit. */ 11657 *(p - 16) |= 1; 11658 } 11659 11660 /* Make sure we are on a 16-byte boundary, in case someone has been 11661 putting data into a text section. */ 11662 if (bytes & 15) 11663 { 11664 int fix = bytes & 15; 11665 memset (p, 0, fix); 11666 p += fix; 11667 bytes -= fix; 11668 fragp->fr_fix += fix; 11669 } 11670 11671 /* Instruction bundles are always little-endian. */ 11672 memcpy (p, nop_type, 16); 11673 fragp->fr_var = 16; 11674} 11675 11676static void 11677ia64_float_to_chars_bigendian (char *lit, LITTLENUM_TYPE *words, 11678 int prec) 11679{ 11680 while (prec--) 11681 { 11682 number_to_chars_bigendian (lit, (long) (*words++), 11683 sizeof (LITTLENUM_TYPE)); 11684 lit += sizeof (LITTLENUM_TYPE); 11685 } 11686} 11687 11688static void 11689ia64_float_to_chars_littleendian (char *lit, LITTLENUM_TYPE *words, 11690 int prec) 11691{ 11692 while (prec--) 11693 { 11694 number_to_chars_littleendian (lit, (long) (words[prec]), 11695 sizeof (LITTLENUM_TYPE)); 11696 lit += sizeof (LITTLENUM_TYPE); 11697 } 11698} 11699 11700void 11701ia64_elf_section_change_hook (void) 11702{ 11703 if (elf_section_type (now_seg) == SHT_IA_64_UNWIND 11704 && elf_linked_to_section (now_seg) == NULL) 11705 elf_linked_to_section (now_seg) = text_section; 11706 dot_byteorder (-1); 11707} 11708 11709/* Check if a label should be made global. */ 11710void 11711ia64_check_label (symbolS *label) 11712{ 11713 if (*input_line_pointer == ':') 11714 { 11715 S_SET_EXTERNAL (label); 11716 input_line_pointer++; 11717 } 11718} 11719 11720/* Used to remember where .alias and .secalias directives are seen. We 11721 will rename symbol and section names when we are about to output 11722 the relocatable file. */ 11723struct alias 11724{ 11725 const char *file; /* The file where the directive is seen. */ 11726 unsigned int line; /* The line number the directive is at. */ 11727 const char *name; /* The original name of the symbol. */ 11728}; 11729 11730/* Called for .alias and .secalias directives. If SECTION is 1, it is 11731 .secalias. Otherwise, it is .alias. */ 11732static void 11733dot_alias (int section) 11734{ 11735 char *name, *alias; 11736 char delim; 11737 char *end_name; 11738 int len; 11739 struct alias *h; 11740 const char *a; 11741 htab_t ahash, nhash; 11742 const char *kind; 11743 11744 delim = get_symbol_name (&name); 11745 end_name = input_line_pointer; 11746 *end_name = delim; 11747 11748 if (name == end_name) 11749 { 11750 as_bad (_("expected symbol name")); 11751 ignore_rest_of_line (); 11752 return; 11753 } 11754 11755 SKIP_WHITESPACE_AFTER_NAME (); 11756 11757 if (*input_line_pointer != ',') 11758 { 11759 *end_name = 0; 11760 as_bad (_("expected comma after \"%s\""), name); 11761 *end_name = delim; 11762 ignore_rest_of_line (); 11763 return; 11764 } 11765 11766 input_line_pointer++; 11767 *end_name = 0; 11768 ia64_canonicalize_symbol_name (name); 11769 11770 /* We call demand_copy_C_string to check if alias string is valid. 11771 There should be a closing `"' and no `\0' in the string. */ 11772 alias = demand_copy_C_string (&len); 11773 if (alias == NULL) 11774 { 11775 ignore_rest_of_line (); 11776 return; 11777 } 11778 11779 /* Make a copy of name string. */ 11780 len = strlen (name) + 1; 11781 obstack_grow (¬es, name, len); 11782 name = obstack_finish (¬es); 11783 11784 if (section) 11785 { 11786 kind = "section"; 11787 ahash = secalias_hash; 11788 nhash = secalias_name_hash; 11789 } 11790 else 11791 { 11792 kind = "symbol"; 11793 ahash = alias_hash; 11794 nhash = alias_name_hash; 11795 } 11796 11797 /* Check if alias has been used before. */ 11798 11799 h = (struct alias *) str_hash_find (ahash, alias); 11800 if (h) 11801 { 11802 if (strcmp (h->name, name)) 11803 as_bad (_("`%s' is already the alias of %s `%s'"), 11804 alias, kind, h->name); 11805 obstack_free (¬es, name); 11806 obstack_free (¬es, alias); 11807 goto out; 11808 } 11809 11810 /* Check if name already has an alias. */ 11811 a = (const char *) str_hash_find (nhash, name); 11812 if (a) 11813 { 11814 if (strcmp (a, alias)) 11815 as_bad (_("%s `%s' already has an alias `%s'"), kind, name, a); 11816 obstack_free (¬es, name); 11817 obstack_free (¬es, alias); 11818 goto out; 11819 } 11820 11821 h = XNEW (struct alias); 11822 h->file = as_where (&h->line); 11823 h->name = name; 11824 11825 str_hash_insert (ahash, alias, h, 0); 11826 str_hash_insert (nhash, name, alias, 0); 11827 11828out: 11829 demand_empty_rest_of_line (); 11830} 11831 11832/* It renames the original symbol name to its alias. */ 11833static int 11834do_alias (void **slot, void *arg ATTRIBUTE_UNUSED) 11835{ 11836 string_tuple_t *tuple = *((string_tuple_t **) slot); 11837 struct alias *h = (struct alias *) tuple->value; 11838 symbolS *sym = symbol_find (h->name); 11839 11840 if (sym == NULL) 11841 { 11842#ifdef TE_VMS 11843 /* Uses .alias extensively to alias CRTL functions to same with 11844 decc$ prefix. Sometimes function gets optimized away and a 11845 warning results, which should be suppressed. */ 11846 if (strncmp (tuple->key, "decc$", 5) != 0) 11847#endif 11848 as_warn_where (h->file, h->line, 11849 _("symbol `%s' aliased to `%s' is not used"), 11850 h->name, tuple->key); 11851 } 11852 else 11853 S_SET_NAME (sym, (char *) tuple->key); 11854 11855 return 1; 11856} 11857 11858/* Called from write_object_file. */ 11859void 11860ia64_adjust_symtab (void) 11861{ 11862 htab_traverse (alias_hash, do_alias, NULL); 11863} 11864 11865/* It renames the original section name to its alias. */ 11866static int 11867do_secalias (void **slot, void *arg ATTRIBUTE_UNUSED) 11868{ 11869 string_tuple_t *tuple = *((string_tuple_t **) slot); 11870 struct alias *h = (struct alias *) tuple->value; 11871 segT sec = bfd_get_section_by_name (stdoutput, h->name); 11872 11873 if (sec == NULL) 11874 as_warn_where (h->file, h->line, 11875 _("section `%s' aliased to `%s' is not used"), 11876 h->name, tuple->key); 11877 else 11878 sec->name = tuple->key; 11879 11880 return 1; 11881} 11882 11883/* Called from write_object_file. */ 11884void 11885ia64_frob_file (void) 11886{ 11887 htab_traverse (secalias_hash, do_secalias, NULL); 11888} 11889 11890#ifdef TE_VMS 11891#define NT_VMS_MHD 1 11892#define NT_VMS_LNM 2 11893 11894/* Integrity VMS 8.x identifies it's ELF modules with a standard ELF 11895 .note section. */ 11896 11897/* Manufacture a VMS-like time string. */ 11898static void 11899get_vms_time (char *Now) 11900{ 11901 char *pnt; 11902 time_t timeb; 11903 11904 time (&timeb); 11905 pnt = ctime (&timeb); 11906 pnt[3] = 0; 11907 pnt[7] = 0; 11908 pnt[10] = 0; 11909 pnt[16] = 0; 11910 pnt[24] = 0; 11911 sprintf (Now, "%2s-%3s-%s %s", pnt + 8, pnt + 4, pnt + 20, pnt + 11); 11912} 11913 11914void 11915ia64_vms_note (void) 11916{ 11917 char *p; 11918 asection *seg = now_seg; 11919 subsegT subseg = now_subseg; 11920 asection *secp = NULL; 11921 char *bname; 11922 char buf [256]; 11923 symbolS *sym; 11924 11925 /* Create the .note section. */ 11926 11927 secp = subseg_new (".note", 0); 11928 bfd_set_section_flags (secp, SEC_HAS_CONTENTS | SEC_READONLY); 11929 11930 /* Module header note (MHD). */ 11931 bname = xstrdup (lbasename (out_file_name)); 11932 if ((p = strrchr (bname, '.'))) 11933 *p = '\0'; 11934 11935 /* VMS note header is 24 bytes long. */ 11936 p = frag_more (8 + 8 + 8); 11937 number_to_chars_littleendian (p + 0, 8, 8); 11938 number_to_chars_littleendian (p + 8, 40 + strlen (bname), 8); 11939 number_to_chars_littleendian (p + 16, NT_VMS_MHD, 8); 11940 11941 p = frag_more (8); 11942 strcpy (p, "IPF/VMS"); 11943 11944 p = frag_more (17 + 17 + strlen (bname) + 1 + 5); 11945 get_vms_time (p); 11946 strcpy (p + 17, "24-FEB-2005 15:00"); 11947 p += 17 + 17; 11948 strcpy (p, bname); 11949 p += strlen (bname) + 1; 11950 free (bname); 11951 strcpy (p, "V1.0"); 11952 11953 frag_align (3, 0, 0); 11954 11955 /* Language processor name note. */ 11956 sprintf (buf, "GNU assembler version %s (%s) using BFD version %s", 11957 VERSION, TARGET_ALIAS, BFD_VERSION_STRING); 11958 11959 p = frag_more (8 + 8 + 8); 11960 number_to_chars_littleendian (p + 0, 8, 8); 11961 number_to_chars_littleendian (p + 8, strlen (buf) + 1, 8); 11962 number_to_chars_littleendian (p + 16, NT_VMS_LNM, 8); 11963 11964 p = frag_more (8); 11965 strcpy (p, "IPF/VMS"); 11966 11967 p = frag_more (strlen (buf) + 1); 11968 strcpy (p, buf); 11969 11970 frag_align (3, 0, 0); 11971 11972 secp = subseg_new (".vms_display_name_info", 0); 11973 bfd_set_section_flags (secp, SEC_HAS_CONTENTS | SEC_READONLY); 11974 11975 /* This symbol should be passed on the command line and be variable 11976 according to language. */ 11977 sym = symbol_new ("__gnat_vms_display_name@gnat_demangler_rtl", 11978 absolute_section, &zero_address_frag, 0); 11979 symbol_table_insert (sym); 11980 symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING | BSF_DYNAMIC; 11981 11982 p = frag_more (4); 11983 /* Format 3 of VMS demangler Spec. */ 11984 number_to_chars_littleendian (p, 3, 4); 11985 11986 p = frag_more (4); 11987 /* Place holder for symbol table index of above symbol. */ 11988 number_to_chars_littleendian (p, -1, 4); 11989 11990 frag_align (3, 0, 0); 11991 11992 /* We probably can't restore the current segment, for there likely 11993 isn't one yet... */ 11994 if (seg && subseg) 11995 subseg_set (seg, subseg); 11996} 11997 11998#endif /* TE_VMS */ 11999