1233545Sjchandra/* m68k-parse.h -- header file for m68k assembler 2233545Sjchandra Copyright (C) 1987-2020 Free Software Foundation, Inc. 3233545Sjchandra 4233545Sjchandra This file is part of GAS, the GNU Assembler. 5233545Sjchandra 6233545Sjchandra GAS is free software; you can redistribute it and/or modify 7233545Sjchandra it under the terms of the GNU General Public License as published by 8233545Sjchandra the Free Software Foundation; either version 3, or (at your option) 9233545Sjchandra any later version. 10233545Sjchandra 11233545Sjchandra GAS is distributed in the hope that it will be useful, 12233545Sjchandra but WITHOUT ANY WARRANTY; without even the implied warranty of 13233545Sjchandra MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14233545Sjchandra GNU General Public License for more details. 15233545Sjchandra 16233545Sjchandra You should have received a copy of the GNU General Public License 17233545Sjchandra along with GAS; see the file COPYING. If not, write to the Free 18233545Sjchandra Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19233545Sjchandra 02110-1301, USA. */ 20233545Sjchandra 21233545Sjchandra#ifndef M68K_PARSE_H 22233545Sjchandra#define M68K_PARSE_H 23233545Sjchandra 24233545Sjchandra/* This header file defines things which are shared between the 25233545Sjchandra operand parser in m68k.y and the m68k assembler proper in 26233545Sjchandra tc-m68k.c. */ 27233545Sjchandra 28233545Sjchandra/* The various m68k registers. */ 29233545Sjchandra 30233545Sjchandra/* DATA and ADDR have to be contiguous, so that reg-DATA gives 31233545Sjchandra 0-7==data reg, 8-15==addr reg for operands that take both types. 32233545Sjchandra 33233545Sjchandra We don't use forms like "ADDR0 = ADDR" here because this file is 34233545Sjchandra likely to be used on an Apollo, and the broken Apollo compiler 35233545Sjchandra gives an `undefined variable' error if we do that, according to 36233545Sjchandra troy@cbme.unsw.edu.au. */ 37233545Sjchandra 38233545Sjchandra#define DATA DATA0 39233545Sjchandra#define ADDR ADDR0 40233545Sjchandra#define SP ADDR7 41233545Sjchandra#define BAD BAD0 42233545Sjchandra#define BAC BAC0 43233545Sjchandra 44233545Sjchandraenum m68k_register 45233545Sjchandra{ 46233545Sjchandra DATA0 = 1, /* 1- 8 == data registers 0-7 */ 47233545Sjchandra DATA1, 48233657Sjchandra DATA2, 49233657Sjchandra DATA3, 50233545Sjchandra DATA4, 51233545Sjchandra DATA5, 52233545Sjchandra DATA6, 53233545Sjchandra DATA7, 54233545Sjchandra 55233545Sjchandra ADDR0, 56233545Sjchandra ADDR1, 57233545Sjchandra ADDR2, 58233545Sjchandra ADDR3, 59233545Sjchandra ADDR4, 60233657Sjchandra ADDR5, 61233657Sjchandra ADDR6, 62233545Sjchandra ADDR7, 63233545Sjchandra 64233545Sjchandra FP0, /* Eight FP registers */ 65233545Sjchandra FP1, 66233545Sjchandra FP2, 67233545Sjchandra FP3, 68233545Sjchandra FP4, 69233545Sjchandra FP5, 70233545Sjchandra FP6, 71233545Sjchandra FP7, 72233657Sjchandra 73233657Sjchandra COP0, /* Co-processor #0-#7 */ 74233657Sjchandra COP1, 75233657Sjchandra COP2, 76233545Sjchandra COP3, 77233657Sjchandra COP4, 78233657Sjchandra COP5, 79233657Sjchandra COP6, 80233657Sjchandra COP7, 81233657Sjchandra 82233657Sjchandra PC, /* Program counter */ 83233657Sjchandra ZPC, /* Hack for Program space, but 0 addressing */ 84233657Sjchandra SR, /* Status Reg */ 85233657Sjchandra CCR, /* Condition code Reg */ 86233657Sjchandra ACC, /* Accumulator Reg0 (EMAC or ACC on MAC). */ 87233657Sjchandra ACC1, /* Accumulator Reg 1 (EMAC). */ 88233545Sjchandra ACC2, /* Accumulator Reg 2 (EMAC). */ 89233657Sjchandra ACC3, /* Accumulator Reg 3 (EMAC). */ 90233657Sjchandra ACCEXT01, /* Accumulator extension 0&1 (EMAC). */ 91233545Sjchandra ACCEXT23, /* Accumulator extension 2&3 (EMAC). */ 92233657Sjchandra MACSR, /* MAC Status Reg */ 93233545Sjchandra MASK, /* Modulus Reg */ 94233545Sjchandra 95233657Sjchandra /* These have to be grouped together for the movec instruction to work. */ 96233657Sjchandra USP, /* User Stack Pointer */ 97233545Sjchandra ISP, /* Interrupt stack pointer */ 98233657Sjchandra SFC, 99233545Sjchandra DFC, 100233545Sjchandra CACR, 101233545Sjchandra VBR, 102233545Sjchandra CAAR, 103233545Sjchandra CPUCR, 104233545Sjchandra MSP, 105233545Sjchandra ITT0, 106233545Sjchandra ITT1, 107233545Sjchandra DTT0, 108233545Sjchandra DTT1, 109233545Sjchandra MMUSR, 110233545Sjchandra TC, 111233545Sjchandra SRP, 112233545Sjchandra URP, 113233545Sjchandra BUSCR, /* 68060 added these. */ 114233545Sjchandra PCR, 115233545Sjchandra ROMBAR, /* mcf5200 added these. */ 116233545Sjchandra RAMBAR_ALT, /* Some CF chips have RAMBAR using 117233545Sjchandra RAMBAR0's number */ 118233545Sjchandra RAMBAR0, 119233545Sjchandra RAMBAR1, 120233545Sjchandra MMUBAR, /* mcfv4e added these. */ 121233545Sjchandra ROMBAR0, /* mcfv4e added these. */ 122233545Sjchandra ROMBAR1, /* mcfv4e added these. */ 123233545Sjchandra MPCR, EDRAMBAR, SECMBAR, /* mcfv4e added these. */ 124233545Sjchandra PCR1U0, PCR1L0, PCR1U1, PCR1L1,/* mcfv4e added these. */ 125233545Sjchandra PCR2U0, PCR2L0, PCR2U1, PCR2L1,/* mcfv4e added these. */ 126233545Sjchandra PCR3U0, PCR3L0, PCR3U1, PCR3L1,/* mcfv4e added these. */ 127233545Sjchandra MBAR0, MBAR1, /* mcfv4e added these. */ 128233545Sjchandra ACR0, ACR1, ACR2, ACR3, /* mcf5200 added these. */ 129233545Sjchandra ACR4, ACR5, ACR6, ACR7, /* mcf54418 added these. */ 130233545Sjchandra FLASHBAR, RAMBAR, /* mcf528x added these. */ 131233545Sjchandra MBAR2, /* mcf5249 added this. */ 132233545Sjchandra MBAR, 133233545Sjchandra RGPIOBAR, /* mcf54418 added this. */ 134233545Sjchandra ASID, /* m5475. */ 135233545Sjchandra CAC, /* fido added this. */ 136233545Sjchandra MBO, 137233545Sjchandra#define last_movec_reg MBO 138233545Sjchandra /* End of movec ordering constraints. */ 139233545Sjchandra 140233545Sjchandra FPI, 141233545Sjchandra FPS, 142233545Sjchandra FPC, 143233545Sjchandra 144233545Sjchandra DRP, /* 68851 or 68030 MMU regs */ 145233545Sjchandra CRP, 146233545Sjchandra CAL, 147233545Sjchandra VAL, 148233545Sjchandra SCC, 149233545Sjchandra AC, 150233545Sjchandra BAD0, 151233545Sjchandra BAD1, 152233545Sjchandra BAD2, 153233545Sjchandra BAD3, 154233545Sjchandra BAD4, 155233545Sjchandra BAD5, 156233545Sjchandra BAD6, 157233545Sjchandra BAD7, 158233545Sjchandra BAC0, 159233545Sjchandra BAC1, 160233545Sjchandra BAC2, 161233545Sjchandra BAC3, 162233545Sjchandra BAC4, 163233545Sjchandra BAC5, 164233545Sjchandra BAC6, 165233545Sjchandra BAC7, 166233545Sjchandra PSR, /* aka MMUSR on 68030 (but not MMUSR on 68040) 167233545Sjchandra and ACUSR on 68ec030 */ 168233545Sjchandra PCSR, 169233545Sjchandra 170233545Sjchandra IC, /* instruction cache token */ 171233545Sjchandra DC, /* data cache token */ 172233545Sjchandra NC, /* no cache token */ 173233545Sjchandra BC, /* both caches token */ 174233545Sjchandra 175233545Sjchandra TT0, /* 68030 access control unit regs */ 176233545Sjchandra TT1, 177233545Sjchandra 178233545Sjchandra ZDATA0, /* suppressed data registers. */ 179233545Sjchandra ZDATA1, 180233545Sjchandra ZDATA2, 181233545Sjchandra ZDATA3, 182233545Sjchandra ZDATA4, 183233545Sjchandra ZDATA5, 184233545Sjchandra ZDATA6, 185233545Sjchandra ZDATA7, 186233545Sjchandra 187233545Sjchandra ZADDR0, /* suppressed address registers. */ 188233545Sjchandra ZADDR1, 189233545Sjchandra ZADDR2, 190233545Sjchandra ZADDR3, 191233545Sjchandra ZADDR4, 192233545Sjchandra ZADDR5, 193233545Sjchandra ZADDR6, 194233545Sjchandra ZADDR7, 195233545Sjchandra 196233545Sjchandra /* Upper and lower half of data and address registers. Order *must* 197233545Sjchandra be DATAxL, ADDRxL, DATAxU, ADDRxU. */ 198233545Sjchandra DATA0L, /* lower half of data registers */ 199233545Sjchandra DATA1L, 200233545Sjchandra DATA2L, 201233545Sjchandra DATA3L, 202233545Sjchandra DATA4L, 203233545Sjchandra DATA5L, 204233545Sjchandra DATA6L, 205233545Sjchandra DATA7L, 206233545Sjchandra 207233545Sjchandra ADDR0L, /* lower half of address registers */ 208233545Sjchandra ADDR1L, 209233545Sjchandra ADDR2L, 210233545Sjchandra ADDR3L, 211233545Sjchandra ADDR4L, 212233545Sjchandra ADDR5L, 213233545Sjchandra ADDR6L, 214233545Sjchandra ADDR7L, 215233545Sjchandra 216233545Sjchandra DATA0U, /* upper half of data registers */ 217233545Sjchandra DATA1U, 218233545Sjchandra DATA2U, 219233545Sjchandra DATA3U, 220233545Sjchandra DATA4U, 221233545Sjchandra DATA5U, 222233545Sjchandra DATA6U, 223233545Sjchandra DATA7U, 224233545Sjchandra 225233545Sjchandra ADDR0U, /* upper half of address registers */ 226233545Sjchandra ADDR1U, 227233545Sjchandra ADDR2U, 228233545Sjchandra ADDR3U, 229233545Sjchandra ADDR4U, 230233545Sjchandra ADDR5U, 231233545Sjchandra ADDR6U, 232233545Sjchandra ADDR7U, 233233545Sjchandra}; 234233545Sjchandra 235233545Sjchandra/* Size information. */ 236233545Sjchandra 237233545Sjchandraenum m68k_size 238233545Sjchandra{ 239233545Sjchandra /* Unspecified. */ 240233545Sjchandra SIZE_UNSPEC, 241233545Sjchandra 242233545Sjchandra /* Byte. */ 243233545Sjchandra SIZE_BYTE, 244233545Sjchandra 245233545Sjchandra /* Word (2 bytes). */ 246233545Sjchandra SIZE_WORD, 247233545Sjchandra 248233545Sjchandra /* Longword (4 bytes). */ 249233545Sjchandra SIZE_LONG 250233545Sjchandra}; 251233545Sjchandra 252233545Sjchandra/* The structure used to hold information about an index register. */ 253233545Sjchandra 254233545Sjchandrastruct m68k_indexreg 255233545Sjchandra{ 256233545Sjchandra /* The index register itself. */ 257233545Sjchandra enum m68k_register reg; 258233545Sjchandra 259233545Sjchandra /* The size to use. */ 260233545Sjchandra enum m68k_size size; 261233545Sjchandra 262233545Sjchandra /* The value to scale by. */ 263233545Sjchandra int scale; 264233545Sjchandra}; 265233545Sjchandra 266233545Sjchandra#ifdef OBJ_ELF 267233545Sjchandra/* The type of a PIC expression. */ 268233545Sjchandra 269233545Sjchandraenum pic_relocation 270233545Sjchandra{ 271233545Sjchandra pic_none, /* not pic */ 272233545Sjchandra pic_plt_pcrel, /* @PLTPC */ 273233545Sjchandra pic_got_pcrel, /* @GOTPC */ 274233545Sjchandra pic_plt_off, /* @PLT */ 275233545Sjchandra pic_got_off, /* @GOT */ 276233545Sjchandra pic_tls_gd, /* @TLSGD */ 277233545Sjchandra pic_tls_ldm, /* @TLSLDM */ 278233545Sjchandra pic_tls_ldo, /* @TLSLDO */ 279233545Sjchandra pic_tls_ie, /* @TLSIE */ 280233545Sjchandra pic_tls_le /* @TLSLE */ 281233545Sjchandra}; 282233545Sjchandra#endif 283233545Sjchandra 284233545Sjchandra/* The structure used to hold information about an expression. */ 285233545Sjchandra 286233545Sjchandrastruct m68k_exp 287233545Sjchandra{ 288233545Sjchandra /* The size to use. */ 289233545Sjchandra enum m68k_size size; 290233545Sjchandra 291233545Sjchandra#ifdef OBJ_ELF 292233545Sjchandra /* The type of pic relocation if any. */ 293233545Sjchandra enum pic_relocation pic_reloc; 294233545Sjchandra#endif 295233545Sjchandra 296233545Sjchandra /* The expression itself. */ 297233545Sjchandra expressionS exp; 298233545Sjchandra}; 299233545Sjchandra 300233545Sjchandra/* The operand modes. */ 301233545Sjchandra 302233545Sjchandraenum m68k_operand_type 303233545Sjchandra{ 304233545Sjchandra IMMED = 1, 305233545Sjchandra ABSL, 306233545Sjchandra DREG, 307233545Sjchandra AREG, 308233545Sjchandra FPREG, 309233545Sjchandra CONTROL, 310233545Sjchandra AINDR, 311233545Sjchandra AINC, 312233545Sjchandra ADEC, 313233545Sjchandra DISP, 314233545Sjchandra BASE, 315233545Sjchandra POST, 316233545Sjchandra PRE, 317233545Sjchandra LSH, /* MAC/EMAC scalefactor '<<'. */ 318233545Sjchandra RSH, /* MAC/EMAC scalefactor '>>'. */ 319233545Sjchandra REGLST 320233545Sjchandra}; 321233545Sjchandra 322233545Sjchandra/* The structure used to hold a parsed operand. */ 323233545Sjchandra 324233545Sjchandrastruct m68k_op 325233545Sjchandra{ 326233545Sjchandra /* The type of operand. */ 327233545Sjchandra enum m68k_operand_type mode; 328233545Sjchandra 329233545Sjchandra /* The main register. */ 330233545Sjchandra enum m68k_register reg; 331233545Sjchandra 332233545Sjchandra /* The register mask for mode REGLST. */ 333233545Sjchandra unsigned long mask; 334233545Sjchandra 335233545Sjchandra /* An error message. */ 336233545Sjchandra const char *error; 337233545Sjchandra 338233545Sjchandra /* The index register. */ 339233545Sjchandra struct m68k_indexreg index; 340233545Sjchandra 341233545Sjchandra /* The displacement. */ 342233545Sjchandra struct m68k_exp disp; 343233545Sjchandra 344233545Sjchandra /* The outer displacement. */ 345233545Sjchandra struct m68k_exp odisp; 346233545Sjchandra 347233545Sjchandra /* Is a trailing '&' added to an <ea>? (for MAC/EMAC mask addressing). */ 348233545Sjchandra int trailing_ampersand; 349233545Sjchandra}; 350233545Sjchandra 351233545Sjchandra#endif /* ! defined (M68K_PARSE_H) */ 352233545Sjchandra 353/* The parsing function. */ 354 355extern int m68k_ip_op (char *, struct m68k_op *); 356 357/* Whether register prefixes are optional. */ 358extern int flag_reg_prefix_optional; 359