1/* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992-2022 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26/* Note that some other tm.h files include this one and then override 27 many of the definitions. */ 28 29#ifndef RS6000_OPTS_H 30#include "config/rs6000/rs6000-opts.h" 31#endif 32 33/* 128-bit floating point precision values. */ 34#ifndef RS6000_MODES_H 35#include "config/rs6000/rs6000-modes.h" 36#endif 37 38/* Definitions for the object file format. These are set at 39 compile-time. */ 40 41#define OBJECT_XCOFF 1 42#define OBJECT_ELF 2 43#define OBJECT_MACHO 4 44 45#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 46#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 47#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 48 49#ifndef TARGET_AIX 50#define TARGET_AIX 0 51#endif 52 53#ifndef TARGET_AIX_OS 54#define TARGET_AIX_OS 0 55#endif 56 57/* Turn off TOC support if pc-relative addressing is used. */ 58#define TARGET_TOC (TARGET_HAS_TOC && !TARGET_PCREL) 59 60/* On 32-bit systems without a TOC or pc-relative addressing, we need to use 61 ADDIS/ADDI to load up the address of a symbol. */ 62#define TARGET_NO_TOC_OR_PCREL (!TARGET_HAS_TOC && !TARGET_PCREL) 63 64/* Control whether function entry points use a "dot" symbol when 65 ABI_AIX. */ 66#define DOT_SYMBOLS 1 67 68/* Default string to use for cpu if not specified. */ 69#ifndef TARGET_CPU_DEFAULT 70#define TARGET_CPU_DEFAULT ((char *)0) 71#endif 72 73/* If configured for PPC405, support PPC405CR Erratum77. */ 74#ifdef CONFIG_PPC405CR 75#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 76#else 77#define PPC405_ERRATUM77 0 78#endif 79 80#ifndef SUBTARGET_DRIVER_SELF_SPECS 81# define SUBTARGET_DRIVER_SELF_SPECS "" 82#endif 83 84/* Only for use in the testsuite: -mdejagnu-cpu=<value> filters out all 85 -mcpu= as well as -mtune= options then simply adds -mcpu=<value>, 86 while -mdejagnu-tune=<value> filters out all -mtune= options then 87 simply adds -mtune=<value>. 88 With older versions of Dejagnu the command line arguments you set in 89 RUNTESTFLAGS override those set in the testcases; with these options, 90 the testcase will always win. */ 91#define DRIVER_SELF_SPECS \ 92 "%{mdejagnu-cpu=*: %<mcpu=* %<mtune=* -mcpu=%*}", \ 93 "%{mdejagnu-tune=*: %<mtune=* -mtune=%*}", \ 94 "%{mdejagnu-*: %<mdejagnu-*}", \ 95 SUBTARGET_DRIVER_SELF_SPECS 96 97#if CHECKING_P 98#define ASM_OPT_ANY "" 99#else 100#define ASM_OPT_ANY " -many" 101#endif 102 103/* Common ASM definitions used by ASM_SPEC among the various targets for 104 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.cc to 105 provide the default assembler options if the user uses -mcpu=native, so if 106 you make changes here, make them also there. PR63177: Do not pass -mpower8 107 to the assembler if -mpower9-vector was also used. */ 108#define ASM_CPU_SPEC \ 109"%{mcpu=native: %(asm_cpu_native); \ 110 mcpu=power10: -mpower10; \ 111 mcpu=power9: -mpower9; \ 112 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ 113 mcpu=power7: -mpower7; \ 114 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 115 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 116 mcpu=power5+: -mpower5; \ 117 mcpu=power5: -mpower5; \ 118 mcpu=power4: -mpower4; \ 119 mcpu=power3: -mppc64; \ 120 mcpu=powerpc: -mppc; \ 121 mcpu=powerpc64: -mppc64; \ 122 mcpu=a2: -ma2; \ 123 mcpu=cell: -mcell; \ 124 mcpu=rs64: -mppc64; \ 125 mcpu=401: -mppc; \ 126 mcpu=403: -m403; \ 127 mcpu=405: -m405; \ 128 mcpu=405fp: -m405; \ 129 mcpu=440: -m440; \ 130 mcpu=440fp: -m440; \ 131 mcpu=464: -m440; \ 132 mcpu=464fp: -m440; \ 133 mcpu=476: -m476; \ 134 mcpu=476fp: -m476; \ 135 mcpu=505: -mppc; \ 136 mcpu=601: -m601; \ 137 mcpu=602: -mppc; \ 138 mcpu=603: -mppc; \ 139 mcpu=603e: -mppc; \ 140 mcpu=ec603e: -mppc; \ 141 mcpu=604: -mppc; \ 142 mcpu=604e: -mppc; \ 143 mcpu=620: -mppc64; \ 144 mcpu=630: -mppc64; \ 145 mcpu=740: -mppc; \ 146 mcpu=750: -mppc; \ 147 mcpu=G3: -mppc; \ 148 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 149 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 150 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 151 mcpu=801: -mppc; \ 152 mcpu=821: -mppc; \ 153 mcpu=823: -mppc; \ 154 mcpu=860: -mppc; \ 155 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 156 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 157 mcpu=8540: -me500; \ 158 mcpu=8548: -me500; \ 159 mcpu=e300c2: -me300; \ 160 mcpu=e300c3: -me300; \ 161 mcpu=e500mc: -me500mc; \ 162 mcpu=e500mc64: -me500mc64; \ 163 mcpu=e5500: -me5500; \ 164 mcpu=e6500: -me6500; \ 165 mcpu=titan: -mtitan; \ 166 !mcpu*: %{mpower9-vector: -mpower9; \ 167 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ 168 mvsx: -mpower7; \ 169 mpowerpc64: -mppc64;: %(asm_default)}; \ 170 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ 171%{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \ 172ASM_OPT_ANY 173 174#define CPP_DEFAULT_SPEC "" 175 176#define ASM_DEFAULT_SPEC "" 177#define ASM_DEFAULT_EXTRA "" 178 179/* This macro defines names of additional specifications to put in the specs 180 that can be used in various specifications like CC1_SPEC. Its definition 181 is an initializer with a subgrouping for each command option. 182 183 Each subgrouping contains a string constant, that defines the 184 specification name, and a string constant that used by the GCC driver 185 program. 186 187 Do not define this macro if it does not need to do anything. */ 188 189#define SUBTARGET_EXTRA_SPECS 190 191#define EXTRA_SPECS \ 192 { "cpp_default", CPP_DEFAULT_SPEC }, \ 193 { "asm_cpu", ASM_CPU_SPEC }, \ 194 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 195 { "asm_default", ASM_DEFAULT_SPEC ASM_DEFAULT_EXTRA }, \ 196 { "cc1_cpu", CC1_CPU_SPEC }, \ 197 SUBTARGET_EXTRA_SPECS 198 199/* -mcpu=native handling only makes sense with compiler running on 200 an PowerPC chip. If changing this condition, also change 201 the condition in driver-rs6000.cc. */ 202#if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 203/* In driver-rs6000.cc. */ 204extern const char *host_detect_local_cpu (int argc, const char **argv); 205#define EXTRA_SPEC_FUNCTIONS \ 206 { "local_cpu_detect", host_detect_local_cpu }, 207#define HAVE_LOCAL_CPU_DETECT 208#define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 209 210#else 211#define ASM_CPU_NATIVE_SPEC "%(asm_default)" 212#endif 213 214#ifndef CC1_CPU_SPEC 215#ifdef HAVE_LOCAL_CPU_DETECT 216#define CC1_CPU_SPEC \ 217"%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 218 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 219#else 220#define CC1_CPU_SPEC "" 221#endif 222#endif 223 224/* Architecture type. */ 225 226/* Define TARGET_MFCRF if the target assembler does not support the 227 optional field operand for mfcr. */ 228 229#ifndef HAVE_AS_MFCRF 230#undef TARGET_MFCRF 231#define TARGET_MFCRF 0 232#endif 233 234#ifndef TARGET_SECURE_PLT 235#define TARGET_SECURE_PLT 0 236#endif 237 238#ifndef TARGET_CMODEL 239#define TARGET_CMODEL CMODEL_SMALL 240#endif 241 242#define TARGET_32BIT (! TARGET_64BIT) 243 244#ifndef HAVE_AS_TLS 245#define HAVE_AS_TLS 0 246#endif 247 248#ifndef HAVE_AS_PLTSEQ 249#define HAVE_AS_PLTSEQ 0 250#endif 251 252#ifndef TARGET_PLTSEQ 253#define TARGET_PLTSEQ 0 254#endif 255 256#ifndef TARGET_LINK_STACK 257#define TARGET_LINK_STACK 0 258#endif 259 260#ifndef SET_TARGET_LINK_STACK 261#define SET_TARGET_LINK_STACK(X) do { } while (0) 262#endif 263 264#ifndef TARGET_FLOAT128_ENABLE_TYPE 265#define TARGET_FLOAT128_ENABLE_TYPE 0 266#endif 267 268/* Return 1 for a symbol ref for a thread-local storage symbol. */ 269#define RS6000_SYMBOL_REF_TLS_P(RTX) \ 270 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0) 271 272#ifdef IN_LIBGCC2 273/* For libgcc2 we make sure this is a compile time constant */ 274#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 275#undef TARGET_POWERPC64 276#define TARGET_POWERPC64 1 277#else 278#undef TARGET_POWERPC64 279#define TARGET_POWERPC64 0 280#endif 281#else 282 /* The option machinery will define this. */ 283#endif 284 285#define TARGET_DEFAULT (MASK_MULTIPLE) 286 287/* Define generic processor types based upon current deployment. */ 288#define PROCESSOR_COMMON PROCESSOR_PPC601 289#define PROCESSOR_POWERPC PROCESSOR_PPC604 290#define PROCESSOR_POWERPC64 PROCESSOR_RS64A 291 292/* Define the default processor. This is overridden by other tm.h files. */ 293#define PROCESSOR_DEFAULT PROCESSOR_PPC603 294#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 295 296/* Specify the dialect of assembler to use. Only new mnemonics are supported 297 starting with GCC 4.8, i.e. just one dialect, but for backwards 298 compatibility with older inline asm ASSEMBLER_DIALECT needs to be 299 defined. */ 300#define ASSEMBLER_DIALECT 1 301 302/* Debug support */ 303#define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 304#define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 305#define MASK_DEBUG_REG 0x04 /* debug register handling */ 306#define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 307#define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 308#define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 309#define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 310#define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 311 | MASK_DEBUG_ARG \ 312 | MASK_DEBUG_REG \ 313 | MASK_DEBUG_ADDR \ 314 | MASK_DEBUG_COST \ 315 | MASK_DEBUG_TARGET \ 316 | MASK_DEBUG_BUILTIN) 317 318#define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 319#define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 320#define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 321#define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 322#define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 323#define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 324#define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 325 326/* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM 327 long double format that uses a pair of doubles, or IEEE 128-bit floating 328 point. KFmode was added as a way to represent IEEE 128-bit floating point, 329 even if the default for long double is the IBM long double format. 330 Similarly IFmode is the IBM long double format even if the default is IEEE 331 128-bit. Don't allow IFmode if -msoft-float. */ 332#define FLOAT128_IEEE_P(MODE) \ 333 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 334 && ((MODE) == TFmode || (MODE) == TCmode)) \ 335 || ((MODE) == KFmode) || ((MODE) == KCmode)) 336 337#define FLOAT128_IBM_P(MODE) \ 338 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 339 && ((MODE) == TFmode || (MODE) == TCmode)) \ 340 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) 341 342/* Helper macros to say whether a 128-bit floating point type can go in a 343 single vector register, or whether it needs paired scalar values. */ 344#define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) 345 346#define FLOAT128_2REG_P(MODE) \ 347 (FLOAT128_IBM_P (MODE) \ 348 || ((MODE) == TDmode) \ 349 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) 350 351/* Return true for floating point that does not use a vector register. */ 352#define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ 353 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) 354 355/* Describe the vector unit used for arithmetic operations. */ 356extern enum rs6000_vector rs6000_vector_unit[]; 357 358#define VECTOR_UNIT_NONE_P(MODE) \ 359 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 360 361#define VECTOR_UNIT_VSX_P(MODE) \ 362 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 363 364#define VECTOR_UNIT_P8_VECTOR_P(MODE) \ 365 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) 366 367#define VECTOR_UNIT_ALTIVEC_P(MODE) \ 368 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 369 370#define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ 371 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 372 (int)VECTOR_VSX, \ 373 (int)VECTOR_P8_VECTOR)) 374 375/* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either 376 altivec (VMX) or VSX vector instructions. P8 vector support is upwards 377 compatible, so allow it as well, rather than changing all of the uses of the 378 macro. */ 379#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 380 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 381 (int)VECTOR_ALTIVEC, \ 382 (int)VECTOR_P8_VECTOR)) 383 384/* Describe whether to use VSX loads or Altivec loads. For now, just use the 385 same unit as the vector unit we are using, but we may want to migrate to 386 using VSX style loads even for types handled by altivec. */ 387extern enum rs6000_vector rs6000_vector_mem[]; 388 389#define VECTOR_MEM_NONE_P(MODE) \ 390 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 391 392#define VECTOR_MEM_VSX_P(MODE) \ 393 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 394 395#define VECTOR_MEM_P8_VECTOR_P(MODE) \ 396 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 397 398#define VECTOR_MEM_ALTIVEC_P(MODE) \ 399 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 400 401#define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ 402 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 403 (int)VECTOR_VSX, \ 404 (int)VECTOR_P8_VECTOR)) 405 406#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 407 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 408 (int)VECTOR_ALTIVEC, \ 409 (int)VECTOR_P8_VECTOR)) 410 411/* Return the alignment of a given vector type, which is set based on the 412 vector unit use. VSX for instance can load 32 or 64 bit aligned words 413 without problems, while Altivec requires 128-bit aligned vectors. */ 414extern int rs6000_vector_align[]; 415 416#define VECTOR_ALIGN(MODE) \ 417 ((rs6000_vector_align[(MODE)] != 0) \ 418 ? rs6000_vector_align[(MODE)] \ 419 : (int)GET_MODE_BITSIZE ((MODE))) 420 421/* Element number of the 64-bit value in a 128-bit vector that can be accessed 422 with scalar instructions. */ 423#define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 424 425/* Element number of the 64-bit value in a 128-bit vector that can be accessed 426 with the ISA 3.0 MFVSRLD instructions. */ 427#define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) 428 429/* Alignment options for fields in structures for sub-targets following 430 AIX-like ABI. 431 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 432 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 433 434 Override the macro definitions when compiling libobjc to avoid undefined 435 reference to rs6000_alignment_flags due to library's use of GCC alignment 436 macros which use the macros below. */ 437 438#ifndef IN_TARGET_LIBS 439#define MASK_ALIGN_POWER 0x00000000 440#define MASK_ALIGN_NATURAL 0x00000001 441#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 442#else 443#define TARGET_ALIGN_NATURAL 0 444#endif 445 446/* We use values 126..128 to pick the appropriate long double type (IFmode, 447 KFmode, TFmode). */ 448#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) 449#define TARGET_IEEEQUAD rs6000_ieeequad 450#define TARGET_ALTIVEC_ABI rs6000_altivec_abi 451#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 452 453/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 454 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ 455#define TARGET_FCFID (TARGET_POWERPC64 \ 456 || TARGET_PPC_GPOPT /* 970/power4 */ \ 457 || TARGET_POPCNTB /* ISA 2.02 */ \ 458 || TARGET_CMPB /* ISA 2.05 */ \ 459 || TARGET_POPCNTD) /* ISA 2.06 */ 460 461#define TARGET_FCTIDZ TARGET_FCFID 462#define TARGET_STFIWX TARGET_PPC_GFXOPT 463#define TARGET_LFIWAX TARGET_CMPB 464#define TARGET_LFIWZX TARGET_POPCNTD 465#define TARGET_FCFIDS TARGET_POPCNTD 466#define TARGET_FCFIDU TARGET_POPCNTD 467#define TARGET_FCFIDUS TARGET_POPCNTD 468#define TARGET_FCTIDUZ TARGET_POPCNTD 469#define TARGET_FCTIWUZ TARGET_POPCNTD 470#define TARGET_CTZ TARGET_MODULO 471#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) 472#define TARGET_MADDLD TARGET_MODULO 473 474#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 475#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 476#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) 477#define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 478 && TARGET_POWERPC64) 479#define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 480 && TARGET_POWERPC64) 481 482/* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ 483#define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT 484#define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) 485 486/* This wants to be set for p8 and newer. On p7, overlapping unaligned 487 loads are slow. */ 488#define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX 489 490/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present 491 in power7, so conditionalize them on p8 features. TImode syncs need quad 492 memory support. */ 493#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ 494 || TARGET_QUAD_MEMORY_ATOMIC \ 495 || TARGET_DIRECT_MOVE) 496 497#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC 498 499/* Power7 has both 32-bit load and store integer for the FPRs, so we don't need 500 to allocate the SDmode stack slot to get the value into the proper location 501 in the register. */ 502#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 503 504/* ISA 3.0 has new min/max functions that don't need fast math that are being 505 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct 506 answers if the arguments are not in the normal range. */ 507#define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 508 && (TARGET_P9_MINMAX || !flag_trapping_math)) 509 510/* In switching from using target_flags to using rs6000_isa_flags, the options 511 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 512 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 513#define MASK_ALTIVEC OPTION_MASK_ALTIVEC 514#define MASK_CMPB OPTION_MASK_CMPB 515#define MASK_CRYPTO OPTION_MASK_CRYPTO 516#define MASK_DFP OPTION_MASK_DFP 517#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE 518#define MASK_DLMZB OPTION_MASK_DLMZB 519#define MASK_EABI OPTION_MASK_EABI 520#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD 521#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW 522#define MASK_FPRND OPTION_MASK_FPRND 523#define MASK_P8_FUSION OPTION_MASK_P8_FUSION 524#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 525#define MASK_HTM OPTION_MASK_HTM 526#define MASK_ISEL OPTION_MASK_ISEL 527#define MASK_MFCRF OPTION_MASK_MFCRF 528#define MASK_MMA OPTION_MASK_MMA 529#define MASK_MULHW OPTION_MASK_MULHW 530#define MASK_MULTIPLE OPTION_MASK_MULTIPLE 531#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 532#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR 533#define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR 534#define MASK_P9_MISC OPTION_MASK_P9_MISC 535#define MASK_POPCNTB OPTION_MASK_POPCNTB 536#define MASK_POPCNTD OPTION_MASK_POPCNTD 537#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 538#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 539#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 540#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 541#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 542#define MASK_UPDATE OPTION_MASK_UPDATE 543#define MASK_VSX OPTION_MASK_VSX 544#define MASK_POWER10 OPTION_MASK_POWER10 545#define MASK_P10_FUSION OPTION_MASK_P10_FUSION 546 547#ifndef IN_LIBGCC2 548#define MASK_POWERPC64 OPTION_MASK_POWERPC64 549#endif 550 551#ifdef TARGET_64BIT 552#define MASK_64BIT OPTION_MASK_64BIT 553#endif 554 555#ifdef TARGET_LITTLE_ENDIAN 556#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 557#endif 558 559#ifdef TARGET_REGNAMES 560#define MASK_REGNAMES OPTION_MASK_REGNAMES 561#endif 562 563#ifdef TARGET_PROTOTYPE 564#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 565#endif 566 567#ifdef TARGET_MODULO 568#define RS6000_BTM_MODULO OPTION_MASK_MODULO 569#endif 570 571 572/* For power systems, we want to enable Altivec and VSX builtins even if the 573 user did not use -maltivec or -mvsx to allow the builtins to be used inside 574 of #pragma GCC target or the target attribute to change the code level for a 575 given system. */ 576 577#define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ 578 || TARGET_PPC_GPOPT /* 970/power4 */ \ 579 || TARGET_POPCNTB /* ISA 2.02 */ \ 580 || TARGET_CMPB /* ISA 2.05 */ \ 581 || TARGET_POPCNTD /* ISA 2.06 */ \ 582 || TARGET_ALTIVEC \ 583 || TARGET_VSX \ 584 || TARGET_HARD_FLOAT) 585 586/* E500 cores only support plain "sync", not lwsync. */ 587#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 588 || rs6000_cpu == PROCESSOR_PPC8548) 589 590 591/* Which machine supports the various reciprocal estimate instructions. */ 592#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) 593 594#define TARGET_FRE (TARGET_HARD_FLOAT \ 595 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 596 597#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 598 && TARGET_PPC_GFXOPT) 599 600#define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ 601 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 602 603/* Macro to say whether we can do optimizations where we need to do parts of 604 the calculation in 64-bit GPRs and then is transfered to the vector 605 registers. */ 606#define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ 607 && TARGET_P8_VECTOR \ 608 && TARGET_POWERPC64) 609 610/* Inlining allows targets to define the meanings of bits in target_info 611 field of ipa_fn_summary by itself, the used bits for rs6000 are listed 612 below. */ 613#define RS6000_FN_TARGET_INFO_HTM 1 614 615/* Whether the various reciprocal divide/square root estimate instructions 616 exist, and whether we should automatically generate code for the instruction 617 by default. */ 618#define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 619#define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 620#define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 621#define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 622 623extern unsigned char rs6000_recip_bits[]; 624 625#define RS6000_RECIP_HAVE_RE_P(MODE) \ 626 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 627 628#define RS6000_RECIP_AUTO_RE_P(MODE) \ 629 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 630 631#define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 632 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 633 634#define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 635 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 636 637/* The default CPU for TARGET_OPTION_OVERRIDE. */ 638#define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 639 640/* Target pragma. */ 641#define REGISTER_TARGET_PRAGMAS() do { \ 642 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 643 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 644 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 645 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 646} while (0) 647 648/* Target #defines. */ 649#define TARGET_CPU_CPP_BUILTINS() \ 650 rs6000_cpu_cpp_builtins (pfile) 651 652/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 653 we're compiling for. Some configurations may need to override it. */ 654#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 655 do \ 656 { \ 657 if (BYTES_BIG_ENDIAN) \ 658 { \ 659 builtin_define ("__BIG_ENDIAN__"); \ 660 builtin_define ("_BIG_ENDIAN"); \ 661 builtin_assert ("machine=bigendian"); \ 662 } \ 663 else \ 664 { \ 665 builtin_define ("__LITTLE_ENDIAN__"); \ 666 builtin_define ("_LITTLE_ENDIAN"); \ 667 builtin_assert ("machine=littleendian"); \ 668 } \ 669 } \ 670 while (0) 671 672/* Target machine storage layout. */ 673 674/* Define this if most significant bit is lowest numbered 675 in instructions that operate on numbered bit-fields. */ 676/* That is true on RS/6000. */ 677#define BITS_BIG_ENDIAN 1 678 679/* Define this if most significant byte of a word is the lowest numbered. */ 680/* That is true on RS/6000. */ 681#define BYTES_BIG_ENDIAN 1 682 683/* Define this if most significant word of a multiword number is lowest 684 numbered. 685 686 For RS/6000 we can decide arbitrarily since there are no machine 687 instructions for them. Might as well be consistent with bits and bytes. */ 688#define WORDS_BIG_ENDIAN 1 689 690/* This says that for the IBM long double the larger magnitude double 691 comes first. It's really a two element double array, and arrays 692 don't index differently between little- and big-endian. */ 693#define LONG_DOUBLE_LARGE_FIRST 1 694 695#define MAX_BITS_PER_WORD 64 696 697/* Width of a word, in units (bytes). */ 698#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 699#ifdef IN_LIBGCC2 700#define MIN_UNITS_PER_WORD UNITS_PER_WORD 701#else 702#define MIN_UNITS_PER_WORD 4 703#endif 704#define UNITS_PER_FP_WORD 8 705#define UNITS_PER_ALTIVEC_WORD 16 706#define UNITS_PER_VSX_WORD 16 707 708/* Type used for ptrdiff_t, as a string used in a declaration. */ 709#define PTRDIFF_TYPE "int" 710 711/* Type used for size_t, as a string used in a declaration. */ 712#define SIZE_TYPE "long unsigned int" 713 714/* Type used for wchar_t, as a string used in a declaration. */ 715#define WCHAR_TYPE "short unsigned int" 716 717/* Width of wchar_t in bits. */ 718#define WCHAR_TYPE_SIZE 16 719 720/* A C expression for the size in bits of the type `short' on the 721 target machine. If you don't define this, the default is half a 722 word. (If this would be less than one storage unit, it is 723 rounded up to one unit.) */ 724#define SHORT_TYPE_SIZE 16 725 726/* A C expression for the size in bits of the type `int' on the 727 target machine. If you don't define this, the default is one 728 word. */ 729#define INT_TYPE_SIZE 32 730 731/* A C expression for the size in bits of the type `long' on the 732 target machine. If you don't define this, the default is one 733 word. */ 734#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 735 736/* A C expression for the size in bits of the type `long long' on the 737 target machine. If you don't define this, the default is two 738 words. */ 739#define LONG_LONG_TYPE_SIZE 64 740 741/* A C expression for the size in bits of the type `float' on the 742 target machine. If you don't define this, the default is one 743 word. */ 744#define FLOAT_TYPE_SIZE 32 745 746/* A C expression for the size in bits of the type `double' on the 747 target machine. If you don't define this, the default is two 748 words. */ 749#define DOUBLE_TYPE_SIZE 64 750 751/* A C expression for the size in bits of the type `long double' on the target 752 machine. If you don't define this, the default is two words. */ 753#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 754 755/* Work around rs6000_long_double_type_size dependency in ada/targtyps.cc. */ 756#define WIDEST_HARDWARE_FP_SIZE 64 757 758/* Width in bits of a pointer. 759 See also the macro `Pmode' defined below. */ 760extern unsigned rs6000_pointer_size; 761#define POINTER_SIZE rs6000_pointer_size 762 763/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 764#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 765 766/* Boundary (in *bits*) on which stack pointer should be aligned. */ 767#define STACK_BOUNDARY \ 768 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 769 ? 64 : 128) 770 771/* Allocation boundary (in *bits*) for the code of a function. */ 772#define FUNCTION_BOUNDARY 32 773 774/* No data type is required to be aligned rounder than this. Warning, if 775 BIGGEST_ALIGNMENT is changed, then this may be an ABI break. An example 776 of where this can break an ABI is in GLIBC's struct _Unwind_Exception. */ 777#define BIGGEST_ALIGNMENT 128 778 779/* Alignment of field after `int : 0' in a structure. */ 780#define EMPTY_FIELD_BOUNDARY 32 781 782/* Every structure's size must be a multiple of this. */ 783#define STRUCTURE_SIZE_BOUNDARY 8 784 785/* A bit-field declared as `int' forces `int' alignment for the struct. */ 786#define PCC_BITFIELD_TYPE_MATTERS 1 787 788enum data_align { align_abi, align_opt, align_both }; 789 790/* A C expression to compute the alignment for a variables in the 791 local store. TYPE is the data type, and ALIGN is the alignment 792 that the object would ordinarily have. */ 793#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 794 rs6000_data_alignment (TYPE, ALIGN, align_both) 795 796/* Make arrays of chars word-aligned for the same reasons. */ 797#define DATA_ALIGNMENT(TYPE, ALIGN) \ 798 rs6000_data_alignment (TYPE, ALIGN, align_opt) 799 800/* Align vectors to 128 bits. */ 801#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 802 rs6000_data_alignment (TYPE, ALIGN, align_abi) 803 804/* Nonzero if move instructions will actually fail to work 805 when given unaligned data. */ 806#define STRICT_ALIGNMENT 0 807 808/* Standard register usage. */ 809 810/* Number of actual hardware registers. 811 The hardware registers are assigned numbers for the compiler 812 from 0 to just below FIRST_PSEUDO_REGISTER. 813 All registers that the compiler knows about must be given numbers, 814 even those that are not normally considered general registers. 815 816 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 817 a count register, a link register, and 8 condition register fields, 818 which we view here as separate registers. AltiVec adds 32 vector 819 registers and a VRsave register. 820 821 In addition, the difference between the frame and argument pointers is 822 a function of the number of registers saved, so we need to have a 823 register for AP that will later be eliminated in favor of SP or FP. 824 This is a normal register, but it is fixed. 825 826 We also create a pseudo register for float/int conversions, that will 827 really represent the memory location used. It is represented here as 828 a register, in order to work around problems in allocating stack storage 829 in inline functions. 830 831 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 832 pointer, which is eventually eliminated in favor of SP or FP. */ 833 834#define FIRST_PSEUDO_REGISTER 111 835 836/* Use standard DWARF numbering for DWARF debugging information. */ 837#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) 838 839/* Use gcc hard register numbering for eh_frame. */ 840#define DWARF_FRAME_REGNUM(REGNO) (REGNO) 841 842/* Map register numbers held in the call frame info that gcc has 843 collected using DWARF_FRAME_REGNUM to those that should be output in 844 .debug_frame and .eh_frame. */ 845#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 846 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1) 847 848/* 1 for registers that have pervasive standard uses 849 and are not available for the register allocator. 850 851 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 852 as a local register; for all other OS's r2 is the TOC pointer. 853 854 On System V implementations, r13 is fixed and not available for use. */ 855 856#define FIXED_REGISTERS \ 857 {/* GPRs */ \ 858 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 859 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 860 /* FPRs */ \ 861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 862 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 863 /* VRs */ \ 864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 866 /* lr ctr ca ap */ \ 867 0, 0, 1, 1, \ 868 /* cr0..cr7 */ \ 869 0, 0, 0, 0, 0, 0, 0, 0, \ 870 /* vrsave vscr sfp */ \ 871 1, 1, 1 \ 872} 873 874/* Like `CALL_USED_REGISTERS' except this macro doesn't require that 875 the entire set of `FIXED_REGISTERS' be included. 876 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 877 This macro is optional. If not specified, it defaults to the value 878 of `CALL_USED_REGISTERS'. */ 879 880#define CALL_REALLY_USED_REGISTERS \ 881 {/* GPRs */ \ 882 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 883 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 884 /* FPRs */ \ 885 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 886 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 887 /* VRs */ \ 888 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 889 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 890 /* lr ctr ca ap */ \ 891 1, 1, 1, 1, \ 892 /* cr0..cr7 */ \ 893 1, 1, 0, 0, 0, 1, 1, 1, \ 894 /* vrsave vscr sfp */ \ 895 0, 0, 0 \ 896} 897 898#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 899 900#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 901#define FIRST_SAVED_FP_REGNO (14+32) 902#define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 903 904/* List the order in which to allocate registers. Each register must be 905 listed once, even those in FIXED_REGISTERS. 906 907 We allocate in the following order: 908 fp0 (not saved or used for anything) 909 fp13 - fp2 (not saved; incoming fp arg registers) 910 fp1 (not saved; return value) 911 fp31 - fp14 (saved; order given to save least number) 912 cr7, cr5 (not saved or special) 913 cr6 (not saved, but used for vector operations) 914 cr1 (not saved, but used for FP operations) 915 cr0 (not saved, but used for arithmetic operations) 916 cr4, cr3, cr2 (saved) 917 r9 (not saved; best for TImode) 918 r10, r8-r4 (not saved; highest first for less conflict with params) 919 r3 (not saved; return value register) 920 r11 (not saved; later alloc to help shrink-wrap) 921 r0 (not saved; cannot be base reg) 922 r31 - r13 (saved; order given to save least number) 923 r12 (not saved; if used for DImode or DFmode would use r13) 924 ctr (not saved; when we have the choice ctr is better) 925 lr (saved) 926 r1, r2, ap, ca (fixed) 927 v0 - v1 (not saved or used for anything) 928 v13 - v3 (not saved; incoming vector arg registers) 929 v2 (not saved; incoming vector arg reg; return value) 930 v19 - v14 (not saved or used for anything) 931 v31 - v20 (saved; order given to save least number) 932 vrsave, vscr (fixed) 933 sfp (fixed) 934*/ 935 936#if FIXED_R2 == 1 937#define MAYBE_R2_AVAILABLE 938#define MAYBE_R2_FIXED 2, 939#else 940#define MAYBE_R2_AVAILABLE 2, 941#define MAYBE_R2_FIXED 942#endif 943 944#if FIXED_R13 == 1 945#define EARLY_R12 12, 946#define LATE_R12 947#else 948#define EARLY_R12 949#define LATE_R12 12, 950#endif 951 952#define REG_ALLOC_ORDER \ 953 {32, \ 954 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ 955 /* not use fr14 which is a saved register. */ \ 956 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 957 33, \ 958 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 959 50, 49, 48, 47, 46, \ 960 100, 107, 105, 106, 101, 104, 103, 102, \ 961 MAYBE_R2_AVAILABLE \ 962 9, 10, 8, 7, 6, 5, 4, \ 963 3, EARLY_R12 11, 0, \ 964 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 965 18, 17, 16, 15, 14, 13, LATE_R12 \ 966 97, 96, \ 967 1, MAYBE_R2_FIXED 99, 98, \ 968 /* AltiVec registers. */ \ 969 64, 65, \ 970 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \ 971 66, \ 972 83, 82, 81, 80, 79, 78, \ 973 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ 974 108, 109, \ 975 110 \ 976} 977 978/* True if register is floating-point. */ 979#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 980 981/* True if register is a condition register. */ 982#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 983 984/* True if register is a condition register, but not cr0. */ 985#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 986 987/* True if register is an integer register. */ 988#define INT_REGNO_P(N) \ 989 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 990 991/* True if register is the CA register. */ 992#define CA_REGNO_P(N) ((N) == CA_REGNO) 993 994/* True if register is an AltiVec register. */ 995#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 996 997/* True if register is a VSX register. */ 998#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 999 1000/* Alternate name for any vector register supporting floating point, no matter 1001 which instruction set(s) are available. */ 1002#define VFLOAT_REGNO_P(N) \ 1003 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1004 1005/* Alternate name for any vector register supporting integer, no matter which 1006 instruction set(s) are available. */ 1007#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1008 1009/* Alternate name for any vector register supporting logical operations, no 1010 matter which instruction set(s) are available. Allow GPRs as well as the 1011 vector registers. */ 1012#define VLOGICAL_REGNO_P(N) \ 1013 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ 1014 || (TARGET_VSX && FP_REGNO_P (N))) \ 1015 1016/* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1017 enough space to account for vectors in FP regs. However, TFmode/TDmode 1018 should not use VSX instructions to do a caller save. */ 1019#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1020 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ 1021 ? (MODE) \ 1022 : TARGET_VSX \ 1023 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1024 && FP_REGNO_P (REGNO) \ 1025 ? V2DFmode \ 1026 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ 1027 ? DFmode \ 1028 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ 1029 ? DImode \ 1030 : choose_hard_reg_mode ((REGNO), (NREGS), NULL)) 1031 1032#define VSX_VECTOR_MODE(MODE) \ 1033 ((MODE) == V4SFmode \ 1034 || (MODE) == V2DFmode) \ 1035 1036/* Modes that are not vectors, but require vector alignment. Treat these like 1037 vectors in terms of loads and stores. */ 1038#define VECTOR_ALIGNMENT_P(MODE) \ 1039 (FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode) 1040 1041#define ALTIVEC_VECTOR_MODE(MODE) \ 1042 ((MODE) == V16QImode \ 1043 || (MODE) == V8HImode \ 1044 || (MODE) == V4SFmode \ 1045 || (MODE) == V4SImode \ 1046 || VECTOR_ALIGNMENT_P (MODE)) 1047 1048#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1049 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1050 || (MODE) == V2DImode || (MODE) == V1TImode) 1051 1052/* Post-reload, we can't use any new AltiVec registers, as we already 1053 emitted the vrsave mask. */ 1054 1055#define HARD_REGNO_RENAME_OK(SRC, DST) \ 1056 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1057 1058/* Specify the cost of a branch insn; roughly the number of extra insns that 1059 should be added to avoid a branch. 1060 1061 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1062 unscheduled conditional branch. */ 1063 1064#define BRANCH_COST(speed_p, predictable_p) 3 1065 1066/* Override BRANCH_COST heuristic which empirically produces worse 1067 performance for removing short circuiting from the logical ops. */ 1068 1069#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1070 1071/* Specify the registers used for certain standard purposes. 1072 The values of these macros are register numbers. */ 1073 1074/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1075/* #define PC_REGNUM */ 1076 1077/* Register to use for pushing function arguments. */ 1078#define STACK_POINTER_REGNUM 1 1079 1080/* Base register for access to local variables of the function. */ 1081#define HARD_FRAME_POINTER_REGNUM 31 1082 1083/* Base register for access to local variables of the function. */ 1084#define FRAME_POINTER_REGNUM 110 1085 1086/* Base register for access to arguments of the function. */ 1087#define ARG_POINTER_REGNUM 99 1088 1089/* Place to put static chain when calling a function that requires it. */ 1090#define STATIC_CHAIN_REGNUM 11 1091 1092/* Base register for access to thread local storage variables. */ 1093#define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) 1094 1095 1096/* Define the classes of registers for register constraints in the 1097 machine description. Also define ranges of constants. 1098 1099 One of the classes must always be named ALL_REGS and include all hard regs. 1100 If there is more than one class, another class must be named NO_REGS 1101 and contain no registers. 1102 1103 The name GENERAL_REGS must be the name of a class (or an alias for 1104 another name such as ALL_REGS). This is the class of registers 1105 that is allowed by "g" or "r" in a register constraint. 1106 Also, registers outside this class are allocated only when 1107 instructions express preferences for them. 1108 1109 The classes must be numbered in nondecreasing order; that is, 1110 a larger-numbered class must never be contained completely 1111 in a smaller-numbered class. 1112 1113 For any two classes, it is very desirable that there be another 1114 class that represents their union. */ 1115 1116/* The RS/6000 has three types of registers, fixed-point, floating-point, and 1117 condition registers, plus three special registers, CTR, and the link 1118 register. AltiVec adds a vector register class. VSX registers overlap the 1119 FPR registers and the Altivec registers. 1120 1121 However, r0 is special in that it cannot be used as a base register. 1122 So make a class for registers valid as base registers. 1123 1124 Also, cr0 is the only condition code register that can be used in 1125 arithmetic insns, so make a separate class for it. */ 1126 1127enum reg_class 1128{ 1129 NO_REGS, 1130 BASE_REGS, 1131 GENERAL_REGS, 1132 FLOAT_REGS, 1133 ALTIVEC_REGS, 1134 VSX_REGS, 1135 VRSAVE_REGS, 1136 VSCR_REGS, 1137 GEN_OR_FLOAT_REGS, 1138 GEN_OR_VSX_REGS, 1139 LINK_REGS, 1140 CTR_REGS, 1141 LINK_OR_CTR_REGS, 1142 SPECIAL_REGS, 1143 SPEC_OR_GEN_REGS, 1144 CR0_REGS, 1145 CR_REGS, 1146 NON_FLOAT_REGS, 1147 CA_REGS, 1148 ALL_REGS, 1149 LIM_REG_CLASSES 1150}; 1151 1152#define N_REG_CLASSES (int) LIM_REG_CLASSES 1153 1154/* Give names of register classes as strings for dump file. */ 1155 1156#define REG_CLASS_NAMES \ 1157{ \ 1158 "NO_REGS", \ 1159 "BASE_REGS", \ 1160 "GENERAL_REGS", \ 1161 "FLOAT_REGS", \ 1162 "ALTIVEC_REGS", \ 1163 "VSX_REGS", \ 1164 "VRSAVE_REGS", \ 1165 "VSCR_REGS", \ 1166 "GEN_OR_FLOAT_REGS", \ 1167 "GEN_OR_VSX_REGS", \ 1168 "LINK_REGS", \ 1169 "CTR_REGS", \ 1170 "LINK_OR_CTR_REGS", \ 1171 "SPECIAL_REGS", \ 1172 "SPEC_OR_GEN_REGS", \ 1173 "CR0_REGS", \ 1174 "CR_REGS", \ 1175 "NON_FLOAT_REGS", \ 1176 "CA_REGS", \ 1177 "ALL_REGS" \ 1178} 1179 1180/* Define which registers fit in which classes. 1181 This is an initializer for a vector of HARD_REG_SET 1182 of length N_REG_CLASSES. */ 1183 1184#define REG_CLASS_CONTENTS \ 1185{ \ 1186 /* NO_REGS. */ \ 1187 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1188 /* BASE_REGS. */ \ 1189 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \ 1190 /* GENERAL_REGS. */ \ 1191 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \ 1192 /* FLOAT_REGS. */ \ 1193 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ 1194 /* ALTIVEC_REGS. */ \ 1195 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ 1196 /* VSX_REGS. */ \ 1197 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1198 /* VRSAVE_REGS. */ \ 1199 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ 1200 /* VSCR_REGS. */ \ 1201 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ 1202 /* GEN_OR_FLOAT_REGS. */ \ 1203 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \ 1204 /* GEN_OR_VSX_REGS. */ \ 1205 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \ 1206 /* LINK_REGS. */ \ 1207 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \ 1208 /* CTR_REGS. */ \ 1209 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \ 1210 /* LINK_OR_CTR_REGS. */ \ 1211 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \ 1212 /* SPECIAL_REGS. */ \ 1213 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \ 1214 /* SPEC_OR_GEN_REGS. */ \ 1215 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \ 1216 /* CR0_REGS. */ \ 1217 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \ 1218 /* CR_REGS. */ \ 1219 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \ 1220 /* NON_FLOAT_REGS. */ \ 1221 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \ 1222 /* CA_REGS. */ \ 1223 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ 1224 /* ALL_REGS. */ \ 1225 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ 1226} 1227 1228/* The same information, inverted: 1229 Return the class number of the smallest class containing 1230 reg number REGNO. This could be a conditional expression 1231 or could index an array. */ 1232 1233extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1234 1235#define REGNO_REG_CLASS(REGNO) \ 1236 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ 1237 rs6000_regno_regclass[(REGNO)]) 1238 1239/* Register classes for various constraints that are based on the target 1240 switches. */ 1241enum r6000_reg_class_enum { 1242 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1243 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1244 RS6000_CONSTRAINT_v, /* Altivec registers */ 1245 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1246 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ 1247 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ 1248 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ 1249 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ 1250 RS6000_CONSTRAINT_MAX 1251}; 1252 1253extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1254 1255/* The class value for index registers, and the one for base regs. */ 1256#define INDEX_REG_CLASS GENERAL_REGS 1257#define BASE_REG_CLASS BASE_REGS 1258 1259/* Return whether a given register class can hold VSX objects. */ 1260#define VSX_REG_CLASS_P(CLASS) \ 1261 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1262 1263/* Return whether a given register class targets general purpose registers. */ 1264#define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) 1265 1266/* Given an rtx X being reloaded into a reg required to be 1267 in class CLASS, return the class of reg to actually use. 1268 In general this is just CLASS; but on some machines 1269 in some cases it is preferable to use a more restrictive class. 1270 1271 On the RS/6000, we have to return NO_REGS when we want to reload a 1272 floating-point CONST_DOUBLE to force it to be copied to memory. 1273 1274 We also don't want to reload integer values into floating-point 1275 registers if we can at all help it. In fact, this can 1276 cause reload to die, if it tries to generate a reload of CTR 1277 into a FP register and discovers it doesn't have the memory location 1278 required. 1279 1280 ??? Would it be a good idea to have reload do the converse, that is 1281 try to reload floating modes into FP registers if possible? 1282 */ 1283 1284#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1285 rs6000_preferred_reload_class_ptr (X, CLASS) 1286 1287/* Return the register class of a scratch register needed to copy IN into 1288 or out of a register in CLASS in MODE. If it can be done directly, 1289 NO_REGS is returned. */ 1290 1291#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1292 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1293 1294/* Return the maximum number of consecutive registers 1295 needed to represent mode MODE in a register of class CLASS. 1296 1297 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1298 a single reg is enough for two words, unless we have VSX, where the FP 1299 registers can hold 128 bits. */ 1300#define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1301 1302/* Stack layout; function entry, exit and calling. */ 1303 1304/* Define this if pushing a word on the stack 1305 makes the stack pointer a smaller address. */ 1306#define STACK_GROWS_DOWNWARD 1 1307 1308/* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1309#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1310 1311/* Define this to nonzero if the nominal address of the stack frame 1312 is at the high-address end of the local variables; 1313 that is, each additional local variable allocated 1314 goes at a more negative offset in the frame. 1315 1316 On the RS/6000, we grow upwards, from the area after the outgoing 1317 arguments. */ 1318#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 1319 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 1320 1321/* Size of the fixed area on the stack */ 1322#define RS6000_SAVE_AREA \ 1323 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ 1324 << (TARGET_64BIT ? 1 : 0)) 1325 1326/* Stack offset for toc save slot. */ 1327#define RS6000_TOC_SAVE_SLOT \ 1328 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) 1329 1330/* Align an address */ 1331#define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) 1332 1333/* Offset within stack frame to start allocating local variables at. 1334 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1335 first local allocated. Otherwise, it is the offset to the BEGINNING 1336 of the first local allocated. 1337 1338 On the RS/6000, the frame pointer is the same as the stack pointer, 1339 except for dynamic allocations. So we start after the fixed area and 1340 outgoing parameter area. 1341 1342 If the function uses dynamic stack space (CALLS_ALLOCA is set), that 1343 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the 1344 sizes of the fixed area and the parameter area must be a multiple of 1345 STACK_BOUNDARY. */ 1346 1347#define RS6000_STARTING_FRAME_OFFSET \ 1348 (cfun->calls_alloca \ 1349 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ 1350 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ 1351 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1352 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1353 + RS6000_SAVE_AREA)) 1354 1355/* Offset from the stack pointer register to an item dynamically 1356 allocated on the stack, e.g., by `alloca'. 1357 1358 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1359 length of the outgoing arguments. The default is correct for most 1360 machines. See `function.cc' for details. 1361 1362 This value must be a multiple of STACK_BOUNDARY (hard coded in 1363 `emit-rtl.cc'). */ 1364#define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1365 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ 1366 + STACK_POINTER_OFFSET, \ 1367 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) 1368 1369/* If we generate an insn to push BYTES bytes, 1370 this says how many the stack pointer really advances by. 1371 On RS/6000, don't define this because there are no push insns. */ 1372/* #define PUSH_ROUNDING(BYTES) */ 1373 1374/* Offset of first parameter from the argument pointer register value. 1375 On the RS/6000, we define the argument pointer to the start of the fixed 1376 area. */ 1377#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1378 1379/* Offset from the argument pointer register value to the top of 1380 stack. This is different from FIRST_PARM_OFFSET because of the 1381 register save area. */ 1382#define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1383 1384/* Define this if stack space is still allocated for a parameter passed 1385 in a register. The value is the number of bytes allocated to this 1386 area. */ 1387#define REG_PARM_STACK_SPACE(FNDECL) \ 1388 rs6000_reg_parm_stack_space ((FNDECL), false) 1389 1390/* Define this macro if space guaranteed when compiling a function body 1391 is different to space required when making a call, a situation that 1392 can arise with K&R style function definitions. */ 1393#define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ 1394 rs6000_reg_parm_stack_space ((FNDECL), true) 1395 1396/* Define this if the above stack space is to be considered part of the 1397 space allocated by the caller. */ 1398#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1399 1400/* This is the difference between the logical top of stack and the actual sp. 1401 1402 For the RS/6000, sp points past the fixed area. */ 1403#define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1404 1405/* Define this if the maximum size of all the outgoing args is to be 1406 accumulated and pushed during the prologue. The amount can be 1407 found in the variable crtl->outgoing_args_size. */ 1408#define ACCUMULATE_OUTGOING_ARGS 1 1409 1410/* Define how to find the value returned by a library function 1411 assuming the value has mode MODE. */ 1412 1413#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1414 1415/* DRAFT_V4_STRUCT_RET defaults off. */ 1416#define DRAFT_V4_STRUCT_RET 0 1417 1418/* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1419#define DEFAULT_PCC_STRUCT_RETURN 0 1420 1421/* Mode of stack savearea. 1422 FUNCTION is VOIDmode because calling convention maintains SP. 1423 BLOCK needs Pmode for SP. 1424 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1425#define STACK_SAVEAREA_MODE(LEVEL) \ 1426 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1427 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) 1428 1429/* Minimum and maximum general purpose registers used to hold arguments. */ 1430#define GP_ARG_MIN_REG 3 1431#define GP_ARG_MAX_REG 10 1432#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1433 1434/* Minimum and maximum floating point registers used to hold arguments. */ 1435#define FP_ARG_MIN_REG 33 1436#define FP_ARG_AIX_MAX_REG 45 1437#define FP_ARG_V4_MAX_REG 40 1438#define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ 1439 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) 1440#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1441 1442/* Minimum and maximum AltiVec registers used to hold arguments. */ 1443#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1444#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1445#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1446 1447/* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ 1448#define AGGR_ARG_NUM_REG 8 1449 1450/* Return registers */ 1451#define GP_ARG_RETURN GP_ARG_MIN_REG 1452#define FP_ARG_RETURN FP_ARG_MIN_REG 1453#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1454#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ 1455 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1456#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ 1457 ? (ALTIVEC_ARG_RETURN \ 1458 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ 1459 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1460 1461/* Flags for the call/call_value rtl operations set up by function_arg */ 1462#define CALL_NORMAL 0x00000000 /* no special processing */ 1463/* Bits in 0x00000001 are unused. */ 1464#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1465#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1466#define CALL_LONG 0x00000008 /* always call indirect */ 1467#define CALL_LIBCALL 0x00000010 /* libcall */ 1468 1469/* Identify PLT sequence for rs6000_pltseq_template. */ 1470enum rs6000_pltseq_enum { 1471 RS6000_PLTSEQ_TOCSAVE, 1472 RS6000_PLTSEQ_PLT16_HA, 1473 RS6000_PLTSEQ_PLT16_LO, 1474 RS6000_PLTSEQ_MTCTR, 1475 RS6000_PLTSEQ_PLT_PCREL34 1476}; 1477 1478#define IS_V4_FP_ARGS(OP) \ 1479 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0) 1480 1481/* We don't have prologue and epilogue functions to save/restore 1482 everything for most ABIs. */ 1483#define WORLD_SAVE_P(INFO) 0 1484 1485/* 1 if N is a possible register number for a function value 1486 as seen by the caller. 1487 1488 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1489#define FUNCTION_VALUE_REGNO_P(N) \ 1490 ((N) == GP_ARG_RETURN \ 1491 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ 1492 && TARGET_HARD_FLOAT) \ 1493 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ 1494 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1495 1496/* 1 if N is a possible register number for function argument passing. 1497 On RS/6000, these are r3-r10 and fp1-fp13. 1498 On AltiVec, v2 - v13 are used for passing vectors. */ 1499#define FUNCTION_ARG_REGNO_P(N) \ 1500 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ 1501 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ 1502 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1503 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ 1504 && TARGET_HARD_FLOAT)) 1505 1506/* Define a data type for recording info about an argument list 1507 during the scan of that argument list. This data type should 1508 hold all necessary information about the function itself 1509 and about the args processed so far, enough to enable macros 1510 such as FUNCTION_ARG to determine where the next arg should go. 1511 1512 On the RS/6000, this is a structure. The first element is the number of 1513 total argument words, the second is used to store the next 1514 floating-point register number, and the third says how many more args we 1515 have prototype types for. 1516 1517 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1518 the next available GP register, `fregno' is the next available FP 1519 register, and `words' is the number of words used on the stack. 1520 1521 The varargs/stdarg support requires that this structure's size 1522 be a multiple of sizeof(int). */ 1523 1524typedef struct rs6000_args 1525{ 1526 int words; /* # words used for passing GP registers */ 1527 int fregno; /* next available FP register */ 1528 int vregno; /* next available AltiVec register */ 1529 int nargs_prototype; /* # args left in the current prototype */ 1530 int prototype; /* Whether a prototype was defined */ 1531 int stdarg; /* Whether function is a stdarg function. */ 1532 int call_cookie; /* Do special things for this call */ 1533 int sysv_gregno; /* next available GP register */ 1534 int intoffset; /* running offset in struct (darwin64) */ 1535 int use_stack; /* any part of struct on stack (darwin64) */ 1536 int floats_in_gpr; /* count of SFmode floats taking up 1537 GPR space (darwin64) */ 1538 int named; /* false for varargs params */ 1539 int escapes; /* if function visible outside tu */ 1540 int libcall; /* If this is a compiler generated call. */ 1541} CUMULATIVE_ARGS; 1542 1543/* Initialize a variable CUM of type CUMULATIVE_ARGS 1544 for a call to a function whose data type is FNTYPE. 1545 For a library call, FNTYPE is 0. */ 1546 1547#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1548 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1549 N_NAMED_ARGS, FNDECL, VOIDmode) 1550 1551/* Similar, but when scanning the definition of a procedure. We always 1552 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1553 1554#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1555 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1556 1000, current_function_decl, VOIDmode) 1557 1558/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1559 1560#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1561 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1562 0, NULL_TREE, MODE) 1563 1564#define PAD_VARARGS_DOWN \ 1565 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) 1566 1567/* Output assembler code to FILE to increment profiler label # LABELNO 1568 for profiling a function entry. */ 1569 1570#define FUNCTION_PROFILER(FILE, LABELNO) \ 1571 output_function_profiler ((FILE), (LABELNO)); 1572 1573/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1574 the stack pointer does not matter. No definition is equivalent to 1575 always zero. 1576 1577 On the RS/6000, this is nonzero because we can restore the stack from 1578 its backpointer, which we maintain. */ 1579#define EXIT_IGNORE_STACK 1 1580 1581/* Define this macro as a C expression that is nonzero for registers 1582 that are used by the epilogue or the return' pattern. The stack 1583 and frame pointer registers are already be assumed to be used as 1584 needed. */ 1585 1586#define EPILOGUE_USES(REGNO) \ 1587 ((reload_completed && (REGNO) == LR_REGNO) \ 1588 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1589 || (crtl->calls_eh_return \ 1590 && TARGET_AIX \ 1591 && (REGNO) == 2)) 1592 1593 1594/* Length in units of the trampoline for entering a nested function. */ 1595 1596#define TRAMPOLINE_SIZE rs6000_trampoline_size () 1597 1598/* Definitions for __builtin_return_address and __builtin_frame_address. 1599 __builtin_return_address (0) should give link register (LR_REGNO), enable 1600 this. */ 1601/* This should be uncommented, so that the link register is used, but 1602 currently this would result in unmatched insns and spilling fixed 1603 registers so we'll leave it for another day. When these problems are 1604 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1605 (mrs) */ 1606/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1607 1608/* Number of bytes into the frame return addresses can be found. See 1609 rs6000_stack_info in rs6000.cc for more information on how the different 1610 abi's store the return address. */ 1611#define RETURN_ADDRESS_OFFSET \ 1612 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) 1613 1614/* The current return address is in the link register. The return address 1615 of anything farther back is accessed normally at an offset of 8 from the 1616 frame pointer. */ 1617#define RETURN_ADDR_RTX(COUNT, FRAME) \ 1618 (rs6000_return_addr (COUNT, FRAME)) 1619 1620 1621/* Definitions for register eliminations. 1622 1623 We have two registers that can be eliminated on the RS/6000. First, the 1624 frame pointer register can often be eliminated in favor of the stack 1625 pointer register. Secondly, the argument pointer register can always be 1626 eliminated; it is replaced with either the stack or frame pointer. 1627 1628 In addition, we use the elimination mechanism to see if r30 is needed 1629 Initially we assume that it isn't. If it is, we spill it. This is done 1630 by making it an eliminable register. We replace it with itself so that 1631 if it isn't needed, then existing uses won't be modified. */ 1632 1633/* This is an array of structures. Each structure initializes one pair 1634 of eliminable registers. The "from" register number is given first, 1635 followed by "to". Eliminations of the same "from" register are listed 1636 in order of preference. */ 1637#define ELIMINABLE_REGS \ 1638{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1639 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1640 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1641 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1642 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1643 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1644 1645/* Define the offset between two registers, one to be eliminated, and the other 1646 its replacement, at the start of a routine. */ 1647#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1648 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1649 1650/* Addressing modes, and classification of registers for them. */ 1651 1652#define HAVE_PRE_DECREMENT 1 1653#define HAVE_PRE_INCREMENT 1 1654#define HAVE_PRE_MODIFY_DISP 1 1655#define HAVE_PRE_MODIFY_REG 1 1656 1657/* Macros to check register numbers against specific register classes. */ 1658 1659/* These assume that REGNO is a hard or pseudo reg number. 1660 They give nonzero only if REGNO is a hard reg of the suitable class 1661 or a pseudo reg currently allocated to a suitable hard reg. 1662 Since they use reg_renumber, they are safe only once reg_renumber 1663 has been allocated, which happens in reginfo.cc during register 1664 allocation. */ 1665 1666#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1667(HARD_REGISTER_NUM_P (REGNO) \ 1668 ? (REGNO) <= 31 \ 1669 || (REGNO) == ARG_POINTER_REGNUM \ 1670 || (REGNO) == FRAME_POINTER_REGNUM \ 1671 : (reg_renumber[REGNO] >= 0 \ 1672 && (reg_renumber[REGNO] <= 31 \ 1673 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1674 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1675 1676#define REGNO_OK_FOR_BASE_P(REGNO) \ 1677(HARD_REGISTER_NUM_P (REGNO) \ 1678 ? ((REGNO) > 0 && (REGNO) <= 31) \ 1679 || (REGNO) == ARG_POINTER_REGNUM \ 1680 || (REGNO) == FRAME_POINTER_REGNUM \ 1681 : (reg_renumber[REGNO] > 0 \ 1682 && (reg_renumber[REGNO] <= 31 \ 1683 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1684 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1685 1686/* Nonzero if X is a hard reg that can be used as an index 1687 or if it is a pseudo reg in the non-strict case. */ 1688#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1689 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1690 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1691 1692/* Nonzero if X is a hard reg that can be used as a base reg 1693 or if it is a pseudo reg in the non-strict case. */ 1694#define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1695 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1696 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1697 1698 1699/* Maximum number of registers that can appear in a valid memory address. */ 1700 1701#define MAX_REGS_PER_ADDRESS 2 1702 1703/* Recognize any constant value that is a valid address. */ 1704 1705#define CONSTANT_ADDRESS_P(X) \ 1706 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \ 1707 || CONST_INT_P (X) || GET_CODE (X) == CONST \ 1708 || GET_CODE (X) == HIGH) 1709 1710#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1711#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1712 && EASY_VECTOR_15((n) >> 1) \ 1713 && ((n) & 1) == 0) 1714 1715#define EASY_VECTOR_MSB(n,mode) \ 1716 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ 1717 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1718 1719 1720#define FIND_BASE_TERM rs6000_find_base_term 1721 1722/* The register number of the register used to address a table of 1723 static data addresses in memory. In some cases this register is 1724 defined by a processor's "application binary interface" (ABI). 1725 When this macro is defined, RTL is generated for this register 1726 once, as with the stack pointer and frame pointer registers. If 1727 this macro is not defined, it is up to the machine-dependent files 1728 to allocate such a register (if necessary). */ 1729 1730#define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1731#define PIC_OFFSET_TABLE_REGNUM \ 1732 (TARGET_TOC ? TOC_REGISTER \ 1733 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ 1734 : INVALID_REGNUM) 1735 1736#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1737 1738/* Define this macro if the register defined by 1739 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1740 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1741 1742/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1743 1744/* A C expression that is nonzero if X is a legitimate immediate 1745 operand on the target machine when generating position independent 1746 code. You can assume that X satisfies `CONSTANT_P', so you need 1747 not check this. You can also assume FLAG_PIC is true, so you need 1748 not check it either. You need not define this macro if all 1749 constants (including `SYMBOL_REF') can be immediate operands when 1750 generating position independent code. */ 1751 1752/* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1753 1754/* Define as C expression which evaluates to nonzero if the tablejump 1755 instruction expects the table to contain offsets from the address of the 1756 table. 1757 Do not define this if the table should contain absolute addresses. */ 1758#define CASE_VECTOR_PC_RELATIVE rs6000_relative_jumptables 1759 1760/* Specify the machine mode that this machine uses 1761 for the index in the tablejump instruction. */ 1762#define CASE_VECTOR_MODE (rs6000_relative_jumptables ? SImode : Pmode) 1763 1764/* Define this as 1 if `char' should by default be signed; else as 0. */ 1765#define DEFAULT_SIGNED_CHAR 0 1766 1767/* An integer expression for the size in bits of the largest integer machine 1768 mode that should actually be used. */ 1769 1770/* Allow pairs of registers to be used, which is the intent of the default. */ 1771#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1772 1773/* Max number of bytes we can move from memory to memory 1774 in one reasonably fast instruction. */ 1775#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1776#define MAX_MOVE_MAX 8 1777 1778/* Nonzero if access to memory by bytes is no faster than for words. 1779 Also nonzero if doing byte operations (specifically shifts) in registers 1780 is undesirable. */ 1781#define SLOW_BYTE_ACCESS 1 1782 1783/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1784 will either zero-extend or sign-extend. The value of this macro should 1785 be the code that says which one of the two operations is implicitly 1786 done, UNKNOWN if none. */ 1787#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1788 1789/* Define if loading short immediate values into registers sign extends. */ 1790#define SHORT_IMMEDIATES_SIGN_EXTEND 1 1791 1792/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1793#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1794 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) 1795 1796/* The CTZ patterns that are implemented in terms of CLZ return -1 for input of 1797 zero. The hardware instructions added in Power9 and the sequences using 1798 popcount return 32 or 64. */ 1799#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1800 (TARGET_CTZ || TARGET_POPCNTD \ 1801 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ 1802 : ((VALUE) = -1, 2)) 1803 1804/* Specify the machine mode that pointers have. 1805 After generation of rtl, the compiler makes no further distinction 1806 between pointers and any other objects of this machine mode. */ 1807extern scalar_int_mode rs6000_pmode; 1808#define Pmode rs6000_pmode 1809 1810/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 1811#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 1812 1813/* Mode of a function address in a call instruction (for indexing purposes). 1814 Doesn't matter on RS/6000. */ 1815#define FUNCTION_MODE SImode 1816 1817/* Define this if addresses of constant functions 1818 shouldn't be put through pseudo regs where they can be cse'd. 1819 Desirable on machines where ordinary constants are expensive 1820 but a CALL with constant address is cheap. */ 1821#define NO_FUNCTION_CSE 1 1822 1823/* Define this to be nonzero if shift instructions ignore all but the low-order 1824 few bits. 1825 1826 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 1827 have been dropped from the PowerPC architecture. */ 1828#define SHIFT_COUNT_TRUNCATED 0 1829 1830/* Adjust the length of an INSN. LENGTH is the currently-computed length and 1831 should be adjusted to reflect any required changes. This macro is used when 1832 there is some systematic length adjustment required that would be difficult 1833 to express in the length attribute. 1834 1835 In the PowerPC, we use this to adjust the length of an instruction if one or 1836 more prefixed instructions are generated, using the attribute 1837 num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the 1838 hardware requires that a prefied instruciton does not cross a 64-byte 1839 boundary. This means the compiler has to assume the length of the first 1840 prefixed instruction is 12 bytes instead of 8 bytes. Since the length is 1841 already set for the non-prefixed instruction, we just need to udpate for the 1842 difference. */ 1843 1844#define ADJUST_INSN_LENGTH(INSN,LENGTH) \ 1845 (LENGTH) = rs6000_adjust_insn_length ((INSN), (LENGTH)) 1846 1847/* Given a comparison code (EQ, NE, etc.) and the first operand of a 1848 COMPARE, return the mode to be used for the comparison. For 1849 floating-point, CCFPmode should be used. CCUNSmode should be used 1850 for unsigned comparisons. CCEQmode should be used when we are 1851 doing an inequality comparison on the result of a 1852 comparison. CCmode should be used in all other cases. */ 1853 1854#define SELECT_CC_MODE(OP,X,Y) \ 1855 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 1856 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 1857 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 1858 ? CCEQmode : CCmode)) 1859 1860/* Can the condition code MODE be safely reversed? This is safe in 1861 all cases on this port, because at present it doesn't use the 1862 trapping FP comparisons (fcmpo). */ 1863#define REVERSIBLE_CC_MODE(MODE) 1 1864 1865/* Given a condition code and a mode, return the inverse condition. */ 1866#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 1867 1868 1869/* Target cpu costs. */ 1870 1871struct processor_costs { 1872 const int mulsi; /* cost of SImode multiplication. */ 1873 const int mulsi_const; /* cost of SImode multiplication by constant. */ 1874 const int mulsi_const9; /* cost of SImode mult by short constant. */ 1875 const int muldi; /* cost of DImode multiplication. */ 1876 const int divsi; /* cost of SImode division. */ 1877 const int divdi; /* cost of DImode division. */ 1878 const int fp; /* cost of simple SFmode and DFmode insns. */ 1879 const int dmul; /* cost of DFmode multiplication (and fmadd). */ 1880 const int sdiv; /* cost of SFmode division (fdivs). */ 1881 const int ddiv; /* cost of DFmode division (fdiv). */ 1882 const int cache_line_size; /* cache line size in bytes. */ 1883 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 1884 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 1885 const int simultaneous_prefetches; /* number of parallel prefetch 1886 operations. */ 1887 const int sfdf_convert; /* cost of SF->DF conversion. */ 1888}; 1889 1890extern const struct processor_costs *rs6000_cost; 1891 1892/* Control the assembler format that we output. */ 1893 1894/* A C string constant describing how to begin a comment in the target 1895 assembler language. The compiler assumes that the comment will end at 1896 the end of the line. */ 1897#define ASM_COMMENT_START " #" 1898 1899/* Flag to say the TOC is initialized */ 1900extern int toc_initialized; 1901 1902/* Macro to output a special constant pool entry. Go to WIN if we output 1903 it. Otherwise, it is written the usual way. 1904 1905 On the RS/6000, toc entries are handled this way. */ 1906 1907#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 1908{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 1909 { \ 1910 output_toc (FILE, X, LABELNO, MODE); \ 1911 goto WIN; \ 1912 } \ 1913} 1914 1915#ifdef HAVE_GAS_WEAK 1916#define RS6000_WEAK 1 1917#else 1918#define RS6000_WEAK 0 1919#endif 1920 1921#if RS6000_WEAK 1922/* Used in lieu of ASM_WEAKEN_LABEL. */ 1923#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 1924 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) 1925#endif 1926 1927#if HAVE_GAS_WEAKREF 1928#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 1929 do \ 1930 { \ 1931 fputs ("\t.weakref\t", (FILE)); \ 1932 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1933 fputs (", ", (FILE)); \ 1934 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1935 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1936 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1937 { \ 1938 fputs ("\n\t.weakref\t.", (FILE)); \ 1939 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1940 fputs (", .", (FILE)); \ 1941 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1942 } \ 1943 fputc ('\n', (FILE)); \ 1944 } while (0) 1945#endif 1946 1947/* This implements the `alias' attribute. */ 1948#undef ASM_OUTPUT_DEF_FROM_DECLS 1949#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 1950 do \ 1951 { \ 1952 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 1953 const char *name = IDENTIFIER_POINTER (TARGET); \ 1954 if (TREE_CODE (DECL) == FUNCTION_DECL \ 1955 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1956 { \ 1957 if (TREE_PUBLIC (DECL)) \ 1958 { \ 1959 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1960 { \ 1961 fputs ("\t.globl\t.", FILE); \ 1962 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1963 putc ('\n', FILE); \ 1964 } \ 1965 } \ 1966 else if (TARGET_XCOFF) \ 1967 { \ 1968 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1969 { \ 1970 fputs ("\t.lglobl\t.", FILE); \ 1971 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1972 putc ('\n', FILE); \ 1973 fputs ("\t.lglobl\t", FILE); \ 1974 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1975 putc ('\n', FILE); \ 1976 } \ 1977 } \ 1978 fputs ("\t.set\t.", FILE); \ 1979 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1980 fputs (",.", FILE); \ 1981 RS6000_OUTPUT_BASENAME (FILE, name); \ 1982 fputc ('\n', FILE); \ 1983 } \ 1984 ASM_OUTPUT_DEF (FILE, alias, name); \ 1985 } \ 1986 while (0) 1987 1988#define TARGET_ASM_FILE_START rs6000_file_start 1989 1990/* Output to assembler file text saying following lines 1991 may contain character constants, extra white space, comments, etc. */ 1992 1993#define ASM_APP_ON "" 1994 1995/* Output to assembler file text saying following lines 1996 no longer contain unusual constructs. */ 1997 1998#define ASM_APP_OFF "" 1999 2000/* How to refer to registers in assembler output. 2001 This sequence is indexed by compiler's hard-register-number (see above). */ 2002 2003extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2004 2005#define REGISTER_NAMES \ 2006{ \ 2007 &rs6000_reg_names[ 0][0], /* r0 */ \ 2008 &rs6000_reg_names[ 1][0], /* r1 */ \ 2009 &rs6000_reg_names[ 2][0], /* r2 */ \ 2010 &rs6000_reg_names[ 3][0], /* r3 */ \ 2011 &rs6000_reg_names[ 4][0], /* r4 */ \ 2012 &rs6000_reg_names[ 5][0], /* r5 */ \ 2013 &rs6000_reg_names[ 6][0], /* r6 */ \ 2014 &rs6000_reg_names[ 7][0], /* r7 */ \ 2015 &rs6000_reg_names[ 8][0], /* r8 */ \ 2016 &rs6000_reg_names[ 9][0], /* r9 */ \ 2017 &rs6000_reg_names[10][0], /* r10 */ \ 2018 &rs6000_reg_names[11][0], /* r11 */ \ 2019 &rs6000_reg_names[12][0], /* r12 */ \ 2020 &rs6000_reg_names[13][0], /* r13 */ \ 2021 &rs6000_reg_names[14][0], /* r14 */ \ 2022 &rs6000_reg_names[15][0], /* r15 */ \ 2023 &rs6000_reg_names[16][0], /* r16 */ \ 2024 &rs6000_reg_names[17][0], /* r17 */ \ 2025 &rs6000_reg_names[18][0], /* r18 */ \ 2026 &rs6000_reg_names[19][0], /* r19 */ \ 2027 &rs6000_reg_names[20][0], /* r20 */ \ 2028 &rs6000_reg_names[21][0], /* r21 */ \ 2029 &rs6000_reg_names[22][0], /* r22 */ \ 2030 &rs6000_reg_names[23][0], /* r23 */ \ 2031 &rs6000_reg_names[24][0], /* r24 */ \ 2032 &rs6000_reg_names[25][0], /* r25 */ \ 2033 &rs6000_reg_names[26][0], /* r26 */ \ 2034 &rs6000_reg_names[27][0], /* r27 */ \ 2035 &rs6000_reg_names[28][0], /* r28 */ \ 2036 &rs6000_reg_names[29][0], /* r29 */ \ 2037 &rs6000_reg_names[30][0], /* r30 */ \ 2038 &rs6000_reg_names[31][0], /* r31 */ \ 2039 \ 2040 &rs6000_reg_names[32][0], /* fr0 */ \ 2041 &rs6000_reg_names[33][0], /* fr1 */ \ 2042 &rs6000_reg_names[34][0], /* fr2 */ \ 2043 &rs6000_reg_names[35][0], /* fr3 */ \ 2044 &rs6000_reg_names[36][0], /* fr4 */ \ 2045 &rs6000_reg_names[37][0], /* fr5 */ \ 2046 &rs6000_reg_names[38][0], /* fr6 */ \ 2047 &rs6000_reg_names[39][0], /* fr7 */ \ 2048 &rs6000_reg_names[40][0], /* fr8 */ \ 2049 &rs6000_reg_names[41][0], /* fr9 */ \ 2050 &rs6000_reg_names[42][0], /* fr10 */ \ 2051 &rs6000_reg_names[43][0], /* fr11 */ \ 2052 &rs6000_reg_names[44][0], /* fr12 */ \ 2053 &rs6000_reg_names[45][0], /* fr13 */ \ 2054 &rs6000_reg_names[46][0], /* fr14 */ \ 2055 &rs6000_reg_names[47][0], /* fr15 */ \ 2056 &rs6000_reg_names[48][0], /* fr16 */ \ 2057 &rs6000_reg_names[49][0], /* fr17 */ \ 2058 &rs6000_reg_names[50][0], /* fr18 */ \ 2059 &rs6000_reg_names[51][0], /* fr19 */ \ 2060 &rs6000_reg_names[52][0], /* fr20 */ \ 2061 &rs6000_reg_names[53][0], /* fr21 */ \ 2062 &rs6000_reg_names[54][0], /* fr22 */ \ 2063 &rs6000_reg_names[55][0], /* fr23 */ \ 2064 &rs6000_reg_names[56][0], /* fr24 */ \ 2065 &rs6000_reg_names[57][0], /* fr25 */ \ 2066 &rs6000_reg_names[58][0], /* fr26 */ \ 2067 &rs6000_reg_names[59][0], /* fr27 */ \ 2068 &rs6000_reg_names[60][0], /* fr28 */ \ 2069 &rs6000_reg_names[61][0], /* fr29 */ \ 2070 &rs6000_reg_names[62][0], /* fr30 */ \ 2071 &rs6000_reg_names[63][0], /* fr31 */ \ 2072 \ 2073 &rs6000_reg_names[64][0], /* vr0 */ \ 2074 &rs6000_reg_names[65][0], /* vr1 */ \ 2075 &rs6000_reg_names[66][0], /* vr2 */ \ 2076 &rs6000_reg_names[67][0], /* vr3 */ \ 2077 &rs6000_reg_names[68][0], /* vr4 */ \ 2078 &rs6000_reg_names[69][0], /* vr5 */ \ 2079 &rs6000_reg_names[70][0], /* vr6 */ \ 2080 &rs6000_reg_names[71][0], /* vr7 */ \ 2081 &rs6000_reg_names[72][0], /* vr8 */ \ 2082 &rs6000_reg_names[73][0], /* vr9 */ \ 2083 &rs6000_reg_names[74][0], /* vr10 */ \ 2084 &rs6000_reg_names[75][0], /* vr11 */ \ 2085 &rs6000_reg_names[76][0], /* vr12 */ \ 2086 &rs6000_reg_names[77][0], /* vr13 */ \ 2087 &rs6000_reg_names[78][0], /* vr14 */ \ 2088 &rs6000_reg_names[79][0], /* vr15 */ \ 2089 &rs6000_reg_names[80][0], /* vr16 */ \ 2090 &rs6000_reg_names[81][0], /* vr17 */ \ 2091 &rs6000_reg_names[82][0], /* vr18 */ \ 2092 &rs6000_reg_names[83][0], /* vr19 */ \ 2093 &rs6000_reg_names[84][0], /* vr20 */ \ 2094 &rs6000_reg_names[85][0], /* vr21 */ \ 2095 &rs6000_reg_names[86][0], /* vr22 */ \ 2096 &rs6000_reg_names[87][0], /* vr23 */ \ 2097 &rs6000_reg_names[88][0], /* vr24 */ \ 2098 &rs6000_reg_names[89][0], /* vr25 */ \ 2099 &rs6000_reg_names[90][0], /* vr26 */ \ 2100 &rs6000_reg_names[91][0], /* vr27 */ \ 2101 &rs6000_reg_names[92][0], /* vr28 */ \ 2102 &rs6000_reg_names[93][0], /* vr29 */ \ 2103 &rs6000_reg_names[94][0], /* vr30 */ \ 2104 &rs6000_reg_names[95][0], /* vr31 */ \ 2105 \ 2106 &rs6000_reg_names[96][0], /* lr */ \ 2107 &rs6000_reg_names[97][0], /* ctr */ \ 2108 &rs6000_reg_names[98][0], /* ca */ \ 2109 &rs6000_reg_names[99][0], /* ap */ \ 2110 \ 2111 &rs6000_reg_names[100][0], /* cr0 */ \ 2112 &rs6000_reg_names[101][0], /* cr1 */ \ 2113 &rs6000_reg_names[102][0], /* cr2 */ \ 2114 &rs6000_reg_names[103][0], /* cr3 */ \ 2115 &rs6000_reg_names[104][0], /* cr4 */ \ 2116 &rs6000_reg_names[105][0], /* cr5 */ \ 2117 &rs6000_reg_names[106][0], /* cr6 */ \ 2118 &rs6000_reg_names[107][0], /* cr7 */ \ 2119 \ 2120 &rs6000_reg_names[108][0], /* vrsave */ \ 2121 &rs6000_reg_names[109][0], /* vscr */ \ 2122 \ 2123 &rs6000_reg_names[110][0] /* sfp */ \ 2124} 2125 2126/* Table of additional register names to use in user input. */ 2127 2128#define ADDITIONAL_REGISTER_NAMES \ 2129 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2130 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2131 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2132 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2133 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2134 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2135 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2136 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2137 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2138 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2139 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2140 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2141 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2142 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2143 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2144 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2145 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \ 2146 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \ 2147 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \ 2148 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \ 2149 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \ 2150 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \ 2151 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \ 2152 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \ 2153 {"vrsave", 108}, {"vscr", 109}, \ 2154 /* no additional names for: lr, ctr, ap */ \ 2155 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \ 2156 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \ 2157 {"cc", 100},{"sp", 1}, {"toc", 2}, \ 2158 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2159 {"xer", 98}, \ 2160 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2161 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2162 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2163 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2164 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2165 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2166 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2167 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2168 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2169 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \ 2170 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \ 2171 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \ 2172 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \ 2173 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \ 2174 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ 2175 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ 2176 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ 2177} 2178 2179/* This is how to output an element of a case-vector that is relative. */ 2180 2181#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2182 do { char buf[100]; \ 2183 fputs ("\t.long ", FILE); \ 2184 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2185 assemble_name (FILE, buf); \ 2186 putc ('-', FILE); \ 2187 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2188 assemble_name (FILE, buf); \ 2189 putc ('\n', FILE); \ 2190 } while (0) 2191 2192/* This is how to output an element of a case-vector 2193 that is non-relative. */ 2194#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2195 rs6000_output_addr_vec_elt ((FILE), (VALUE)) 2196 2197/* This is how to output an assembler line 2198 that says to advance the location counter 2199 to a multiple of 2**LOG bytes. */ 2200 2201#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2202 if ((LOG) != 0) \ 2203 fprintf (FILE, "\t.align %d\n", (LOG)) 2204 2205/* How to align the given loop. */ 2206#define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2207 2208/* Alignment guaranteed by __builtin_malloc. */ 2209/* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. 2210 However, specifying the stronger guarantee currently leads to 2211 a regression in SPEC CPU2006 437.leslie3d. The stronger 2212 guarantee should be implemented here once that's fixed. */ 2213#define MALLOC_ABI_ALIGNMENT (64) 2214 2215/* Pick up the return address upon entry to a procedure. Used for 2216 dwarf2 unwind information. This also enables the table driven 2217 mechanism. */ 2218 2219#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2220#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2221 2222/* Describe how we implement __builtin_eh_return. */ 2223#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2224#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2225 2226/* Print operand X (an rtx) in assembler syntax to file FILE. 2227 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2228 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2229 2230#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2231 2232/* Define which CODE values are valid. */ 2233 2234#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2235 2236/* Print a memory address as an operand to reference that memory location. */ 2237 2238#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2239 2240/* For switching between functions with different target attributes. */ 2241#define SWITCHABLE_TARGET 1 2242 2243/* uncomment for disabling the corresponding default options */ 2244/* #define MACHINE_no_sched_interblock */ 2245/* #define MACHINE_no_sched_speculative */ 2246/* #define MACHINE_no_sched_speculative_load */ 2247 2248/* General flags. */ 2249extern int frame_pointer_needed; 2250 2251/* Classification of the builtin functions as to which switches enable the 2252 builtin, and what attributes it should have. We used to use the target 2253 flags macros, but we've run out of bits, so we now map the options into new 2254 settings used here. */ 2255 2256/* Builtin operand count. */ 2257#define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2258#define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2259#define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2260#define RS6000_BTC_QUATERNARY 0x00000004 /* normal quaternary 2261 function. */ 2262#define RS6000_BTC_QUINARY 0x00000005 /* normal quinary function. */ 2263#define RS6000_BTC_SENARY 0x00000006 /* normal senary function. */ 2264#define RS6000_BTC_OPND_MASK 0x00000007 /* Mask to isolate operands. */ 2265 2266/* Builtin attributes. */ 2267#define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2268#define RS6000_BTC_PREDICATE 0x00000008 /* predicate function. */ 2269#define RS6000_BTC_ABS 0x00000010 /* Altivec/VSX ABS 2270 function. */ 2271#define RS6000_BTC_DST 0x00000020 /* Altivec DST function. */ 2272 2273#define RS6000_BTC_TYPE_MASK 0x0000003f /* Mask to isolate types */ 2274 2275#define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2276#define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor 2277 modifies global state. */ 2278#define RS6000_BTC_PURE 0x00000200 /* reads global 2279 state/mem and does 2280 not modify global state. */ 2281#define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2282#define RS6000_BTC_QUAD 0x00000800 /* Uses a register quad. */ 2283#define RS6000_BTC_PAIR 0x00001000 /* Uses a register pair. */ 2284#define RS6000_BTC_QUADPAIR 0x00001800 /* Uses a quad and a pair. */ 2285#define RS6000_BTC_ATTR_MASK 0x00001f00 /* Mask of the attributes. */ 2286 2287/* Miscellaneous information. */ 2288#define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ 2289#define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ 2290#define RS6000_BTC_CR 0x04000000 /* function references a CR. */ 2291#define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ 2292#define RS6000_BTC_GIMPLE 0x10000000 /* function should be expanded 2293 into gimple. */ 2294#define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ 2295 2296/* Convenience macros to document the instruction type. */ 2297#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2298#define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2299 2300/* Builtin targets. For now, we reuse the masks for those options that are in 2301 target flags, and pick a random bit for ldbl128, which isn't in 2302 target_flags. */ 2303#define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2304#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2305#define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ 2306#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2307#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2308#define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ 2309#define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ 2310#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2311#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2312#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2313#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2314#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2315#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2316#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2317#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2318#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2319#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2320#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2321#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ 2322#define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ 2323#define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ 2324#define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ 2325#define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ 2326#define RS6000_BTM_P10 MASK_POWER10 2327 2328#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2329 | RS6000_BTM_VSX \ 2330 | RS6000_BTM_P8_VECTOR \ 2331 | RS6000_BTM_P9_VECTOR \ 2332 | RS6000_BTM_P9_MISC \ 2333 | RS6000_BTM_MODULO \ 2334 | RS6000_BTM_CRYPTO \ 2335 | RS6000_BTM_FRE \ 2336 | RS6000_BTM_FRES \ 2337 | RS6000_BTM_FRSQRTE \ 2338 | RS6000_BTM_FRSQRTES \ 2339 | RS6000_BTM_HTM \ 2340 | RS6000_BTM_POPCNTD \ 2341 | RS6000_BTM_CELL \ 2342 | RS6000_BTM_DFP \ 2343 | RS6000_BTM_HARD_FLOAT \ 2344 | RS6000_BTM_LDBL128 \ 2345 | RS6000_BTM_POWERPC64 \ 2346 | RS6000_BTM_FLOAT128 \ 2347 | RS6000_BTM_FLOAT128_HW \ 2348 | RS6000_BTM_MMA \ 2349 | RS6000_BTM_P10) 2350 2351enum rs6000_builtin_type_index 2352{ 2353 RS6000_BTI_NOT_OPAQUE, 2354 RS6000_BTI_opaque_V4SI, 2355 RS6000_BTI_V16QI, /* __vector signed char */ 2356 RS6000_BTI_V1TI, 2357 RS6000_BTI_V2DI, 2358 RS6000_BTI_V2DF, 2359 RS6000_BTI_V4HI, 2360 RS6000_BTI_V4SI, 2361 RS6000_BTI_V4SF, 2362 RS6000_BTI_V8HI, 2363 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ 2364 RS6000_BTI_unsigned_V1TI, 2365 RS6000_BTI_unsigned_V8HI, 2366 RS6000_BTI_unsigned_V4SI, 2367 RS6000_BTI_unsigned_V2DI, 2368 RS6000_BTI_bool_char, /* __bool char */ 2369 RS6000_BTI_bool_short, /* __bool short */ 2370 RS6000_BTI_bool_int, /* __bool int */ 2371 RS6000_BTI_bool_long_long, /* __bool long long */ 2372 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 2373 channels of 1, 5, 5, and 5 bits 2374 respectively as packed with the 2375 vpkpx insn. __pixel is only 2376 meaningful as a vector type. 2377 There is no corresponding scalar 2378 __pixel data type.) */ 2379 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2380 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2381 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2382 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2383 RS6000_BTI_bool_V1TI, /* __vector __bool 128-bit */ 2384 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2385 RS6000_BTI_long, /* long_integer_type_node */ 2386 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2387 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2388 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2389 RS6000_BTI_INTQI, /* (signed) intQI_type_node */ 2390 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2391 RS6000_BTI_INTHI, /* intHI_type_node */ 2392 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2393 RS6000_BTI_INTSI, /* intSI_type_node (signed) */ 2394 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2395 RS6000_BTI_INTDI, /* intDI_type_node */ 2396 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2397 RS6000_BTI_INTTI, /* intTI_type_node */ 2398 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2399 RS6000_BTI_float, /* float_type_node */ 2400 RS6000_BTI_double, /* double_type_node */ 2401 RS6000_BTI_long_double, /* long_double_type_node */ 2402 RS6000_BTI_dfloat64, /* dfloat64_type_node */ 2403 RS6000_BTI_dfloat128, /* dfloat128_type_node */ 2404 RS6000_BTI_void, /* void_type_node */ 2405 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ 2406 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ 2407 RS6000_BTI_const_str, /* pointer to const char * */ 2408 RS6000_BTI_vector_pair, /* unsigned 256-bit types (vector pair). */ 2409 RS6000_BTI_vector_quad, /* unsigned 512-bit types (vector quad). */ 2410 RS6000_BTI_const_ptr_void, /* const pointer to void */ 2411 RS6000_BTI_ptr_V16QI, 2412 RS6000_BTI_ptr_V1TI, 2413 RS6000_BTI_ptr_V2DI, 2414 RS6000_BTI_ptr_V2DF, 2415 RS6000_BTI_ptr_V4SI, 2416 RS6000_BTI_ptr_V4SF, 2417 RS6000_BTI_ptr_V8HI, 2418 RS6000_BTI_ptr_unsigned_V16QI, 2419 RS6000_BTI_ptr_unsigned_V1TI, 2420 RS6000_BTI_ptr_unsigned_V8HI, 2421 RS6000_BTI_ptr_unsigned_V4SI, 2422 RS6000_BTI_ptr_unsigned_V2DI, 2423 RS6000_BTI_ptr_bool_V16QI, 2424 RS6000_BTI_ptr_bool_V8HI, 2425 RS6000_BTI_ptr_bool_V4SI, 2426 RS6000_BTI_ptr_bool_V2DI, 2427 RS6000_BTI_ptr_bool_V1TI, 2428 RS6000_BTI_ptr_pixel_V8HI, 2429 RS6000_BTI_ptr_INTQI, 2430 RS6000_BTI_ptr_UINTQI, 2431 RS6000_BTI_ptr_INTHI, 2432 RS6000_BTI_ptr_UINTHI, 2433 RS6000_BTI_ptr_INTSI, 2434 RS6000_BTI_ptr_UINTSI, 2435 RS6000_BTI_ptr_INTDI, 2436 RS6000_BTI_ptr_UINTDI, 2437 RS6000_BTI_ptr_INTTI, 2438 RS6000_BTI_ptr_UINTTI, 2439 RS6000_BTI_ptr_long_integer, 2440 RS6000_BTI_ptr_long_unsigned, 2441 RS6000_BTI_ptr_float, 2442 RS6000_BTI_ptr_double, 2443 RS6000_BTI_ptr_long_double, 2444 RS6000_BTI_ptr_dfloat64, 2445 RS6000_BTI_ptr_dfloat128, 2446 RS6000_BTI_ptr_vector_pair, 2447 RS6000_BTI_ptr_vector_quad, 2448 RS6000_BTI_ptr_long_long, 2449 RS6000_BTI_ptr_long_long_unsigned, 2450 RS6000_BTI_MAX 2451}; 2452 2453 2454#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2455#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2456#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2457#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2458#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2459#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2460#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2461#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2462#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2463#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2464#define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) 2465#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2466#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2467#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2468#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2469#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2470#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2471#define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) 2472#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2473#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2474#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2475#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2476#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2477#define bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V1TI]) 2478#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2479 2480#define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2481#define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2482#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2483#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2484#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2485#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2486#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2487#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2488#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2489#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2490#define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2491#define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2492#define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) 2493#define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) 2494#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2495#define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2496#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) 2497#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) 2498#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) 2499#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2500#define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) 2501#define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) 2502#define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) 2503#define vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_vector_pair]) 2504#define vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_vector_quad]) 2505#define pcvoid_type_node (rs6000_builtin_types[RS6000_BTI_const_ptr_void]) 2506#define ptr_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V16QI]) 2507#define ptr_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V1TI]) 2508#define ptr_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DI]) 2509#define ptr_V2DF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DF]) 2510#define ptr_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SI]) 2511#define ptr_V4SF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SF]) 2512#define ptr_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V8HI]) 2513#define ptr_unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V16QI]) 2514#define ptr_unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V1TI]) 2515#define ptr_unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V8HI]) 2516#define ptr_unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V4SI]) 2517#define ptr_unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V2DI]) 2518#define ptr_bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V16QI]) 2519#define ptr_bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V8HI]) 2520#define ptr_bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V4SI]) 2521#define ptr_bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V2DI]) 2522#define ptr_bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V1TI]) 2523#define ptr_pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_pixel_V8HI]) 2524#define ptr_intQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTQI]) 2525#define ptr_uintQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTQI]) 2526#define ptr_intHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTHI]) 2527#define ptr_uintHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTHI]) 2528#define ptr_intSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTSI]) 2529#define ptr_uintSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTSI]) 2530#define ptr_intDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTDI]) 2531#define ptr_uintDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTDI]) 2532#define ptr_intTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTTI]) 2533#define ptr_uintTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTTI]) 2534#define ptr_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_integer]) 2535#define ptr_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_unsigned]) 2536#define ptr_float_type_node (rs6000_builtin_types[RS6000_BTI_ptr_float]) 2537#define ptr_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_double]) 2538#define ptr_long_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_double]) 2539#define ptr_dfloat64_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat64]) 2540#define ptr_dfloat128_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat128]) 2541#define ptr_vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_pair]) 2542#define ptr_vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_quad]) 2543#define ptr_long_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long]) 2544#define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned]) 2545 2546extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2547 2548#ifndef USED_FOR_TARGET 2549extern GTY(()) tree altivec_builtin_mask_for_load; 2550extern GTY(()) section *toc_section; 2551 2552/* A C structure for machine-specific, per-function data. 2553 This is added to the cfun structure. */ 2554typedef struct GTY(()) machine_function 2555{ 2556 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ 2557 int ra_needs_full_frame; 2558 /* Flags if __builtin_return_address (0) was used. */ 2559 int ra_need_lr; 2560 /* Cache lr_save_p after expansion of builtin_eh_return. */ 2561 int lr_save_state; 2562 /* Whether we need to save the TOC to the reserved stack location in the 2563 function prologue. */ 2564 bool save_toc_in_prologue; 2565 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 2566 varargs save area. */ 2567 HOST_WIDE_INT varargs_save_offset; 2568 /* Alternative internal arg pointer for -fsplit-stack. */ 2569 rtx split_stack_arg_pointer; 2570 bool split_stack_argp_used; 2571 /* Flag if r2 setup is needed with ELFv2 ABI. */ 2572 bool r2_setup_needed; 2573 /* The number of components we use for separate shrink-wrapping. */ 2574 int n_components; 2575 /* The components already handled by separate shrink-wrapping, which should 2576 not be considered by the prologue and epilogue. */ 2577 bool gpr_is_wrapped_separately[32]; 2578 bool fpr_is_wrapped_separately[32]; 2579 bool lr_is_wrapped_separately; 2580 bool toc_is_wrapped_separately; 2581 bool mma_return_type_error; 2582} machine_function; 2583#endif 2584 2585 2586#define TARGET_SUPPORTS_WIDE_INT 1 2587 2588#if (GCC_VERSION >= 3000) 2589#pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 2590#endif 2591 2592/* Whether a given VALUE is a valid 16 or 34-bit signed integer. */ 2593#define SIGNED_INTEGER_NBIT_P(VALUE, N) \ 2594 IN_RANGE ((VALUE), \ 2595 -(HOST_WIDE_INT_1 << ((N)-1)), \ 2596 (HOST_WIDE_INT_1 << ((N)-1)) - 1) 2597 2598#define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) 2599#define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) 2600 2601/* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra 2602 argument that gives a length to validate a range of addresses, to allow for 2603 splitting insns into several insns, each of which has an offsettable 2604 address. */ 2605#define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2606 IN_RANGE ((VALUE), \ 2607 -(HOST_WIDE_INT_1 << 15), \ 2608 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA)) 2609 2610#define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2611 IN_RANGE ((VALUE), \ 2612 -(HOST_WIDE_INT_1 << 33), \ 2613 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA)) 2614 2615/* Define this if some processing needs to be done before outputting the 2616 assembler code. On the PowerPC, we remember if the current insn is a normal 2617 prefixed insn where we need to emit a 'p' before the insn. */ 2618#define FINAL_PRESCAN_INSN(INSN, OPERANDS, NOPERANDS) \ 2619do \ 2620 { \ 2621 if (TARGET_PREFIXED) \ 2622 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS); \ 2623 } \ 2624while (0) 2625 2626/* Do anything special before emitting an opcode. We use it to emit a 'p' for 2627 prefixed insns that is set in FINAL_PRESCAN_INSN. */ 2628#define ASM_OUTPUT_OPCODE(STREAM, OPCODE) \ 2629 do \ 2630 { \ 2631 if (TARGET_PREFIXED) \ 2632 rs6000_asm_output_opcode (STREAM); \ 2633 } \ 2634 while (0) 2635