1; Options for the RISC-V port of the compiler 2; 3; Copyright (C) 2011-2022 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT 13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15; License for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21HeaderInclude 22config/riscv/riscv-opts.h 23 24mbig-endian 25Target RejectNegative Mask(BIG_ENDIAN) 26Assume target CPU is configured as big endian. 27 28mlittle-endian 29Target RejectNegative InverseMask(BIG_ENDIAN) 30Assume target CPU is configured as little endian. 31 32mbranch-cost= 33Target RejectNegative Joined UInteger Var(riscv_branch_cost) 34-mbranch-cost=N Set the cost of branches to roughly N instructions. 35 36mplt 37Target Var(TARGET_PLT) Init(1) 38When generating -fpic code, allow the use of PLTs. Ignored for fno-pic. 39 40mabi= 41Target RejectNegative Joined Enum(abi_type) Var(riscv_abi) Init(ABI_ILP32) Negative(mabi=) 42Specify integer and floating-point calling convention. 43 44mpreferred-stack-boundary= 45Target RejectNegative Joined UInteger Var(riscv_preferred_stack_boundary_arg) 46Attempt to keep stack aligned to this power of 2. 47 48Enum 49Name(abi_type) Type(enum riscv_abi_type) 50Supported ABIs (for use with the -mabi= option): 51 52EnumValue 53Enum(abi_type) String(ilp32) Value(ABI_ILP32) 54 55EnumValue 56Enum(abi_type) String(ilp32e) Value(ABI_ILP32E) 57 58EnumValue 59Enum(abi_type) String(ilp32f) Value(ABI_ILP32F) 60 61EnumValue 62Enum(abi_type) String(ilp32d) Value(ABI_ILP32D) 63 64EnumValue 65Enum(abi_type) String(lp64) Value(ABI_LP64) 66 67EnumValue 68Enum(abi_type) String(lp64f) Value(ABI_LP64F) 69 70EnumValue 71Enum(abi_type) String(lp64d) Value(ABI_LP64D) 72 73mfdiv 74Target Mask(FDIV) 75Use hardware floating-point divide and square root instructions. 76 77mdiv 78Target Mask(DIV) 79Use hardware instructions for integer division. 80 81march= 82Target RejectNegative Joined Negative(march=) 83-march= Generate code for given RISC-V ISA (e.g. RV64IM). ISA strings must be 84lower-case. 85 86mtune= 87Target RejectNegative Joined Var(riscv_tune_string) 88-mtune=PROCESSOR Optimize the output for PROCESSOR. 89 90mcpu= 91Target RejectNegative Joined Var(riscv_cpu_string) 92-mcpu=PROCESSOR Use architecture of and optimize the output for PROCESSOR. 93 94msmall-data-limit= 95Target Joined Separate UInteger Var(g_switch_value) Init(8) 96-msmall-data-limit=N Put global and static data smaller than <number> bytes into a special section (on some targets). 97 98msave-restore 99Target Mask(SAVE_RESTORE) 100Use smaller but slower prologue and epilogue code. 101 102mshorten-memrefs 103Target Bool Var(riscv_mshorten_memrefs) Init(1) 104Convert BASE + LARGE_OFFSET addresses to NEW_BASE + SMALL_OFFSET to allow more 105memory accesses to be generated as compressed instructions. Currently targets 10632-bit integer load/stores. 107 108mcmodel= 109Target RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) 110Specify the code model. 111 112mstrict-align 113Target Mask(STRICT_ALIGN) Save 114Do not generate unaligned memory accesses. 115 116Enum 117Name(code_model) Type(enum riscv_code_model) 118Known code models (for use with the -mcmodel= option): 119 120EnumValue 121Enum(code_model) String(medlow) Value(CM_MEDLOW) 122 123EnumValue 124Enum(code_model) String(medany) Value(CM_MEDANY) 125 126mexplicit-relocs 127Target Mask(EXPLICIT_RELOCS) 128Use %reloc() operators, rather than assembly macros, to load addresses. 129 130mrelax 131Target Bool Var(riscv_mrelax) Init(1) 132Take advantage of linker relaxations to reduce the number of instructions 133required to materialize symbol addresses. 134 135Mask(64BIT) 136 137Mask(MUL) 138 139Mask(ATOMIC) 140 141Mask(HARD_FLOAT) 142 143Mask(DOUBLE_FLOAT) 144 145Mask(RVC) 146 147Mask(RVE) 148 149Mask(VECTOR) 150 151mriscv-attribute 152Target Var(riscv_emit_attribute_p) Init(-1) 153Emit RISC-V ELF attribute. 154 155malign-data= 156Target RejectNegative Joined Var(riscv_align_data_type) Enum(riscv_align_data) Init(riscv_align_data_type_xlen) 157Use the given data alignment. 158 159Enum 160Name(riscv_align_data) Type(enum riscv_align_data) 161Known data alignment choices (for use with the -malign-data= option): 162 163EnumValue 164Enum(riscv_align_data) String(xlen) Value(riscv_align_data_type_xlen) 165 166EnumValue 167Enum(riscv_align_data) String(natural) Value(riscv_align_data_type_natural) 168 169mstack-protector-guard= 170Target RejectNegative Joined Enum(stack_protector_guard) Var(riscv_stack_protector_guard) Init(SSP_GLOBAL) 171Use given stack-protector guard. 172 173Enum 174Name(stack_protector_guard) Type(enum stack_protector_guard) 175Valid arguments to -mstack-protector-guard=: 176 177EnumValue 178Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 179 180EnumValue 181Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 182 183mstack-protector-guard-reg= 184Target RejectNegative Joined Var(riscv_stack_protector_guard_reg_str) 185Use the given base register for addressing the stack-protector guard. 186 187TargetVariable 188int riscv_stack_protector_guard_reg = 0 189 190mstack-protector-guard-offset= 191Target RejectNegative Joined Integer Var(riscv_stack_protector_guard_offset_str) 192Use the given offset for addressing the stack-protector guard. 193 194TargetVariable 195long riscv_stack_protector_guard_offset = 0 196 197TargetVariable 198int riscv_zi_subext 199 200TargetVariable 201int riscv_zb_subext 202 203TargetVariable 204int riscv_zk_subext 205 206TargetVariable 207int riscv_vector_elen_flags 208 209TargetVariable 210int riscv_zvl_flags 211 212Enum 213Name(isa_spec_class) Type(enum riscv_isa_spec_class) 214Supported ISA specs (for use with the -misa-spec= option): 215 216EnumValue 217Enum(isa_spec_class) String(2.2) Value(ISA_SPEC_CLASS_2P2) 218 219EnumValue 220Enum(isa_spec_class) String(20190608) Value(ISA_SPEC_CLASS_20190608) 221 222EnumValue 223Enum(isa_spec_class) String(20191213) Value(ISA_SPEC_CLASS_20191213) 224 225misa-spec= 226Target RejectNegative Joined Enum(isa_spec_class) Var(riscv_isa_spec) Init(TARGET_DEFAULT_ISA_SPEC) 227Set the version of RISC-V ISA spec. 228