1;; Machine description for AArch64 architecture. 2;; Copyright (C) 2009-2022 Free Software Foundation, Inc. 3;; Contributed by ARM Ltd. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but 13;; WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15;; General Public License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_register_constraint "k" "STACK_REG" 22 "@internal The stack register.") 23 24(define_register_constraint "Ucs" "TAILCALL_ADDR_REGS" 25 "@internal Registers suitable for an indirect tail call") 26 27(define_register_constraint "Ucr" 28 "aarch64_harden_sls_blr_p () ? STUB_REGS : GENERAL_REGS" 29 "@internal Registers to be used for an indirect call. 30 This is usually the general registers, but when we are hardening against 31 Straight Line Speculation we disallow x16, x17, and x30 so we can use 32 indirection stubs. These indirection stubs cannot use the above registers 33 since they will be reached by a BL that may have to go through a linker 34 veneer.") 35 36(define_register_constraint "w" "FP_REGS" 37 "Floating point and SIMD vector registers.") 38 39(define_register_constraint "Upa" "PR_REGS" 40 "SVE predicate registers p0 - p15.") 41 42(define_register_constraint "Upl" "PR_LO_REGS" 43 "SVE predicate registers p0 - p7.") 44 45(define_register_constraint "x" "FP_LO_REGS" 46 "Floating point and SIMD vector registers V0 - V15.") 47 48(define_register_constraint "y" "FP_LO8_REGS" 49 "Floating point and SIMD vector registers V0 - V7.") 50 51(define_constraint "c" 52 "@internal The condition code register." 53 (match_operand 0 "cc_register")) 54 55(define_constraint "I" 56 "A constant that can be used with an ADD operation." 57 (and (match_code "const_int") 58 (match_test "aarch64_uimm12_shift (ival)"))) 59 60(define_constraint "Uaa" 61 "@internal A constant that matches two uses of add instructions." 62 (and (match_code "const_int") 63 (match_test "aarch64_pluslong_strict_immedate (op, VOIDmode)"))) 64 65(define_constraint "Uai" 66 "@internal 67 A constraint that matches a VG-based constant that can be added by 68 a single INC or DEC." 69 (match_operand 0 "aarch64_sve_scalar_inc_dec_immediate")) 70 71(define_constraint "Uav" 72 "@internal 73 A constraint that matches a VG-based constant that can be added by 74 a single ADDVL or ADDPL." 75 (match_operand 0 "aarch64_sve_addvl_addpl_immediate")) 76 77(define_constraint "Uat" 78 "@internal 79 A constraint that matches a VG-based constant that can be added by 80 using multiple instructions, with one temporary register." 81 (match_operand 0 "aarch64_split_add_offset_immediate")) 82 83(define_constraint "J" 84 "A constant that can be used with a SUB operation (once negated)." 85 (and (match_code "const_int") 86 (match_test "aarch64_uimm12_shift (-ival)"))) 87 88;; We can't use the mode of a CONST_INT to determine the context in 89;; which it is being used, so we must have a separate constraint for 90;; each context. 91 92(define_constraint "K" 93 "A constant that can be used with a 32-bit logical operation." 94 (and (match_code "const_int") 95 (match_test "aarch64_bitmask_imm (ival, SImode)"))) 96 97(define_constraint "L" 98 "A constant that can be used with a 64-bit logical operation." 99 (and (match_code "const_int") 100 (match_test "aarch64_bitmask_imm (ival, DImode)"))) 101 102(define_constraint "M" 103 "A constant that can be used with a 32-bit MOV immediate operation." 104 (and (match_code "const_int") 105 (match_test "aarch64_move_imm (ival, SImode)"))) 106 107(define_constraint "N" 108 "A constant that can be used with a 64-bit MOV immediate operation." 109 (and (match_code "const_int") 110 (match_test "aarch64_move_imm (ival, DImode)"))) 111 112(define_constraint "Uti" 113 "A constant that can be used with a 128-bit MOV immediate operation." 114 (and (ior (match_code "const_int") 115 (match_code "const_wide_int")) 116 (match_test "aarch64_mov128_immediate (op)"))) 117 118(define_constraint "UsO" 119 "A constant that can be used with a 32-bit and operation." 120 (and (match_code "const_int") 121 (match_test "aarch64_and_bitmask_imm (ival, SImode)"))) 122 123(define_constraint "UsP" 124 "A constant that can be used with a 64-bit and operation." 125 (and (match_code "const_int") 126 (match_test "aarch64_and_bitmask_imm (ival, DImode)"))) 127 128(define_constraint "S" 129 "A constraint that matches an absolute symbolic address." 130 (and (match_code "const,symbol_ref,label_ref") 131 (match_test "aarch64_symbolic_address_p (op)"))) 132 133(define_constraint "Y" 134 "Floating point constant zero." 135 (and (match_code "const_double") 136 (match_test "aarch64_float_const_zero_rtx_p (op)"))) 137 138(define_constraint "Z" 139 "Integer or floating-point constant zero." 140 (match_test "op == CONST0_RTX (GET_MODE (op))")) 141 142(define_constraint "Ush" 143 "A constraint that matches an absolute symbolic address high part." 144 (and (match_code "high") 145 (match_test "aarch64_valid_symref (XEXP (op, 0), GET_MODE (XEXP (op, 0)))"))) 146 147(define_constraint "Usa" 148 "@internal 149 A constraint that matches an absolute symbolic address that can be 150 loaded by a single ADR." 151 (and (match_code "const,symbol_ref,label_ref") 152 (match_test "aarch64_symbolic_address_p (op)") 153 (match_test "aarch64_mov_operand_p (op, GET_MODE (op))"))) 154 155;; const is needed here to support UNSPEC_SALT_ADDR. 156(define_constraint "Usw" 157 "@internal 158 A constraint that matches a small GOT access." 159 (and (match_code "const,symbol_ref") 160 (match_test "aarch64_classify_symbolic_expression (op) 161 == SYMBOL_SMALL_GOT_4G"))) 162 163(define_constraint "Uss" 164 "@internal 165 A constraint that matches an immediate shift constant in SImode." 166 (and (match_code "const_int") 167 (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) 168 169(define_constraint "Usn" 170 "A constant that can be used with a CCMN operation (once negated)." 171 (and (match_code "const_int") 172 (match_test "IN_RANGE (ival, -31, 0)"))) 173 174(define_constraint "Usd" 175 "@internal 176 A constraint that matches an immediate shift constant in DImode." 177 (and (match_code "const_int") 178 (match_test "(unsigned HOST_WIDE_INT) ival < 64"))) 179 180(define_constraint "Usf" 181 "@internal Usf is a symbol reference under the context where plt stub allowed." 182 (and (match_code "symbol_ref") 183 (match_test "!(aarch64_is_noplt_call_p (op) 184 || aarch64_is_long_call_p (op))"))) 185 186(define_constraint "Usg" 187 "@internal 188 A constraint that matches an immediate right shift constant in SImode 189 suitable for a SISD instruction." 190 (and (match_code "const_int") 191 (match_test "IN_RANGE (ival, 1, 31)"))) 192 193(define_constraint "Usj" 194 "@internal 195 A constraint that matches an immediate right shift constant in DImode 196 suitable for a SISD instruction." 197 (and (match_code "const_int") 198 (match_test "IN_RANGE (ival, 1, 63)"))) 199 200(define_constraint "UsM" 201 "@internal 202 A constraint that matches the immediate constant -1." 203 (match_test "op == constm1_rtx")) 204 205(define_constraint "Ulc" 206 "@internal 207 A constraint that matches a constant integer whose bits are consecutive ones 208 from the MSB." 209 (and (match_code "const_int") 210 (match_test "aarch64_high_bits_all_ones_p (ival)"))) 211 212(define_constraint "Usv" 213 "@internal 214 A constraint that matches a VG-based constant that can be loaded by 215 a single CNT[BHWD]." 216 (match_operand 0 "aarch64_sve_cnt_immediate")) 217 218(define_constraint "Usi" 219 "@internal 220 A constraint that matches an immediate operand valid for 221 the SVE INDEX instruction." 222 (match_operand 0 "aarch64_sve_index_immediate")) 223 224(define_constraint "Ui1" 225 "@internal 226 A constraint that matches the immediate constant +1." 227 (match_test "op == const1_rtx")) 228 229(define_constraint "Ui2" 230 "@internal 231 A constraint that matches the integers 0...3." 232 (and (match_code "const_int") 233 (match_test "(unsigned HOST_WIDE_INT) ival <= 3"))) 234 235(define_constraint "Ui3" 236 "@internal 237 A constraint that matches the integers 0...4." 238 (and (match_code "const_int") 239 (match_test "(unsigned HOST_WIDE_INT) ival <= 4"))) 240 241(define_constraint "Ui7" 242 "@internal 243 A constraint that matches the integers 0...7." 244 (and (match_code "const_int") 245 (match_test "(unsigned HOST_WIDE_INT) ival <= 7"))) 246 247(define_constraint "Up3" 248 "@internal 249 A constraint that matches the integers 2^(0...4)." 250 (and (match_code "const_int") 251 (match_test "(unsigned) exact_log2 (ival) <= 4"))) 252 253(define_constraint "Uph" 254 "@internal 255 A constraint that matches HImode integers zero extendable to 256 SImode plus_operand." 257 (and (match_code "const_int") 258 (match_test "aarch64_plushi_immediate (op, VOIDmode)"))) 259 260(define_memory_constraint "Q" 261 "A memory address which uses a single base register with no offset." 262 (and (match_code "mem") 263 (match_test "REG_P (XEXP (op, 0))"))) 264 265(define_memory_constraint "Ust" 266 "@internal 267 A memory address with 9bit unscaled offset." 268 (match_operand 0 "aarch64_9bit_offset_memory_operand")) 269 270(define_memory_constraint "Ump" 271 "@internal 272 A memory address suitable for a load/store pair operation." 273 (and (match_code "mem") 274 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 275 true, ADDR_QUERY_LDP_STP)"))) 276 277;; Used for storing or loading pairs in an AdvSIMD register using an STP/LDP 278;; as a vector-concat. The address mode uses the same constraints as if it 279;; were for a single value. 280(define_memory_constraint "Umn" 281 "@internal 282 A memory address suitable for a load/store pair operation." 283 (and (match_code "mem") 284 (match_test "aarch64_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 285 true, 286 ADDR_QUERY_LDP_STP_N)"))) 287 288(define_address_constraint "UPb" 289 "@internal 290 An address valid for SVE PRFB instructions." 291 (match_test "aarch64_sve_prefetch_operand_p (op, VNx16QImode)")) 292 293(define_address_constraint "UPd" 294 "@internal 295 An address valid for SVE PRFD instructions." 296 (match_test "aarch64_sve_prefetch_operand_p (op, VNx2DImode)")) 297 298(define_address_constraint "UPh" 299 "@internal 300 An address valid for SVE PRFH instructions." 301 (match_test "aarch64_sve_prefetch_operand_p (op, VNx8HImode)")) 302 303(define_address_constraint "UPw" 304 "@internal 305 An address valid for SVE PRFW instructions." 306 (match_test "aarch64_sve_prefetch_operand_p (op, VNx4SImode)")) 307 308(define_memory_constraint "Utf" 309 "@internal 310 An address valid for SVE LDFF1 instructions." 311 (and (match_code "mem") 312 (match_test "aarch64_sve_ldff1_operand_p (op)"))) 313 314(define_memory_constraint "Utn" 315 "@internal 316 An address valid for SVE LDNF1 instructions." 317 (and (match_code "mem") 318 (match_test "aarch64_sve_ldnf1_operand_p (op)"))) 319 320(define_memory_constraint "Utr" 321 "@internal 322 An address valid for SVE LDR and STR instructions (as distinct from 323 LD[1234] and ST[1234] patterns)." 324 (and (match_code "mem") 325 (match_test "aarch64_sve_ldr_operand_p (op)"))) 326 327(define_memory_constraint "Utv" 328 "@internal 329 An address valid for loading/storing opaque structure 330 types wider than TImode." 331 (and (match_code "mem") 332 (match_test "aarch64_simd_mem_operand_p (op)"))) 333 334(define_relaxed_memory_constraint "Utq" 335 "@internal 336 An address valid for loading or storing a 128-bit AdvSIMD register" 337 (and (match_code "mem") 338 (match_test "aarch64_legitimate_address_p (GET_MODE (op), 339 XEXP (op, 0), 1)") 340 (match_test "aarch64_legitimate_address_p (V2DImode, 341 XEXP (op, 0), 1)"))) 342 343(define_relaxed_memory_constraint "UtQ" 344 "@internal 345 An address valid for SVE LD1RQs." 346 (and (match_code "mem") 347 (match_test "aarch64_sve_ld1rq_operand_p (op)"))) 348 349(define_relaxed_memory_constraint "UOb" 350 "@internal 351 An address valid for SVE LD1ROH." 352 (and (match_code "mem") 353 (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)"))) 354 355(define_relaxed_memory_constraint "UOh" 356 "@internal 357 An address valid for SVE LD1ROH." 358 (and (match_code "mem") 359 (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)"))) 360 361 362(define_relaxed_memory_constraint "UOw" 363 "@internal 364 An address valid for SVE LD1ROW." 365 (and (match_code "mem") 366 (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)"))) 367 368(define_relaxed_memory_constraint "UOd" 369 "@internal 370 An address valid for SVE LD1ROD." 371 (and (match_code "mem") 372 (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)"))) 373 374(define_relaxed_memory_constraint "Uty" 375 "@internal 376 An address valid for SVE LD1Rs." 377 (and (match_code "mem") 378 (match_test "aarch64_sve_ld1r_operand_p (op)"))) 379 380(define_memory_constraint "Utx" 381 "@internal 382 An address valid for SVE structure mov patterns (as distinct from 383 LD[234] and ST[234] patterns)." 384 (match_operand 0 "aarch64_sve_struct_memory_operand")) 385 386(define_constraint "Ufc" 387 "A floating point constant which can be used with an\ 388 FMOV immediate operation." 389 (and (match_code "const_double,const_vector") 390 (match_test "aarch64_float_const_representable_p (op)"))) 391 392(define_constraint "Uvi" 393 "A floating point constant which can be used with a\ 394 MOVI immediate operation." 395 (and (match_code "const_double") 396 (match_test "aarch64_can_const_movi_rtx_p (op, GET_MODE (op))"))) 397 398(define_constraint "Do" 399 "@internal 400 A constraint that matches vector of immediates for orr." 401 (and (match_code "const_vector") 402 (match_test "aarch64_simd_valid_immediate (op, NULL, 403 AARCH64_CHECK_ORR)"))) 404 405(define_constraint "Db" 406 "@internal 407 A constraint that matches vector of immediates for bic." 408 (and (match_code "const_vector") 409 (match_test "aarch64_simd_valid_immediate (op, NULL, 410 AARCH64_CHECK_BIC)"))) 411 412(define_constraint "Dn" 413 "@internal 414 A constraint that matches vector of immediates." 415 (and (match_code "const,const_vector") 416 (match_test "aarch64_simd_valid_immediate (op, NULL)"))) 417 418(define_constraint "Dh" 419 "@internal 420 A constraint that matches an immediate operand valid for\ 421 AdvSIMD scalar move in HImode." 422 (and (match_code "const_int") 423 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 424 HImode)"))) 425 426(define_constraint "Dq" 427 "@internal 428 A constraint that matches an immediate operand valid for\ 429 AdvSIMD scalar move in QImode." 430 (and (match_code "const_int") 431 (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, 432 QImode)"))) 433 434(define_constraint "Dt" 435 "@internal 436 A const_double which is the reciprocal of an exact power of two, can be 437 used in an scvtf with fract bits operation" 438 (and (match_code "const_double") 439 (match_test "aarch64_fpconst_pow2_recip (op) > 0"))) 440 441(define_constraint "Dl" 442 "@internal 443 A constraint that matches vector of immediates for left shifts." 444 (and (match_code "const,const_vector") 445 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 446 true)"))) 447 448(define_constraint "D1" 449 "@internal 450 A constraint that matches vector of immediates that is bits(mode)-1." 451 (and (match_code "const,const_vector") 452 (match_test "aarch64_const_vec_all_same_in_range_p (op, 453 GET_MODE_UNIT_BITSIZE (mode) - 1, 454 GET_MODE_UNIT_BITSIZE (mode) - 1)"))) 455 456(define_constraint "Dr" 457 "@internal 458 A constraint that matches vector of immediates for right shifts." 459 (and (match_code "const,const_vector") 460 (match_test "aarch64_simd_shift_imm_p (op, GET_MODE (op), 461 false)"))) 462(define_constraint "Dz" 463 "@internal 464 A constraint that matches a vector of immediate zero." 465 (and (match_code "const,const_vector") 466 (match_test "op == CONST0_RTX (GET_MODE (op))"))) 467 468(define_constraint "Dm" 469 "@internal 470 A constraint that matches a vector of immediate minus one." 471 (and (match_code "const,const_vector") 472 (match_test "op == CONST1_RTX (GET_MODE (op))"))) 473 474(define_constraint "Dd" 475 "@internal 476 A constraint that matches an integer immediate operand valid\ 477 for AdvSIMD scalar operations in DImode." 478 (and (match_code "const_int") 479 (match_test "aarch64_can_const_movi_rtx_p (op, DImode)"))) 480 481(define_constraint "Ds" 482 "@internal 483 A constraint that matches an integer immediate operand valid\ 484 for AdvSIMD scalar operations in SImode." 485 (and (match_code "const_int") 486 (match_test "aarch64_can_const_movi_rtx_p (op, SImode)"))) 487 488(define_address_constraint "Dp" 489 "@internal 490 An address valid for a prefetch instruction." 491 (match_test "aarch64_address_valid_for_prefetch_p (op, true)")) 492 493(define_constraint "vgb" 494 "@internal 495 A constraint that matches an immediate offset valid for SVE LD1B 496 gather instructions." 497 (match_operand 0 "aarch64_sve_gather_immediate_b")) 498 499(define_constraint "vgd" 500 "@internal 501 A constraint that matches an immediate offset valid for SVE LD1D 502 gather instructions." 503 (match_operand 0 "aarch64_sve_gather_immediate_d")) 504 505(define_constraint "vgh" 506 "@internal 507 A constraint that matches an immediate offset valid for SVE LD1H 508 gather instructions." 509 (match_operand 0 "aarch64_sve_gather_immediate_h")) 510 511(define_constraint "vgw" 512 "@internal 513 A constraint that matches an immediate offset valid for SVE LD1W 514 gather instructions." 515 (match_operand 0 "aarch64_sve_gather_immediate_w")) 516 517(define_constraint "vsa" 518 "@internal 519 A constraint that matches an immediate operand valid for SVE 520 arithmetic instructions." 521 (match_operand 0 "aarch64_sve_arith_immediate")) 522 523(define_constraint "vsb" 524 "@internal 525 A constraint that matches an immediate operand valid for SVE UMAX 526 and UMIN operations." 527 (match_operand 0 "aarch64_sve_vsb_immediate")) 528 529(define_constraint "vsc" 530 "@internal 531 A constraint that matches a signed immediate operand valid for SVE 532 CMP instructions." 533 (match_operand 0 "aarch64_sve_cmp_vsc_immediate")) 534 535(define_constraint "vss" 536 "@internal 537 A constraint that matches a signed immediate operand valid for SVE 538 DUP instructions." 539 (match_test "aarch64_sve_dup_immediate_p (op)")) 540 541(define_constraint "vsd" 542 "@internal 543 A constraint that matches an unsigned immediate operand valid for SVE 544 CMP instructions." 545 (match_operand 0 "aarch64_sve_cmp_vsd_immediate")) 546 547(define_constraint "vsi" 548 "@internal 549 A constraint that matches a vector count operand valid for SVE INC and 550 DEC instructions." 551 (match_operand 0 "aarch64_sve_vector_inc_dec_immediate")) 552 553(define_constraint "vsn" 554 "@internal 555 A constraint that matches an immediate operand whose negative 556 is valid for SVE SUB instructions." 557 (match_operand 0 "aarch64_sve_sub_arith_immediate")) 558 559(define_constraint "vsQ" 560 "@internal 561 Like vsa, but additionally check that the immediate is nonnegative 562 when interpreted as a signed value." 563 (match_operand 0 "aarch64_sve_qadd_immediate")) 564 565(define_constraint "vsS" 566 "@internal 567 Like vsn, but additionally check that the immediate is negative 568 when interpreted as a signed value." 569 (match_operand 0 "aarch64_sve_qsub_immediate")) 570 571(define_constraint "vsl" 572 "@internal 573 A constraint that matches an immediate operand valid for SVE logical 574 operations." 575 (match_operand 0 "aarch64_sve_logical_immediate")) 576 577(define_constraint "vsm" 578 "@internal 579 A constraint that matches an immediate operand valid for SVE MUL, 580 SMAX and SMIN operations." 581 (match_operand 0 "aarch64_sve_vsm_immediate")) 582 583(define_constraint "vsA" 584 "@internal 585 A constraint that matches an immediate operand valid for SVE FADD 586 and FSUB operations." 587 (match_operand 0 "aarch64_sve_float_arith_immediate")) 588 589;; "B" for "bound". 590(define_constraint "vsB" 591 "@internal 592 A constraint that matches an immediate operand valid for SVE FMAX 593 and FMIN operations." 594 (match_operand 0 "aarch64_sve_float_maxmin_immediate")) 595 596(define_constraint "vsM" 597 "@internal 598 A constraint that matches an immediate operand valid for SVE FMUL 599 operations." 600 (match_operand 0 "aarch64_sve_float_mul_immediate")) 601 602(define_constraint "vsN" 603 "@internal 604 A constraint that matches the negative of vsA" 605 (match_operand 0 "aarch64_sve_float_negated_arith_immediate")) 606