1/* Decide whether to use 64 or 32-bit types to do the emulation. If we are 2 doing IEEE-128 with VSX, use 64-bit emulation even if we are compiling for a 3 32-bit target. */ 4 5#if defined(_ARCH_PPC64) || defined(__VSX__) || defined(__FLOAT128__) 6#define _FP_W_TYPE_SIZE 64 7#define _FP_W_TYPE unsigned long long 8#define _FP_WS_TYPE signed long long 9#define _FP_I_TYPE long long 10 11#ifdef _ARCH_PPC64 12typedef int TItype __attribute__ ((mode (TI))); 13typedef unsigned int UTItype __attribute__ ((mode (TI))); 14 15#define TI_BITS (__CHAR_BIT__ * (int)sizeof(TItype)) 16#endif 17 18#else /* 32-bits */ 19#define _FP_W_TYPE_SIZE 32 20#define _FP_W_TYPE unsigned int 21#define _FP_WS_TYPE signed int 22#define _FP_I_TYPE int 23#endif /* 32-bits */ 24 25/* The type of the result of a floating point comparison. This must 26 match `__libgcc_cmp_return__' in GCC for the target. */ 27typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); 28#define CMPtype __gcc_CMPtype 29 30#define _FP_MUL_MEAT_S(R,X,Y) \ 31 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm) 32 33#if (_FP_W_TYPE_SIZE==64) 34#define _FP_MUL_MEAT_D(R,X,Y) \ 35 _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) 36#define _FP_MUL_MEAT_Q(R,X,Y) \ 37 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) 38#else 39#define _FP_MUL_MEAT_D(R,X,Y) \ 40 _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm) 41#define _FP_MUL_MEAT_Q(R,X,Y) \ 42 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm) 43#endif 44 45#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y) 46 47#if (_FP_W_TYPE_SIZE==64) 48#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv(D,R,X,Y) 49#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv(Q,R,X,Y) 50#else 51#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y) 52#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y) 53#endif 54 55#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1) 56 57#if (_FP_W_TYPE_SIZE==64) 58#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1) 59#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1 60#else 61#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1 62#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1 63#endif 64 65#define _FP_NANSIGN_S 0 66#define _FP_NANSIGN_D 0 67#define _FP_NANSIGN_Q 0 68 69#define _FP_KEEPNANFRACP 1 70#define _FP_QNANNEGATEDP 0 71 72/* Someone please check this. */ 73#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \ 74 do { \ 75 if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \ 76 && !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \ 77 { \ 78 R##_s = Y##_s; \ 79 _FP_FRAC_COPY_##wc(R,Y); \ 80 } \ 81 else \ 82 { \ 83 R##_s = X##_s; \ 84 _FP_FRAC_COPY_##wc(R,X); \ 85 } \ 86 R##_c = FP_CLS_NAN; \ 87 } while (0) 88 89#define _FP_TININESS_AFTER_ROUNDING 0 90 91#define __LITTLE_ENDIAN 1234 92#define __BIG_ENDIAN 4321 93 94#if defined __BIG_ENDIAN__ || defined _BIG_ENDIAN 95# if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN 96# error "Both BIG_ENDIAN and LITTLE_ENDIAN defined!" 97# endif 98# define __BYTE_ORDER __BIG_ENDIAN 99#else 100# if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN 101# define __BYTE_ORDER __LITTLE_ENDIAN 102# else 103# error "Cannot determine current byte order" 104# endif 105#endif 106 107/* Only provide exception support if we have hardware floating point using 108 floating point registers and we can execute the mtfsf instruction. This 109 would only be true if we are using the emulation routines for IEEE 128-bit 110 floating point on pre-ISA 3.0 machines without the IEEE 128-bit floating 111 point support. */ 112 113#ifdef __FLOAT128__ 114#define ISA_BIT(x) (1LL << (63 - x)) 115 116/* Use the same bits of the FPSCR. */ 117# define FP_EX_INVALID ISA_BIT(34) 118# define FP_EX_OVERFLOW ISA_BIT(35) 119# define FP_EX_UNDERFLOW ISA_BIT(36) 120# define FP_EX_DIVZERO ISA_BIT(37) 121# define FP_EX_INEXACT ISA_BIT(38) 122# define FP_EX_ALL (FP_EX_INVALID | FP_EX_OVERFLOW \ 123 | FP_EX_UNDERFLOW | FP_EX_DIVZERO \ 124 | FP_EX_INEXACT) 125 126void __sfp_handle_exceptions (int); 127 128# define FP_HANDLE_EXCEPTIONS \ 129 do { \ 130 if (__builtin_expect (_fex, 0)) \ 131 __sfp_handle_exceptions (_fex); \ 132 } while (0) 133 134/* The FP_EX_* bits track whether the exception has occurred. This macro 135 must set the FP_EX_* bits of those exceptions which are configured to 136 trap. The FPSCR bit which indicates this is 22 ISA bits above the 137 respective FP_EX_* bit. Note, the ISA labels bits from msb to lsb, 138 so 22 ISA bits above is 22 bits below when counted from the lsb. */ 139# define FP_TRAPPING_EXCEPTIONS ((_fpscr.i << 22) & FP_EX_ALL) 140 141# define FP_RND_NEAREST 0x0 142# define FP_RND_ZERO 0x1 143# define FP_RND_PINF 0x2 144# define FP_RND_MINF 0x3 145# define FP_RND_MASK 0x3 146 147# define _FP_DECL_EX \ 148 union { unsigned long long i; double d; } _fpscr __attribute__ ((unused)) = \ 149 { .i = FP_RND_NEAREST } 150 151#define FP_INIT_ROUNDMODE \ 152 do { \ 153 __asm__ __volatile__ ("mffs %0" \ 154 : "=f" (_fpscr.d)); \ 155 } while (0) 156 157# define FP_ROUNDMODE (_fpscr.i & FP_RND_MASK) 158#endif /* !__FLOAT128__ */ 159 160/* Define ALIASNAME as a strong alias for NAME. */ 161# define strong_alias(name, aliasname) _strong_alias(name, aliasname) 162# define _strong_alias(name, aliasname) \ 163 extern __typeof (name) aliasname __attribute__ ((alias (#name))); 164