1/* Copyright (C) 2009-2020 Free Software Foundation, Inc.
2   Contributed by ARM Ltd.
3
4   This file is free software; you can redistribute it and/or modify it
5   under the terms of the GNU General Public License as published by the
6   Free Software Foundation; either version 3, or (at your option) any
7   later version.
8
9   This file is distributed in the hope that it will be useful, but
10   WITHOUT ANY WARRANTY; without even the implied warranty of
11   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12   General Public License for more details.
13
14   Under Section 7 of GPL version 3, you are granted additional
15   permissions described in the GCC Runtime Library Exception, version
16   3.1, as published by the Free Software Foundation.
17
18   You should have received a copy of the GNU General Public License and
19   a copy of the GCC Runtime Library Exception along with this program;
20   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
21   <http://www.gnu.org/licenses/>.  */
22
23/* Always include AArch64 unwinder header file.  */
24#include "config/aarch64/aarch64-unwind.h"
25
26#ifndef inhibit_libc
27
28#include <signal.h>
29#include <sys/ucontext.h>
30
31
32/* Since insns are always stored LE, on a BE system the opcodes will
33   be loaded byte-reversed.  Therefore, define two sets of opcodes,
34   one for LE and one for BE.  */
35
36#if __AARCH64EB__
37#define MOVZ_X8_8B	0x681180d2
38#define SVC_0		0x010000d4
39#else
40#define MOVZ_X8_8B	0xd2801168
41#define SVC_0		0xd4000001
42#endif
43
44#define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state
45
46static _Unwind_Reason_Code
47aarch64_fallback_frame_state (struct _Unwind_Context *context,
48			      _Unwind_FrameState * fs)
49{
50  /* The kernel creates an rt_sigframe on the stack immediately prior
51     to delivering a signal.
52
53     This structure must have the same shape as the linux kernel
54     equivalent.  */
55  struct rt_sigframe
56  {
57    siginfo_t info;
58    ucontext_t uc;
59  };
60
61  struct rt_sigframe *rt_;
62  _Unwind_Ptr new_cfa;
63  unsigned *pc = context->ra;
64  struct sigcontext *sc;
65  struct _aarch64_ctx *extension_marker;
66  int i;
67
68  /* A signal frame will have a return address pointing to
69     __default_sa_restorer. This code is hardwired as:
70
71     0xd2801168         movz x8, #0x8b
72     0xd4000001         svc  0x0
73   */
74  if (pc[0] != MOVZ_X8_8B || pc[1] != SVC_0)
75    {
76      return _URC_END_OF_STACK;
77    }
78
79  rt_ = context->cfa;
80  sc = &rt_->uc.uc_mcontext;
81
82/* This define duplicates the definition in aarch64.md */
83#define SP_REGNUM 31
84
85  new_cfa = (_Unwind_Ptr) sc;
86  fs->regs.cfa_how = CFA_REG_OFFSET;
87  fs->regs.cfa_reg = __LIBGCC_STACK_POINTER_REGNUM__;
88  fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
89
90  for (i = 0; i < AARCH64_DWARF_NUMBER_R; i++)
91    {
92      fs->regs.reg[AARCH64_DWARF_R0 + i].how = REG_SAVED_OFFSET;
93      fs->regs.reg[AARCH64_DWARF_R0 + i].loc.offset =
94	(_Unwind_Ptr) & (sc->regs[i]) - new_cfa;
95    }
96
97  /* The core context may be extended with an arbitrary set of
98     additional contexts appended sequentially. Each additional
99     context contains a magic identifier and size in bytes.  The size
100     field can be used to skip over unrecognized context extensions.
101     The end of the context sequence is marked by a context with magic
102     0 or size 0.  */
103  for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved;
104       extension_marker->magic;
105       extension_marker = (struct _aarch64_ctx *)
106       ((unsigned char *) extension_marker + extension_marker->size))
107    {
108      if (extension_marker->magic == FPSIMD_MAGIC)
109	{
110	  struct fpsimd_context *ctx =
111	    (struct fpsimd_context *) extension_marker;
112	  int i;
113
114	  for (i = 0; i < AARCH64_DWARF_NUMBER_V; i++)
115	    {
116	      _Unwind_Sword offset;
117
118	      fs->regs.reg[AARCH64_DWARF_V0 + i].how = REG_SAVED_OFFSET;
119
120	      /* sigcontext contains 32 128bit registers for V0 to
121		 V31.  The kernel will have saved the contents of the
122		 V registers.  We want to unwind the callee save D
123		 registers.  Each D register comprises the least
124		 significant half of the corresponding V register.  We
125		 need to offset into the saved V register dependent on
126		 our endianness to find the saved D register.  */
127
128	      offset = (_Unwind_Ptr) & (ctx->vregs[i]) - new_cfa;
129
130	      /* The endianness adjustment code below expects that a
131		 saved V register is 16 bytes.  */
132	      gcc_assert (sizeof (ctx->vregs[0]) == 16);
133#if defined (__AARCH64EB__)
134	      offset = offset + 8;
135#endif
136	      fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset;
137	    }
138	}
139      else
140	{
141	  /* There is context provided that we do not recognize!  */
142	}
143    }
144
145  fs->regs.reg[31].how = REG_SAVED_OFFSET;
146  fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa;
147
148  fs->signal_frame = 1;
149
150  fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].how =
151    REG_SAVED_VAL_OFFSET;
152  fs->regs.reg[__LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__].loc.offset =
153    (_Unwind_Ptr) (sc->pc) - new_cfa;
154
155  fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
156
157  return _URC_NO_REASON;
158}
159
160#endif
161