spu.h revision 1.3
1/* Copyright (C) 2006-2013 Free Software Foundation, Inc. 2 3 This file is free software; you can redistribute it and/or modify it under 4 the terms of the GNU General Public License as published by the Free 5 Software Foundation; either version 3 of the License, or (at your option) 6 any later version. 7 8 This file is distributed in the hope that it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 for more details. 12 13 You should have received a copy of the GNU General Public License 14 along with GCC; see the file COPYING3. If not see 15 <http://www.gnu.org/licenses/>. */ 16 17 18/* Run-time Target */ 19#define TARGET_CPU_CPP_BUILTINS() spu_cpu_cpp_builtins(pfile) 20 21#define C_COMMON_OVERRIDE_OPTIONS spu_c_common_override_options() 22 23#define INIT_EXPANDERS spu_init_expanders() 24 25/* Which processor to generate code or schedule for. */ 26enum processor_type 27{ 28 PROCESSOR_CELL, 29 PROCESSOR_CELLEDP 30}; 31 32extern GTY(()) int spu_arch; 33extern GTY(()) int spu_tune; 34 35/* Support for a compile-time default architecture and tuning. The rules are: 36 --with-arch is ignored if -march is specified. 37 --with-tune is ignored if -mtune is specified. */ 38#define OPTION_DEFAULT_SPECS \ 39 {"arch", "%{!march=*:-march=%(VALUE)}" }, \ 40 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" } 41 42/* Default target_flags if no switches specified. */ 43#ifndef TARGET_DEFAULT 44#define TARGET_DEFAULT (MASK_ERROR_RELOC | MASK_SAFE_DMA | MASK_BRANCH_HINTS \ 45 | MASK_SAFE_HINTS | MASK_ADDRESS_SPACE_CONVERSION) 46#endif 47 48 49/* Storage Layout */ 50 51#define BITS_BIG_ENDIAN 1 52 53#define BYTES_BIG_ENDIAN 1 54 55#define WORDS_BIG_ENDIAN 1 56 57#define BITS_PER_UNIT 8 58 59/* GCC uses word_mode in many places, assuming that it is the fastest 60 integer mode. That is not the case for SPU though. We can't use 61 32 here because (of some reason I can't remember.) */ 62#define BITS_PER_WORD 128 63 64#define UNITS_PER_WORD (BITS_PER_WORD/BITS_PER_UNIT) 65 66/* When building libgcc, we need to assume 4 words per units even 67 though UNITS_PER_WORD is 16, because the SPU has basically a 32-bit 68 instruction set although register size is 128 bits. In particular, 69 this causes libgcc to contain __divdi3 instead of __divti3 etc. 70 However, we allow this default to be re-defined on the command 71 line, so that we can use the LIB2_SIDITI_CONV_FUNCS mechanism 72 to get (in addition) TImode versions of some routines. */ 73#ifndef LIBGCC2_UNITS_PER_WORD 74#define LIBGCC2_UNITS_PER_WORD 4 75#endif 76 77#define POINTER_SIZE 32 78 79#define PARM_BOUNDARY 128 80 81#define STACK_BOUNDARY 128 82 83/* We want it 8-byte aligned so we can properly use dual-issue 84 instructions, which can only happen on an 8-byte aligned address. */ 85#define FUNCTION_BOUNDARY 64 86 87/* We would like to allow a larger alignment for data objects (for DMA) 88 but the aligned attribute is limited by BIGGEST_ALIGNMENT. We don't 89 define BIGGEST_ALIGNMENT as larger because it is used in other places 90 and would end up wasting space. (Is this still true?) */ 91#define BIGGEST_ALIGNMENT 128 92 93#define MINIMUM_ATOMIC_ALIGNMENT 128 94 95/* Make all static objects 16-byte aligned. This allows us to assume 96 they are also padded to 16-bytes, which means we can use a single 97 load or store instruction to access them. Do the same for objects 98 on the stack. (Except a bug (?) allows some stack objects to be 99 unaligned.) */ 100#define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128) 101#define CONSTANT_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128) 102#define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128) 103 104#define EMPTY_FIELD_BOUNDARY 32 105 106#define STRICT_ALIGNMENT 1 107 108/* symbol_ref's of functions are not aligned to 16 byte boundary. */ 109#define ALIGNED_SYMBOL_REF_P(X) \ 110 (GET_CODE (X) == SYMBOL_REF \ 111 && (SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1) == 0 \ 112 && (! SYMBOL_REF_FUNCTION_P (X) \ 113 || align_functions >= 16)) 114 115#define PCC_BITFIELD_TYPE_MATTERS 1 116 117#define MAX_FIXED_MODE_SIZE 128 118 119#define STACK_SAVEAREA_MODE(save_level) \ 120 (save_level == SAVE_FUNCTION ? VOIDmode \ 121 : save_level == SAVE_NONLOCAL ? SImode \ 122 : Pmode) 123 124#define STACK_SIZE_MODE SImode 125 126 127/* Type Layout */ 128 129#define INT_TYPE_SIZE 32 130 131#define LONG_TYPE_SIZE 32 132 133#define LONG_LONG_TYPE_SIZE 64 134 135#define FLOAT_TYPE_SIZE 32 136 137#define DOUBLE_TYPE_SIZE 64 138 139#define LONG_DOUBLE_TYPE_SIZE 64 140 141#define DEFAULT_SIGNED_CHAR 0 142 143#define STDINT_LONG32 0 144 145 146/* Register Basics */ 147 148/* 128-130 are special registers that never appear in assembly code. */ 149#define FIRST_PSEUDO_REGISTER 131 150 151#define FIXED_REGISTERS { \ 152 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 153 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 154 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 155 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 156 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 157 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 158 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 159 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 160 1, 1, 1 \ 161} 162 163#define CALL_USED_REGISTERS { \ 164 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 165 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 166 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 167 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 168 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 169 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 170 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 171 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 172 1, 1, 1 \ 173} 174 175 176/* Values in Registers */ 177 178#define HARD_REGNO_NREGS(REGNO, MODE) \ 179 ((GET_MODE_BITSIZE(MODE)+MAX_FIXED_MODE_SIZE-1)/MAX_FIXED_MODE_SIZE) 180 181#define HARD_REGNO_MODE_OK(REGNO, MODE) 1 182 183#define MODES_TIEABLE_P(MODE1, MODE2) \ 184 (GET_MODE_BITSIZE (MODE1) <= MAX_FIXED_MODE_SIZE \ 185 && GET_MODE_BITSIZE (MODE2) <= MAX_FIXED_MODE_SIZE) 186 187 188/* Register Classes */ 189 190enum reg_class { 191 NO_REGS, 192 GENERAL_REGS, 193 ALL_REGS, 194 LIM_REG_CLASSES 195}; 196 197#define N_REG_CLASSES (int) LIM_REG_CLASSES 198 199#define REG_CLASS_NAMES \ 200{ "NO_REGS", \ 201 "GENERAL_REGS", \ 202 "ALL_REGS" \ 203} 204 205#define REG_CLASS_CONTENTS { \ 206 {0, 0, 0, 0, 0}, /* no regs */ \ 207 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}, /* general regs */ \ 208 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x3}} /* all regs */ 209 210#define REGNO_REG_CLASS(REGNO) (GENERAL_REGS) 211 212#define BASE_REG_CLASS GENERAL_REGS 213 214#define INDEX_REG_CLASS GENERAL_REGS 215 216#define REGNO_OK_FOR_BASE_P(regno) \ 217 ((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0)) 218 219#define REGNO_OK_FOR_INDEX_P(regno) \ 220 ((regno) < FIRST_PSEUDO_REGISTER || (regno > LAST_VIRTUAL_REGISTER && reg_renumber[regno] >= 0)) 221 222#define INT_REG_OK_FOR_INDEX_P(X,STRICT) \ 223 ((!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X)))) 224#define INT_REG_OK_FOR_BASE_P(X,STRICT) \ 225 ((!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X)))) 226 227/* GCC assumes that modes are in the lowpart of a register, which is 228 only true for SPU. */ 229#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 230 ((GET_MODE_SIZE (FROM) > 4 || GET_MODE_SIZE (TO) > 4) \ 231 && (GET_MODE_SIZE (FROM) < 16 || GET_MODE_SIZE (TO) < 16) \ 232 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) 233 234#define REGISTER_TARGET_PRAGMAS() do { \ 235c_register_addr_space ("__ea", ADDR_SPACE_EA); \ 236targetm.resolve_overloaded_builtin = spu_resolve_overloaded_builtin; \ 237}while (0); 238 239 240/* Frame Layout */ 241 242#define STACK_GROWS_DOWNWARD 243 244#define FRAME_GROWS_DOWNWARD 1 245 246#define STARTING_FRAME_OFFSET (0) 247 248#define STACK_POINTER_OFFSET 32 249 250#define FIRST_PARM_OFFSET(FNDECL) (0) 251 252#define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16) 253 254#define RETURN_ADDR_RTX(COUNT,FP) (spu_return_addr (COUNT, FP)) 255 256/* Should this be defined? Would it simplify our implementation. */ 257/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 258 259#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG(Pmode, LINK_REGISTER_REGNUM) 260 261#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM) 262 263#define ARG_POINTER_CFA_OFFSET(FNDECL) \ 264 (crtl->args.pretend_args_size - STACK_POINTER_OFFSET) 265 266 267/* Stack Checking */ 268 269/* We store the Available Stack Size in the second slot of the stack 270 register. We emit stack checking code during the prologue. */ 271#define STACK_CHECK_BUILTIN 1 272 273 274/* Frame Registers, and other registers */ 275 276#define STACK_POINTER_REGNUM 1 277 278/* Will be eliminated. */ 279#define FRAME_POINTER_REGNUM 128 280 281/* This is not specified in any ABI, so could be set to anything. */ 282#define HARD_FRAME_POINTER_REGNUM 127 283 284/* Will be eliminated. */ 285#define ARG_POINTER_REGNUM 129 286 287#define STATIC_CHAIN_REGNUM 2 288 289#define LINK_REGISTER_REGNUM 0 290 291/* Used to keep track of instructions that have clobbered the hint 292 * buffer. Users can also specify it in inline asm. */ 293#define HBR_REGNUM 130 294 295#define MAX_REGISTER_ARGS 72 296#define FIRST_ARG_REGNUM 3 297#define LAST_ARG_REGNUM (FIRST_ARG_REGNUM + MAX_REGISTER_ARGS - 1) 298 299#define MAX_REGISTER_RETURN 72 300#define FIRST_RETURN_REGNUM 3 301#define LAST_RETURN_REGNUM (FIRST_RETURN_REGNUM + MAX_REGISTER_RETURN - 1) 302 303 304/* Elimination */ 305 306#define ELIMINABLE_REGS \ 307 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 308 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 309 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 310 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 311 312#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 313 ((OFFSET) = spu_initial_elimination_offset((FROM),(TO))) 314 315 316/* Stack Arguments */ 317 318#define ACCUMULATE_OUTGOING_ARGS 1 319 320#define REG_PARM_STACK_SPACE(FNDECL) 0 321 322#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 323 324 325/* Register Arguments */ 326 327#define CUMULATIVE_ARGS int 328 329#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ 330 ((CUM) = 0) 331 332/* The SPU ABI wants 32/64-bit types at offset 0 in the quad-word on the 333 stack. 8/16-bit types should be at offsets 3/2 respectively. */ 334#define FUNCTION_ARG_OFFSET(MODE, TYPE) \ 335(((TYPE) && INTEGRAL_TYPE_P (TYPE) && GET_MODE_SIZE (MODE) < 4) \ 336 ? (4 - GET_MODE_SIZE (MODE)) \ 337 : 0) 338 339#define FUNCTION_ARG_PADDING(MODE,TYPE) upward 340 341#define PAD_VARARGS_DOWN 0 342 343#define FUNCTION_ARG_REGNO_P(N) ((N) >= (FIRST_ARG_REGNUM) && (N) <= (LAST_ARG_REGNUM)) 344 345/* Scalar Return */ 346 347#define FUNCTION_VALUE(VALTYPE, FUNC) \ 348 (spu_function_value((VALTYPE),(FUNC))) 349 350#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FIRST_RETURN_REGNUM) 351 352#define FUNCTION_VALUE_REGNO_P(N) ((N) >= (FIRST_RETURN_REGNUM) && (N) <= (LAST_RETURN_REGNUM)) 353 354 355/* Machine-specific symbol_ref flags. */ 356#define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) 357 358/* Aggregate Return */ 359 360#define DEFAULT_PCC_STRUCT_RETURN 0 361 362 363/* Function Entry */ 364 365#define EXIT_IGNORE_STACK 0 366 367#define EPILOGUE_USES(REGNO) ((REGNO)==1 ? 1 : 0) 368 369 370/* Profiling */ 371 372#define FUNCTION_PROFILER(FILE, LABELNO) \ 373 spu_function_profiler ((FILE), (LABELNO)); 374 375#define NO_PROFILE_COUNTERS 1 376 377#define PROFILE_BEFORE_PROLOGUE 1 378 379 380/* Trampolines */ 381 382#define TRAMPOLINE_SIZE (TARGET_LARGE_MEM ? 20 : 16) 383 384#define TRAMPOLINE_ALIGNMENT 128 385 386/* Addressing Modes */ 387 388#define CONSTANT_ADDRESS_P(X) spu_constant_address_p(X) 389 390#define MAX_REGS_PER_ADDRESS 2 391 392#define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ 393do { \ 394 rtx new_rtx = spu_legitimize_reload_address (AD, MODE, OPNUM, \ 395 (int)(TYPE)); \ 396 if (new_rtx) \ 397 { \ 398 (AD) = new_rtx; \ 399 goto WIN; \ 400 } \ 401} while (0) 402 403 404/* Costs */ 405 406#define BRANCH_COST(speed_p, predictable_p) spu_branch_cost 407 408#define SLOW_BYTE_ACCESS 0 409 410#define MOVE_RATIO(speed) ((speed)? 32 : 4) 411 412#define NO_FUNCTION_CSE 413 414 415/* Sections */ 416 417#define TEXT_SECTION_ASM_OP ".text" 418 419#define DATA_SECTION_ASM_OP ".data" 420 421#define JUMP_TABLES_IN_TEXT_SECTION 1 422 423 424/* PIC */ 425#define PIC_OFFSET_TABLE_REGNUM 126 426 427 428/* File Framework */ 429 430#define ASM_APP_ON "" 431 432#define ASM_APP_OFF "" 433 434 435/* Uninitialized Data */ 436#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 437( fputs (".comm ", (FILE)), \ 438 assemble_name ((FILE), (NAME)), \ 439 fprintf ((FILE), ",%d\n", (ROUNDED))) 440 441#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 442( fputs (".lcomm ", (FILE)), \ 443 assemble_name ((FILE), (NAME)), \ 444 fprintf ((FILE), ",%d\n", (ROUNDED))) 445 446 447/* Label Output */ 448#define ASM_OUTPUT_LABEL(FILE,NAME) \ 449 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 450 451#define ASM_OUTPUT_LABELREF(FILE, NAME) \ 452 asm_fprintf (FILE, "%U%s", default_strip_name_encoding (NAME)) 453 454#define ASM_OUTPUT_SYMBOL_REF(FILE, X) \ 455 do \ 456 { \ 457 tree decl; \ 458 assemble_name (FILE, XSTR ((X), 0)); \ 459 if ((decl = SYMBOL_REF_DECL ((X))) != 0 \ 460 && TREE_CODE (decl) == VAR_DECL \ 461 && TYPE_ADDR_SPACE (TREE_TYPE (decl))) \ 462 fputs ("@ppu", FILE); \ 463 } while (0) 464 465 466/* Instruction Output */ 467#define REGISTER_NAMES \ 468{"$lr", "$sp", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \ 469 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", \ 470 "$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39", "$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47", \ 471 "$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55", "$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63", \ 472 "$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71", "$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79", \ 473 "$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87", "$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95", \ 474 "$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103", "$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111", \ 475 "$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119", "$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127", \ 476 "$vfp", "$vap", "hbr" \ 477} 478 479#define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) 480 481#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 482 print_operand_address (FILE, ADDR) 483 484#define LOCAL_LABEL_PREFIX "." 485 486#define USER_LABEL_PREFIX "" 487 488#define ASM_COMMENT_START "#" 489 490 491/* Dispatch Tables */ 492 493#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 494 fprintf (FILE, "\t.word .L%d-.L%d\n", VALUE, REL) 495 496#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 497 fprintf (FILE, "\t.word .L%d\n", VALUE) 498 499 500/* Alignment Output */ 501 502#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 503 do { if (LOG!=0) fprintf (FILE, "\t.align\t%d\n", (LOG)); } while (0) 504 505 506/* Misc */ 507 508#define CASE_VECTOR_MODE SImode 509 510#define MOVE_MAX 16 511 512#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) ((INPREC) <= 32 && (OUTPREC) <= (INPREC)) 513 514#define STORE_FLAG_VALUE -1 515 516#define Pmode SImode 517 518#define FUNCTION_MODE QImode 519 520#define NO_IMPLICIT_EXTERN_C 1 521 522 523/* Address spaces. */ 524#define ADDR_SPACE_EA 1 525 526 527/* Builtins. */ 528 529enum spu_builtin_type 530{ 531 B_INSN, 532 B_JUMP, 533 B_BISLED, 534 B_CALL, 535 B_HINT, 536 B_OVERLOAD, 537 B_INTERNAL 538}; 539 540struct spu_builtin_description 541{ 542 int fcode; 543 int icode; 544 const char *name; 545 enum spu_builtin_type type; 546 547 /* The first element of parm is always the return type. The rest 548 are a zero terminated list of parameters. */ 549 int parm[5]; 550}; 551 552extern struct spu_builtin_description spu_builtins[]; 553 554