sparc.opt revision 1.9 
1; Options for the SPARC port of the compiler
2;
3; Copyright (C) 2005-2018 Free Software Foundation, Inc.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
9; Software Foundation; either version 3, or (at your option) any later
10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT
13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15; License for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21HeaderInclude
22config/sparc/sparc-opts.h
23
24;; Debug flags
25TargetVariable
26unsigned int sparc_debug
27
28mfpu
29Target Report Mask(FPU)
30Use hardware FP.
31
32mhard-float
33Target RejectNegative Mask(FPU)
34Use hardware FP.
35
36msoft-float
37Target RejectNegative InverseMask(FPU)
38Do not use hardware FP.
39
40mflat
41Target Report Mask(FLAT)
42Use flat register window model.
43
44munaligned-doubles
45Target Report Mask(UNALIGNED_DOUBLES)
46Assume possible double misalignment.
47
48mapp-regs
49Target Report Mask(APP_REGS)
50Use ABI reserved registers.
51
52mhard-quad-float
53Target Report RejectNegative Mask(HARD_QUAD)
54Use hardware quad FP instructions.
55
56msoft-quad-float
57Target Report RejectNegative InverseMask(HARD_QUAD)
58Do not use hardware quad fp instructions.
59
60mlra
61Target Report Mask(LRA)
62Enable Local Register Allocation.
63
64mv8plus
65Target Report Mask(V8PLUS)
66Compile for V8+ ABI.
67
68mvis
69Target Report Mask(VIS)
70Use UltraSPARC Visual Instruction Set version 1.0 extensions.
71
72mvis2
73Target Report Mask(VIS2)
74Use UltraSPARC Visual Instruction Set version 2.0 extensions.
75
76mvis3
77Target Report Mask(VIS3)
78Use UltraSPARC Visual Instruction Set version 3.0 extensions.
79
80mvis4
81Target Report Mask(VIS4)
82Use UltraSPARC Visual Instruction Set version 4.0 extensions.
83
84mvis4b
85Target Report Mask(VIS4B)
86Use additional VIS instructions introduced in OSA2017.
87
88mcbcond
89Target Report Mask(CBCOND)
90Use UltraSPARC Compare-and-Branch extensions.
91
92mfmaf
93Target Report Mask(FMAF)
94Use UltraSPARC Fused Multiply-Add extensions.
95
96mfsmuld
97Target Report Mask(FSMULD)
98Use Floating-point Multiply Single to Double (FsMULd) instruction.
99
100mpopc
101Target Report Mask(POPC)
102Use UltraSPARC Population-Count instruction.
103
104msubxc
105Target Report Mask(SUBXC)
106Use UltraSPARC Subtract-Extended-with-Carry instruction.
107
108mptr64
109Target Report RejectNegative Mask(PTR64)
110Pointers are 64-bit.
111
112mptr32
113Target Report RejectNegative InverseMask(PTR64)
114Pointers are 32-bit.
115
116m64
117Target Report RejectNegative Mask(64BIT)
118Use 64-bit ABI.
119
120m32
121Target Report RejectNegative InverseMask(64BIT)
122Use 32-bit ABI.
123
124mstack-bias
125Target Report Mask(STACK_BIAS)
126Use stack bias.
127
128mfaster-structs
129Target Report Mask(FASTER_STRUCTS)
130Use structs on stronger alignment for double-word copies.
131
132mrelax
133Target
134Optimize tail call instructions in assembler and linker.
135
136muser-mode
137Target Report InverseMask(SV_MODE)
138Do not generate code that can only run in supervisor mode (default).
139
140mcpu=
141Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7)
142Use features of and schedule code for given CPU.
143
144mtune=
145Target RejectNegative Joined Var(sparc_cpu) Enum(sparc_processor_type) Init(PROCESSOR_V7)
146Schedule code for given CPU.
147
148Enum
149Name(sparc_processor_type) Type(enum processor_type)
150
151EnumValue
152Enum(sparc_processor_type) String(native) Value(PROCESSOR_NATIVE) DriverOnly
153
154EnumValue
155Enum(sparc_processor_type) String(v7) Value(PROCESSOR_V7)
156
157EnumValue
158Enum(sparc_processor_type) String(cypress) Value(PROCESSOR_CYPRESS)
159
160EnumValue
161Enum(sparc_processor_type) String(v8) Value(PROCESSOR_V8)
162
163EnumValue
164Enum(sparc_processor_type) String(supersparc) Value(PROCESSOR_SUPERSPARC)
165
166EnumValue
167Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC)
168
169EnumValue
170Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON)
171
172EnumValue
173Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3)
174
175EnumValue
176Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7)
177
178EnumValue
179Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE)
180
181EnumValue
182Enum(sparc_processor_type) String(f930) Value(PROCESSOR_F930)
183
184EnumValue
185Enum(sparc_processor_type) String(f934) Value(PROCESSOR_F934)
186
187EnumValue
188Enum(sparc_processor_type) String(sparclite86x) Value(PROCESSOR_SPARCLITE86X)
189
190EnumValue
191Enum(sparc_processor_type) String(sparclet) Value(PROCESSOR_SPARCLET)
192
193EnumValue
194Enum(sparc_processor_type) String(tsc701) Value(PROCESSOR_TSC701)
195
196EnumValue
197Enum(sparc_processor_type) String(v9) Value(PROCESSOR_V9)
198
199EnumValue
200Enum(sparc_processor_type) String(ultrasparc) Value(PROCESSOR_ULTRASPARC)
201
202EnumValue
203Enum(sparc_processor_type) String(ultrasparc3) Value(PROCESSOR_ULTRASPARC3)
204
205EnumValue
206Enum(sparc_processor_type) String(niagara) Value(PROCESSOR_NIAGARA)
207
208EnumValue
209Enum(sparc_processor_type) String(niagara2) Value(PROCESSOR_NIAGARA2)
210
211EnumValue
212Enum(sparc_processor_type) String(niagara3) Value(PROCESSOR_NIAGARA3)
213
214EnumValue
215Enum(sparc_processor_type) String(niagara4) Value(PROCESSOR_NIAGARA4)
216
217EnumValue
218Enum(sparc_processor_type) String(niagara7) Value(PROCESSOR_NIAGARA7)
219
220EnumValue
221Enum(sparc_processor_type) String(m8) Value(PROCESSOR_M8)
222
223mcmodel=
224Target RejectNegative Joined Var(sparc_cmodel_string)
225Use given SPARC-V9 code model.
226
227mdebug=
228Target RejectNegative Joined Var(sparc_debug_string)
229Enable debug output.
230
231mstd-struct-return
232Target Report Var(sparc_std_struct_return)
233Enable strict 32-bit psABI struct return checking.
234
235mfix-at697f
236Target Report RejectNegative Var(sparc_fix_at697f)
237Enable workaround for single erratum of AT697F processor
238(corresponding to erratum #13 of AT697E processor).
239
240mfix-ut699
241Target Report RejectNegative Var(sparc_fix_ut699)
242Enable workarounds for the errata of the UT699 processor.
243
244mfix-ut700
245Target Report RejectNegative Var(sparc_fix_ut700)
246Enable workarounds for the errata of the UT699E/UT700 processor.
247
248mfix-gr712rc
249Target Report RejectNegative Var(sparc_fix_gr712rc)
250Enable workarounds for the errata of the GR712RC processor.
251
252;; Enable workaround for back-to-back store errata
253TargetVariable
254unsigned int sparc_fix_b2bst
255
256;; Enable workaround for GRLIB-TN-0013 errata
257TargetVariable
258unsigned int sparc_fix_lost_divsqrt
259
260Mask(LONG_DOUBLE_128)
261;; Use 128-bit long double
262
263Mask(LEON)
264;; Generate code for LEON
265
266Mask(LEON3)
267;; Generate code for LEON3
268
269Mask(SPARCLITE)
270;; Generate code for SPARClite
271
272Mask(SPARCLET)
273;; Generate code for SPARClet
274
275Mask(V8)
276;; Generate code for SPARC-V8
277
278Mask(V9)
279;; Generate code for SPARC-V9
280
281Mask(DEPRECATED_V8_INSNS)
282;; Generate code that uses the V8 instructions deprecated
283;; in the V9 architecture.
284
285mmemory-model=
286Target RejectNegative Joined Var(sparc_memory_model) Enum(sparc_memory_model) Init(SMM_DEFAULT)
287Specify the memory model in effect for the program.
288
289Enum
290Name(sparc_memory_model) Type(enum sparc_memory_model_type)
291
292EnumValue
293Enum(sparc_memory_model) String(default) Value(SMM_DEFAULT)
294
295EnumValue
296Enum(sparc_memory_model) String(rmo) Value(SMM_RMO)
297
298EnumValue
299Enum(sparc_memory_model) String(pso) Value(SMM_PSO)
300
301EnumValue
302Enum(sparc_memory_model) String(tso) Value(SMM_TSO)
303
304EnumValue
305Enum(sparc_memory_model) String(sc) Value(SMM_SC)
306