sh.opt revision 1.1
1; Options for the SH port of the compiler. 2 3; Copyright (C) 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15; for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21;; Used for various architecture options. 22Mask(SH_E) 23 24;; Set if the default precision of th FPU is single. 25Mask(FPU_SINGLE) 26 27;; Set if we should generate code using type 2A insns. 28Mask(HARD_SH2A) 29 30;; Set if we should generate code using type 2A DF insns. 31Mask(HARD_SH2A_DOUBLE) 32 33;; Set if compiling for SH4 hardware (to be used for insn costs etc.) 34Mask(HARD_SH4) 35 36;; Set if we should generate code for a SH5 CPU (either ISA). 37Mask(SH5) 38 39;; Set if we should save all target registers. 40Mask(SAVE_ALL_TARGET_REGS) 41 42m1 43Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) 44Generate SH1 code 45 46m2 47Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2) 48Generate SH2 code 49 50m2a 51Target RejectNegative Condition(SUPPORT_SH2A) 52Generate default double-precision SH2a-FPU code 53 54m2a-nofpu 55Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) 56Generate SH2a FPU-less code 57 58m2a-single 59Target RejectNegative Condition(SUPPORT_SH2A_SINGLE) 60Generate default single-precision SH2a-FPU code 61 62m2a-single-only 63Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY) 64Generate only single-precision SH2a-FPU code 65 66m2e 67Target RejectNegative Condition(SUPPORT_SH2E) 68Generate SH2e code 69 70m3 71Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) 72Generate SH3 code 73 74m3e 75Target RejectNegative Condition(SUPPORT_SH3E) 76Generate SH3e code 77 78m4 79Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4) 80Generate SH4 code 81 82m4-100 83Target RejectNegative Condition(SUPPORT_SH4) 84Generate SH4-100 code 85 86m4-200 87Target RejectNegative Condition(SUPPORT_SH4) 88Generate SH4-200 code 89 90;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and 91;; pipeline - irrespective of ABI. 92m4-300 93Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300) 94Generate SH4-300 code 95 96m4-nofpu 97Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 98Generate SH4 FPU-less code 99 100m4-100-nofpu 101Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 102Generate SH4-100 FPU-less code 103 104m4-200-nofpu 105Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 106Generate SH4-200 FPU-less code 107 108m4-300-nofpu 109Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists 110Generate SH4-300 FPU-less code 111 112m4-340 113Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) VarExists 114Generate code for SH4 340 series (MMU/FPU-less) 115;; passes -isa=sh4-nommu-nofpu to the assembler. 116 117m4-400 118Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 119Generate code for SH4 400 series (MMU/FPU-less) 120;; passes -isa=sh4-nommu-nofpu to the assembler. 121 122m4-500 123Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 124Generate code for SH4 500 series (FPU-less). 125;; passes -isa=sh4-nofpu to the assembler. 126 127m4-single 128Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 129Generate default single-precision SH4 code 130 131m4-100-single 132Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 133Generate default single-precision SH4-100 code 134 135m4-200-single 136Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 137Generate default single-precision SH4-200 code 138 139m4-300-single 140Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) VarExists 141Generate default single-precision SH4-300 code 142 143m4-single-only 144Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 145Generate only single-precision SH4 code 146 147m4-100-single-only 148Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 149Generate only single-precision SH4-100 code 150 151m4-200-single-only 152Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 153Generate only single-precision SH4-200 code 154 155m4-300-single-only 156Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) VarExists 157Generate only single-precision SH4-300 code 158 159m4a 160Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) 161Generate SH4a code 162 163m4a-nofpu 164Target RejectNegative Condition(SUPPORT_SH4A_NOFPU) 165Generate SH4a FPU-less code 166 167m4a-single 168Target RejectNegative Condition(SUPPORT_SH4A_SINGLE) 169Generate default single-precision SH4a code 170 171m4a-single-only 172Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY) 173Generate only single-precision SH4a code 174 175m4al 176Target RejectNegative Condition(SUPPORT_SH4AL) 177Generate SH4al-dsp code 178 179m5-32media 180Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) 181Generate 32-bit SHmedia code 182 183m5-32media-nofpu 184Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) 185Generate 32-bit FPU-less SHmedia code 186 187m5-64media 188Target RejectNegative Condition(SUPPORT_SH5_64MEDIA) 189Generate 64-bit SHmedia code 190 191m5-64media-nofpu 192Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU) 193Generate 64-bit FPU-less SHmedia code 194 195m5-compact 196Target RejectNegative Condition(SUPPORT_SH5_32MEDIA) 197Generate SHcompact code 198 199m5-compact-nofpu 200Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU) 201Generate FPU-less SHcompact code 202 203madjust-unroll 204Target Report Mask(ADJUST_UNROLL) Condition(SUPPORT_ANY_SH5) 205Throttle unrolling to avoid thrashing target registers unless the unroll benefit outweighs this 206 207mb 208Target Report RejectNegative InverseMask(LITTLE_ENDIAN) 209Generate code in big endian mode 210 211mbigtable 212Target Report RejectNegative Mask(BIGTABLE) 213Generate 32-bit offsets in switch tables 214 215mbitops 216Target Report RejectNegative Mask(BITOPS) 217Generate bit instructions 218 219mbranch-cost= 220Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) 221Cost to assume for a branch insn 222 223mcbranchdi 224Target Var(TARGET_CBRANCHDI4) 225Enable cbranchdi4 pattern 226 227mcmpeqdi 228Target Var(TARGET_CMPEQDI_T) 229Emit cmpeqdi_t pattern even when -mcbranchdi is in effect. 230 231mcut2-workaround 232Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND) 233Enable SH5 cut2 workaround 234 235mdalign 236Target Report RejectNegative Mask(ALIGN_DOUBLE) 237Align doubles at 64-bit boundaries 238 239mdiv= 240Target RejectNegative Joined Var(sh_div_str) Init("") 241Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table 242 243mdivsi3_libfunc= 244Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") 245Specify name for 32 bit signed division function 246 247mfmovd 248Target RejectNegative Mask(FMOVD) 249Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required. 250 251mfixed-range= 252Target RejectNegative Joined Var(sh_fixed_range_str) 253Specify range of registers to make fixed 254 255mfused-madd 256Target Var(TARGET_FMAC) 257Enable the use of the fused floating point multiply-accumulate operation 258 259mgettrcost= 260Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1) 261Cost to assume for gettr insn 262 263mhitachi 264Target Report RejectNegative Mask(HITACHI) 265Follow Renesas (formerly Hitachi) / SuperH calling conventions 266 267mieee 268Target Report Mask(IEEE) 269Increase the IEEE compliance for floating-point code 270 271mindexed-addressing 272Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA) 273Enable the use of the indexed addressing mode for SHmedia32/SHcompact 274 275minline-ic_invalidate 276Target Report Var(TARGET_INLINE_IC_INVALIDATE) 277inline code to invalidate instruction cache entries after setting up nested function trampolines 278 279minvalid-symbols 280Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5) 281Assume symbols might be invalid 282 283misize 284Target Report RejectNegative Mask(DUMPISIZE) 285Annotate assembler instructions with estimated addresses 286 287ml 288Target Report RejectNegative Mask(LITTLE_ENDIAN) 289Generate code in little endian mode 290 291mnomacsave 292Target Report RejectNegative Mask(NOMACSAVE) 293Mark MAC register as call-clobbered 294 295;; ??? This option is not useful, but is retained in case there are people 296;; who are still relying on it. It may be deleted in the future. 297mpadstruct 298Target Report RejectNegative Mask(PADSTRUCT) 299Make structs a multiple of 4 bytes (warning: ABI altered) 300 301mprefergot 302Target Report RejectNegative Mask(PREFERGOT) 303Emit function-calls using global offset table when generating PIC 304 305mpt-fixed 306Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5) 307Assume pt* instructions won't trap 308 309mrelax 310Target Report RejectNegative Mask(RELAX) 311Shorten address references during linking 312 313mrenesas 314Target Mask(HITACHI) MaskExists 315Follow Renesas (formerly Hitachi) / SuperH calling conventions 316 317mspace 318Target Report RejectNegative Mask(SMALLCODE) 319Deprecated. Use -Os instead 320 321multcost= 322Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) 323Cost to assume for a multiply insn 324 325musermode 326Target Report RejectNegative Mask(USERMODE) 327Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode. 328 329;; We might want to enable this by default for TARGET_HARD_SH4, because 330;; zero-offset branches have zero latency. Needs some benchmarking. 331mpretend-cmove 332Target Var(TARGET_PRETEND_CMOVE) 333Pretend a branch-around-a-move is a conditional move. 334