1; Options for the SH port of the compiler. 2 3; Copyright (C) 2005-2020 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15; for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21;; Used for various architecture options. 22Mask(SH_E) 23 24;; Set if the default precision of the FPU is single. 25Mask(FPU_SINGLE) 26 27;; Set if the a double-precision FPU is present but is restricted to 28;; single precision usage only. 29Mask(FPU_SINGLE_ONLY) 30 31;; Set if we should generate code using type 2A insns. 32Mask(HARD_SH2A) 33 34;; Set if we should generate code using type 2A DF insns. 35Mask(HARD_SH2A_DOUBLE) 36 37;; Set if compiling for SH4 hardware (to be used for insn costs etc.) 38Mask(HARD_SH4) 39 40m1 41Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1) 42Generate SH1 code. 43 44m2 45Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2) 46Generate SH2 code. 47 48m2a 49Target RejectNegative Condition(SUPPORT_SH2A) 50Generate default double-precision SH2a-FPU code. 51 52m2a-nofpu 53Target RejectNegative Condition(SUPPORT_SH2A_NOFPU) 54Generate SH2a FPU-less code. 55 56m2a-single 57Target RejectNegative Condition(SUPPORT_SH2A_SINGLE) 58Generate default single-precision SH2a-FPU code. 59 60m2a-single-only 61Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY) 62Generate only single-precision SH2a-FPU code. 63 64m2e 65Target RejectNegative Condition(SUPPORT_SH2E) 66Generate SH2e code. 67 68m3 69Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) 70Generate SH3 code. 71 72m3e 73Target RejectNegative Condition(SUPPORT_SH3E) 74Generate SH3e code. 75 76m4 77Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4) 78Generate SH4 code. 79 80m4-100 81Target RejectNegative Condition(SUPPORT_SH4) 82Generate SH4-100 code. 83 84m4-200 85Target RejectNegative Condition(SUPPORT_SH4) 86Generate SH4-200 code. 87 88;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and 89;; pipeline - irrespective of ABI. 90m4-300 91Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300) 92Generate SH4-300 code. 93 94m4-nofpu 95Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 96Generate SH4 FPU-less code. 97 98m4-100-nofpu 99Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 100Generate SH4-100 FPU-less code. 101 102m4-200-nofpu 103Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 104Generate SH4-200 FPU-less code. 105 106m4-300-nofpu 107Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) 108Generate SH4-300 FPU-less code. 109 110m4-340 111Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300) 112Generate code for SH4 340 series (MMU/FPU-less). 113;; passes -isa=sh4-nommu-nofpu to the assembler. 114 115m4-400 116Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 117Generate code for SH4 400 series (MMU/FPU-less). 118;; passes -isa=sh4-nommu-nofpu to the assembler. 119 120m4-500 121Target RejectNegative Condition(SUPPORT_SH4_NOFPU) 122Generate code for SH4 500 series (FPU-less). 123;; passes -isa=sh4-nofpu to the assembler. 124 125m4-single 126Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 127Generate default single-precision SH4 code. 128 129m4-100-single 130Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 131Generate default single-precision SH4-100 code. 132 133m4-200-single 134Target RejectNegative Condition(SUPPORT_SH4_SINGLE) 135Generate default single-precision SH4-200 code. 136 137m4-300-single 138Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300) 139Generate default single-precision SH4-300 code. 140 141m4-single-only 142Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 143Generate only single-precision SH4 code. 144 145m4-100-single-only 146Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 147Generate only single-precision SH4-100 code. 148 149m4-200-single-only 150Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) 151Generate only single-precision SH4-200 code. 152 153m4-300-single-only 154Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300) 155Generate only single-precision SH4-300 code. 156 157m4a 158Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A) 159Generate SH4a code. 160 161m4a-nofpu 162Target RejectNegative Condition(SUPPORT_SH4A_NOFPU) 163Generate SH4a FPU-less code. 164 165m4a-single 166Target RejectNegative Condition(SUPPORT_SH4A_SINGLE) 167Generate default single-precision SH4a code. 168 169m4a-single-only 170Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY) 171Generate only single-precision SH4a code. 172 173m4al 174Target RejectNegative Condition(SUPPORT_SH4AL) 175Generate SH4al-dsp code. 176 177maccumulate-outgoing-args 178Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1) 179Reserve space for outgoing arguments in the function prologue. 180 181mb 182Target Report RejectNegative InverseMask(LITTLE_ENDIAN) 183Generate code in big endian mode. 184 185mbigtable 186Target Report RejectNegative Mask(BIGTABLE) 187Generate 32-bit offsets in switch tables. 188 189mbitops 190Target Report RejectNegative Mask(BITOPS) 191Generate bit instructions. 192 193mbranch-cost= 194Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1) 195Cost to assume for a branch insn. 196 197mzdcbranch 198Target Report Var(TARGET_ZDCBRANCH) 199Assume that zero displacement conditional branches are fast. 200 201mcbranch-force-delay-slot 202Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0) 203Force the usage of delay slots for conditional branches. 204 205mdalign 206Target Report RejectNegative Mask(ALIGN_DOUBLE) 207Align doubles at 64-bit boundaries. 208 209mdiv= 210Target RejectNegative Joined Var(sh_div_str) Init("") 211Division strategy, one of: call-div1, call-fp, call-table. 212 213mdivsi3_libfunc= 214Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("") 215Specify name for 32 bit signed division function. 216 217mfdpic 218Target Report Var(TARGET_FDPIC) Init(0) 219Generate ELF FDPIC code. 220 221mfmovd 222Target RejectNegative Mask(FMOVD) 223Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required. 224 225mfixed-range= 226Target RejectNegative Joined Var(sh_fixed_range_str) 227Specify range of registers to make fixed. 228 229mhitachi 230Target Report RejectNegative Mask(HITACHI) 231Follow Renesas (formerly Hitachi) / SuperH calling conventions. 232 233mieee 234Target Var(TARGET_IEEE) 235Increase the IEEE compliance for floating-point comparisons. 236 237minline-ic_invalidate 238Target Report Var(TARGET_INLINE_IC_INVALIDATE) 239Inline code to invalidate instruction cache entries after setting up nested function trampolines. 240 241misize 242Target Report RejectNegative Mask(DUMPISIZE) 243Annotate assembler instructions with estimated addresses. 244 245ml 246Target Report RejectNegative Mask(LITTLE_ENDIAN) 247Generate code in little endian mode. 248 249mnomacsave 250Target Report RejectNegative Mask(NOMACSAVE) 251Mark MAC register as call-clobbered. 252 253;; ??? This option is not useful, but is retained in case there are people 254;; who are still relying on it. It may be deleted in the future. 255mpadstruct 256Target Report RejectNegative Mask(PADSTRUCT) 257Make structs a multiple of 4 bytes (warning: ABI altered). 258 259mprefergot 260Target Report RejectNegative Mask(PREFERGOT) 261Emit function-calls using global offset table when generating PIC. 262 263mrelax 264Target Report RejectNegative Mask(RELAX) 265Shorten address references during linking. 266 267mrenesas 268Target Mask(HITACHI) 269Follow Renesas (formerly Hitachi) / SuperH calling conventions. 270 271matomic-model= 272Target Report RejectNegative Joined Var(sh_atomic_model_str) 273Specify the model for atomic operations. 274 275mtas 276Target Report RejectNegative Var(TARGET_ENABLE_TAS) 277Use tas.b instruction for __atomic_test_and_set. 278 279multcost= 280Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) 281Cost to assume for a multiply insn. 282 283musermode 284Target Var(TARGET_USERMODE) 285Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode. 286 287;; We might want to enable this by default for TARGET_HARD_SH4, because 288;; zero-offset branches have zero latency. Needs some benchmarking. 289mpretend-cmove 290Target Var(TARGET_PRETEND_CMOVE) 291Pretend a branch-around-a-move is a conditional move. 292 293mfsca 294Target Var(TARGET_FSCA) 295Enable the use of the fsca instruction. 296 297mfsrra 298Target Var(TARGET_FSRRA) 299Enable the use of the fsrra instruction. 300 301mlra 302Target Report Var(sh_lra_flag) Init(0) Save 303Use LRA instead of reload (transitional). 304