sh.md revision 1.8
1;;- Machine description for Renesas / SuperH SH. 2;; Copyright (C) 1993-2017 Free Software Foundation, Inc. 3;; Contributed by Steve Chamberlain (sac@cygnus.com). 4;; Improved by Jim Wilson (wilson@cygnus.com). 5 6;; This file is part of GCC. 7 8;; GCC is free software; you can redistribute it and/or modify 9;; it under the terms of the GNU General Public License as published by 10;; the Free Software Foundation; either version 3, or (at your option) 11;; any later version. 12 13;; GCC is distributed in the hope that it will be useful, 14;; but WITHOUT ANY WARRANTY; without even the implied warranty of 15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16;; GNU General Public License for more details. 17 18;; You should have received a copy of the GNU General Public License 19;; along with GCC; see the file COPYING3. If not see 20;; <http://www.gnu.org/licenses/>. 21 22 23;; ??? Should prepend a * to all pattern names which are not used. 24;; This will make the compiler smaller, and rebuilds after changes faster. 25 26;; ??? Should be enhanced to include support for many more GNU superoptimizer 27;; sequences. Especially the sequences for arithmetic right shifts. 28 29;; ??? Should check all DImode patterns for consistency and usefulness. 30 31;; ??? The MAC.W and MAC.L instructions are not supported. There is no 32;; way to generate them. 33 34;; BSR is not generated by the compiler proper, but when relaxing, it 35;; generates .uses pseudo-ops that allow linker relaxation to create 36;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c 37 38;; Special constraints for SH machine description: 39;; 40;; t -- T 41;; x -- mac 42;; l -- pr 43;; z -- r0 44;; 45;; Special formats used for outputting SH instructions: 46;; 47;; %. -- print a .s if insn needs delay slot 48;; %@ -- print rte/rts if is/isn't an interrupt function 49;; %# -- output a nop if there is nothing to put in the delay slot 50;; %O -- print a constant without the # 51;; %R -- print the lsw reg of a double 52;; %S -- print the msw reg of a double 53;; %T -- print next word of a double REG or MEM 54;; 55;; Special predicates: 56;; 57;; arith_operand -- operand is valid source for arithmetic op 58;; arith_reg_operand -- operand is valid register for arithmetic op 59;; general_movdst_operand -- operand is valid move destination 60;; general_movsrc_operand -- operand is valid move source 61;; logical_operand -- operand is valid source for logical op 62 63;; ------------------------------------------------------------------------- 64;; Constants 65;; ------------------------------------------------------------------------- 66 67(define_constants [ 68 (AP_REG 145) 69 (PR_REG 146) 70 (T_REG 147) 71 (GBR_REG 144) 72 (MACH_REG 148) 73 (MACL_REG 149) 74 (FPUL_REG 150) 75 (RAP_REG 152) 76 77 (FPSCR_REG 151) 78 79 ;; Virtual FPSCR - bits that are used by FP ops. 80 (FPSCR_MODES_REG 154) 81 82 ;; Virtual FPSCR - bits that are updated by FP ops. 83 (FPSCR_STAT_REG 155) 84 85 (PIC_REG 12) 86 (FP_REG 14) 87 (SP_REG 15) 88 89 (R0_REG 0) 90 (R1_REG 1) 91 (R2_REG 2) 92 (R3_REG 3) 93 (R4_REG 4) 94 (R5_REG 5) 95 (R6_REG 6) 96 (R7_REG 7) 97 (R8_REG 8) 98 (R9_REG 9) 99 (R10_REG 10) 100 (R20_REG 20) 101 (R21_REG 21) 102 (R22_REG 22) 103 (R23_REG 23) 104 105 (DR0_REG 64) 106 (DR2_REG 66) 107 (DR4_REG 68) 108 109 (XD0_REG 136) 110 111 (FPSCR_PR 524288) ;; 1 << 19 112 (FPSCR_SZ 1048576) ;; 1 << 20 113 (FPSCR_FR 2097152) ;; 1 << 21 114]) 115 116(define_c_enum "unspec" [ 117 ;; These are used with unspec. 118 UNSPEC_MOVA 119 UNSPEC_CASESI 120 UNSPEC_BBR 121 UNSPEC_SFUNC 122 UNSPEC_PIC 123 UNSPEC_GOT 124 UNSPEC_GOTOFF 125 UNSPEC_PLT 126 UNSPEC_CALLER 127 UNSPEC_GOTPLT 128 UNSPEC_PCREL 129 UNSPEC_ICACHE 130 UNSPEC_FCOSA 131 UNSPEC_FSRRA 132 UNSPEC_FSINA 133 UNSPEC_ALLOCO 134 UNSPEC_TLSGD 135 UNSPEC_TLSLDM 136 UNSPEC_TLSIE 137 UNSPEC_DTPOFF 138 UNSPEC_GOTTPOFF 139 UNSPEC_TPOFF 140 UNSPEC_RA 141 UNSPEC_THUNK 142 UNSPEC_CHKADD 143 UNSPEC_SP_SET 144 UNSPEC_SP_TEST 145 UNSPEC_MOVUA 146 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR. 147 UNSPEC_SYMOFF 148 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .). 149 UNSPEC_PCREL_SYMOFF 150 ;; For FDPIC 151 UNSPEC_GOTFUNCDESC 152 UNSPEC_GOTOFFFUNCDESC 153 ;; Misc builtins 154 UNSPEC_BUILTIN_STRLEN 155]) 156 157(define_c_enum "unspecv" [ 158 ;; These are used with unspec_volatile. 159 UNSPECV_BLOCKAGE 160 UNSPECV_ALIGN 161 UNSPECV_CONST2 162 UNSPECV_CONST4 163 UNSPECV_CONST8 164 UNSPECV_WINDOW_END 165 UNSPECV_CONST_END 166 UNSPECV_EH_RETURN 167 UNSPECV_GBR 168 UNSPECV_SP_SWITCH_B 169 UNSPECV_SP_SWITCH_E 170 171 UNSPECV_FPSCR_MODES 172 UNSPECV_FPSCR_STAT 173]) 174 175;; ------------------------------------------------------------------------- 176;; Attributes 177;; ------------------------------------------------------------------------- 178 179;; Target CPU. 180 181(define_attr "cpu" 182 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a" 183 (const (symbol_ref "sh_cpu_attr"))) 184 185(define_attr "endian" "big,little" 186 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN") 187 (const_string "little") (const_string "big")))) 188 189;; Indicate if the default fpu mode is single precision. 190(define_attr "fpu_single" "yes,no" 191 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE") 192 (const_string "yes") (const_string "no")))) 193 194(define_attr "fmovd" "yes,no" 195 (const (if_then_else (symbol_ref "TARGET_FMOVD") 196 (const_string "yes") (const_string "no")))) 197;; pipeline model 198(define_attr "pipe_model" "sh1,sh4" 199 (const 200 (cond [(symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")] 201 (const_string "sh1")))) 202 203;; cbranch conditional branch instructions 204;; jump unconditional jumps 205;; arith ordinary arithmetic 206;; arith3 a compound insn that behaves similarly to a sequence of 207;; three insns of type arith 208;; arith3b like above, but might end with a redirected branch 209;; load from memory 210;; load_si Likewise, SImode variant for general register. 211;; fload Likewise, but load to fp register. 212;; store to memory 213;; fstore floating point register to memory 214;; move general purpose register to register 215;; movi8 8-bit immediate to general purpose register 216;; mt_group other sh4 mt instructions 217;; fmove register to register, floating point 218;; smpy word precision integer multiply 219;; dmpy longword or doublelongword precision integer multiply 220;; return rts 221;; pload load of pr reg, which can't be put into delay slot of rts 222;; prset copy register to pr reg, ditto 223;; pstore store of pr reg, which can't be put into delay slot of jsr 224;; prget copy pr to register, ditto 225;; pcload pc relative load of constant value 226;; pcfload Likewise, but load to fp register. 227;; pcload_si Likewise, SImode variant for general register. 228;; rte return from exception 229;; sfunc special function call with known used registers 230;; call function call 231;; fp floating point 232;; fpscr_toggle toggle a bit in the fpscr 233;; fdiv floating point divide (or square root) 234;; gp_fpul move from general purpose register to fpul 235;; fpul_gp move from fpul to general purpose register 236;; mac_gp move from mac[lh] to general purpose register 237;; gp_mac move from general purpose register to mac[lh] 238;; mac_mem move from mac[lh] to memory 239;; mem_mac move from memory to mac[lh] 240;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv 241;; ftrc_s fix_truncsfsi2_i4 242;; dfdiv double precision floating point divide (or square root) 243;; cwb ic_invalidate_line_i 244;; movua SH4a unaligned load 245;; fsrra square root reciprocal approximate 246;; fsca sine and cosine approximate 247;; tls_load load TLS related address 248;; nil no-op move, will be deleted. 249 250(define_attr "type" 251 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si, 252 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore, 253 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s, 254 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp, 255 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load, 256 nil,other" 257 (const_string "other")) 258 259;; We define a new attribute namely "insn_class".We use 260;; this for the DFA based pipeline description. 261;; 262;; mt_group SH4 "mt" group instructions. 263;; 264;; ex_group SH4 "ex" group instructions. 265;; 266;; ls_group SH4 "ls" group instructions. 267;; 268(define_attr "insn_class" 269 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none" 270 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group") 271 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group") 272 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload, 273 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group") 274 (eq_attr "type" "cbranch,jump") (const_string "br_group") 275 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv") 276 (const_string "fe_group") 277 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore, 278 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb, 279 gp_mac,mac_mem,mem_mac") (const_string "co_group")] 280 (const_string "none"))) 281 282;; nil are zero instructions, and arith3 / arith3b are multiple instructions, 283;; so these do not belong in an insn group, although they are modeled 284;; with their own define_insn_reservations. 285 286;; Indicate what precision must be selected in fpscr for this insn, if any. 287(define_attr "fp_mode" "single,double,none" (const_string "none")) 288 289;; Indicate if the fpu mode is set by this instruction 290;; "unknown" must have the value as "none" in fp_mode, and means 291;; that the instruction/abi has left the processor in an unknown 292;; state. 293;; "none" means that nothing has changed and no mode is set. 294;; This attribute is only used for the Renesas ABI. 295(define_attr "fp_set" "single,double,unknown,none" (const_string "none")) 296 297; If a conditional branch destination is within -252..258 bytes away 298; from the instruction it can be 2 bytes long. Something in the 299; range -4090..4100 bytes can be 6 bytes long. All other conditional 300; branches are initially assumed to be 16 bytes long. 301; In machine_dependent_reorg, we split all branches that are longer than 302; 2 bytes. 303 304;; The maximum range used for SImode constant pool entries is 1018. A final 305;; instruction can add 8 bytes while only being 4 bytes in size, thus we 306;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch 307;; instruction around the pool table, 2 bytes of alignment before the table, 308;; and 30 bytes of alignment after the table. That gives a maximum total 309;; pool size of 1058 bytes. 310;; Worst case code/pool content size ratio is 1:2 (using asms). 311;; Thus, in the worst case, there is one instruction in front of a maximum 312;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of 313;; code. For the last n bytes of code, there are 2n + 36 bytes of pool. 314;; If we have a forward branch, the initial table will be put after the 315;; unconditional branch. 316;; 317;; ??? We could do much better by keeping track of the actual pcloads within 318;; the branch range and in the pcload range in front of the branch range. 319 320;; ??? This looks ugly because genattrtab won't allow if_then_else or cond 321;; inside an le. 322(define_attr "short_cbranch_p" "no,yes" 323 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD") 324 (const_string "no") 325 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506)) 326 (const_string "yes") 327 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn") 328 (const_string "no") 329 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508)) 330 (const_string "yes") 331 ] (const_string "no"))) 332 333(define_attr "med_branch_p" "no,yes" 334 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990)) 335 (const_int 1988)) 336 (const_string "yes") 337 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD") 338 (const_string "no") 339 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092)) 340 (const_int 8186)) 341 (const_string "yes") 342 ] (const_string "no"))) 343 344(define_attr "med_cbranch_p" "no,yes" 345 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988)) 346 (const_int 1986)) 347 (const_string "yes") 348 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD") 349 (const_string "no") 350 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090)) 351 (const_int 8184)) 352 (const_string "yes") 353 ] (const_string "no"))) 354 355(define_attr "braf_branch_p" "no,yes" 356 (cond [(match_test "! TARGET_SH2") 357 (const_string "no") 358 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330)) 359 (const_int 20660)) 360 (const_string "yes") 361 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD") 362 (const_string "no") 363 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764)) 364 (const_int 65530)) 365 (const_string "yes") 366 ] (const_string "no"))) 367 368(define_attr "braf_cbranch_p" "no,yes" 369 (cond [(match_test "! TARGET_SH2") 370 (const_string "no") 371 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328)) 372 (const_int 20658)) 373 (const_string "yes") 374 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD") 375 (const_string "no") 376 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762)) 377 (const_int 65528)) 378 (const_string "yes") 379 ] (const_string "no"))) 380 381;; An unconditional jump in the range -4092..4098 can be 2 bytes long. 382;; For wider ranges, we need a combination of a code and a data part. 383;; If we can get a scratch register for a long range jump, the code 384;; part can be 4 bytes long; otherwise, it must be 8 bytes long. 385;; If the jump is in the range -32764..32770, the data part can be 2 bytes 386;; long; otherwise, it must be 6 bytes long. 387 388;; All other instructions are two bytes long by default. 389 390;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)), 391;; but getattrtab doesn't understand this. 392(define_attr "length" "" 393 (cond [(eq_attr "type" "cbranch") 394 (cond [(eq_attr "short_cbranch_p" "yes") 395 (const_int 2) 396 (eq_attr "med_cbranch_p" "yes") 397 (const_int 6) 398 (eq_attr "braf_cbranch_p" "yes") 399 (const_int 12) 400;; ??? using pc is not computed transitively. 401 (ne (match_dup 0) (match_dup 0)) 402 (const_int 14) 403 (match_test "flag_pic") 404 (const_int 24) 405 ] (const_int 16)) 406 (eq_attr "type" "jump") 407 (cond [(eq_attr "med_branch_p" "yes") 408 (const_int 2) 409 (and (match_test "prev_nonnote_insn (insn)") 410 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))") 411 (symbol_ref "INSN")) 412 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))") 413 (symbol_ref "code_for_indirect_jump_scratch")))) 414 (cond [(eq_attr "braf_branch_p" "yes") 415 (const_int 6) 416 (not (match_test "flag_pic")) 417 (const_int 10) 418 (match_test "TARGET_SH2") 419 (const_int 10)] (const_int 18)) 420 (eq_attr "braf_branch_p" "yes") 421 (const_int 10) 422;; ??? using pc is not computed transitively. 423 (ne (match_dup 0) (match_dup 0)) 424 (const_int 12) 425 (match_test "flag_pic") 426 (const_int 22) 427 ] (const_int 14)) 428 ] (const_int 2))) 429 430;; DFA descriptions for the pipelines 431 432(include "sh1.md") 433(include "sh4.md") 434 435(include "iterators.md") 436(include "predicates.md") 437(include "constraints.md") 438 439;; Definitions for filling delay slots 440 441(define_attr "needs_delay_slot" "yes,no" (const_string "no")) 442 443(define_attr "banked" "yes,no" 444 (cond [(match_test "sh_loads_bankedreg_p (insn)") 445 (const_string "yes")] 446 (const_string "no"))) 447 448;; ??? This should be (nil) instead of (const_int 0) 449(define_attr "hit_stack" "yes,no" 450 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)")) 451 (const_string "no")] 452 (const_string "yes"))) 453 454(define_attr "interrupt_function" "no,yes" 455 (const (symbol_ref "current_function_interrupt"))) 456 457(define_attr "in_delay_slot" "yes,no" 458 (cond [(eq_attr "type" "cbranch") (const_string "no") 459 (eq_attr "type" "pcload,pcload_si") (const_string "no") 460 (eq_attr "type" "fpscr_toggle") (const_string "no") 461 (eq_attr "needs_delay_slot" "yes") (const_string "no") 462 (eq_attr "length" "2") (const_string "yes") 463 ] (const_string "no"))) 464 465(define_attr "cond_delay_slot" "yes,no" 466 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes") 467 ] (const_string "no"))) 468 469(define_attr "is_sfunc" "" 470 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0))) 471 472;; SH4 Double-precision computation with double-precision result - 473;; the two halves are ready at different times. 474(define_attr "dfp_comp" "yes,no" 475 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")] 476 (const_string "no"))) 477 478;; Insns for which the latency of a preceding fp insn is decreased by one. 479(define_attr "late_fp_use" "yes,no" (const_string "no")) 480;; And feeding insns for which this relevant. 481(define_attr "any_fp_comp" "yes,no" 482 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv") 483 (const_string "yes")] 484 (const_string "no"))) 485 486(define_attr "any_int_load" "yes,no" 487 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si") 488 (const_string "yes")] 489 (const_string "no"))) 490 491(define_attr "highpart" "user, ignore, extend, depend, must_split" 492 (const_string "user")) 493 494(define_delay 495 (eq_attr "needs_delay_slot" "yes") 496 [(eq_attr "in_delay_slot" "yes") (nil) (nil)]) 497 498;; Since a normal return (rts) implicitly uses the PR register, 499;; we can't allow PR register loads in an rts delay slot. 500;; On the SH1* and SH2*, the rte instruction reads the return pc from the 501;; stack, and thus we can't put a pop instruction in its delay slot. 502;; On the SH3* and SH4*, the rte instruction does not use the stack, so a 503;; pop instruction can go in the delay slot, unless it references a banked 504;; register (the register bank is switched by rte). 505(define_delay 506 (eq_attr "type" "return") 507 [(and (eq_attr "in_delay_slot" "yes") 508 (ior (and (eq_attr "interrupt_function" "no") 509 (eq_attr "type" "!pload,prset")) 510 (and (eq_attr "interrupt_function" "yes") 511 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no")) 512 (eq_attr "banked" "no")))) 513 (nil) (nil)]) 514 515;; Since a call implicitly uses the PR register, we can't allow 516;; a PR register store in a jsr delay slot. 517 518(define_delay 519 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc")) 520 [(and (eq_attr "in_delay_slot" "yes") 521 (eq_attr "type" "!pstore,prget")) (nil) (nil)]) 522 523;; Conditional branches with delay slots are available starting with SH2. 524;; If zero displacement conditional branches are fast, disable the delay 525;; slot if the branch jumps over only one 2-byte insn. 526(define_delay 527 (and (eq_attr "type" "cbranch") 528 (match_test "TARGET_SH2") 529 (not (and (match_test "TARGET_ZDCBRANCH") 530 (match_test "sh_cbranch_distance (insn, 4) == 2")))) 531 [(eq_attr "cond_delay_slot" "yes") (nil) (nil)]) 532 533;; ------------------------------------------------------------------------- 534;; SImode signed integer comparisons 535;; ------------------------------------------------------------------------- 536 537;; Patterns to generate the tst instruction which are usually formed by 538;; the combine pass. 539;; The canonical form here being used is (eq (and (op) (op)) 0). 540;; For some bit patterns, such as contiguous bits, we also must accept 541;; zero_extract forms. Single bit tests are also handled via zero_extract 542;; patterns in the 'bit field extract patterns' section. All variants 543;; are eventually converted to the 'tstsi_t' insn. 544;; As long as pseudos can be created (before RA), 'tstsi_t' will also accept 545;; constants that won't fit into 8 bits. After having captured the constant 546;; we can decide better whether/how to load it into a register and do other 547;; post-combine optimizations such as bypassing sign/zero extensions. 548(define_insn_and_split "tstsi_t" 549 [(set (reg:SI T_REG) 550 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "%z,r") 551 (match_operand:SI 1 "arith_or_int_operand" "K08,?r")) 552 (const_int 0)))] 553 "TARGET_SH1 554 && (can_create_pseudo_p () || arith_reg_operand (operands[1], SImode) 555 || satisfies_constraint_K08 (operands[1]))" 556 "tst %1,%0" 557 "TARGET_SH1 && can_create_pseudo_p () && CONST_INT_P (operands[1]) 558 && !sh_in_recog_treg_set_expr ()" 559 [(const_int 0)] 560{ 561 gcc_assert (CONST_INT_P (operands[1])); 562 563 HOST_WIDE_INT op1val = INTVAL (operands[1]); 564 rtx reg = operands[0]; 565 if (SUBREG_P (reg)) 566 reg = SUBREG_REG (reg); 567 gcc_assert (REG_P (reg)); 568 bool op0_dead_after_this = 569 sh_reg_dead_or_unused_after_insn (curr_insn, REGNO (reg)); 570 571 if (optimize) 572 { 573 if (dump_file) 574 fprintf (dump_file, 575 "tstsi_t: trying to optimize const_int 0x%08x\n", 576 (uint32_t)op1val); 577 578 /* See if we can convert a test with a reg and a constant into 579 something simpler, if the reg is known to be zero or sign 580 extended. */ 581 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0], 582 curr_insn); 583 if (eop0.ext_code != UNKNOWN) 584 { 585 /* Adjust the constant, trying to eliminate bits that are not 586 contributing to the result. */ 587 if (eop0.from_mode == QImode) 588 op1val = (op1val 589 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFFFF80) 590 ? 0x80 : 0)) & 0xFF; 591 else if (eop0.from_mode == HImode) 592 op1val = (op1val 593 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFF8000) 594 ? 0x8000 : 0)) & 0xFFFF; 595 596 if (dump_file) 597 fprintf (dump_file, "tstsi_t: using effective const_int: 0x%08x\n", 598 (uint32_t)op1val); 599 600 /* Try to bypass the sign/zero extension first if op0 dies after 601 this insn. */ 602 if (op0_dead_after_this && eop0.can_use_as_unextended_reg ()) 603 { 604 if (dump_file) 605 fprintf (dump_file, "tstsi_t: bypassing sign/zero extension\n"); 606 607 operands[0] = eop0.use_as_unextended_reg (curr_insn); 608 } 609 else if ((eop0.from_mode == QImode && op1val == 0xFF) 610 || (eop0.from_mode == HImode && op1val == 0xFFFF)) 611 { 612 if (dump_file) 613 fprintf (dump_file, "tstsi_t: converting to cmpeqsi_t\n"); 614 emit_insn (gen_cmpeqsi_t (eop0.use_as_extended_reg (curr_insn), 615 const0_rtx)); 616 DONE; 617 } 618 else if (eop0.ext_code == SIGN_EXTEND 619 && ((eop0.from_mode == QImode && op1val == 0x80) 620 || (eop0.from_mode == HImode && op1val == 0x8000))) 621 { 622 if (dump_file) 623 fprintf (dump_file, "tstsi_t: converting to cmpgesi_t\n"); 624 emit_insn (gen_cmpgesi_t (eop0.use_as_extended_reg (curr_insn), 625 const0_rtx)); 626 DONE; 627 } 628 else if (!CONST_OK_FOR_K08 (op1val)) 629 { 630 if (dump_file) 631 fprintf (dump_file, "tstsi_t: converting const_int to signed " 632 "value\n"); 633 634 /* If here we haven't done anything yet. Convert the constant 635 to a signed value to reduce the constant pool size. */ 636 operands[0] = eop0.use_as_extended_reg (curr_insn); 637 638 if (eop0.from_mode == QImode) 639 op1val |= (op1val & 0x80) ? 0xFFFFFFFFFFFFFF00LL : 0; 640 else if (eop0.from_mode == HImode) 641 op1val |= (op1val & 0x8000) ? 0xFFFFFFFFFFFF0000LL : 0; 642 } 643 else 644 operands[0] = eop0.use_as_extended_reg (curr_insn); 645 } 646 } 647 648 if (dump_file) 649 fprintf (dump_file, "tstsi_t: using const_int 0x%08x\n", 650 (uint32_t)op1val); 651 652 /* Try to fit the constant into 8 bits by shuffling the value in the 653 register operand. 654 Doing that usually results in smaller code as the constants in the 655 pools are avoided (32 bit constant = load + constant = 6 bytes). 656 However, if the constant load (LS insn) can be hoisted insn dependencies 657 can be avoided and chances for parallel execution increase. The common 658 usage pattern is: 659 - load reg from mem 660 - test bits 661 - conditional branch 662 663 FIXME: For now we do that only when optimizing for size until there is 664 a better heuristic. 665 666 FIXME: If there are multiple tst insns in the block with the same 667 constant, avoid the #imm variant to avoid R0 loads. Use the 'tst Rn,Rm' 668 variant instead and load the constant into a reg. For that we'd need 669 to do some analysis. */ 670 671 if (CONST_OK_FOR_K08 (op1val)) 672 { 673 /* Do nothing. */ 674 } 675 else if ((op1val & 0xFFFF) == 0 676 && CONST_OK_FOR_K08 (op1val >> 16) && optimize_size) 677 { 678 /* Use a swap.w insn to do a shift + reg copy (to R0) in one insn. */ 679 op1val = op1val >> 16; 680 rtx r = gen_reg_rtx (SImode); 681 emit_insn (gen_rotlsi3_16 (r, operands[0])); 682 operands[0] = r; 683 } 684 else if ((op1val & 0xFF) == 0 685 && CONST_OK_FOR_K08 (op1val >> 8) && optimize_size) 686 { 687 /* Use a swap.b insn to do a shift + reg copy (to R0) in one insn. */ 688 op1val = op1val >> 8; 689 rtx r = gen_reg_rtx (SImode); 690 emit_insn (gen_swapbsi2 (r, operands[0])); 691 operands[0] = r; 692 } 693 else if ((op1val & 3) == 0 694 && CONST_OK_FOR_K08 (op1val >> 2) && optimize_size) 695 { 696 op1val = op1val >> 2; 697 rtx r = gen_reg_rtx (SImode); 698 emit_insn (gen_lshrsi3_k (r, operands[0], GEN_INT (2))); 699 operands[0] = r; 700 } 701 else if ((op1val & 1) == 0 702 && CONST_OK_FOR_K08 (op1val >> 1) && optimize_size) 703 { 704 op1val = op1val >> 1; 705 rtx r = gen_reg_rtx (SImode); 706 emit_insn (gen_shlr (r, operands[0])); 707 operands[0] = r; 708 } 709 710 operands[1] = GEN_INT (op1val); 711 712 if (!satisfies_constraint_K08 (operands[1])) 713 operands[1] = force_reg (SImode, operands[1]); 714 715 emit_insn (gen_tstsi_t (operands[0], operands[1])); 716 DONE; 717} 718 [(set_attr "type" "mt_group")]) 719 720;; This pattern is used by combine when testing QI/HImode subregs with a 721;; negative constant. Ignore high bits by masking them out in the constant. 722(define_insn_and_split "*tst<mode>_t" 723 [(set (reg:SI T_REG) 724 (eq:SI (subreg:SI 725 (and:QIHI (match_operand:QIHI 0 "arith_reg_operand") 726 (match_operand 1 "const_int_operand")) 0) 727 (const_int 0)))] 728 "TARGET_SH1 && can_create_pseudo_p ()" 729 "#" 730 "&& 1" 731 [(set (reg:SI T_REG) 732 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))] 733{ 734 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0); 735 operands[1] = GEN_INT (INTVAL (operands[1]) 736 & (<MODE>mode == HImode ? 0xFFFF : 0xFF)); 737}) 738 739;; This pattern might be risky because it also tests the upper bits and not 740;; only the subreg. We have to check whether the operands have been sign 741;; or zero extended. In the worst case, a zero extension has to be inserted 742;; to mask out the unwanted bits. 743(define_insn_and_split "*tst<mode>_t_subregs" 744 [(set (reg:SI T_REG) 745 (eq:SI 746 (subreg:QIHI 747 (and:SI (match_operand:SI 0 "arith_reg_operand") 748 (match_operand:SI 1 "arith_reg_operand")) <lowpart_le>) 749 (const_int 0)))] 750 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()" 751 "#" 752 "&& !sh_in_recog_treg_set_expr ()" 753 [(const_int 0)] 754{ 755 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_le>, operands); 756 DONE; 757}) 758 759(define_insn_and_split "*tst<mode>_t_subregs" 760 [(set (reg:SI T_REG) 761 (eq:SI 762 (subreg:QIHI 763 (and:SI (match_operand:SI 0 "arith_reg_operand") 764 (match_operand:SI 1 "arith_reg_operand")) <lowpart_be>) 765 (const_int 0)))] 766 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()" 767 "#" 768 "&& !sh_in_recog_treg_set_expr ()" 769 [(const_int 0)] 770{ 771 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_be>, operands); 772 DONE; 773}) 774 775;; Extract contiguous bits and compare them against zero. 776;; Notice that this will not be used for single bits. Special single bit 777;; extraction patterns are in the 'bit field extract patterns' section. 778(define_insn_and_split "*tst<mode>_t_zero_extract" 779 [(set (reg:SI T_REG) 780 (eq:SI (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand") 781 (match_operand 1 "const_int_operand") 782 (match_operand 2 "const_int_operand")) 783 (const_int 0)))] 784 "TARGET_SH1 && can_create_pseudo_p ()" 785 "#" 786 "&& 1" 787 [(set (reg:SI T_REG) 788 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))] 789{ 790 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2])); 791 if (GET_MODE (operands[0]) != SImode) 792 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0); 793}) 794 795;; Convert '(reg << shift) & mask' into 'reg & (mask >> shift)'. 796;; The shifted-out bits in the mask will always be zero, since the 797;; shifted-in bits in the reg will also be always zero. 798(define_insn_and_split "*tstsi_t_shift_mask" 799 [(set (reg:SI T_REG) 800 (eq:SI (and:SI (ashift:SI (match_operand:SI 0 "arith_reg_operand") 801 (match_operand 1 "const_int_operand")) 802 (match_operand 2 "const_int_operand")) 803 (const_int 0)))] 804 "TARGET_SH1 && can_create_pseudo_p ()" 805 "#" 806 "&& 1" 807 [(set (reg:SI T_REG) 808 (eq:SI (and:SI (match_dup 0) (match_dup 2)) (const_int 0)))] 809{ 810 operands[2] = GEN_INT (INTVAL (operands[2]) >> INTVAL (operands[1])); 811}) 812 813(define_insn "cmpeqsi_t" 814 [(set (reg:SI T_REG) 815 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r") 816 (match_operand:SI 1 "arith_operand" "N,rI08,r")))] 817 "TARGET_SH1" 818 "@ 819 tst %0,%0 820 cmp/eq %1,%0 821 cmp/eq %1,%0" 822 [(set_attr "type" "mt_group")]) 823 824;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn. 825;; Try to fix that in the split1 pass by looking for the previous set 826;; of the tested op. Also see if there is a preceeding sign/zero 827;; extension that can be avoided. 828(define_split 829 [(set (reg:SI T_REG) 830 (eq:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))] 831 "TARGET_SH1 && can_create_pseudo_p () && optimize 832 && !sh_in_recog_treg_set_expr ()" 833 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))] 834{ 835 if (dump_file) 836 fprintf (dump_file, "cmpeqsi_t: trying to optimize const_int 0\n"); 837 838 /* If the tested reg is not dead after this insn, it's probably used by 839 something else after the comparison. It's probably better to leave 840 it as it is. */ 841 rtx reg = operands[0]; 842 if (SUBREG_P (reg)) 843 reg = SUBREG_REG (reg); 844 gcc_assert (REG_P (reg)); 845 if (find_regno_note (curr_insn, REG_DEAD, REGNO (reg)) != NULL_RTX) 846 FAIL; 847 848 /* FIXME: Maybe also search the predecessor basic blocks to catch 849 more cases. */ 850 set_of_reg op = sh_find_set_of_reg (operands[0], curr_insn, 851 prev_nonnote_insn_bb); 852 853 if (op.set_src != NULL && GET_CODE (op.set_src) == AND 854 && !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn)) 855 { 856 if (dump_file) 857 fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n", 858 INSN_UID (op.insn)); 859 860 if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode) 861 && (arith_reg_operand (XEXP (op.set_src, 1), SImode) 862 || CONST_INT_P (XEXP (op.set_src, 1))))) 863 FAIL; 864 865 /* Assume that the operands of the andsi insn are compatible with the 866 operands of the tstsi_t insn, which is generally the case. */ 867 if (dump_file) 868 fprintf (dump_file, "cmpeqsi_t: replacing with tstsi_t\n"); 869 emit_insn (gen_tstsi_t (copy_rtx (XEXP (op.set_src, 0)), 870 copy_rtx (XEXP (op.set_src, 1)))); 871 DONE; 872 } 873 874 /* Converting HImode into tests against 0xFFFF tends to increase the code 875 size, as it will create constant pool entries. Disable it for now. */ 876 const bool enable_himode = false; 877 878 /* FIXME: try to keep the (eq (reg) (const_int 0)). Even if the zero 879 extended reg is used after this insn, if we know that _before_ the zero 880 extension the value was loaded via sign extending mem load, we can just 881 use the value of the mem load directly. */ 882 sh_extending_set_of_reg eop = sh_find_extending_set_of_reg (operands[0], 883 curr_insn); 884 885 if (eop.ext_code != UNKNOWN 886 && (eop.from_mode == QImode || (eop.from_mode == HImode && enable_himode)) 887 && eop.can_use_as_unextended_reg () 888 && !reg_used_between_p (operands[0], eop.insn, curr_insn)) 889 { 890 /* Bypass the sign/zero extension and test against the bit mask, but 891 only if it's the only use of the sign/zero extracted value. 892 Otherwise we'd be introducing new constants in the pool. */ 893 if (dump_file) 894 fprintf (dump_file, "cmpeqsi_t: bypassing sign/zero extension in " 895 "insn %d and using tstsi_t\n", INSN_UID (op.insn)); 896 897 emit_insn (gen_tstsi_t ( 898 eop.use_as_unextended_reg (curr_insn), 899 GEN_INT (eop.from_mode == QImode ? 0xFF : 0xFFFF))); 900 DONE; 901 } 902 903 if (dump_file) 904 fprintf (dump_file, "cmpeqsi_t: nothing optimized\n"); 905 FAIL; 906}) 907 908(define_insn "cmpgtsi_t" 909 [(set (reg:SI T_REG) 910 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r") 911 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))] 912 "TARGET_SH1" 913 "@ 914 cmp/pl %0 915 cmp/gt %1,%0" 916 [(set_attr "type" "mt_group")]) 917 918(define_insn "cmpgesi_t" 919 [(set (reg:SI T_REG) 920 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r") 921 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))] 922 "TARGET_SH1" 923 "@ 924 cmp/pz %0 925 cmp/ge %1,%0" 926 [(set_attr "type" "mt_group")]) 927 928;; Recombine a cmp/pz followed by a nott into a shll. 929;; On non-SH2A recombine a cmp/pz followed by a movrt into shll-movt. 930;; On SH2A cmp/pz-movrt is slightly better, as it does not mutate the input. 931(define_split 932 [(set (reg:SI T_REG) 933 (ge:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))] 934 935 "TARGET_SH1 && can_create_pseudo_p () && optimize 936 && !sh_in_recog_treg_set_expr ()" 937 [(const_int 0)] 938{ 939 if (dump_file) 940 fprintf (dump_file, "cmpgesi_t: trying to optimize for const_int 0\n"); 941 942 rtx_insn* i = next_nonnote_insn_bb (curr_insn); 943 944 if (dump_file) 945 { 946 fprintf (dump_file, "cmpgesi_t: following insn is \n"); 947 print_rtl_single (dump_file, i); 948 fprintf (dump_file, "\n"); 949 } 950 951 if (sh_is_nott_insn (i)) 952 { 953 if (dump_file) 954 fprintf (dump_file, 955 "cmpgesi_t: replacing (cmp/pz, nott) with (shll)\n"); 956 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0])); 957 set_insn_deleted (i); 958 DONE; 959 } 960 961 /* On non-SH2A negc is used as movrt replacement, which sets T = 1. 962 Thus we can remove it only if T is marked as dead afterwards. */ 963 if (rtx dest_reg = !TARGET_SH2A 964 && sh_reg_dead_or_unused_after_insn (i, T_REG) 965 ? sh_movrt_set_dest (i) : NULL) 966 { 967 if (dump_file) 968 fprintf (dump_file, 969 "cmpgesi_t: replacing (cmp/pz, movrt) with (shll, movt)\n"); 970 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0])); 971 add_reg_note (emit_insn (gen_movt (dest_reg, get_t_reg_rtx ())), 972 REG_DEAD, get_t_reg_rtx ()); 973 set_insn_deleted (i); 974 DONE; 975 } 976 977 if (dump_file) 978 fprintf (dump_file, "cmpgesi_t: nothing optimized\n"); 979 980 FAIL; 981}) 982 983;; FIXME: This is actually wrong. There is no way to literally move a 984;; general reg to t reg. Luckily, it seems that this pattern will be only 985;; used when the general reg is known be either '0' or '1' during combine. 986;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T. 987;; Due to interactions with other patterns, combine fails to pick the latter 988;; and invert the dependent logic. 989(define_insn "*negtstsi" 990 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))] 991 "TARGET_SH1 && !sh_in_recog_treg_set_expr ()" 992 "cmp/pl %0" 993 [(set_attr "type" "mt_group")]) 994 995;; Some integer sign comparison patterns can be realized with the div0s insn. 996;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31) 997;; 998;; The 'cmp_div0s' pattern is our canonical form, into which all the other 999;; variations are converted. The negative forms will split into a trailing 1000;; nott sequence, which will be eliminated either by the 1001;; 'any_treg_expr_to_reg' pattern, or by the 'sh_treg_combine' pass. 1002(define_insn "cmp_div0s" 1003 [(set (reg:SI T_REG) 1004 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r") 1005 (match_operand:SI 1 "arith_reg_operand" "r")) 1006 (const_int 31)))] 1007 "TARGET_SH1" 1008 "div0s %0,%1" 1009 [(set_attr "type" "arith")]) 1010 1011(define_insn_and_split "*cmp_div0s_1" 1012 [(set (reg:SI T_REG) 1013 (xor:SI (ge:SI (match_operand:SI 0 "arith_reg_operand") 1014 (const_int 0)) 1015 (ge:SI (match_operand:SI 1 "arith_reg_operand") 1016 (const_int 0))))] 1017 "TARGET_SH1 && can_create_pseudo_p ()" 1018 "#" 1019 "&& 1" 1020 [(set (reg:SI T_REG) 1021 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))]) 1022 1023(define_insn_and_split "*cmp_div0s_2" 1024 [(set (reg:SI T_REG) 1025 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand") 1026 (const_int 31)) 1027 (ge:SI (match_operand:SI 1 "arith_reg_operand") 1028 (const_int 0))))] 1029 "TARGET_SH1 && can_create_pseudo_p ()" 1030 "#" 1031 "&& 1" 1032 [(set (reg:SI T_REG) 1033 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))]) 1034 1035(define_insn_and_split "*cmp_div0s_3" 1036 [(set (reg:SI T_REG) 1037 (eq:SI (ge:SI (match_operand:SI 0 "arith_reg_operand") 1038 (const_int 0)) 1039 (ge:SI (match_operand:SI 1 "arith_reg_operand") 1040 (const_int 0))))] 1041 "TARGET_SH1 && can_create_pseudo_p ()" 1042 "#" 1043 "&& 1" 1044 [(set (reg:SI T_REG) 1045 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31))) 1046 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) 1047 1048(define_insn_and_split "*cmp_div0s_4" 1049 [(set (reg:SI T_REG) 1050 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand") 1051 (match_operand:SI 1 "arith_reg_operand")) 1052 (const_int 0)))] 1053 "TARGET_SH1 && can_create_pseudo_p ()" 1054 "#" 1055 "&& 1" 1056 [(set (reg:SI T_REG) 1057 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31))) 1058 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) 1059 1060(define_insn_and_split "*cmp_div0s_5" 1061 [(set (reg:SI T_REG) 1062 (xor:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand") 1063 (const_int 31)) 1064 (ge:SI (match_operand:SI 1 "arith_reg_operand") 1065 (const_int 0))))] 1066 "TARGET_SH1 && can_create_pseudo_p ()" 1067 "#" 1068 "&& 1" 1069 [(set (reg:SI T_REG) 1070 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31))) 1071 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) 1072 1073(define_insn_and_split "*cmp_div0s_6" 1074 [(set (reg:SI T_REG) 1075 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand") 1076 (const_int 31)) 1077 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand") 1078 (const_int 31))))] 1079 "TARGET_SH1 && can_create_pseudo_p ()" 1080 "#" 1081 "&& 1" 1082 [(set (reg:SI T_REG) 1083 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31))) 1084 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) 1085 1086;; In some cases, it might be shorter to get a tested bit into bit 31 and 1087;; use div0s. Otherwise it's usually better to just leave the xor and tst 1088;; sequence. The only thing we can try to do here is avoiding the large 1089;; tst constant. 1090(define_insn_and_split "*cmp_div0s_7" 1091 [(set (reg:SI T_REG) 1092 (zero_extract:SI (xor:SI (match_operand:SI 0 "arith_reg_operand") 1093 (match_operand:SI 1 "arith_reg_operand")) 1094 (const_int 1) 1095 (match_operand 2 "const_int_operand")))] 1096 "TARGET_SH1 && can_create_pseudo_p () 1097 && (INTVAL (operands[2]) == 7 || INTVAL (operands[2]) == 15 1098 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29 1099 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)" 1100 "#" 1101 "&& 1" 1102 [(const_int 0)] 1103{ 1104 const int bitpos = INTVAL (operands[2]); 1105 1106 rtx op0 = gen_reg_rtx (SImode); 1107 rtx op1 = gen_reg_rtx (SImode); 1108 1109 if (bitpos == 23 || bitpos == 30 || bitpos == 29) 1110 { 1111 emit_insn (gen_ashlsi3 (op0, operands[0], GEN_INT (31 - bitpos))); 1112 emit_insn (gen_ashlsi3 (op1, operands[1], GEN_INT (31 - bitpos))); 1113 } 1114 else if (bitpos == 15) 1115 { 1116 emit_insn (gen_extendhisi2 (op0, gen_lowpart (HImode, operands[0]))); 1117 emit_insn (gen_extendhisi2 (op1, gen_lowpart (HImode, operands[1]))); 1118 } 1119 else if (bitpos == 7) 1120 { 1121 emit_insn (gen_extendqisi2 (op0, gen_lowpart (QImode, operands[0]))); 1122 emit_insn (gen_extendqisi2 (op1, gen_lowpart (QImode, operands[1]))); 1123 } 1124 else if (bitpos == 31) 1125 { 1126 op0 = operands[0]; 1127 op1 = operands[1]; 1128 } 1129 else 1130 gcc_unreachable (); 1131 1132 emit_insn (gen_cmp_div0s (op0, op1)); 1133 DONE; 1134}) 1135 1136;; For bits 0..7 using a xor and tst #imm,r0 sequence seems to be better. 1137;; Thus allow the following patterns only for higher bit positions where 1138;; we it's more likely to save the large tst constant. 1139(define_insn_and_split "*cmp_div0s_8" 1140 [(set (reg:SI T_REG) 1141 (eq:SI (zero_extract:SI (match_operand:SI 0 "arith_reg_operand") 1142 (const_int 1) 1143 (match_operand 2 "const_int_operand")) 1144 (zero_extract:SI (match_operand:SI 1 "arith_reg_operand") 1145 (const_int 1) 1146 (match_dup 2))))] 1147 "TARGET_SH1 && can_create_pseudo_p () 1148 && (INTVAL (operands[2]) == 15 1149 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29 1150 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)" 1151 "#" 1152 "&& 1" 1153 [(set (reg:SI T_REG) 1154 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1)) 1155 (const_int 1) (match_dup 2))) 1156 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) 1157 1158(define_insn_and_split "*cmp_div0s_9" 1159 [(set (reg:SI T_REG) 1160 (zero_extract:SI (xor:SI (xor:SI (match_operand:SI 0 "arith_reg_operand") 1161 (match_operand:SI 1 "arith_reg_operand")) 1162 (match_operand 2 "const_int_operand")) 1163 (const_int 1) 1164 (match_operand 3 "const_int_operand")))] 1165 "TARGET_SH1 && can_create_pseudo_p () 1166 && (INTVAL (operands[2]) & 0xFFFFFFFF) == (1U << INTVAL (operands[3])) 1167 && (INTVAL (operands[3]) == 15 1168 || INTVAL (operands[3]) == 23 || INTVAL (operands[3]) == 29 1169 || INTVAL (operands[3]) == 30 || INTVAL (operands[3]) == 31)" 1170 "#" 1171 "&& 1" 1172 [(set (reg:SI T_REG) 1173 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1)) 1174 (const_int 1) (match_dup 3))) 1175 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) 1176 1177;; ------------------------------------------------------------------------- 1178;; SImode compare and branch 1179;; ------------------------------------------------------------------------- 1180 1181(define_expand "cbranchsi4" 1182 [(set (pc) 1183 (if_then_else (match_operator 0 "comparison_operator" 1184 [(match_operand:SI 1 "arith_operand" "") 1185 (match_operand:SI 2 "arith_operand" "")]) 1186 (label_ref (match_operand 3 "" "")) 1187 (pc))) 1188 (clobber (reg:SI T_REG))] 1189 "can_create_pseudo_p ()" 1190{ 1191 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE, -1); 1192 DONE; 1193}) 1194 1195;; Combine patterns to invert compare and branch operations for which we 1196;; don't have actual comparison insns. These patterns are used in cases 1197;; which appear after the initial cbranchsi expansion, which also does 1198;; some condition inversion. 1199(define_split 1200 [(set (pc) 1201 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "") 1202 (match_operand:SI 1 "arith_reg_or_0_operand" "")) 1203 (label_ref (match_operand 2)) 1204 (pc))) 1205 (clobber (reg:SI T_REG))] 1206 "TARGET_SH1" 1207 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1))) 1208 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 1209 (label_ref (match_dup 2)) 1210 (pc)))]) 1211 1212;; FIXME: These don't seem to have any effect on the generated cbranch code 1213;; anymore, but only on some register allocation choices. 1214(define_split 1215 [(set (pc) 1216 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "") 1217 (match_operand:SI 1 "arith_reg_or_0_operand" "")) 1218 (label_ref (match_operand 2)) 1219 (pc))) 1220 (clobber (reg:SI T_REG))] 1221 "TARGET_SH1" 1222 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1))) 1223 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 1224 (label_ref (match_dup 2)) 1225 (pc)))]) 1226 1227(define_split 1228 [(set (pc) 1229 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "") 1230 (match_operand:SI 1 "arith_reg_or_0_operand" "")) 1231 (label_ref (match_operand 2)) 1232 (pc))) 1233 (clobber (reg:SI T_REG))] 1234 "TARGET_SH1" 1235 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1))) 1236 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 1237 (label_ref (match_dup 2)) 1238 (pc)))]) 1239 1240(define_split 1241 [(set (pc) 1242 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "") 1243 (match_operand:SI 1 "arith_reg_operand" "")) 1244 (label_ref (match_operand 2)) 1245 (pc))) 1246 (clobber (reg:SI T_REG))] 1247 "TARGET_SH1" 1248 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1))) 1249 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 1250 (label_ref (match_dup 2)) 1251 (pc)))]) 1252 1253(define_split 1254 [(set (pc) 1255 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "") 1256 (match_operand:SI 1 "arith_reg_operand" "")) 1257 (label_ref (match_operand 2)) 1258 (pc))) 1259 (clobber (reg:SI T_REG))] 1260 "TARGET_SH1" 1261 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1))) 1262 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 1263 (label_ref (match_dup 2)) 1264 (pc)))]) 1265 1266;; ------------------------------------------------------------------------- 1267;; SImode unsigned integer comparisons 1268;; ------------------------------------------------------------------------- 1269 1270;; Usually comparisons of 'unsigned int >= 0' are optimized away completely. 1271;; However, especially when optimizations are off (e.g. -O0) such comparisons 1272;; might remain and we have to handle them. If the '>= 0' case wasn't 1273;; handled here, something else would just load a '0' into the second operand 1274;; and do the comparison. We can do slightly better by just setting the 1275;; T bit to '1'. 1276(define_insn_and_split "cmpgeusi_t" 1277 [(set (reg:SI T_REG) 1278 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r") 1279 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))] 1280 "TARGET_SH1" 1281 "cmp/hs %1,%0" 1282 "&& satisfies_constraint_Z (operands[1])" 1283 [(set (reg:SI T_REG) (const_int 1))] 1284 "" 1285 [(set_attr "type" "mt_group")]) 1286 1287(define_insn "cmpgtusi_t" 1288 [(set (reg:SI T_REG) 1289 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r") 1290 (match_operand:SI 1 "arith_reg_operand" "r")))] 1291 "TARGET_SH1" 1292 "cmp/hi %1,%0" 1293 [(set_attr "type" "mt_group")]) 1294 1295;; ------------------------------------------------------------------------- 1296;; DImode compare and branch 1297;; ------------------------------------------------------------------------- 1298 1299;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism. 1300;; Therefore, we aim to have a set of three branches that go straight to the 1301;; destination, i.e. only one of them is taken at any one time. 1302;; This mechanism should also be slightly better for the sh4-200. 1303 1304(define_expand "cbranchdi4" 1305 [(set (pc) 1306 (if_then_else (match_operator 0 "comparison_operator" 1307 [(match_operand:DI 1 "arith_operand") 1308 (match_operand:DI 2 "arith_operand")]) 1309 (label_ref (match_operand 3)) 1310 (pc))) 1311 (clobber (reg:SI T_REG))] 1312 "TARGET_SH2 && can_create_pseudo_p ()" 1313{ 1314 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0]))) 1315 FAIL; 1316 DONE; 1317}) 1318 1319;; ------------------------------------------------------------------------- 1320;; DImode signed integer comparisons 1321;; ------------------------------------------------------------------------- 1322 1323(define_insn "" 1324 [(set (reg:SI T_REG) 1325 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r") 1326 (match_operand:DI 1 "arith_operand" "r")) 1327 (const_int 0)))] 1328 "TARGET_SH1" 1329{ 1330 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0", 1331 insn, operands); 1332} 1333 [(set_attr "length" "6") 1334 (set_attr "type" "arith3b")]) 1335 1336(define_insn "cmpeqdi_t" 1337 [(set (reg:SI T_REG) 1338 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r") 1339 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))] 1340 "TARGET_SH1" 1341{ 1342 static const char* alt[] = 1343 { 1344 "tst %S0,%S0" "\n" 1345 " bf 0f" "\n" 1346 " tst %R0,%R0" "\n" 1347 "0:", 1348 1349 "cmp/eq %S1,%S0" "\n" 1350 " bf 0f" "\n" 1351 " cmp/eq %R1,%R0" "\n" 1352 "0:" 1353 }; 1354 return alt[which_alternative]; 1355} 1356 [(set_attr "length" "6") 1357 (set_attr "type" "arith3b")]) 1358 1359(define_split 1360 [(set (reg:SI T_REG) 1361 (eq:SI (match_operand:DI 0 "arith_reg_operand" "") 1362 (match_operand:DI 1 "arith_reg_or_0_operand" "")))] 1363;; If we applied this split when not optimizing, it would only be 1364;; applied during the machine-dependent reorg, when no new basic blocks 1365;; may be created. 1366 "TARGET_SH1 && reload_completed && optimize" 1367 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3))) 1368 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 1369 (label_ref (match_dup 6)) 1370 (pc))) 1371 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5))) 1372 (match_dup 6)] 1373{ 1374 operands[2] = gen_highpart (SImode, operands[0]); 1375 operands[3] = operands[1] == const0_rtx 1376 ? const0_rtx 1377 : gen_highpart (SImode, operands[1]); 1378 operands[4] = gen_lowpart (SImode, operands[0]); 1379 operands[5] = gen_lowpart (SImode, operands[1]); 1380 operands[6] = gen_label_rtx (); 1381}) 1382 1383(define_insn "cmpgtdi_t" 1384 [(set (reg:SI T_REG) 1385 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r") 1386 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))] 1387 "TARGET_SH2" 1388{ 1389 static const char* alt[] = 1390 { 1391 "cmp/eq %S1,%S0" "\n" 1392 " bf{.|/}s 0f" "\n" 1393 " cmp/gt %S1,%S0" "\n" 1394 " cmp/hi %R1,%R0" "\n" 1395 "0:", 1396 1397 "tst %S0,%S0" "\n" 1398 " bf{.|/}s 0f" "\n" 1399 " cmp/pl %S0" "\n" 1400 " cmp/hi %S0,%R0" "\n" 1401 "0:" 1402 }; 1403 return alt[which_alternative]; 1404} 1405 [(set_attr "length" "8") 1406 (set_attr "type" "arith3")]) 1407 1408(define_insn "cmpgedi_t" 1409 [(set (reg:SI T_REG) 1410 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r") 1411 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))] 1412 "TARGET_SH2" 1413{ 1414 static const char* alt[] = 1415 { 1416 "cmp/eq %S1,%S0" "\n" 1417 " bf{.|/}s 0f" "\n" 1418 " cmp/ge %S1,%S0" "\n" 1419 " cmp/hs %R1,%R0" "\n" 1420 "0:", 1421 1422 "cmp/pz %S0" 1423 }; 1424 return alt[which_alternative]; 1425} 1426 [(set_attr "length" "8,2") 1427 (set_attr "type" "arith3,mt_group")]) 1428 1429;; ------------------------------------------------------------------------- 1430;; DImode unsigned integer comparisons 1431;; ------------------------------------------------------------------------- 1432 1433(define_insn "cmpgeudi_t" 1434 [(set (reg:SI T_REG) 1435 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r") 1436 (match_operand:DI 1 "arith_reg_operand" "r")))] 1437 "TARGET_SH2" 1438{ 1439 return "cmp/eq %S1,%S0" "\n" 1440 " bf{.|/}s 0f" "\n" 1441 " cmp/hs %S1,%S0" "\n" 1442 " cmp/hs %R1,%R0" "\n" 1443 "0:"; 1444} 1445 [(set_attr "length" "8") 1446 (set_attr "type" "arith3")]) 1447 1448(define_insn "cmpgtudi_t" 1449 [(set (reg:SI T_REG) 1450 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r") 1451 (match_operand:DI 1 "arith_reg_operand" "r")))] 1452 "TARGET_SH2" 1453{ 1454 return "cmp/eq %S1,%S0" "\n" 1455 " bf{.|/}s 0f" "\n" 1456 " cmp/hi %S1,%S0" "\n" 1457 " cmp/hi %R1,%R0" "\n" 1458 "0:"; 1459} 1460 [(set_attr "length" "8") 1461 (set_attr "type" "arith3")]) 1462 1463;; ------------------------------------------------------------------------- 1464;; Conditional move instructions 1465;; ------------------------------------------------------------------------- 1466 1467(define_insn "*movsicc_t_false" 1468 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") 1469 (if_then_else (eq (reg:SI T_REG) (const_int 0)) 1470 (match_operand:SI 1 "general_movsrc_operand" "r,I08") 1471 (match_operand:SI 2 "arith_reg_operand" "0,0")))] 1472 "TARGET_PRETEND_CMOVE 1473 && (arith_reg_operand (operands[1], SImode) 1474 || (immediate_operand (operands[1], SImode) 1475 && satisfies_constraint_I08 (operands[1])))" 1476{ 1477 return "bt 0f" "\n" 1478 " mov %1,%0" "\n" 1479 "0:"; 1480} 1481 [(set_attr "type" "mt_group,arith") ;; poor approximation 1482 (set_attr "length" "4")]) 1483 1484(define_insn "*movsicc_t_true" 1485 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") 1486 (if_then_else (ne (reg:SI T_REG) (const_int 0)) 1487 (match_operand:SI 1 "general_movsrc_operand" "r,I08") 1488 (match_operand:SI 2 "arith_reg_operand" "0,0")))] 1489 "TARGET_PRETEND_CMOVE 1490 && (arith_reg_operand (operands[1], SImode) 1491 || (immediate_operand (operands[1], SImode) 1492 && satisfies_constraint_I08 (operands[1])))" 1493{ 1494 return "bf 0f" "\n" 1495 " mov %1,%0" "\n" 1496 "0:"; 1497} 1498 [(set_attr "type" "mt_group,arith") ;; poor approximation 1499 (set_attr "length" "4")]) 1500 1501(define_expand "movsicc" 1502 [(set (match_operand:SI 0 "arith_reg_dest" "") 1503 (if_then_else:SI (match_operand 1 "comparison_operator" "") 1504 (match_operand:SI 2 "arith_reg_or_0_operand" "") 1505 (match_operand:SI 3 "arith_reg_operand" "")))] 1506 "TARGET_PRETEND_CMOVE" 1507{ 1508 rtx_code code = GET_CODE (operands[1]); 1509 rtx_code new_code = code; 1510 rtx op0 = XEXP (operands[1], 0); 1511 rtx op1 = XEXP (operands[1], 1); 1512 1513 if (! currently_expanding_to_rtl) 1514 FAIL; 1515 1516 switch (code) 1517 { 1518 case LT: case LE: case LEU: case LTU: 1519 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT) 1520 break; 1521 /* FALLTHRU */ 1522 case NE: 1523 new_code = reverse_condition (code); 1524 break; 1525 case EQ: case GT: case GE: case GEU: case GTU: 1526 break; 1527 default: 1528 FAIL; 1529 } 1530 1531 sh_emit_scc_to_t (new_code, op0, op1); 1532 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode, 1533 gen_rtx_REG (SImode, T_REG), const0_rtx); 1534}) 1535 1536;; ------------------------------------------------------------------------- 1537;; Addition instructions 1538;; ------------------------------------------------------------------------- 1539 1540(define_insn_and_split "adddi3" 1541 [(set (match_operand:DI 0 "arith_reg_dest") 1542 (plus:DI (match_operand:DI 1 "arith_reg_operand") 1543 (match_operand:DI 2 "arith_reg_operand"))) 1544 (clobber (reg:SI T_REG))] 1545 "TARGET_SH1" 1546 "#" 1547 "&& can_create_pseudo_p ()" 1548 [(const_int 0)] 1549{ 1550 emit_insn (gen_clrt ()); 1551 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]), 1552 gen_lowpart (SImode, operands[1]), 1553 gen_lowpart (SImode, operands[2]))); 1554 emit_insn (gen_addc (gen_highpart (SImode, operands[0]), 1555 gen_highpart (SImode, operands[1]), 1556 gen_highpart (SImode, operands[2]))); 1557 DONE; 1558}) 1559 1560(define_insn "addc" 1561 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 1562 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0") 1563 (match_operand:SI 2 "arith_reg_operand" "r")) 1564 (reg:SI T_REG))) 1565 (set (reg:SI T_REG) 1566 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))] 1567 "TARGET_SH1" 1568 "addc %2,%0" 1569 [(set_attr "type" "arith")]) 1570 1571;; A simplified version of the addc insn, where the exact value of the 1572;; T bit doesn't matter. This is easier for combine to pick up. 1573;; We allow a reg or 0 for one of the operands in order to be able to 1574;; do 'reg + T' sequences. 1575(define_insn_and_split "*addc" 1576 [(set (match_operand:SI 0 "arith_reg_dest") 1577 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand") 1578 (match_operand:SI 2 "arith_reg_or_0_operand")) 1579 (match_operand 3 "treg_set_expr"))) 1580 (clobber (reg:SI T_REG))] 1581 "TARGET_SH1 && can_create_pseudo_p ()" 1582 "#" 1583 "&& 1" 1584 [(const_int 0)] 1585{ 1586 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn); 1587 if (ti.has_trailing_nott ()) 1588 { 1589 if (operands[2] == const0_rtx) 1590 { 1591 /* op1 + 0 + (1 - T) = op1 + 1 - T = op1 - (-1) - T */ 1592 remove_insn (ti.trailing_nott ()); 1593 emit_insn (gen_subc (operands[0], operands[1], 1594 force_reg (SImode, GEN_INT (-1)))); 1595 DONE; 1596 } 1597 else if (!TARGET_SH2A) 1598 { 1599 /* op1 + op2 + (1 - T) = op1 - (0 - op2 - 1) - T = op1 - ~op2 - T 1600 On SH2A keep the nott insn, because nott-addc sequence doesn't 1601 mutate the inputs. */ 1602 remove_insn (ti.trailing_nott ()); 1603 rtx tmp = gen_reg_rtx (SImode); 1604 emit_insn (gen_one_cmplsi2 (tmp, operands[2])); 1605 emit_insn (gen_subc (operands[0], operands[1], tmp)); 1606 DONE; 1607 } 1608 } 1609 1610 emit_insn (gen_addc (operands[0], operands[1], 1611 force_reg (SImode, operands[2]))); 1612 DONE; 1613}) 1614 1615(define_insn_and_split "*addc" 1616 [(set (match_operand:SI 0 "arith_reg_dest") 1617 (plus:SI (plus:SI (match_operand 1 "treg_set_expr") 1618 (match_operand:SI 2 "arith_reg_operand")) 1619 (match_operand:SI 3 "arith_reg_operand"))) 1620 (clobber (reg:SI T_REG))] 1621 "TARGET_SH1 && can_create_pseudo_p ()" 1622 "#" 1623 "&& 1" 1624 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3)) 1625 (match_dup 1))) 1626 (clobber (reg:SI T_REG))])]) 1627 1628(define_insn_and_split "*addc" 1629 [(set (match_operand:SI 0 "arith_reg_dest") 1630 (plus:SI (match_operand 1 "treg_set_expr") 1631 (plus:SI (match_operand:SI 2 "arith_reg_operand") 1632 (match_operand:SI 3 "arith_reg_operand")))) 1633 (clobber (reg:SI T_REG))] 1634 "TARGET_SH1 && can_create_pseudo_p ()" 1635 "#" 1636 "&& 1" 1637 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3)) 1638 (match_dup 1))) 1639 (clobber (reg:SI T_REG))])]) 1640 1641;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern 1642;; matched. Split this up into a simple sub add sequence, as this will save 1643;; us one sett insn. 1644(define_insn_and_split "*minus_plus_one" 1645 [(set (match_operand:SI 0 "arith_reg_dest" "") 1646 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "") 1647 (match_operand:SI 2 "arith_reg_operand" "")) 1648 (const_int 1)))] 1649 "TARGET_SH1" 1650 "#" 1651 "&& 1" 1652 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2))) 1653 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))]) 1654 1655 1656;; The tree optimiziers canonicalize 1657;; reg + (reg & 1) 1658;; into 1659;; (reg + 1) & -2 1660;; 1661;; On SH2A an add-bclr sequence will be used to handle this. 1662;; On non-SH2A re-emit the add-and sequence to improve register utilization. 1663(define_insn_and_split "*round_int_even" 1664 [(set (match_operand:SI 0 "arith_reg_dest") 1665 (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand") 1666 (const_int 1)) 1667 (const_int -2)))] 1668 "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p () 1669 && !reg_overlap_mentioned_p (operands[0], operands[1])" 1670 "#" 1671 "&& 1" 1672 [(set (match_dup 0) (const_int -2)) 1673 (set (match_dup 2) (plus:SI (match_dup 1) (const_int 1))) 1674 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))] 1675{ 1676 operands[2] = gen_reg_rtx (SImode); 1677}) 1678 1679;; If the *round_int_even pattern is combined with another plus, 1680;; convert it into an addc pattern to emit an shlr-addc sequence. 1681;; This split is taken by combine on non-SH2A and SH2A. 1682(define_split 1683 [(set (match_operand:SI 0 "arith_reg_dest") 1684 (plus:SI (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand") 1685 (const_int 1)) 1686 (const_int -2)) 1687 (match_operand:SI 2 "arith_reg_operand")))] 1688 "TARGET_SH1 && can_create_pseudo_p ()" 1689 [(parallel [(set (match_dup 0) 1690 (plus:SI (plus:SI (match_dup 1) (match_dup 2)) 1691 (and:SI (match_dup 1) (const_int 1)))) 1692 (clobber (reg:SI T_REG))])]) 1693 1694;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn. 1695;; If the 0 constant can be CSE-ed, this becomes a one instruction 1696;; operation, as opposed to sequences such as 1697;; movt r2 1698;; add r2,r3 1699;; 1700;; Even if the constant is not CSE-ed, a sequence such as 1701;; mov #0,r2 1702;; addc r2,r3 1703;; can be scheduled much better since the load of the constant can be 1704;; done earlier, before any comparison insns that store the result in 1705;; the T bit. 1706;; However, avoid things like 'reg + 1', which would expand into a 1707;; 3 insn sequence, instead of add #imm8. 1708(define_insn_and_split "*addc_t_r" 1709 [(set (match_operand:SI 0 "arith_reg_dest") 1710 (plus:SI (match_operand 1 "treg_set_expr_not_const01") 1711 (match_operand:SI 2 "arith_reg_operand"))) 1712 (clobber (reg:SI T_REG))] 1713 "TARGET_SH1 && can_create_pseudo_p ()" 1714 "#" 1715 "&& 1" 1716 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (const_int 0)) 1717 (match_dup 1))) 1718 (clobber (reg:SI T_REG))])]) 1719 1720(define_insn_and_split "*addc_r_t" 1721 [(set (match_operand:SI 0 "arith_reg_dest") 1722 (plus:SI (match_operand:SI 1 "arith_reg_operand") 1723 (match_operand 2 "treg_set_expr_not_const01"))) 1724 (clobber (reg:SI T_REG))] 1725 "TARGET_SH1 && can_create_pseudo_p ()" 1726 "#" 1727 "&& 1" 1728 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (const_int 0)) 1729 (match_dup 2))) 1730 (clobber (reg:SI T_REG))])]) 1731 1732;; Convert '2 * reg + T' into 'reg + reg + T'. 1733(define_insn_and_split "*addc_2r_t" 1734 [(set (match_operand:SI 0 "arith_reg_dest") 1735 (plus:SI (match_operand 1 "treg_set_expr") 1736 (ashift:SI (match_operand:SI 2 "arith_reg_operand") 1737 (const_int 1)))) 1738 (clobber (reg:SI T_REG))] 1739 "TARGET_SH1 && can_create_pseudo_p ()" 1740 "#" 1741 "&& 1" 1742 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 2)) 1743 (match_dup 1))) 1744 (clobber (reg:SI T_REG))])]) 1745 1746(define_insn_and_split "*addc_2r_t" 1747 [(set (match_operand:SI 0 "arith_reg_dest") 1748 (plus:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand") 1749 (const_int 1)) 1750 (match_operand 2 "treg_set_expr"))) 1751 (clobber (reg:SI T_REG))] 1752 "TARGET_SH1 && can_create_pseudo_p ()" 1753 "#" 1754 "&& 1" 1755 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1)) 1756 (match_dup 2))) 1757 (clobber (reg:SI T_REG))])]) 1758 1759;; Convert '(op2 + T) - op3' into 'op2 + (-op3) + T' 1760(define_insn_and_split "*addc_negreg_t" 1761 [(set (match_operand:SI 0 "arith_reg_dest") 1762 (minus:SI (plus:SI (match_operand 1 "treg_set_expr") 1763 (match_operand:SI 2 "arith_reg_operand")) 1764 (match_operand:SI 3 "arith_reg_operand"))) 1765 (clobber (reg:SI T_REG))] 1766 "TARGET_SH1 && can_create_pseudo_p ()" 1767 "#" 1768 "&& 1" 1769 [(set (match_dup 4) (neg:SI (match_dup 3))) 1770 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 4)) 1771 (match_dup 1))) 1772 (clobber (reg:SI T_REG))])] 1773{ 1774 operands[4] = gen_reg_rtx (SImode); 1775}) 1776 1777(define_expand "addsi3" 1778 [(set (match_operand:SI 0 "arith_reg_dest") 1779 (plus:SI (match_operand:SI 1 "arith_reg_operand") 1780 (match_operand:SI 2 "arith_or_int_operand")))] 1781 "" 1782{ 1783 if (!arith_operand (operands[2], SImode)) 1784 { 1785 if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1])) 1786 { 1787 emit_insn (gen_addsi3_scr (operands[0], operands[1], operands[2])); 1788 DONE; 1789 } 1790 } 1791}) 1792 1793;; The *addsi3_compact is made an insn_and_split and accepts actually 1794;; impossible constraints to make LRA's register elimination work well on SH. 1795;; The problem is that LRA expects something like 1796;; (set rA (plus rB (const_int N))) 1797;; to work. We can do that, but we have to split out an additional reg-reg 1798;; copy or constant load before the actual add insn. 1799;; Use u constraint for that case to avoid the invalid value in the stack 1800;; pointer. 1801;; This also results in better code when LRA is not used. However, we have 1802;; to use different sets of patterns and the order of these patterns is 1803;; important. 1804;; In some cases the constant zero might end up in operands[2] of the 1805;; patterns. We have to accept that and convert it into a reg-reg move. 1806(define_insn_and_split "*addsi3_compact_lra" 1807 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u") 1808 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r") 1809 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))] 1810 "TARGET_SH1 && sh_lra_p () 1811 && (! reg_overlap_mentioned_p (operands[0], operands[1]) 1812 || arith_operand (operands[2], SImode))" 1813 "@ 1814 add %2,%0 1815 #" 1816 "&& reload_completed 1817 && ! reg_overlap_mentioned_p (operands[0], operands[1])" 1818 [(set (match_dup 0) (match_dup 2)) 1819 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))] 1820{ 1821 /* Prefer 'mov r0,r1; add #imm8,r1' over 'mov #imm8,r1; add r0,r1' */ 1822 if (satisfies_constraint_I08 (operands[2])) 1823 std::swap (operands[1], operands[2]); 1824} 1825 [(set_attr "type" "arith")]) 1826 1827(define_insn_and_split "addsi3_scr" 1828 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u,&u") 1829 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r,r") 1830 (match_operand:SI 2 "arith_or_int_operand" "rI08,r,n"))) 1831 (clobber (match_scratch:SI 3 "=X,X,&u"))] 1832 "TARGET_SH1" 1833 "@ 1834 add %2,%0 1835 # 1836 #" 1837 "&& reload_completed" 1838 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 1839{ 1840 if (operands[2] == const0_rtx) 1841 { 1842 emit_move_insn (operands[0], operands[1]); 1843 DONE; 1844 } 1845 1846 if (CONST_INT_P (operands[2]) && !satisfies_constraint_I08 (operands[2])) 1847 { 1848 if (reg_overlap_mentioned_p (operands[0], operands[1])) 1849 { 1850 emit_move_insn (operands[3], operands[2]); 1851 emit_move_insn (operands[0], operands[1]); 1852 operands[2] = operands[3]; 1853 } 1854 else 1855 { 1856 emit_move_insn (operands[0], operands[2]); 1857 operands[2] = operands[1]; 1858 } 1859 } 1860 else if (!reg_overlap_mentioned_p (operands[0], operands[1])) 1861 { 1862 if (!reg_overlap_mentioned_p (operands[0], operands[2])) 1863 emit_move_insn (operands[0], operands[1]); 1864 else 1865 operands[2] = operands[1]; 1866 } 1867} 1868 [(set_attr "type" "arith")]) 1869 1870;; Old reload might generate add insns directly (not through the expander) for 1871;; address register calculations when reloading, in which case it won't try 1872;; the addsi_scr pattern. Because reload will sometimes try to validate 1873;; the generated insns and their constraints, this pattern must be 1874;; recognizable during and after reload. However, when reload generates 1875;; address register calculations for the stack pointer, we don't allow this 1876;; pattern. This will make reload prefer using indexed @(reg + reg) address 1877;; modes when the displacement of a @(disp + reg) doesn't fit. 1878(define_insn_and_split "*addsi3" 1879 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 1880 (plus:SI (match_operand:SI 1 "arith_reg_operand" "r") 1881 (match_operand:SI 2 "arith_or_int_operand" "rn")))] 1882 "TARGET_SH1 && !sh_lra_p () 1883 && (reload_completed || reload_in_progress) 1884 && !reg_overlap_mentioned_p (operands[0], operands[1]) 1885 && (!reload_in_progress 1886 || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG) 1887 && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))" 1888 "#" 1889 "&& 1" 1890 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] 1891{ 1892 if (operands[2] == const0_rtx) 1893 { 1894 emit_move_insn (operands[0], operands[1]); 1895 DONE; 1896 } 1897 1898 if (CONST_INT_P (operands[2])) 1899 { 1900 if (satisfies_constraint_I08 (operands[2])) 1901 emit_move_insn (operands[0], operands[1]); 1902 else 1903 { 1904 emit_move_insn (operands[0], operands[2]); 1905 operands[2] = operands[1]; 1906 } 1907 } 1908 else if (!reg_overlap_mentioned_p (operands[0], operands[2])) 1909 emit_move_insn (operands[0], operands[1]); 1910 else 1911 operands[2] = operands[1]; 1912}) 1913 1914(define_insn_and_split "*addsi3" 1915 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") 1916 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r") 1917 (match_operand:SI 2 "arith_operand" "rI08,Z")))] 1918 "TARGET_SH1 && !sh_lra_p ()" 1919 "@ 1920 add %2,%0 1921 #" 1922 "&& operands[2] == const0_rtx" 1923 [(set (match_dup 0) (match_dup 1))] 1924{ 1925} 1926 [(set_attr "type" "arith")]) 1927 1928;; ------------------------------------------------------------------------- 1929;; Subtraction instructions 1930;; ------------------------------------------------------------------------- 1931 1932(define_insn_and_split "subdi3" 1933 [(set (match_operand:DI 0 "arith_reg_dest") 1934 (minus:DI (match_operand:DI 1 "arith_reg_operand") 1935 (match_operand:DI 2 "arith_reg_operand"))) 1936 (clobber (reg:SI T_REG))] 1937 "TARGET_SH1" 1938 "#" 1939 "&& can_create_pseudo_p ()" 1940 [(const_int 0)] 1941{ 1942 emit_insn (gen_clrt ()); 1943 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]), 1944 gen_lowpart (SImode, operands[1]), 1945 gen_lowpart (SImode, operands[2]))); 1946 emit_insn (gen_subc (gen_highpart (SImode, operands[0]), 1947 gen_highpart (SImode, operands[1]), 1948 gen_highpart (SImode, operands[2]))); 1949 DONE; 1950}) 1951 1952(define_insn "subc" 1953 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 1954 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0") 1955 (match_operand:SI 2 "arith_reg_operand" "r")) 1956 (reg:SI T_REG))) 1957 (set (reg:SI T_REG) 1958 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2)) 1959 (reg:SI T_REG)) 1960 (match_dup 1)))] 1961 "TARGET_SH1" 1962 "subc %2,%0" 1963 [(set_attr "type" "arith")]) 1964 1965;; A simplified version of the subc insn, where the exact value of the 1966;; T bit doesn't matter. This is easier for combine to pick up. 1967;; We allow a reg or 0 for one of the operands in order to be able to 1968;; do 'reg - T' sequences. Reload will load the constant 0 into the reg 1969;; as needed. 1970(define_insn_and_split "*subc" 1971 [(set (match_operand:SI 0 "arith_reg_dest") 1972 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand") 1973 (match_operand:SI 2 "arith_reg_or_0_operand")) 1974 (match_operand 3 "treg_set_expr"))) 1975 (clobber (reg:SI T_REG))] 1976 "TARGET_SH1 && can_create_pseudo_p ()" 1977 "#" 1978 "&& 1" 1979 [(const_int 0)] 1980{ 1981 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn); 1982 if (ti.has_trailing_nott ()) 1983 { 1984 if (operands[2] == const0_rtx) 1985 { 1986 /* op1 - (1 - T) = op1 - 1 + T = op1 + (-1) + T */ 1987 remove_insn (ti.trailing_nott ()); 1988 emit_insn (gen_addc (operands[0], operands[1], 1989 force_reg (SImode, GEN_INT (-1)))); 1990 DONE; 1991 } 1992 else if (!TARGET_SH2A) 1993 { 1994 /* op1 - op2 - (1 - T) = op1 + (0 - op2 - 1) + T = op1 + ~op2 + T 1995 On SH2A keep the nott insn, because nott-subc sequence doesn't 1996 mutate the inputs. */ 1997 remove_insn (ti.trailing_nott ()); 1998 rtx tmp = gen_reg_rtx (SImode); 1999 emit_insn (gen_one_cmplsi2 (tmp, operands[2])); 2000 emit_insn (gen_addc (operands[0], operands[1], tmp)); 2001 DONE; 2002 } 2003 } 2004 2005 emit_insn (gen_subc (operands[0], operands[1], 2006 force_reg (SImode, operands[2]))); 2007 DONE; 2008}) 2009 2010;; Convert reg - T - reg = reg - reg - T 2011(define_insn_and_split "*subc" 2012 [(set (match_operand:SI 0 "arith_reg_dest") 2013 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand") 2014 (match_operand 2 "treg_set_expr")) 2015 (match_operand:SI 3 "arith_reg_operand"))) 2016 (clobber (reg:SI T_REG))] 2017 "TARGET_SH1 && can_create_pseudo_p ()" 2018 "#" 2019 "&& 1" 2020 [(parallel [(set (match_dup 0) 2021 (minus:SI (minus:SI (match_dup 1) (match_dup 3)) 2022 (match_dup 2))) 2023 (clobber (reg:SI T_REG))])]) 2024 2025;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled 2026;; better, if the sett insn can be done early. 2027;; Notice that combine turns 'a - b - 1' into 'a + (~b)'. 2028(define_insn_and_split "*subc" 2029 [(set (match_operand:SI 0 "arith_reg_dest" "") 2030 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" "")) 2031 (match_operand:SI 2 "arith_reg_operand" ""))) 2032 (clobber (reg:SI T_REG))] 2033 "TARGET_SH1 && can_create_pseudo_p ()" 2034 "#" 2035 "&& 1" 2036 [(parallel [(set (match_dup 0) 2037 (minus:SI (minus:SI (match_dup 2) (match_dup 1)) 2038 (const_int 1))) 2039 (clobber (reg:SI T_REG))])]) 2040 2041;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn. 2042;; If the 0 constant can be CSE-ed, this becomes a one instruction 2043;; operation, as opposed to sequences such as 2044;; movt r2 2045;; sub r2,r3 2046;; 2047;; Even if the constant is not CSE-ed, a sequence such as 2048;; mov #0,r2 2049;; subc r2,r3 2050;; can be scheduled much better since the load of the constant can be 2051;; done earlier, before any comparison insns that store the result in 2052;; the T bit. 2053;; However, avoid things like 'reg - 1', which would expand into a 2054;; 3 insn sequence, instead of add #imm8. 2055(define_insn_and_split "*subc" 2056 [(set (match_operand:SI 0 "arith_reg_dest" "") 2057 (minus:SI (match_operand:SI 1 "arith_reg_operand" "") 2058 (match_operand 2 "treg_set_expr_not_const01"))) 2059 (clobber (reg:SI T_REG))] 2060 "TARGET_SH1 && can_create_pseudo_p ()" 2061 "#" 2062 "&& 1" 2063 [(parallel [(set (match_dup 0) 2064 (minus:SI (minus:SI (match_dup 1) (const_int 0)) 2065 (match_dup 2))) 2066 (clobber (reg:SI T_REG))])]) 2067 2068;; Convert 2069;; (1 - T) - op2 = 1 - op2 - T 2070(define_insn_and_split "*subc_negt_reg" 2071 [(set (match_operand:SI 0 "arith_reg_dest") 2072 (minus:SI (match_operand 1 "treg_set_expr_not_const01") 2073 (match_operand:SI 2 "arith_reg_operand"))) 2074 (clobber (reg:SI T_REG))] 2075 "TARGET_SH1 && can_create_pseudo_p ()" 2076 "#" 2077 "&& 1" 2078 [(const_int 0)] 2079{ 2080 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn); 2081 if (ti.remove_trailing_nott ()) 2082 { 2083 /* (1 - T) - op2 = 1 - op2 - T */ 2084 emit_insn (gen_subc (operands[0], 2085 force_reg (SImode, GEN_INT (1)), operands[2])); 2086 } 2087 else 2088 { 2089 /* T - op2: use movt,sub sequence. */ 2090 rtx tmp = gen_reg_rtx (SImode); 2091 emit_insn (gen_movt (tmp, get_t_reg_rtx ())); 2092 emit_insn (gen_subsi3 (operands[0], tmp, operands[2])); 2093 } 2094 DONE; 2095}) 2096 2097;; Convert 2098;; op1 - (1 - T) + op3 = op1 - 1 + T + op3 2099;; (op1 - T) + op3 = op1 - (-op3) - T 2100(define_insn_and_split "*subc_negreg_t" 2101 [(set (match_operand:SI 0 "arith_reg_dest") 2102 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand") 2103 (match_operand 2 "treg_set_expr")) 2104 (match_operand:SI 3 "arith_reg_operand"))) 2105 (clobber (reg:SI T_REG))] 2106 "TARGET_SH1 && can_create_pseudo_p ()" 2107 "#" 2108 "&& 1" 2109 [(const_int 0)] 2110{ 2111 sh_treg_insns ti = sh_split_treg_set_expr (operands[2], curr_insn); 2112 if (ti.remove_trailing_nott ()) 2113 { 2114 /* op1 - (1 - T) + op3 = (op1 - 1) + op3 + T */ 2115 rtx tmp = gen_reg_rtx (SImode); 2116 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-1))); 2117 emit_insn (gen_addc (operands[0], tmp, operands[3])); 2118 } 2119 else 2120 { 2121 /* (op1 - T) + op3' = 'op1 - (-op3) - T */ 2122 rtx tmp = gen_reg_rtx (SImode); 2123 emit_insn (gen_negsi2 (tmp, operands[3])); 2124 emit_insn (gen_subc (operands[0], operands[1], tmp)); 2125 } 2126 DONE; 2127}) 2128 2129(define_insn "*subsi3_internal" 2130 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2131 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0") 2132 (match_operand:SI 2 "arith_reg_operand" "r")))] 2133 "TARGET_SH1" 2134 "sub %2,%0" 2135 [(set_attr "type" "arith")]) 2136 2137;; Convert 2138;; constant - reg 2139;; to 2140;; neg reg 2141;; add reg, #const 2142;; since this will sometimes save one instruction. 2143;; Otherwise we might get a sequence like 2144;; mov #const, rY 2145;; sub rY, rX 2146;; mov rX, rY 2147;; if the source and dest regs are the same. 2148(define_expand "subsi3" 2149 [(set (match_operand:SI 0 "arith_reg_operand" "") 2150 (minus:SI (match_operand:SI 1 "arith_operand" "") 2151 (match_operand:SI 2 "arith_reg_operand" "")))] 2152 "" 2153{ 2154 if (CONST_INT_P (operands[1])) 2155 { 2156 emit_insn (gen_negsi2 (operands[0], operands[2])); 2157 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); 2158 DONE; 2159 } 2160}) 2161 2162;; ------------------------------------------------------------------------- 2163;; Division instructions 2164;; ------------------------------------------------------------------------- 2165 2166;; We take advantage of the library routines which don't clobber as many 2167;; registers as a normal function call would. 2168 2169;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it 2170;; also has an effect on the register that holds the address of the sfunc. 2171;; To make this work, we have an extra dummy insn that shows the use 2172;; of this register for reorg. 2173 2174(define_insn "use_sfunc_addr" 2175 [(set (reg:SI PR_REG) 2176 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))] 2177 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])" 2178 "" 2179 [(set_attr "length" "0")]) 2180 2181(define_insn "udivsi3_sh2a" 2182 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2183 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0") 2184 (match_operand:SI 2 "arith_reg_operand" "z")))] 2185 "TARGET_SH2A" 2186 "divu %2,%1" 2187 [(set_attr "type" "arith") 2188 (set_attr "in_delay_slot" "no")]) 2189 2190;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than 2191;; hard register 0. If we used hard register 0, then the next instruction 2192;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg 2193;; gets allocated to a stack slot that needs its address reloaded, then 2194;; there is nothing to prevent reload from using r0 to reload the address. 2195;; This reload would clobber the value in r0 we are trying to store. 2196;; If we let reload allocate r0, then this problem can never happen. 2197(define_insn "udivsi3_i1" 2198 [(set (match_operand:SI 0 "register_operand" "=z,z") 2199 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2200 (clobber (reg:SI T_REG)) 2201 (clobber (reg:SI PR_REG)) 2202 (clobber (reg:SI R1_REG)) 2203 (clobber (reg:SI R4_REG)) 2204 (use (match_operand:SI 1 "arith_reg_operand" "r,r")) 2205 (use (match_operand 2 "" "Z,Ccl"))] 2206 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1" 2207 "@ 2208 jsr @%1%# 2209 bsrf %1\n%O2:%#" 2210 [(set_attr "type" "sfunc") 2211 (set_attr "needs_delay_slot" "yes")]) 2212 2213(define_insn "udivsi3_i4" 2214 [(set (match_operand:SI 0 "register_operand" "=y,y") 2215 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2216 (clobber (reg:SI T_REG)) 2217 (clobber (reg:SI PR_REG)) 2218 (clobber (reg:DF DR0_REG)) 2219 (clobber (reg:DF DR2_REG)) 2220 (clobber (reg:DF DR4_REG)) 2221 (clobber (reg:SI R0_REG)) 2222 (clobber (reg:SI R1_REG)) 2223 (clobber (reg:SI R4_REG)) 2224 (clobber (reg:SI R5_REG)) 2225 (clobber (reg:SI FPSCR_STAT_REG)) 2226 (use (match_operand:SI 1 "arith_reg_operand" "r,r")) 2227 (use (match_operand 2 "" "Z,Ccl")) 2228 (use (reg:SI FPSCR_MODES_REG))] 2229 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE" 2230 "@ 2231 jsr @%1%# 2232 bsrf %1\n%O2:%#" 2233 [(set_attr "type" "sfunc") 2234 (set_attr "fp_mode" "double") 2235 (set_attr "needs_delay_slot" "yes")]) 2236 2237(define_insn "udivsi3_i4_single" 2238 [(set (match_operand:SI 0 "register_operand" "=y,y") 2239 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2240 (clobber (reg:SI T_REG)) 2241 (clobber (reg:SI PR_REG)) 2242 (clobber (reg:DF DR0_REG)) 2243 (clobber (reg:DF DR2_REG)) 2244 (clobber (reg:DF DR4_REG)) 2245 (clobber (reg:SI R0_REG)) 2246 (clobber (reg:SI R1_REG)) 2247 (clobber (reg:SI R4_REG)) 2248 (clobber (reg:SI R5_REG)) 2249 (use (match_operand:SI 1 "arith_reg_operand" "r,r")) 2250 (use (match_operand 2 "" "Z,Ccl"))] 2251 "TARGET_FPU_ANY && TARGET_FPU_SINGLE" 2252 "@ 2253 jsr @%1%# 2254 bsrf %1\n%O2:%#" 2255 [(set_attr "type" "sfunc") 2256 (set_attr "needs_delay_slot" "yes")]) 2257 2258(define_insn "udivsi3_i4_int" 2259 [(set (match_operand:SI 0 "register_operand" "=z") 2260 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2261 (clobber (reg:SI T_REG)) 2262 (clobber (reg:SI R1_REG)) 2263 (clobber (reg:SI PR_REG)) 2264 (clobber (reg:SI MACH_REG)) 2265 (clobber (reg:SI MACL_REG)) 2266 (use (match_operand:SI 1 "arith_reg_operand" "r"))] 2267 "TARGET_SH1" 2268 "jsr @%1%#" 2269 [(set_attr "type" "sfunc") 2270 (set_attr "needs_delay_slot" "yes")]) 2271 2272 2273(define_expand "udivsi3" 2274 [(set (match_operand:SI 0 "register_operand") 2275 (udiv:SI (match_operand:SI 1 "general_operand") 2276 (match_operand:SI 2 "general_operand")))] 2277 "" 2278{ 2279 rtx last; 2280 rtx func_ptr = gen_reg_rtx (Pmode); 2281 2282 /* Emit the move of the address to a pseudo outside of the libcall. */ 2283 if (TARGET_DIVIDE_CALL_TABLE) 2284 { 2285 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since 2286 that causes problems when the divide code is supposed to come from a 2287 separate library. Division by zero is undefined, so dividing 1 can be 2288 implemented by comparing with the divisor. */ 2289 if (operands[1] == const1_rtx && currently_expanding_to_rtl) 2290 { 2291 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]); 2292 emit_insn (gen_cstoresi4 (operands[0], test, 2293 operands[1], operands[2])); 2294 DONE; 2295 } 2296 else if (operands[2] == const0_rtx) 2297 { 2298 emit_move_insn (operands[0], operands[2]); 2299 DONE; 2300 } 2301 function_symbol (func_ptr, "__udivsi3_i4i", SFUNC_GOT); 2302 last = gen_udivsi3_i4_int (operands[0], func_ptr); 2303 } 2304 else if (TARGET_DIVIDE_CALL_FP) 2305 { 2306 rtx lab = function_symbol (func_ptr, "__udivsi3_i4", SFUNC_STATIC).lab; 2307 if (TARGET_FPU_SINGLE) 2308 last = gen_udivsi3_i4_single (operands[0], func_ptr, lab); 2309 else 2310 last = gen_udivsi3_i4 (operands[0], func_ptr, lab); 2311 } 2312 else if (TARGET_SH2A) 2313 { 2314 operands[1] = force_reg (SImode, operands[1]); 2315 operands[2] = force_reg (SImode, operands[2]); 2316 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2])); 2317 DONE; 2318 } 2319 else 2320 { 2321 rtx lab = function_symbol (func_ptr, "__udivsi3", SFUNC_STATIC).lab; 2322 last = gen_udivsi3_i1 (operands[0], func_ptr, lab); 2323 } 2324 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]); 2325 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]); 2326 emit_insn (last); 2327 DONE; 2328}) 2329 2330(define_insn "divsi3_sh2a" 2331 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2332 (div:SI (match_operand:SI 1 "arith_reg_operand" "0") 2333 (match_operand:SI 2 "arith_reg_operand" "z")))] 2334 "TARGET_SH2A" 2335 "divs %2,%1" 2336 [(set_attr "type" "arith") 2337 (set_attr "in_delay_slot" "no")]) 2338 2339(define_insn "divsi3_i1" 2340 [(set (match_operand:SI 0 "register_operand" "=z") 2341 (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2342 (clobber (reg:SI T_REG)) 2343 (clobber (reg:SI PR_REG)) 2344 (clobber (reg:SI R1_REG)) 2345 (clobber (reg:SI R2_REG)) 2346 (clobber (reg:SI R3_REG)) 2347 (use (match_operand:SI 1 "arith_reg_operand" "r"))] 2348 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1" 2349 "jsr @%1%#" 2350 [(set_attr "type" "sfunc") 2351 (set_attr "needs_delay_slot" "yes")]) 2352 2353(define_insn "divsi3_i4" 2354 [(set (match_operand:SI 0 "register_operand" "=y,y") 2355 (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2356 (clobber (reg:SI PR_REG)) 2357 (clobber (reg:DF DR0_REG)) 2358 (clobber (reg:DF DR2_REG)) 2359 (clobber (reg:SI FPSCR_STAT_REG)) 2360 (use (match_operand:SI 1 "arith_reg_operand" "r,r")) 2361 (use (match_operand 2 "" "Z,Ccl")) 2362 (use (reg:SI FPSCR_MODES_REG))] 2363 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE" 2364 "@ 2365 jsr @%1%# 2366 bsrf %1\n%O2:%#" 2367 [(set_attr "type" "sfunc") 2368 (set_attr "fp_mode" "double") 2369 (set_attr "needs_delay_slot" "yes")]) 2370 2371(define_insn "divsi3_i4_single" 2372 [(set (match_operand:SI 0 "register_operand" "=y,y") 2373 (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2374 (clobber (reg:SI PR_REG)) 2375 (clobber (reg:DF DR0_REG)) 2376 (clobber (reg:DF DR2_REG)) 2377 (clobber (reg:SI R2_REG)) 2378 (use (match_operand:SI 1 "arith_reg_operand" "r,r")) 2379 (use (match_operand 2 "" "Z,Ccl"))] 2380 "TARGET_FPU_ANY && TARGET_FPU_SINGLE" 2381 "@ 2382 jsr @%1%# 2383 bsrf %1\n%O2:%#" 2384 [(set_attr "type" "sfunc") 2385 (set_attr "needs_delay_slot" "yes")]) 2386 2387(define_insn "divsi3_i4_int" 2388 [(set (match_operand:SI 0 "register_operand" "=z") 2389 (div:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2390 (clobber (reg:SI T_REG)) 2391 (clobber (reg:SI PR_REG)) 2392 (clobber (reg:SI R1_REG)) 2393 (clobber (reg:SI MACH_REG)) 2394 (clobber (reg:SI MACL_REG)) 2395 (use (match_operand:SI 1 "arith_reg_operand" "r"))] 2396 "TARGET_SH1" 2397 "jsr @%1%#" 2398 [(set_attr "type" "sfunc") 2399 (set_attr "needs_delay_slot" "yes")]) 2400 2401(define_expand "divsi3" 2402 [(set (match_operand:SI 0 "register_operand") 2403 (div:SI (match_operand:SI 1 "general_operand") 2404 (match_operand:SI 2 "general_operand")))] 2405 "" 2406{ 2407 rtx last; 2408 rtx func_ptr = gen_reg_rtx (Pmode); 2409 2410 /* Emit the move of the address to a pseudo outside of the libcall. */ 2411 if (TARGET_DIVIDE_CALL_TABLE) 2412 { 2413 function_symbol (func_ptr, sh_divsi3_libfunc, SFUNC_GOT); 2414 last = gen_divsi3_i4_int (operands[0], func_ptr); 2415 } 2416 else if (TARGET_DIVIDE_CALL_FP) 2417 { 2418 rtx lab = function_symbol (func_ptr, sh_divsi3_libfunc, 2419 SFUNC_STATIC).lab; 2420 if (TARGET_FPU_SINGLE) 2421 last = gen_divsi3_i4_single (operands[0], func_ptr, lab); 2422 else 2423 last = gen_divsi3_i4 (operands[0], func_ptr, lab); 2424 } 2425 else if (TARGET_SH2A) 2426 { 2427 operands[1] = force_reg (SImode, operands[1]); 2428 operands[2] = force_reg (SImode, operands[2]); 2429 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2])); 2430 DONE; 2431 } 2432 else 2433 { 2434 function_symbol (func_ptr, sh_divsi3_libfunc, SFUNC_GOT); 2435 last = gen_divsi3_i1 (operands[0], func_ptr); 2436 } 2437 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]); 2438 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]); 2439 emit_insn (last); 2440 DONE; 2441}) 2442 2443 2444;; ------------------------------------------------------------------------- 2445;; Multiplication instructions 2446;; ------------------------------------------------------------------------- 2447 2448(define_insn_and_split "mulhisi3" 2449 [(set (match_operand:SI 0 "arith_reg_dest") 2450 (mult:SI (sign_extend:SI (match_operand:HI 1 "arith_reg_operand")) 2451 (sign_extend:SI (match_operand:HI 2 "arith_reg_operand")))) 2452 (clobber (reg:SI MACL_REG))] 2453 "TARGET_SH1 && can_create_pseudo_p ()" 2454 "#" 2455 "&& 1" 2456 [(set (reg:SI MACL_REG) (mult:SI (sign_extend:SI (match_dup 1)) 2457 (sign_extend:SI (match_dup 2)))) 2458 (set (match_dup 0) (reg:SI MACL_REG))]) 2459 2460(define_insn_and_split "umulhisi3" 2461 [(set (match_operand:SI 0 "arith_reg_dest") 2462 (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand")) 2463 (zero_extend:SI (match_operand:HI 2 "arith_reg_operand")))) 2464 (clobber (reg:SI MACL_REG))] 2465 "TARGET_SH1 && can_create_pseudo_p ()" 2466 "#" 2467 "&& 1" 2468 [(set (reg:SI MACL_REG) (mult:SI (zero_extend:SI (match_dup 1)) 2469 (zero_extend:SI (match_dup 2)))) 2470 (set (match_dup 0) (reg:SI MACL_REG))]) 2471 2472(define_insn "umulhisi3_i" 2473 [(set (reg:SI MACL_REG) 2474 (mult:SI (zero_extend:SI 2475 (match_operand:HI 0 "arith_reg_operand" "r")) 2476 (zero_extend:SI 2477 (match_operand:HI 1 "arith_reg_operand" "r"))))] 2478 "TARGET_SH1" 2479 "mulu.w %1,%0" 2480 [(set_attr "type" "smpy")]) 2481 2482(define_insn "mulhisi3_i" 2483 [(set (reg:SI MACL_REG) 2484 (mult:SI (sign_extend:SI 2485 (match_operand:HI 0 "arith_reg_operand" "r")) 2486 (sign_extend:SI 2487 (match_operand:HI 1 "arith_reg_operand" "r"))))] 2488 "TARGET_SH1" 2489 "muls.w %1,%0" 2490 [(set_attr "type" "smpy")]) 2491 2492 2493;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate 2494;; a call to a routine which clobbers known registers. 2495(define_insn "mulsi3_call" 2496 [(set (match_operand:SI 1 "register_operand" "=z") 2497 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG))) 2498 (clobber (reg:SI MACL_REG)) 2499 (clobber (reg:SI T_REG)) 2500 (clobber (reg:SI PR_REG)) 2501 (clobber (reg:SI R3_REG)) 2502 (clobber (reg:SI R2_REG)) 2503 (clobber (reg:SI R1_REG)) 2504 (use (match_operand:SI 0 "arith_reg_operand" "r"))] 2505 "TARGET_SH1" 2506 "jsr @%0%#" 2507 [(set_attr "type" "sfunc") 2508 (set_attr "needs_delay_slot" "yes")]) 2509 2510(define_insn "mul_r" 2511 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2512 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0") 2513 (match_operand:SI 2 "arith_reg_operand" "z")))] 2514 "TARGET_SH2A" 2515 "mulr %2,%0" 2516 [(set_attr "type" "dmpy")]) 2517 2518(define_insn "mul_l" 2519 [(set (reg:SI MACL_REG) 2520 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r") 2521 (match_operand:SI 1 "arith_reg_operand" "r")))] 2522 "TARGET_SH2" 2523 "mul.l %1,%0" 2524 [(set_attr "type" "dmpy")]) 2525 2526(define_insn_and_split "mulsi3_i" 2527 [(set (match_operand:SI 0 "arith_reg_dest") 2528 (mult:SI (match_operand:SI 1 "arith_reg_operand") 2529 (match_operand:SI 2 "arith_reg_operand"))) 2530 (clobber (reg:SI MACL_REG))] 2531 "TARGET_SH2 && can_create_pseudo_p ()" 2532 "#" 2533 "&& 1" 2534 [(set (reg:SI MACL_REG) (mult:SI (match_dup 1) (match_dup 2))) 2535 (set (match_dup 0) (reg:SI MACL_REG))]) 2536 2537(define_expand "mulsi3" 2538 [(set (match_operand:SI 0 "arith_reg_dest") 2539 (mult:SI (match_operand:SI 1 "arith_reg_operand") 2540 (match_operand:SI 2 "arith_reg_operand")))] 2541 "TARGET_SH1" 2542{ 2543 if (!TARGET_SH2) 2544 { 2545 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]); 2546 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]); 2547 2548 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym; 2549 2550 emit_insn (gen_mulsi3_call (force_reg (SImode, sym), operands[0])); 2551 } 2552 else 2553 { 2554 /* FIXME: For some reason, expanding the mul_l insn and the macl store 2555 insn early gives slightly better code. In particular it prevents 2556 the decrement-test loop type to be used in some cases which saves 2557 one multiplication in the loop setup code. 2558 2559 emit_insn (gen_mulsi3_i (operands[0], operands[1], operands[2])); 2560 */ 2561 2562 emit_insn (gen_mul_l (operands[1], operands[2])); 2563 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG)); 2564 } 2565 DONE; 2566}) 2567 2568(define_insn "mulsidi3_i" 2569 [(set (reg:SI MACH_REG) 2570 (truncate:SI 2571 (lshiftrt:DI 2572 (mult:DI 2573 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r")) 2574 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))) 2575 (const_int 32)))) 2576 (set (reg:SI MACL_REG) 2577 (mult:SI (match_dup 0) 2578 (match_dup 1)))] 2579 "TARGET_SH2" 2580 "dmuls.l %1,%0" 2581 [(set_attr "type" "dmpy")]) 2582 2583(define_expand "mulsidi3" 2584 [(set (match_operand:DI 0 "arith_reg_dest") 2585 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand")) 2586 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))] 2587 "TARGET_SH2" 2588{ 2589 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2])); 2590 DONE; 2591}) 2592 2593(define_insn_and_split "mulsidi3_compact" 2594 [(set (match_operand:DI 0 "arith_reg_dest") 2595 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand")) 2596 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand")))) 2597 (clobber (reg:SI MACH_REG)) 2598 (clobber (reg:SI MACL_REG))] 2599 "TARGET_SH2 && can_create_pseudo_p ()" 2600 "#" 2601 "&& 1" 2602 [(const_int 0)] 2603{ 2604 rtx low_dst = gen_lowpart (SImode, operands[0]); 2605 rtx high_dst = gen_highpart (SImode, operands[0]); 2606 2607 emit_insn (gen_mulsidi3_i (operands[1], operands[2])); 2608 2609 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG)); 2610 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG)); 2611 /* We need something to tag the possible REG_EQUAL notes on to. */ 2612 emit_move_insn (operands[0], operands[0]); 2613 DONE; 2614}) 2615 2616(define_insn "umulsidi3_i" 2617 [(set (reg:SI MACH_REG) 2618 (truncate:SI 2619 (lshiftrt:DI 2620 (mult:DI 2621 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r")) 2622 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))) 2623 (const_int 32)))) 2624 (set (reg:SI MACL_REG) 2625 (mult:SI (match_dup 0) 2626 (match_dup 1)))] 2627 "TARGET_SH2" 2628 "dmulu.l %1,%0" 2629 [(set_attr "type" "dmpy")]) 2630 2631(define_expand "umulsidi3" 2632 [(set (match_operand:DI 0 "arith_reg_dest") 2633 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand")) 2634 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))] 2635 "TARGET_SH2" 2636{ 2637 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2])); 2638 DONE; 2639}) 2640 2641(define_insn_and_split "umulsidi3_compact" 2642 [(set (match_operand:DI 0 "arith_reg_dest") 2643 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand")) 2644 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand")))) 2645 (clobber (reg:SI MACH_REG)) 2646 (clobber (reg:SI MACL_REG))] 2647 "TARGET_SH2 && can_create_pseudo_p ()" 2648 "#" 2649 "&& 1" 2650 [(const_int 0)] 2651{ 2652 rtx low_dst = gen_lowpart (SImode, operands[0]); 2653 rtx high_dst = gen_highpart (SImode, operands[0]); 2654 2655 emit_insn (gen_umulsidi3_i (operands[1], operands[2])); 2656 2657 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG)); 2658 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG)); 2659 /* We need something to tag the possible REG_EQUAL notes on to. */ 2660 emit_move_insn (operands[0], operands[0]); 2661 DONE; 2662}) 2663 2664(define_insn "smulsi3_highpart_i" 2665 [(set (reg:SI MACH_REG) 2666 (truncate:SI 2667 (lshiftrt:DI 2668 (mult:DI 2669 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r")) 2670 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))) 2671 (const_int 32)))) 2672 (clobber (reg:SI MACL_REG))] 2673 "TARGET_SH2" 2674 "dmuls.l %1,%0" 2675 [(set_attr "type" "dmpy")]) 2676 2677(define_insn_and_split "smulsi3_highpart" 2678 [(set (match_operand:SI 0 "arith_reg_dest") 2679 (truncate:SI 2680 (lshiftrt:DI 2681 (mult:DI 2682 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand")) 2683 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))) 2684 (const_int 32)))) 2685 (clobber (reg:SI MACL_REG)) 2686 (clobber (reg:SI MACH_REG))] 2687 "TARGET_SH2 && can_create_pseudo_p ()" 2688 "#" 2689 "&& 1" 2690 [(const_int 0)] 2691{ 2692 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2])); 2693 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG)); 2694}) 2695 2696(define_insn "umulsi3_highpart_i" 2697 [(set (reg:SI MACH_REG) 2698 (truncate:SI 2699 (lshiftrt:DI 2700 (mult:DI 2701 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r")) 2702 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))) 2703 (const_int 32)))) 2704 (clobber (reg:SI MACL_REG))] 2705 "TARGET_SH2" 2706 "dmulu.l %1,%0" 2707 [(set_attr "type" "dmpy")]) 2708 2709(define_insn_and_split "umulsi3_highpart" 2710 [(set (match_operand:SI 0 "arith_reg_dest") 2711 (truncate:SI 2712 (lshiftrt:DI 2713 (mult:DI 2714 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand")) 2715 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))) 2716 (const_int 32)))) 2717 (clobber (reg:SI MACL_REG))] 2718 "TARGET_SH2 && can_create_pseudo_p ()" 2719 "#" 2720 "&& 1" 2721 [(const_int 0)] 2722{ 2723 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2])); 2724 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG)); 2725}) 2726 2727;; ------------------------------------------------------------------------- 2728;; Logical operations 2729;; ------------------------------------------------------------------------- 2730 2731(define_expand "andsi3" 2732 [(set (match_operand:SI 0 "arith_reg_dest") 2733 (and:SI (match_operand:SI 1 "arith_reg_operand") 2734 (match_operand:SI 2 "logical_and_operand")))] 2735 "" 2736{ 2737 /* If it is possible to turn the and insn into a zero extension 2738 already, redundant zero extensions will be folded, which results 2739 in better code. 2740 Ideally the splitter of *andsi_compact would be enough, if redundant 2741 zero extensions were detected after the combine pass, which does not 2742 happen at the moment. */ 2743 2744 if (satisfies_constraint_Jmb (operands[2])) 2745 { 2746 emit_insn (gen_zero_extendqisi2 (operands[0], 2747 gen_lowpart (QImode, operands[1]))); 2748 DONE; 2749 } 2750 else if (satisfies_constraint_Jmw (operands[2])) 2751 { 2752 emit_insn (gen_zero_extendhisi2 (operands[0], 2753 gen_lowpart (HImode, operands[1]))); 2754 DONE; 2755 } 2756}) 2757 2758(define_insn_and_split "*andsi_compact" 2759 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r") 2760 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0") 2761 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))] 2762 "TARGET_SH1" 2763 "@ 2764 extu.b %1,%0 2765 extu.w %1,%0 2766 and %2,%0 2767 and %2,%0" 2768 "&& 1" 2769 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))] 2770{ 2771 if (satisfies_constraint_Jmb (operands[2])) 2772 operands[1] = gen_lowpart (QImode, operands[1]); 2773 else if (satisfies_constraint_Jmw (operands[2])) 2774 operands[1] = gen_lowpart (HImode, operands[1]); 2775 else 2776 FAIL; 2777} 2778 [(set_attr "type" "arith")]) 2779 2780(define_insn "*andsi3_bclr" 2781 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2782 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0") 2783 (match_operand:SI 2 "const_int_operand" "Psz")))] 2784 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])" 2785 "bclr %W2,%0" 2786 [(set_attr "type" "arith")]) 2787 2788(define_expand "iorsi3" 2789 [(set (match_operand:SI 0 "arith_reg_dest") 2790 (ior:SI (match_operand:SI 1 "arith_reg_operand") 2791 (match_operand:SI 2 "logical_operand")))]) 2792 2793(define_insn "*iorsi3_compact" 2794 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z") 2795 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") 2796 (match_operand:SI 2 "logical_operand" "r,K08")))] 2797 "TARGET_SH1 2798 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))" 2799 "or %2,%0" 2800 [(set_attr "type" "arith")]) 2801 2802(define_insn "*iorsi3_bset" 2803 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2804 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0") 2805 (match_operand:SI 2 "const_int_operand" "Pso")))] 2806 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])" 2807 "bset %V2,%0" 2808 [(set_attr "type" "arith")]) 2809 2810(define_insn "xorsi3" 2811 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r") 2812 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0") 2813 (match_operand:SI 2 "logical_operand" "K08,r")))] 2814 "TARGET_SH1" 2815 "xor %2,%0" 2816 [(set_attr "type" "arith")]) 2817 2818;; The *logical_op_t pattern helps combine eliminating sign/zero extensions 2819;; of results where one of the inputs is a T bit store. Notice that this 2820;; pattern must not match during reload. If reload picks this pattern it 2821;; will be impossible to split it afterwards. 2822(define_insn_and_split "*logical_op_t" 2823 [(set (match_operand:SI 0 "arith_reg_dest") 2824 (match_operator:SI 3 "logical_operator" 2825 [(match_operand:SI 1 "arith_reg_operand") 2826 (match_operand:SI 2 "t_reg_operand")]))] 2827 "TARGET_SH1 && can_create_pseudo_p ()" 2828 "#" 2829 "&& 1" 2830 [(set (match_dup 4) (reg:SI T_REG)) 2831 (set (match_dup 0) (match_dup 3))] 2832{ 2833 operands[4] = gen_reg_rtx (SImode); 2834 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 2835 operands[1], operands[4]); 2836}) 2837 2838;; ------------------------------------------------------------------------- 2839;; Shifts and rotates 2840;; ------------------------------------------------------------------------- 2841 2842;; Let combine see that we can get the MSB and LSB into the T bit 2843;; via shll and shlr. This allows it to plug it into insns that can have 2844;; the T bit as an input (e.g. addc). 2845;; On SH2A use bld #0,Rn instead of shlr to avoid mutating the input. 2846(define_insn_and_split "*reg_lsb_t" 2847 [(set (reg:SI T_REG) 2848 (and:SI (match_operand:SI 0 "arith_reg_operand") 2849 (const_int 1)))] 2850 "TARGET_SH1 && can_create_pseudo_p ()" 2851 "#" 2852 "&& 1" 2853 [(const_int 0)] 2854{ 2855 emit_insn (TARGET_SH2A ? gen_bldsi_reg (operands[0], const0_rtx) 2856 : gen_shlr (gen_reg_rtx (SImode), operands[0])); 2857}) 2858 2859(define_insn_and_split "*reg_msb_t" 2860 [(set (reg:SI T_REG) 2861 (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand") 2862 (const_int 31)))] 2863 "TARGET_SH1 && can_create_pseudo_p ()" 2864 "#" 2865 "&& 1" 2866 [(const_int 0)] 2867{ 2868 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0])); 2869}) 2870 2871(define_expand "rotrsi3" 2872 [(set (match_operand:SI 0 "arith_reg_dest") 2873 (rotatert:SI (match_operand:SI 1 "arith_reg_operand") 2874 (match_operand:SI 2 "const_int_operand")))] 2875 "TARGET_SH1" 2876{ 2877 HOST_WIDE_INT ival = INTVAL (operands[2]); 2878 if (ival == 1) 2879 { 2880 emit_insn (gen_rotrsi3_1 (operands[0], operands[1])); 2881 DONE; 2882 } 2883 2884 FAIL; 2885}) 2886 2887(define_insn "rotrsi3_1" 2888 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2889 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0") 2890 (const_int 1))) 2891 (set (reg:SI T_REG) 2892 (and:SI (match_dup 1) (const_int 1)))] 2893 "TARGET_SH1" 2894 "rotr %0" 2895 [(set_attr "type" "arith")]) 2896 2897;; A slimplified version of rotr for combine. 2898(define_insn "*rotrsi3_1" 2899 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2900 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0") 2901 (const_int 1))) 2902 (clobber (reg:SI T_REG))] 2903 "TARGET_SH1" 2904 "rotr %0" 2905 [(set_attr "type" "arith")]) 2906 2907(define_insn "rotlsi3_1" 2908 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2909 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0") 2910 (const_int 1))) 2911 (set (reg:SI T_REG) 2912 (lshiftrt:SI (match_dup 1) (const_int 31)))] 2913 "TARGET_SH1" 2914 "rotl %0" 2915 [(set_attr "type" "arith")]) 2916 2917;; A simplified version of rotl for combine. 2918(define_insn "*rotlsi3_1" 2919 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2920 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0") 2921 (const_int 1))) 2922 (clobber (reg:SI T_REG))] 2923 "TARGET_SH1" 2924 "rotl %0" 2925 [(set_attr "type" "arith")]) 2926 2927(define_insn "rotlsi3_31" 2928 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2929 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0") 2930 (const_int 31))) 2931 (clobber (reg:SI T_REG))] 2932 "TARGET_SH1" 2933 "rotr %0" 2934 [(set_attr "type" "arith")]) 2935 2936(define_insn "rotlsi3_16" 2937 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 2938 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r") 2939 (const_int 16)))] 2940 "TARGET_SH1" 2941 "swap.w %1,%0" 2942 [(set_attr "type" "arith")]) 2943 2944(define_expand "rotlsi3" 2945 [(set (match_operand:SI 0 "arith_reg_dest") 2946 (rotate:SI (match_operand:SI 1 "arith_reg_operand") 2947 (match_operand:SI 2 "const_int_operand")))] 2948 "TARGET_SH1" 2949{ 2950 static const char rot_tab[] = { 2951 000, 000, 000, 000, 000, 000, 010, 001, 2952 001, 001, 011, 013, 003, 003, 003, 003, 2953 003, 003, 003, 003, 003, 013, 012, 002, 2954 002, 002, 010, 000, 000, 000, 000, 000, 2955 }; 2956 2957 int count = INTVAL (operands[2]); 2958 int choice = rot_tab[count]; 2959 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1) 2960 FAIL; 2961 choice &= 7; 2962 switch (choice) 2963 { 2964 case 0: 2965 emit_move_insn (operands[0], operands[1]); 2966 count -= (count & 16) * 2; 2967 break; 2968 case 3: 2969 emit_insn (gen_rotlsi3_16 (operands[0], operands[1])); 2970 count -= 16; 2971 break; 2972 case 1: 2973 case 2: 2974 { 2975 rtx parts[2]; 2976 parts[0] = gen_reg_rtx (SImode); 2977 parts[1] = gen_reg_rtx (SImode); 2978 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1])); 2979 emit_move_insn (parts[choice-1], operands[1]); 2980 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8))); 2981 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8))); 2982 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1])); 2983 count = (count & ~16) - 8; 2984 } 2985 } 2986 2987 for (; count > 0; count--) 2988 emit_insn (gen_rotlsi3_1 (operands[0], operands[0])); 2989 for (; count < 0; count++) 2990 emit_insn (gen_rotlsi3_31 (operands[0], operands[0])); 2991 2992 DONE; 2993}) 2994 2995(define_insn "rotlhi3_8" 2996 [(set (match_operand:HI 0 "arith_reg_dest" "=r") 2997 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r") 2998 (const_int 8)))] 2999 "TARGET_SH1" 3000 "swap.b %1,%0" 3001 [(set_attr "type" "arith")]) 3002 3003(define_expand "rotlhi3" 3004 [(set (match_operand:HI 0 "arith_reg_operand") 3005 (rotate:HI (match_operand:HI 1 "arith_reg_operand") 3006 (match_operand:HI 2 "const_int_operand")))] 3007 "TARGET_SH1" 3008{ 3009 if (INTVAL (operands[2]) != 8) 3010 FAIL; 3011}) 3012 3013;; The rotcr and rotcl insns are used primarily in DImode shifts by one. 3014;; They can also be used to implement things like 3015;; bool t = a == b; 3016;; int x0 = (y >> 1) | (t << 31); // rotcr 3017;; int x1 = (y << 1) | t; // rotcl 3018(define_insn "rotcr" 3019 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3020 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 3021 (const_int 1)) 3022 (ashift:SI (match_operand:SI 2 "t_reg_operand") 3023 (const_int 31)))) 3024 (set (reg:SI T_REG) 3025 (and:SI (match_dup 1) (const_int 1)))] 3026 "TARGET_SH1" 3027 "rotcr %0" 3028 [(set_attr "type" "arith")]) 3029 3030(define_insn "rotcl" 3031 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3032 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") 3033 (const_int 1)) 3034 (match_operand:SI 2 "t_reg_operand"))) 3035 (set (reg:SI T_REG) 3036 (lshiftrt:SI (match_dup 1) (const_int 31)))] 3037 "TARGET_SH1" 3038 "rotcl %0" 3039 [(set_attr "type" "arith")]) 3040 3041;; Simplified rotcr version for combine, which allows arbitrary shift 3042;; amounts for the reg. If the shift amount is '1' rotcr can be used 3043;; directly. Otherwise we have to insert a shift in between. 3044(define_insn_and_split "*rotcr" 3045 [(set (match_operand:SI 0 "arith_reg_dest") 3046 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_or_0_operand") 3047 (match_operand:SI 2 "const_int_operand")) 3048 (ashift:SI (match_operand 3 "arith_reg_or_treg_set_expr") 3049 (const_int 31)))) 3050 (clobber (reg:SI T_REG))] 3051 "TARGET_SH1 && can_create_pseudo_p ()" 3052 "#" 3053 "&& 1" 3054 [(const_int 0)] 3055{ 3056 rtx_insn *prev_set_t_insn = NULL; 3057 3058 if (!arith_reg_operand (operands[3], SImode)) 3059 { 3060 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn); 3061 if (!ti.was_treg_operand ()) 3062 prev_set_t_insn = ti.first_insn (); 3063 3064 operands[3] = get_t_reg_rtx (); 3065 3066 if (TARGET_SH2A && ti.has_trailing_nott () && operands[1] == const0_rtx) 3067 { 3068 /* Convert to a movrt, rotr sequence. */ 3069 remove_insn (ti.trailing_nott ()); 3070 rtx tmp = gen_reg_rtx (SImode); 3071 emit_insn (gen_movnegt (tmp, get_t_reg_rtx ())); 3072 emit_insn (gen_rotrsi3_1 (operands[0], tmp)); 3073 DONE; 3074 } 3075 } 3076 3077 if (operands[1] == const0_rtx) 3078 { 3079 operands[1] = gen_reg_rtx (SImode); 3080 emit_insn (gen_movt (operands[1], get_t_reg_rtx ())); 3081 } 3082 3083 if (INTVAL (operands[2]) > 1) 3084 { 3085 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1); 3086 rtx tmp_t_reg = NULL_RTX; 3087 3088 /* If we're going to emit a shift sequence that clobbers the T_REG, 3089 try to find the previous insn that sets the T_REG and emit the 3090 shift insn before that insn, to remove the T_REG dependency. 3091 If the insn that sets the T_REG cannot be found, store the T_REG 3092 in a temporary reg and restore it after the shift. */ 3093 if (sh_lshrsi_clobbers_t_reg_p (shift_count) 3094 && ! sh_dynamicalize_shift_p (shift_count)) 3095 { 3096 if (prev_set_t_insn == NULL) 3097 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn); 3098 3099 /* Skip the nott insn, which was probably inserted by the splitter 3100 of *rotcr_neg_t. Don't use one of the recog functions 3101 here during insn splitting, since that causes problems in later 3102 passes. */ 3103 if (prev_set_t_insn != NULL_RTX) 3104 { 3105 rtx pat = PATTERN (prev_set_t_insn); 3106 if (GET_CODE (pat) == SET 3107 && t_reg_operand (XEXP (pat, 0), SImode) 3108 && negt_reg_operand (XEXP (pat, 1), SImode)) 3109 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn); 3110 } 3111 3112 if (! (prev_set_t_insn != NULL_RTX 3113 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn) 3114 && ! reg_referenced_p (get_t_reg_rtx (), 3115 PATTERN (prev_set_t_insn)))) 3116 { 3117 prev_set_t_insn = NULL; 3118 tmp_t_reg = gen_reg_rtx (SImode); 3119 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ())); 3120 } 3121 } 3122 3123 rtx shift_result = gen_reg_rtx (SImode); 3124 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count); 3125 operands[1] = shift_result; 3126 3127 /* Emit the shift insn before the insn that sets T_REG, if possible. */ 3128 if (prev_set_t_insn != NULL_RTX) 3129 emit_insn_before (shift_insn, prev_set_t_insn); 3130 else 3131 emit_insn (shift_insn); 3132 3133 /* Restore T_REG if it has been saved before. */ 3134 if (tmp_t_reg != NULL_RTX) 3135 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx)); 3136 } 3137 3138 /* For the rotcr insn to work, operands[3] must be in T_REG. 3139 If it is not we can get it there by shifting it right one bit. 3140 In this case T_REG is not an input for this insn, thus we don't have to 3141 pay attention as of where to insert the shlr insn. */ 3142 if (! t_reg_operand (operands[3], SImode)) 3143 { 3144 /* We don't care about the shifted result here, only the T_REG. */ 3145 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3])); 3146 operands[3] = get_t_reg_rtx (); 3147 } 3148 3149 emit_insn (gen_rotcr (operands[0], operands[1], operands[3])); 3150 DONE; 3151}) 3152 3153;; If combine tries the same as above but with swapped operands, split 3154;; it so that it will try the pattern above. 3155(define_split 3156 [(set (match_operand:SI 0 "arith_reg_dest") 3157 (ior:SI (ashift:SI (match_operand 1 "arith_reg_or_treg_set_expr") 3158 (const_int 31)) 3159 (lshiftrt:SI (match_operand:SI 2 "arith_reg_or_0_operand") 3160 (match_operand:SI 3 "const_int_operand"))))] 3161 "TARGET_SH1 && can_create_pseudo_p ()" 3162 [(parallel [(set (match_dup 0) 3163 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3)) 3164 (ashift:SI (match_dup 1) (const_int 31)))) 3165 (clobber (reg:SI T_REG))])]) 3166 3167;; Basically the same as the rotcr pattern above, but for rotcl. 3168;; FIXME: Fold copy pasted split code for rotcr and rotcl. 3169(define_insn_and_split "*rotcl" 3170 [(set (match_operand:SI 0 "arith_reg_dest") 3171 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand") 3172 (match_operand:SI 2 "const_int_operand")) 3173 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand") 3174 (const_int 1)))) 3175 (clobber (reg:SI T_REG))] 3176 "TARGET_SH1" 3177 "#" 3178 "&& can_create_pseudo_p ()" 3179 [(const_int 0)] 3180{ 3181 gcc_assert (INTVAL (operands[2]) > 0); 3182 3183 if (INTVAL (operands[2]) > 1) 3184 { 3185 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1); 3186 rtx_insn *prev_set_t_insn = NULL; 3187 rtx tmp_t_reg = NULL_RTX; 3188 3189 /* If we're going to emit a shift sequence that clobbers the T_REG, 3190 try to find the previous insn that sets the T_REG and emit the 3191 shift insn before that insn, to remove the T_REG dependency. 3192 If the insn that sets the T_REG cannot be found, store the T_REG 3193 in a temporary reg and restore it after the shift. */ 3194 if (sh_ashlsi_clobbers_t_reg_p (shift_count) 3195 && ! sh_dynamicalize_shift_p (shift_count)) 3196 { 3197 prev_set_t_insn = prev_nonnote_insn_bb (curr_insn); 3198 3199 /* Skip the nott insn, which was probably inserted by the splitter 3200 of *rotcl_neg_t. Don't use one of the recog functions 3201 here during insn splitting, since that causes problems in later 3202 passes. */ 3203 if (prev_set_t_insn != NULL_RTX) 3204 { 3205 rtx pat = PATTERN (prev_set_t_insn); 3206 if (GET_CODE (pat) == SET 3207 && t_reg_operand (XEXP (pat, 0), SImode) 3208 && negt_reg_operand (XEXP (pat, 1), SImode)) 3209 prev_set_t_insn = prev_nonnote_insn_bb (prev_set_t_insn); 3210 } 3211 3212 if (! (prev_set_t_insn != NULL_RTX 3213 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn) 3214 && ! reg_referenced_p (get_t_reg_rtx (), 3215 PATTERN (prev_set_t_insn)))) 3216 { 3217 prev_set_t_insn = NULL; 3218 tmp_t_reg = gen_reg_rtx (SImode); 3219 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ())); 3220 } 3221 } 3222 3223 rtx shift_result = gen_reg_rtx (SImode); 3224 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count); 3225 operands[1] = shift_result; 3226 3227 /* Emit the shift insn before the insn that sets T_REG, if possible. */ 3228 if (prev_set_t_insn != NULL_RTX) 3229 emit_insn_before (shift_insn, prev_set_t_insn); 3230 else 3231 emit_insn (shift_insn); 3232 3233 /* Restore T_REG if it has been saved before. */ 3234 if (tmp_t_reg != NULL_RTX) 3235 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx)); 3236 } 3237 3238 /* For the rotcl insn to work, operands[3] must be in T_REG. 3239 If it is not we can get it there by shifting it right one bit. 3240 In this case T_REG is not an input for this insn, thus we don't have to 3241 pay attention as of where to insert the shlr insn. */ 3242 if (! t_reg_operand (operands[3], SImode)) 3243 { 3244 /* We don't care about the shifted result here, only the T_REG. */ 3245 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3])); 3246 operands[3] = get_t_reg_rtx (); 3247 } 3248 3249 emit_insn (gen_rotcl (operands[0], operands[1], operands[3])); 3250 DONE; 3251}) 3252 3253;; rotcl combine pattern variations 3254(define_insn_and_split "*rotcl" 3255 [(set (match_operand:SI 0 "arith_reg_dest") 3256 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand") 3257 (match_operand:SI 2 "const_int_operand")) 3258 (match_operand 3 "treg_set_expr"))) 3259 (clobber (reg:SI T_REG))] 3260 "TARGET_SH1" 3261 "#" 3262 "&& can_create_pseudo_p ()" 3263 [(parallel [(set (match_dup 0) 3264 (ior:SI (ashift:SI (match_dup 1) (match_dup 2)) 3265 (and:SI (match_dup 3) (const_int 1)))) 3266 (clobber (reg:SI T_REG))])] 3267{ 3268 sh_split_treg_set_expr (operands[3], curr_insn); 3269 operands[3] = get_t_reg_rtx (); 3270}) 3271 3272(define_insn_and_split "*rotcl" 3273 [(set (match_operand:SI 0 "arith_reg_dest") 3274 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand") 3275 (const_int 1)) 3276 (ashift:SI (match_operand:SI 2 "arith_reg_operand") 3277 (match_operand:SI 3 "const_int_operand")))) 3278 (clobber (reg:SI T_REG))] 3279 "TARGET_SH1" 3280 "#" 3281 "&& can_create_pseudo_p ()" 3282 [(parallel [(set (match_dup 0) 3283 (ior:SI (ashift:SI (match_dup 2) (match_dup 3)) 3284 (and:SI (match_dup 1) (const_int 1)))) 3285 (clobber (reg:SI T_REG))])]) 3286 3287(define_insn_and_split "*rotcl" 3288 [(set (match_operand:SI 0 "arith_reg_dest") 3289 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand") 3290 (match_operand:SI 2 "const_int_operand")) 3291 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand") 3292 (const_int 31)))) 3293 (clobber (reg:SI T_REG))] 3294 "TARGET_SH1" 3295 "#" 3296 "&& can_create_pseudo_p ()" 3297 [(parallel [(set (match_dup 0) 3298 (ior:SI (ashift:SI (match_dup 1) (match_dup 2)) 3299 (and:SI (reg:SI T_REG) (const_int 1)))) 3300 (clobber (reg:SI T_REG))])] 3301{ 3302 /* We don't care about the result of the left shift, only the T_REG. */ 3303 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3])); 3304}) 3305 3306(define_insn_and_split "*rotcl" 3307 [(set (match_operand:SI 0 "arith_reg_dest") 3308 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand") 3309 (const_int 31)) 3310 (ashift:SI (match_operand:SI 1 "arith_reg_operand") 3311 (match_operand:SI 2 "const_int_operand")))) 3312 (clobber (reg:SI T_REG))] 3313 "TARGET_SH1" 3314 "#" 3315 "&& can_create_pseudo_p ()" 3316 [(parallel [(set (match_dup 0) 3317 (ior:SI (ashift:SI (match_dup 1) (match_dup 2)) 3318 (and:SI (reg:SI T_REG) (const_int 1)))) 3319 (clobber (reg:SI T_REG))])] 3320{ 3321 /* We don't care about the result of the left shift, only the T_REG. */ 3322 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3])); 3323}) 3324 3325(define_insn_and_split "*rotcl" 3326 [(set (match_operand:SI 0 "arith_reg_dest") 3327 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand") 3328 (match_operand 2 "const_int_operand")) 3329 (zero_extract:SI (match_operand:SI 3 "arith_reg_operand") 3330 (const_int 1) 3331 (match_operand 4 "const_int_operand")))) 3332 (clobber (reg:SI T_REG))] 3333 "TARGET_SH1" 3334 "#" 3335 "&& can_create_pseudo_p ()" 3336 [(parallel [(set (match_dup 0) 3337 (ior:SI (ashift:SI (match_dup 1) (match_dup 2)) 3338 (and:SI (match_dup 5) (const_int 1)))) 3339 (clobber (reg:SI T_REG))])] 3340{ 3341 if (TARGET_SH2A && satisfies_constraint_K03 (operands[4])) 3342 { 3343 /* On SH2A we can use the bld insn to zero extract a single bit 3344 into the T bit. */ 3345 operands[5] = get_t_reg_rtx (); 3346 emit_insn (gen_bldsi_reg (operands[3], operands[4])); 3347 } 3348 else 3349 { 3350 /* If we can't use the bld insn we have to emit a tst + nott sequence 3351 to get the extracted bit into the T bit. 3352 This will probably be worse than pre-shifting the operand. */ 3353 operands[5] = gen_reg_rtx (SImode); 3354 emit_insn (gen_lshrsi3 (operands[5], operands[3], operands[4])); 3355 } 3356}) 3357 3358;; rotcr combine bridge pattern which will make combine try out more 3359;; complex patterns. 3360(define_insn_and_split "*rotcr" 3361 [(set (match_operand:SI 0 "arith_reg_dest") 3362 (ashift:SI (match_operand 1 "treg_set_expr") (const_int 31)))] 3363 "TARGET_SH1 && can_create_pseudo_p ()" 3364 "#" 3365 "&& 1" 3366 [(parallel [(set (match_dup 0) 3367 (ior:SI (lshiftrt:SI (const_int 0) (const_int 1)) 3368 (ashift:SI (match_dup 1) (const_int 31)))) 3369 (clobber (reg:SI T_REG))])]) 3370 3371(define_insn_and_split "*rotcr" 3372 [(set (match_operand:SI 0 "arith_reg_dest") 3373 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand") 3374 (const_int -2147483648)) ;; 0xffffffff80000000 3375 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand") 3376 (const_int 1)))) 3377 (clobber (reg:SI T_REG))] 3378 "TARGET_SH1" 3379 "#" 3380 "&& can_create_pseudo_p ()" 3381 [(const_int 0)] 3382{ 3383 rtx tmp = gen_reg_rtx (SImode); 3384 emit_insn (gen_shll (tmp, operands[1])); 3385 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ())); 3386 DONE; 3387}) 3388 3389(define_insn_and_split "*rotcr" 3390 [(set (match_operand:SI 0 "arith_reg_dest") 3391 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand") 3392 (const_int 1)) 3393 (const_int -2147483648))) ;; 0xffffffff80000000 3394 (clobber (reg:SI T_REG))] 3395 "TARGET_SH1" 3396 "#" 3397 "&& can_create_pseudo_p ()" 3398 [(const_int 0)] 3399{ 3400 emit_insn (gen_sett ()); 3401 emit_insn (gen_rotcr (operands[0], operands[1], get_t_reg_rtx ())); 3402 DONE; 3403}) 3404 3405;; rotcr combine patterns for rotating in the negated T_REG value. 3406(define_insn_and_split "*rotcr_neg_t" 3407 [(set (match_operand:SI 0 "arith_reg_dest") 3408 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand") 3409 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand") 3410 (match_operand:SI 3 "const_int_operand")))) 3411 (clobber (reg:SI T_REG))] 3412 "TARGET_SH1" 3413 "#" 3414 "&& can_create_pseudo_p ()" 3415 [(parallel [(set (match_dup 0) 3416 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3)) 3417 (ashift:SI (reg:SI T_REG) (const_int 31)))) 3418 (clobber (reg:SI T_REG))])] 3419{ 3420 emit_insn (gen_nott (get_t_reg_rtx ())); 3421}) 3422 3423(define_insn_and_split "*rotcr_neg_t" 3424 [(set (match_operand:SI 0 "arith_reg_dest") 3425 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand") 3426 (match_operand:SI 2 "const_int_operand")) 3427 (match_operand:SI 3 "negt_reg_shl31_operand"))) 3428 (clobber (reg:SI T_REG))] 3429 "TARGET_SH1" 3430 "#" 3431 "&& can_create_pseudo_p ()" 3432 [(parallel [(set (match_dup 0) 3433 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3434 (ashift:SI (reg:SI T_REG) (const_int 31)))) 3435 (clobber (reg:SI T_REG))])] 3436{ 3437 emit_insn (gen_nott (get_t_reg_rtx ())); 3438}) 3439 3440;; rotcl combine patterns for rotating in the negated T_REG value. 3441;; For some strange reason these have to be specified as splits which combine 3442;; will pick up. If they are specified as insn_and_split like the 3443;; *rotcr_neg_t patterns above, combine would recognize them successfully 3444;; but not emit them on non-SH2A targets. 3445(define_split 3446 [(set (match_operand:SI 0 "arith_reg_dest") 3447 (ior:SI (match_operand:SI 1 "negt_reg_operand") 3448 (ashift:SI (match_operand:SI 2 "arith_reg_operand") 3449 (match_operand:SI 3 "const_int_operand"))))] 3450 "TARGET_SH1" 3451 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1))) 3452 (parallel [(set (match_dup 0) 3453 (ior:SI (ashift:SI (match_dup 2) (match_dup 3)) 3454 (and:SI (reg:SI T_REG) (const_int 1)))) 3455 (clobber (reg:SI T_REG))])]) 3456 3457(define_split 3458 [(set (match_operand:SI 0 "arith_reg_dest") 3459 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand") 3460 (match_operand:SI 3 "const_int_operand")) 3461 (match_operand:SI 1 "negt_reg_operand")))] 3462 "TARGET_SH1" 3463 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1))) 3464 (parallel [(set (match_dup 0) 3465 (ior:SI (ashift:SI (match_dup 2) (match_dup 3)) 3466 (and:SI (reg:SI T_REG) (const_int 1)))) 3467 (clobber (reg:SI T_REG))])]) 3468 3469;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3470;; SImode shift left 3471 3472(define_expand "ashlsi3" 3473 [(set (match_operand:SI 0 "arith_reg_operand" "") 3474 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "") 3475 (match_operand:SI 2 "shift_count_operand" "")))] 3476 "" 3477{ 3478 if (TARGET_DYNSHIFT 3479 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2])) 3480 { 3481 /* Don't force the constant into a reg yet. Some other optimizations 3482 might not see through the reg that holds the shift count. */ 3483 } 3484 3485 /* If the ashlsi3_* insn is going to clobber the T_REG it must be 3486 expanded here. */ 3487 if (CONST_INT_P (operands[2]) 3488 && sh_ashlsi_clobbers_t_reg_p (operands[2]) 3489 && ! sh_dynamicalize_shift_p (operands[2])) 3490 { 3491 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1], 3492 operands[2])); 3493 DONE; 3494 } 3495 3496 /* Expand a library call for the dynamic shift. */ 3497 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT) 3498 { 3499 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]); 3500 rtx funcaddr = gen_reg_rtx (Pmode); 3501 rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab; 3502 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab)); 3503 3504 DONE; 3505 } 3506}) 3507 3508(define_insn "ashlsi3_k" 3509 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") 3510 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0") 3511 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))] 3512 "TARGET_SH1" 3513 "@ 3514 add %0,%0 3515 shll%O2 %0" 3516 [(set_attr "type" "arith")]) 3517 3518(define_insn_and_split "ashlsi3_d" 3519 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3520 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") 3521 (match_operand:SI 2 "shift_count_operand" "r")))] 3522 "TARGET_DYNSHIFT" 3523 "shld %2,%0" 3524 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2]) 3525 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])" 3526 [(const_int 0)] 3527{ 3528 if (satisfies_constraint_P27 (operands[2])) 3529 { 3530 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2])); 3531 DONE; 3532 } 3533 else if (! satisfies_constraint_P27 (operands[2])) 3534 { 3535 /* This must happen before reload, otherwise the constant will be moved 3536 into a register due to the "r" constraint, after which this split 3537 cannot be done anymore. 3538 Unfortunately the move insn will not always be eliminated. 3539 Also, here we must not create a shift sequence that clobbers the 3540 T_REG. */ 3541 emit_move_insn (operands[0], operands[1]); 3542 gen_shifty_op (ASHIFT, operands); 3543 DONE; 3544 } 3545 3546 FAIL; 3547} 3548 [(set_attr "type" "dyn_shift")]) 3549 3550;; If dynamic shifts are not available use a library function. 3551;; By specifying the pattern we reduce the number of call clobbered regs. 3552;; In order to make combine understand the truncation of the shift amount 3553;; operand we have to allow it to use pseudo regs for the shift operands. 3554(define_insn "ashlsi3_d_call" 3555 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z") 3556 (ashift:SI (reg:SI R4_REG) 3557 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z") 3558 (const_int 31)))) 3559 (use (match_operand:SI 2 "arith_reg_operand" "r,r")) 3560 (use (match_operand 3 "" "Z,Ccl")) 3561 (clobber (reg:SI T_REG)) 3562 (clobber (reg:SI PR_REG))] 3563 "TARGET_SH1 && !TARGET_DYNSHIFT" 3564 "@ 3565 jsr @%2%# 3566 bsrf %2\n%O3:%#" 3567 [(set_attr "type" "sfunc") 3568 (set_attr "needs_delay_slot" "yes")]) 3569 3570(define_insn_and_split "ashlsi3_n" 3571 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3572 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") 3573 (match_operand:SI 2 "not_p27_shift_count_operand" "")))] 3574 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])" 3575 "#" 3576 "&& (reload_completed 3577 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))" 3578 [(const_int 0)] 3579{ 3580 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()) 3581 { 3582 /* If this pattern was picked and dynamic shifts are supported, switch 3583 to dynamic shift pattern before reload. */ 3584 operands[2] = force_reg (SImode, operands[2]); 3585 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2])); 3586 } 3587 else 3588 gen_shifty_op (ASHIFT, operands); 3589 3590 DONE; 3591}) 3592 3593(define_insn_and_split "ashlsi3_n_clobbers_t" 3594 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3595 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") 3596 (match_operand:SI 2 "not_p27_shift_count_operand" ""))) 3597 (clobber (reg:SI T_REG))] 3598 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])" 3599 "#" 3600 "&& (reload_completed || INTVAL (operands[2]) == 31 3601 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))" 3602 [(const_int 0)] 3603{ 3604 if (INTVAL (operands[2]) == 31) 3605 { 3606 /* If the shift amount is 31 we split into a different sequence before 3607 reload so that it gets a chance to allocate R0 for the sequence. 3608 If it fails to do so (due to pressure on R0), it will take one insn 3609 more for the and. */ 3610 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx)); 3611 emit_insn (gen_rotlsi3_31 (operands[0], operands[0])); 3612 } 3613 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()) 3614 { 3615 /* If this pattern was picked and dynamic shifts are supported, switch 3616 to dynamic shift pattern before reload. */ 3617 operands[2] = force_reg (SImode, operands[2]); 3618 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2])); 3619 } 3620 else 3621 gen_shifty_op (ASHIFT, operands); 3622 3623 DONE; 3624}) 3625 3626(define_insn "shll" 3627 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3628 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1))) 3629 (set (reg:SI T_REG) 3630 (lt:SI (match_dup 1) (const_int 0)))] 3631 "TARGET_SH1" 3632 "shll %0" 3633 [(set_attr "type" "arith")]) 3634 3635(define_insn "*ashlsi_c_void" 3636 [(set (reg:SI T_REG) 3637 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0))) 3638 (clobber (match_scratch:SI 1 "=0"))] 3639 "TARGET_SH1 && cse_not_expected" 3640 "shll %0" 3641 [(set_attr "type" "arith")]) 3642 3643(define_peephole2 3644 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0)) 3645 (set (reg:SI T_REG) 3646 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))] 3647 "TARGET_SH1 3648 && peep2_reg_dead_p (2, operands[0]) 3649 && peep2_reg_dead_p (2, operands[1])" 3650 [(const_int 0)] 3651{ 3652 emit_insn (gen_shll (operands[1], operands[1])); 3653 DONE; 3654}) 3655 3656;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3657;; HImode shift left 3658 3659(define_expand "ashlhi3" 3660 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "") 3661 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "") 3662 (match_operand:SI 2 "nonmemory_operand" ""))) 3663 (clobber (reg:SI T_REG))])] 3664 "TARGET_SH1" 3665{ 3666 if (!CONST_INT_P (operands[2])) 3667 FAIL; 3668 /* It may be possible to call gen_ashlhi3 directly with more generic 3669 operands. Make sure operands[1] is a HImode register here. */ 3670 if (!arith_reg_operand (operands[1], HImode)) 3671 operands[1] = copy_to_mode_reg (HImode, operands[1]); 3672}) 3673 3674(define_insn "ashlhi3_k" 3675 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r") 3676 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0") 3677 (match_operand:HI 2 "const_int_operand" "M,P27")))] 3678 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])" 3679 "@ 3680 add %0,%0 3681 shll%O2 %0" 3682 [(set_attr "type" "arith")]) 3683 3684(define_insn_and_split "*ashlhi3_n" 3685 [(set (match_operand:HI 0 "arith_reg_dest" "=r") 3686 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0") 3687 (match_operand:HI 2 "const_int_operand" "n"))) 3688 (clobber (reg:SI T_REG))] 3689 "TARGET_SH1" 3690 "#" 3691 "&& reload_completed" 3692 [(use (reg:SI R0_REG))] 3693{ 3694 gen_shifty_hi_op (ASHIFT, operands); 3695 DONE; 3696}) 3697 3698;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3699;; DImode shift left 3700 3701(define_expand "ashldi3" 3702 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") 3703 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "") 3704 (match_operand:DI 2 "immediate_operand" ""))) 3705 (clobber (reg:SI T_REG))])] 3706 "" 3707{ 3708 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1) 3709 { 3710 emit_insn (gen_ashldi3_k (operands[0], operands[1])); 3711 DONE; 3712 } 3713 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32) 3714 { 3715 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2])); 3716 DONE; 3717 } 3718 else 3719 FAIL; 3720}) 3721 3722;; Expander for DImode shift left with SImode operations. 3723(define_expand "ashldi3_std" 3724 [(set (match_operand:DI 0 "arith_reg_dest" "=r") 3725 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r") 3726 (match_operand:DI 2 "const_int_operand" "n")))] 3727 "TARGET_SH1 && INTVAL (operands[2]) < 32" 3728{ 3729 rtx low_src = gen_lowpart (SImode, operands[1]); 3730 rtx high_src = gen_highpart (SImode, operands[1]); 3731 rtx dst = gen_reg_rtx (DImode); 3732 rtx low_dst = gen_lowpart (SImode, dst); 3733 rtx high_dst = gen_highpart (SImode, dst); 3734 rtx tmp0 = gen_reg_rtx (SImode); 3735 rtx tmp1 = gen_reg_rtx (SImode); 3736 3737 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2])))); 3738 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2])); 3739 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2])); 3740 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1)); 3741 emit_move_insn (operands[0], dst); 3742 DONE; 3743}) 3744 3745(define_insn_and_split "ashldi3_k" 3746 [(set (match_operand:DI 0 "arith_reg_dest" "=r") 3747 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0") 3748 (const_int 1))) 3749 (clobber (reg:SI T_REG))] 3750 "TARGET_SH1" 3751 "#" 3752 "&& reload_completed" 3753 [(const_int 0)] 3754{ 3755 rtx high = gen_highpart (SImode, operands[0]); 3756 rtx low = gen_lowpart (SImode, operands[0]); 3757 emit_insn (gen_shll (low, low)); 3758 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ())); 3759 DONE; 3760}) 3761 3762;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3763;; SImode arithmetic shift right 3764;; 3765;; We can't do HImode right shifts correctly unless we start out with an 3766;; explicit zero / sign extension; doing that would result in worse overall 3767;; code, so just let the machine independent code widen the mode. 3768;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 . 3769 3770(define_expand "ashrsi3" 3771 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "") 3772 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "") 3773 (match_operand:SI 2 "nonmemory_operand" ""))) 3774 (clobber (reg:SI T_REG))])] 3775 "" 3776{ 3777 if (expand_ashiftrt (operands)) 3778 DONE; 3779 else 3780 FAIL; 3781}) 3782 3783(define_insn "shar" 3784 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3785 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 3786 (const_int 1))) 3787 (set (reg:SI T_REG) 3788 (and:SI (match_dup 1) (const_int 1)))] 3789 "TARGET_SH1" 3790 "shar %0" 3791 [(set_attr "type" "arith")]) 3792 3793(define_insn "ashrsi3_k" 3794 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3795 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 3796 (match_operand:SI 2 "const_int_operand" "M"))) 3797 (clobber (reg:SI T_REG))] 3798 "TARGET_SH1 && INTVAL (operands[2]) == 1" 3799 "shar %0" 3800 [(set_attr "type" "arith")]) 3801 3802(define_insn_and_split "ashrsi2_16" 3803 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3804 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r") 3805 (const_int 16)))] 3806 "TARGET_SH1" 3807 "#" 3808 "&& 1" 3809 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16))) 3810 (set (match_dup 0) (sign_extend:SI (match_dup 2)))] 3811{ 3812 operands[2] = gen_lowpart (HImode, operands[0]); 3813}) 3814 3815(define_insn_and_split "ashrsi2_31" 3816 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3817 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 3818 (const_int 31))) 3819 (clobber (reg:SI T_REG))] 3820 "TARGET_SH1" 3821 "#" 3822 "&& 1" 3823 [(const_int 0)] 3824{ 3825 emit_insn (gen_shll (operands[0], operands[1])); 3826 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ())); 3827 DONE; 3828}) 3829 3830;; If the shift amount is changed by combine it will try to plug the 3831;; use on the symbol of the library function and the PR clobber. 3832(define_insn_and_split "*ashrsi2_31" 3833 [(set (match_operand:SI 0 "arith_reg_dest") 3834 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand") 3835 (const_int 31))) 3836 (clobber (reg:SI T_REG)) 3837 (clobber (reg:SI PR_REG)) 3838 (use (match_operand:SI 2 "symbol_ref_operand"))] 3839 "TARGET_SH1" 3840 "#" 3841 "&& 1" 3842 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31))) 3843 (clobber (reg:SI T_REG))])]) 3844 3845(define_insn "ashrsi3_d" 3846 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3847 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 3848 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))] 3849 "TARGET_DYNSHIFT" 3850 "shad %2,%0" 3851 [(set_attr "type" "dyn_shift")]) 3852 3853(define_insn "ashrsi3_n" 3854 [(set (reg:SI R4_REG) 3855 (ashiftrt:SI (reg:SI R4_REG) 3856 (match_operand:SI 0 "const_int_operand" "i,i"))) 3857 (clobber (reg:SI T_REG)) 3858 (clobber (reg:SI PR_REG)) 3859 (use (match_operand:SI 1 "arith_reg_operand" "r,r")) 3860 (use (match_operand 2 "" "Z,Ccl"))] 3861 "TARGET_SH1" 3862 "@ 3863 jsr @%1%# 3864 bsrf %1\n%O2:%#" 3865 [(set_attr "type" "sfunc") 3866 (set_attr "needs_delay_slot" "yes")]) 3867 3868;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3869;; DImode arithmetic shift right 3870 3871(define_expand "ashrdi3" 3872 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") 3873 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "") 3874 (match_operand:DI 2 "immediate_operand" ""))) 3875 (clobber (reg:SI T_REG))])] 3876 "" 3877{ 3878 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1) 3879 FAIL; 3880}) 3881 3882(define_insn_and_split "ashrdi3_k" 3883 [(set (match_operand:DI 0 "arith_reg_dest" "=r") 3884 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0") 3885 (const_int 1))) 3886 (clobber (reg:SI T_REG))] 3887 "TARGET_SH1" 3888 "#" 3889 "&& reload_completed" 3890 [(const_int 0)] 3891{ 3892 rtx high = gen_highpart (SImode, operands[0]); 3893 rtx low = gen_lowpart (SImode, operands[0]); 3894 emit_insn (gen_shar (high, high)); 3895 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ())); 3896 DONE; 3897}) 3898 3899;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3900;; SImode logical shift right 3901 3902(define_expand "lshrsi3" 3903 [(set (match_operand:SI 0 "arith_reg_dest" "") 3904 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "") 3905 (match_operand:SI 2 "shift_count_operand" "")))] 3906 "" 3907{ 3908 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn 3909 here, otherwise the pattern will never match due to the shift amount reg 3910 negation. */ 3911 if (TARGET_DYNSHIFT 3912 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2])) 3913 { 3914 /* Don't force the constant into a reg yet. Some other optimizations 3915 might not see through the reg that holds the shift count. */ 3916 if (sh_lshrsi_clobbers_t_reg_p (operands[2])) 3917 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1], operands[2])); 3918 else 3919 emit_insn (gen_lshrsi3_n (operands[0], operands[1], operands[2])); 3920 DONE; 3921 } 3922 3923 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2])) 3924 { 3925 rtx neg_count = gen_reg_rtx (SImode); 3926 emit_insn (gen_negsi2 (neg_count, operands[2])); 3927 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count)); 3928 DONE; 3929 } 3930 3931 /* If the lshrsi3_* insn is going to clobber the T_REG it must be 3932 expanded here. */ 3933 if (CONST_INT_P (operands[2]) 3934 && sh_lshrsi_clobbers_t_reg_p (operands[2]) 3935 && ! sh_dynamicalize_shift_p (operands[2])) 3936 { 3937 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1], 3938 operands[2])); 3939 DONE; 3940 } 3941 3942 /* Expand a library call for the dynamic shift. */ 3943 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT) 3944 { 3945 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]); 3946 rtx funcaddr = gen_reg_rtx (Pmode); 3947 rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab; 3948 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab)); 3949 DONE; 3950 } 3951}) 3952 3953(define_insn "lshrsi3_k" 3954 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3955 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 3956 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))] 3957 "TARGET_SH1" 3958 "shlr%O2 %0" 3959 [(set_attr "type" "arith")]) 3960 3961(define_insn_and_split "lshrsi3_d" 3962 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 3963 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 3964 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))] 3965 "TARGET_DYNSHIFT" 3966 "shld %2,%0" 3967 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2]) 3968 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])" 3969 [(const_int 0)] 3970{ 3971 /* The shift count const_int is a negative value for all dynamic 3972 right shift insns. */ 3973 operands[2] = GEN_INT (- INTVAL (operands[2])); 3974 3975 if (satisfies_constraint_P27 (operands[2])) 3976 { 3977 /* This will not be done for a shift amount of 1, because it would 3978 clobber the T_REG. */ 3979 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2])); 3980 DONE; 3981 } 3982 else if (! satisfies_constraint_P27 (operands[2])) 3983 { 3984 /* This must happen before reload, otherwise the constant will be moved 3985 into a register due to the "r" constraint, after which this split 3986 cannot be done anymore. 3987 Unfortunately the move insn will not always be eliminated. 3988 Also, here we must not create a shift sequence that clobbers the 3989 T_REG. */ 3990 emit_move_insn (operands[0], operands[1]); 3991 gen_shifty_op (LSHIFTRT, operands); 3992 DONE; 3993 } 3994 3995 FAIL; 3996} 3997 [(set_attr "type" "dyn_shift")]) 3998 3999;; If dynamic shifts are not available use a library function. 4000;; By specifying the pattern we reduce the number of call clobbered regs. 4001;; In order to make combine understand the truncation of the shift amount 4002;; operand we have to allow it to use pseudo regs for the shift operands. 4003(define_insn "lshrsi3_d_call" 4004 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z") 4005 (lshiftrt:SI (reg:SI R4_REG) 4006 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z") 4007 (const_int 31)))) 4008 (use (match_operand:SI 2 "arith_reg_operand" "r,r")) 4009 (use (match_operand 3 "" "Z,Ccl")) 4010 (clobber (reg:SI T_REG)) 4011 (clobber (reg:SI PR_REG))] 4012 "TARGET_SH1 && !TARGET_DYNSHIFT" 4013 "@ 4014 jsr @%2%# 4015 bsrf %2\n%O3:%#" 4016 [(set_attr "type" "sfunc") 4017 (set_attr "needs_delay_slot" "yes")]) 4018 4019(define_insn_and_split "lshrsi3_n" 4020 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4021 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 4022 (match_operand:SI 2 "not_p27_rshift_count_operand")))] 4023 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])" 4024 "#" 4025 "&& (reload_completed 4026 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))" 4027 [(const_int 0)] 4028{ 4029 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()) 4030 { 4031 /* If this pattern was picked and dynamic shifts are supported, switch 4032 to dynamic shift pattern before reload. */ 4033 operands[2] = GEN_INT (- INTVAL (operands[2])); 4034 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2])); 4035 } 4036 else 4037 gen_shifty_op (LSHIFTRT, operands); 4038 4039 DONE; 4040}) 4041 4042;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of 4043;; the shlr pattern. 4044(define_insn_and_split "lshrsi3_n_clobbers_t" 4045 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4046 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 4047 (match_operand:SI 2 "not_p27_rshift_count_operand"))) 4048 (clobber (reg:SI T_REG))] 4049 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])" 4050 "#" 4051 "&& (reload_completed || INTVAL (operands[2]) == 31 4052 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))" 4053 [(const_int 0)] 4054{ 4055 if (INTVAL (operands[2]) == 31) 4056 { 4057 emit_insn (gen_shll (operands[0], operands[1])); 4058 emit_insn (gen_movt (operands[0], get_t_reg_rtx ())); 4059 } 4060 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()) 4061 { 4062 /* If this pattern was picked and dynamic shifts are supported, switch 4063 to dynamic shift pattern before reload. */ 4064 operands[2] = GEN_INT (- INTVAL (operands[2])); 4065 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2])); 4066 } 4067 else 4068 gen_shifty_op (LSHIFTRT, operands); 4069 4070 DONE; 4071}) 4072 4073(define_insn "shlr" 4074 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4075 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 4076 (const_int 1))) 4077 (set (reg:SI T_REG) 4078 (and:SI (match_dup 1) (const_int 1)))] 4079 "TARGET_SH1" 4080 "shlr %0" 4081 [(set_attr "type" "arith")]) 4082 4083;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4084;; DImode logical shift right 4085 4086(define_expand "lshrdi3" 4087 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "") 4088 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "") 4089 (match_operand:DI 2 "immediate_operand" ""))) 4090 (clobber (reg:SI T_REG))])] 4091 "" 4092{ 4093 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1) 4094 FAIL; 4095}) 4096 4097(define_insn_and_split "lshrdi3_k" 4098 [(set (match_operand:DI 0 "arith_reg_dest" "=r") 4099 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0") 4100 (const_int 1))) 4101 (clobber (reg:SI T_REG))] 4102 "TARGET_SH1" 4103 "#" 4104 "&& reload_completed" 4105 [(const_int 0)] 4106{ 4107 rtx high = gen_highpart (SImode, operands[0]); 4108 rtx low = gen_lowpart (SImode, operands[0]); 4109 emit_insn (gen_shlr (high, high)); 4110 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ())); 4111 DONE; 4112}) 4113 4114;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4115;; Combined left/right shifts 4116 4117(define_split 4118 [(set (match_operand:SI 0 "register_operand" "") 4119 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "") 4120 (match_operand:SI 2 "const_int_operand" "")) 4121 (match_operand:SI 3 "const_int_operand" "")))] 4122 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32" 4123 [(use (reg:SI R0_REG))] 4124{ 4125 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) 4126 FAIL; 4127 DONE; 4128}) 4129 4130(define_split 4131 [(set (match_operand:SI 0 "register_operand" "") 4132 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "") 4133 (match_operand:SI 2 "const_int_operand" "")) 4134 (match_operand:SI 3 "const_int_operand" ""))) 4135 (clobber (reg:SI T_REG))] 4136 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32" 4137 [(use (reg:SI R0_REG))] 4138{ 4139 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) 4140 FAIL; 4141 DONE; 4142}) 4143 4144(define_insn "" 4145 [(set (match_operand:SI 0 "register_operand" "=r") 4146 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 4147 (match_operand:SI 2 "const_int_operand" "n")) 4148 (match_operand:SI 3 "const_int_operand" "n"))) 4149 (clobber (reg:SI T_REG))] 4150 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1" 4151 "#" 4152 [(set (attr "length") 4153 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2)) 4154 (const_string "4") 4155 (eq (symbol_ref "shl_and_length (insn)") (const_int 3)) 4156 (const_string "6") 4157 (eq (symbol_ref "shl_and_length (insn)") (const_int 4)) 4158 (const_string "8") 4159 (eq (symbol_ref "shl_and_length (insn)") (const_int 5)) 4160 (const_string "10") 4161 (eq (symbol_ref "shl_and_length (insn)") (const_int 6)) 4162 (const_string "12") 4163 (eq (symbol_ref "shl_and_length (insn)") (const_int 7)) 4164 (const_string "14") 4165 (eq (symbol_ref "shl_and_length (insn)") (const_int 8)) 4166 (const_string "16")] 4167 (const_string "18"))) 4168 (set_attr "type" "arith")]) 4169 4170(define_insn "" 4171 [(set (match_operand:SI 0 "register_operand" "=z") 4172 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0") 4173 (match_operand:SI 2 "const_int_operand" "n")) 4174 (match_operand:SI 3 "const_int_operand" "n"))) 4175 (clobber (reg:SI T_REG))] 4176 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2" 4177 "#" 4178 [(set (attr "length") 4179 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2)) 4180 (const_string "4") 4181 (eq (symbol_ref "shl_and_length (insn)") (const_int 3)) 4182 (const_string "6") 4183 (eq (symbol_ref "shl_and_length (insn)") (const_int 4)) 4184 (const_string "8")] 4185 (const_string "10"))) 4186 (set_attr "type" "arith")]) 4187 4188;; shift left / and combination with a scratch register: The combine pass 4189;; does not accept the individual instructions, even though they are 4190;; cheap. But it needs a precise description so that it is usable after 4191;; reload. 4192(define_insn "and_shl_scratch" 4193 [(set (match_operand:SI 0 "register_operand" "=r,&r") 4194 (lshiftrt:SI 4195 (ashift:SI 4196 (and:SI 4197 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0") 4198 (match_operand:SI 2 "const_int_operand" "N,n")) 4199 (match_operand:SI 3 "" "0,r")) 4200 (match_operand:SI 4 "const_int_operand" "n,n")) 4201 (match_operand:SI 5 "const_int_operand" "n,n"))) 4202 (clobber (reg:SI T_REG))] 4203 "TARGET_SH1" 4204 "#" 4205 [(set (attr "length") 4206 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2)) 4207 (const_string "4") 4208 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3)) 4209 (const_string "6") 4210 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4)) 4211 (const_string "8") 4212 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5)) 4213 (const_string "10")] 4214 (const_string "12"))) 4215 (set_attr "type" "arith")]) 4216 4217(define_split 4218 [(set (match_operand:SI 0 "register_operand" "") 4219 (lshiftrt:SI 4220 (ashift:SI 4221 (and:SI 4222 (lshiftrt:SI (match_operand:SI 1 "register_operand" "") 4223 (match_operand:SI 2 "const_int_operand" "")) 4224 (match_operand:SI 3 "register_operand" "")) 4225 (match_operand:SI 4 "const_int_operand" "")) 4226 (match_operand:SI 5 "const_int_operand" ""))) 4227 (clobber (reg:SI T_REG))] 4228 "TARGET_SH1" 4229 [(use (reg:SI R0_REG))] 4230{ 4231 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1]; 4232 4233 if (INTVAL (operands[2])) 4234 { 4235 gen_shifty_op (LSHIFTRT, operands); 4236 } 4237 emit_insn (gen_andsi3 (operands[0], operands[0], and_source)); 4238 operands[2] = operands[4]; 4239 gen_shifty_op (ASHIFT, operands); 4240 if (INTVAL (operands[5])) 4241 { 4242 operands[2] = operands[5]; 4243 gen_shifty_op (LSHIFTRT, operands); 4244 } 4245 DONE; 4246}) 4247 4248;; signed left/right shift combination. 4249(define_split 4250 [(set (match_operand:SI 0 "register_operand" "") 4251 (sign_extract:SI 4252 (ashift:SI (match_operand:SI 1 "register_operand" "") 4253 (match_operand:SI 2 "const_int_operand" "")) 4254 (match_operand:SI 3 "const_int_operand" "") 4255 (const_int 0))) 4256 (clobber (reg:SI T_REG))] 4257 "TARGET_SH1" 4258 [(use (reg:SI R0_REG))] 4259{ 4260 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) 4261 FAIL; 4262 DONE; 4263}) 4264 4265(define_insn "shl_sext_ext" 4266 [(set (match_operand:SI 0 "register_operand" "=r") 4267 (sign_extract:SI 4268 (ashift:SI (match_operand:SI 1 "register_operand" "0") 4269 (match_operand:SI 2 "const_int_operand" "n")) 4270 (match_operand:SI 3 "const_int_operand" "n") 4271 (const_int 0))) 4272 (clobber (reg:SI T_REG))] 4273 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5" 4274 "#" 4275 [(set (attr "length") 4276 (cond [(match_test "shl_sext_length (insn)") 4277 (const_string "2") 4278 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2)) 4279 (const_string "4") 4280 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3)) 4281 (const_string "6") 4282 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4)) 4283 (const_string "8") 4284 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5)) 4285 (const_string "10") 4286 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6)) 4287 (const_string "12") 4288 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7)) 4289 (const_string "14") 4290 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8)) 4291 (const_string "16")] 4292 (const_string "18"))) 4293 (set_attr "type" "arith")]) 4294 4295(define_insn "shl_sext_sub" 4296 [(set (match_operand:SI 0 "register_operand" "=z") 4297 (sign_extract:SI 4298 (ashift:SI (match_operand:SI 1 "register_operand" "0") 4299 (match_operand:SI 2 "const_int_operand" "n")) 4300 (match_operand:SI 3 "const_int_operand" "n") 4301 (const_int 0))) 4302 (clobber (reg:SI T_REG))] 4303 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6" 4304 "#" 4305 [(set (attr "length") 4306 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3)) 4307 (const_string "6") 4308 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4)) 4309 (const_string "8") 4310 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5)) 4311 (const_string "10") 4312 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6)) 4313 (const_string "12")] 4314 (const_string "14"))) 4315 (set_attr "type" "arith")]) 4316 4317;; The xtrct_left and xtrct_right patterns are used in expansions of DImode 4318;; shifts by 16, and allow the xtrct instruction to be generated from C 4319;; source. 4320(define_insn "xtrct_left" 4321 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4322 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r") 4323 (const_int 16)) 4324 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0") 4325 (const_int 16))))] 4326 "TARGET_SH1" 4327 "xtrct %1,%0" 4328 [(set_attr "type" "arith")]) 4329 4330(define_insn "xtrct_right" 4331 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4332 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0") 4333 (const_int 16)) 4334 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r") 4335 (const_int 16))))] 4336 "TARGET_SH1" 4337 "xtrct %2,%0" 4338 [(set_attr "type" "arith")]) 4339 4340;; ------------------------------------------------------------------------- 4341;; Unary arithmetic 4342;; ------------------------------------------------------------------------- 4343 4344(define_insn "negc" 4345 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4346 (neg:SI (plus:SI (reg:SI T_REG) 4347 (match_operand:SI 1 "arith_reg_operand" "r")))) 4348 (set (reg:SI T_REG) 4349 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1)) 4350 (const_int 0)))] 4351 "TARGET_SH1" 4352 "negc %1,%0" 4353 [(set_attr "type" "arith")]) 4354 4355;; A simplified version of the negc insn, where the exact value of the 4356;; T bit doesn't matter. This is easier for combine to pick up. 4357;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify 4358;; extra patterns for this case. 4359(define_insn_and_split "*negc" 4360 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4361 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")) 4362 (match_operand 2 "treg_set_expr"))) 4363 (clobber (reg:SI T_REG))] 4364 "TARGET_SH1 && can_create_pseudo_p ()" 4365 "#" 4366 "&& 1" 4367 [(const_int 0)] 4368{ 4369 sh_split_treg_set_expr (operands[2], curr_insn); 4370 emit_insn (gen_negc (operands[0], operands[1])); 4371 DONE; 4372}); 4373 4374;; Don't split into individual negc insns immediately so that neg:DI (abs:DI) 4375;; can be combined. 4376(define_insn_and_split "negdi2" 4377 [(set (match_operand:DI 0 "arith_reg_dest") 4378 (neg:DI (match_operand:DI 1 "arith_reg_operand"))) 4379 (clobber (reg:SI T_REG))] 4380 "TARGET_SH1" 4381 "#" 4382 "&& can_create_pseudo_p ()" 4383 [(const_int 0)] 4384{ 4385 emit_insn (gen_clrt ()); 4386 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]), 4387 gen_lowpart (SImode, operands[1]))); 4388 emit_insn (gen_negc (gen_highpart (SImode, operands[0]), 4389 gen_highpart (SImode, operands[1]))); 4390 DONE; 4391}) 4392 4393(define_insn "negsi2" 4394 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4395 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))] 4396 "TARGET_SH1" 4397 "neg %1,%0" 4398 [(set_attr "type" "arith")]) 4399 4400(define_insn_and_split "one_cmplsi2" 4401 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4402 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))] 4403 "TARGET_SH1" 4404 "not %1,%0" 4405 "&& can_create_pseudo_p ()" 4406 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0))) 4407 (set (match_dup 0) (reg:SI T_REG))] 4408{ 4409/* PR 54685 4410 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following 4411 sequence: 4412 4413 (set (reg0) (not:SI (reg0) (reg1))) 4414 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31))) 4415 (clobber (reg:SI T_REG))]) 4416 4417 ... match and combine the sequence manually in the split pass after the 4418 combine pass. Notice that combine does try the target pattern of this 4419 split, but if the pattern is added it interferes with other patterns, in 4420 particular with the div0s comparisons. 4421 This could also be done with a peephole but doing it here before register 4422 allocation can save one temporary. 4423 When we're here, the not:SI pattern obviously has been matched already 4424 and we only have to see whether the following insn is the left shift. */ 4425 4426 rtx_insn *i = next_nonnote_insn_bb (curr_insn); 4427 if (i == NULL_RTX || !NONJUMP_INSN_P (i)) 4428 FAIL; 4429 4430 rtx p = PATTERN (i); 4431 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2) 4432 FAIL; 4433 4434 rtx p0 = XVECEXP (p, 0, 0); 4435 rtx p1 = XVECEXP (p, 0, 1); 4436 4437 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */ 4438 GET_CODE (p0) == SET 4439 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT 4440 && REG_P (XEXP (XEXP (p0, 1), 0)) 4441 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0]) 4442 && CONST_INT_P (XEXP (XEXP (p0, 1), 1)) 4443 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31 4444 4445 /* (clobber (reg:SI T_REG)) */ 4446 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0)) 4447 && REGNO (XEXP (p1, 0)) == T_REG) 4448 { 4449 operands[0] = XEXP (p0, 0); 4450 set_insn_deleted (i); 4451 } 4452 else 4453 FAIL; 4454} 4455 [(set_attr "type" "arith")]) 4456 4457(define_insn_and_split "abs<mode>2" 4458 [(set (match_operand:SIDI 0 "arith_reg_dest") 4459 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))) 4460 (clobber (reg:SI T_REG))] 4461 "TARGET_SH1" 4462 "#" 4463 "&& can_create_pseudo_p ()" 4464 [(const_int 0)] 4465{ 4466 if (<MODE>mode == SImode) 4467 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx)); 4468 else 4469 { 4470 rtx high_src = gen_highpart (SImode, operands[1]); 4471 emit_insn (gen_cmpgesi_t (high_src, const0_rtx)); 4472 } 4473 4474 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1], 4475 const1_rtx)); 4476 DONE; 4477}) 4478 4479(define_insn_and_split "*negabs<mode>2" 4480 [(set (match_operand:SIDI 0 "arith_reg_dest") 4481 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))) 4482 (clobber (reg:SI T_REG))] 4483 "TARGET_SH1" 4484 "#" 4485 "&& can_create_pseudo_p ()" 4486 [(const_int 0)] 4487{ 4488 if (<MODE>mode == SImode) 4489 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx)); 4490 else 4491 { 4492 rtx high_src = gen_highpart (SImode, operands[1]); 4493 emit_insn (gen_cmpgesi_t (high_src, const0_rtx)); 4494 } 4495 4496 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1], 4497 const0_rtx)); 4498 DONE; 4499}) 4500 4501;; The SH4 202 can do zero-offset branches without pipeline stalls. 4502;; This can be used as some kind of conditional execution, which is useful 4503;; for abs. 4504;; Actually the instruction scheduling should decide whether to use a 4505;; zero-offset branch or not for any generic case involving a single 4506;; instruction on SH4 202. 4507(define_insn_and_split "negsi_cond" 4508 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") 4509 (if_then_else 4510 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N")) 4511 (match_operand:SI 1 "arith_reg_operand" "0,0") 4512 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))] 4513 "TARGET_SH1 && TARGET_ZDCBRANCH" 4514{ 4515 static const char* alt[] = 4516 { 4517 "bt 0f" "\n" 4518 " neg %2,%0" "\n" 4519 "0:", 4520 4521 "bf 0f" "\n" 4522 " neg %2,%0" "\n" 4523 "0:" 4524 }; 4525 return alt[which_alternative]; 4526} 4527 "TARGET_SH1 && ! TARGET_ZDCBRANCH" 4528 [(const_int 0)] 4529{ 4530 rtx_code_label *skip_neg_label = gen_label_rtx (); 4531 4532 emit_move_insn (operands[0], operands[1]); 4533 4534 emit_jump_insn (INTVAL (operands[3]) 4535 ? gen_branch_true (skip_neg_label) 4536 : gen_branch_false (skip_neg_label)); 4537 4538 emit_label_after (skip_neg_label, 4539 emit_insn (gen_negsi2 (operands[0], operands[1]))); 4540 DONE; 4541} 4542 [(set_attr "type" "arith") ;; poor approximation 4543 (set_attr "length" "4")]) 4544 4545(define_insn_and_split "negdi_cond" 4546 [(set (match_operand:DI 0 "arith_reg_dest") 4547 (if_then_else 4548 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand")) 4549 (match_operand:DI 1 "arith_reg_operand") 4550 (neg:DI (match_operand:DI 2 "arith_reg_operand")))) 4551 (clobber (reg:SI T_REG))] 4552 "TARGET_SH1" 4553 "#" 4554 "&& can_create_pseudo_p ()" 4555 [(const_int 0)] 4556{ 4557 rtx_code_label *skip_neg_label = gen_label_rtx (); 4558 4559 emit_move_insn (operands[0], operands[1]); 4560 4561 emit_jump_insn (INTVAL (operands[3]) 4562 ? gen_branch_true (skip_neg_label) 4563 : gen_branch_false (skip_neg_label)); 4564 4565 if (!INTVAL (operands[3])) 4566 emit_insn (gen_clrt ()); 4567 4568 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]), 4569 gen_lowpart (SImode, operands[1]))); 4570 emit_label_after (skip_neg_label, 4571 emit_insn (gen_negc (gen_highpart (SImode, operands[0]), 4572 gen_highpart (SImode, operands[1])))); 4573 DONE; 4574}) 4575 4576(define_expand "bswapsi2" 4577 [(set (match_operand:SI 0 "arith_reg_dest" "") 4578 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))] 4579 "TARGET_SH1" 4580{ 4581 if (! can_create_pseudo_p ()) 4582 FAIL; 4583 else 4584 { 4585 rtx tmp0 = gen_reg_rtx (SImode); 4586 rtx tmp1 = gen_reg_rtx (SImode); 4587 4588 emit_insn (gen_swapbsi2 (tmp0, operands[1])); 4589 emit_insn (gen_rotlsi3_16 (tmp1, tmp0)); 4590 emit_insn (gen_swapbsi2 (operands[0], tmp1)); 4591 DONE; 4592 } 4593}) 4594 4595(define_insn "swapbsi2" 4596 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4597 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r") 4598 (const_int -65536)) ;; 0xFFFF0000 4599 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8)) 4600 (const_int 65280)) 4601 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8)) 4602 (const_int 255)))))] 4603 "TARGET_SH1" 4604 "swap.b %1,%0" 4605 [(set_attr "type" "arith")]) 4606 4607;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying 4608;; partial byte swap expressions such as... 4609;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF). 4610;; ...which are currently not handled by the tree optimizers. 4611;; The combine pass will not initially try to combine the full expression, 4612;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8 4613;; pattern acts as an intermediate pattern that will eventually lead combine 4614;; to the swapbsi2 pattern above. 4615;; As a side effect this also improves code that does (x & 0xFF) << 8 4616;; or (x << 8) & 0xFF00. 4617(define_insn_and_split "*swapbisi2_and_shl8" 4618 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4619 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r") 4620 (const_int 8)) 4621 (const_int 65280)) 4622 (match_operand:SI 2 "arith_reg_operand" "r")))] 4623 "TARGET_SH1 && ! reload_in_progress && ! reload_completed" 4624 "#" 4625 "&& can_create_pseudo_p ()" 4626 [(const_int 0)] 4627{ 4628 rtx tmp0 = gen_reg_rtx (SImode); 4629 rtx tmp1 = gen_reg_rtx (SImode); 4630 4631 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1]))); 4632 emit_insn (gen_swapbsi2 (tmp1, tmp0)); 4633 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2])); 4634 DONE; 4635}) 4636 4637;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another 4638;; intermediate pattern that will help the combine pass arriving at swapbsi2. 4639(define_insn_and_split "*swapbhisi2" 4640 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4641 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r") 4642 (const_int 8)) 4643 (const_int 65280)) 4644 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))] 4645 "TARGET_SH1 && ! reload_in_progress && ! reload_completed" 4646 "#" 4647 "&& can_create_pseudo_p ()" 4648 [(const_int 0)] 4649{ 4650 rtx tmp = gen_reg_rtx (SImode); 4651 4652 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1]))); 4653 emit_insn (gen_swapbsi2 (operands[0], tmp)); 4654 DONE; 4655}) 4656 4657;; In some cases the swapbsi2 pattern might leave a sequence such as... 4658;; swap.b r4,r4 4659;; mov r4,r0 4660;; 4661;; which can be simplified to... 4662;; swap.b r4,r0 4663(define_peephole2 4664 [(set (match_operand:SI 0 "arith_reg_dest" "") 4665 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "") 4666 (const_int -65536)) ;; 0xFFFF0000 4667 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8)) 4668 (const_int 65280)) 4669 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8)) 4670 (const_int 255))))) 4671 (set (match_operand:SI 2 "arith_reg_dest" "") 4672 (match_dup 0))] 4673 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])" 4674 [(set (match_dup 2) 4675 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "") 4676 (const_int -65536)) ;; 0xFFFF0000 4677 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8)) 4678 (const_int 65280)) 4679 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8)) 4680 (const_int 255)))))]) 4681 4682;; ------------------------------------------------------------------------- 4683;; Zero extension instructions 4684;; ------------------------------------------------------------------------- 4685 4686(define_expand "zero_extend<mode>si2" 4687 [(set (match_operand:SI 0 "arith_reg_dest") 4688 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))]) 4689 4690(define_insn_and_split "*zero_extend<mode>si2_compact" 4691 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4692 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))] 4693 "TARGET_SH1" 4694 "extu.<bw> %1,%0" 4695 "&& can_create_pseudo_p ()" 4696 [(set (match_dup 0) (match_dup 2))] 4697{ 4698 /* Sometimes combine fails to combine a T bit or negated T bit store to a 4699 reg with a following zero extension. In the split pass after combine, 4700 try to figure out how the extended reg was set. If it originated from 4701 the T bit we can replace the zero extension with a reg move, which will 4702 be eliminated. Notice that this also helps the *cbranch_t splitter when 4703 it tries to post-combine tests and conditional branches, as it does not 4704 check for zero extensions. */ 4705 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn); 4706 if (operands[2] == NULL_RTX) 4707 FAIL; 4708} 4709 [(set_attr "type" "arith")]) 4710 4711(define_insn "zero_extendqihi2" 4712 [(set (match_operand:HI 0 "arith_reg_dest" "=r") 4713 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))] 4714 "TARGET_SH1" 4715 "extu.b %1,%0" 4716 [(set_attr "type" "arith")]) 4717 4718;; SH2A supports two zero extending load instructions: movu.b and movu.w. 4719;; They could also be used for simple memory addresses like @Rn by setting 4720;; the displacement value to zero. However, doing so too early results in 4721;; missed opportunities for other optimizations such as post-inc or index 4722;; addressing loads. 4723;; We don't allow the zero extending loads to match during RTL expansion, 4724;; as this would pessimize other optimization opportunities such as bit 4725;; extractions of unsigned mems, where the zero extraction is irrelevant. 4726;; If the zero extracting mem loads are emitted early it will be more 4727;; difficult to change them back to sign extending loads (which are preferred). 4728;; The combine pass will also try to combine mem loads and zero extends, 4729;; which is prevented by 'sh_legitimate_combined_insn'. 4730(define_insn "*zero_extend<mode>si2_disp_mem" 4731 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r") 4732 (zero_extend:SI 4733 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))] 4734 "TARGET_SH2A" 4735 "@ 4736 movu.<bw> %1,%0 4737 movu.<bw> @(0,%t1),%0" 4738 [(set_attr "type" "load") 4739 (set_attr "length" "4")]) 4740 4741;; Convert the zero extending loads in sequences such as: 4742;; movu.b @(1,r5),r0 movu.w @(2,r5),r0 4743;; mov.b r0,@(1,r4) mov.b r0,@(1,r4) 4744;; 4745;; back to sign extending loads like: 4746;; mov.b @(1,r5),r0 mov.w @(2,r5),r0 4747;; mov.b r0,@(1,r4) mov.b r0,@(1,r4) 4748;; 4749;; if the extension type is irrelevant. The sign extending mov.{b|w} insn 4750;; is only 2 bytes in size if the displacement is {K04|K05}. 4751;; If the displacement is greater it doesn't matter, so we convert anyways. 4752(define_peephole2 4753 [(set (match_operand:SI 0 "arith_reg_dest" "") 4754 (zero_extend:SI (match_operand 1 "displacement_mem_operand" ""))) 4755 (set (match_operand 2 "nonimmediate_operand" "") 4756 (match_operand 3 "arith_reg_operand" ""))] 4757 "TARGET_SH2A 4758 && REGNO (operands[0]) == REGNO (operands[3]) 4759 && peep2_reg_dead_p (2, operands[0]) 4760 && GET_MODE_SIZE (GET_MODE (operands[2])) 4761 <= GET_MODE_SIZE (GET_MODE (operands[1]))" 4762 [(set (match_dup 0) (sign_extend:SI (match_dup 1))) 4763 (set (match_dup 2) (match_dup 3))]) 4764 4765;; Fold sequences such as 4766;; mov.b @r3,r7 4767;; extu.b r7,r7 4768;; into 4769;; movu.b @(0,r3),r7 4770;; This does not reduce the code size but the number of instructions is 4771;; halved, which results in faster code. 4772(define_peephole2 4773 [(set (match_operand:SI 0 "arith_reg_dest" "") 4774 (sign_extend:SI (match_operand 1 "simple_mem_operand" ""))) 4775 (set (match_operand:SI 2 "arith_reg_dest" "") 4776 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))] 4777 "TARGET_SH2A 4778 && GET_MODE (operands[1]) == GET_MODE (operands[3]) 4779 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode) 4780 && REGNO (operands[0]) == REGNO (operands[3]) 4781 && (REGNO (operands[2]) == REGNO (operands[0]) 4782 || peep2_reg_dead_p (2, operands[0]))" 4783 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))] 4784{ 4785 operands[4] 4786 = replace_equiv_address (operands[1], 4787 gen_rtx_PLUS (SImode, XEXP (operands[1], 0), 4788 const0_rtx)); 4789}) 4790 4791;; ------------------------------------------------------------------------- 4792;; Sign extension instructions 4793;; ------------------------------------------------------------------------- 4794 4795;; ??? This should be a define expand. 4796;; ??? Or perhaps it should be dropped? 4797 4798;; convert_move generates good code for SH[1-4]. 4799 4800(define_expand "extend<mode>si2" 4801 [(set (match_operand:SI 0 "arith_reg_dest") 4802 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))]) 4803 4804(define_insn_and_split "*extend<mode>si2_compact_reg" 4805 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4806 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))] 4807 "TARGET_SH1" 4808 "exts.<bw> %1,%0" 4809 "&& can_create_pseudo_p ()" 4810 [(set (match_dup 0) (match_dup 2))] 4811{ 4812 /* Sometimes combine fails to combine a T bit or negated T bit store to a 4813 reg with a following sign extension. In the split pass after combine, 4814 try to figure the extended reg was set. If it originated from the T 4815 bit we can replace the sign extension with a reg move, which will be 4816 eliminated. */ 4817 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn); 4818 if (operands[2] == NULL_RTX) 4819 FAIL; 4820} 4821 [(set_attr "type" "arith")]) 4822 4823;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute. 4824;; See movqi insns. 4825(define_insn "*extend<mode>si2_compact_mem_disp" 4826 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r") 4827 (sign_extend:SI 4828 (mem:QIHI 4829 (plus:SI 4830 (match_operand:SI 1 "arith_reg_operand" "%r,r") 4831 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))] 4832 "TARGET_SH1 && ! TARGET_SH2A 4833 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)" 4834 "@ 4835 mov.<bw> @(%O2,%1),%0 4836 mov.<bw> @%1,%0" 4837 [(set_attr "type" "load")]) 4838 4839(define_insn "*extend<mode>si2_compact_mem_disp" 4840 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r") 4841 (sign_extend:SI 4842 (mem:QIHI 4843 (plus:SI 4844 (match_operand:SI 1 "arith_reg_operand" "%r,r,r") 4845 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))] 4846 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)" 4847 "@ 4848 mov.<bw> @(%O2,%1),%0 4849 mov.<bw> @%1,%0 4850 mov.<bw> @(%O2,%1),%0" 4851 [(set_attr "type" "load") 4852 (set_attr "length" "2,2,4")]) 4853 4854;; The pre-dec and post-inc mems must be captured by the '<' and '>' 4855;; constraints, otherwise wrong code might get generated. 4856(define_insn "*extend<mode>si2_predec" 4857 [(set (match_operand:SI 0 "arith_reg_dest" "=z") 4858 (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))] 4859 "TARGET_SH2A" 4860 "mov.<bw> %1,%0" 4861 [(set_attr "type" "load")]) 4862 4863;; The *_snd patterns will take care of other QImode/HImode addressing 4864;; modes than displacement addressing. They must be defined _after_ the 4865;; displacement addressing patterns. Otherwise the displacement addressing 4866;; patterns will not be picked. 4867(define_insn "*extend<mode>si2_compact_snd" 4868 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 4869 (sign_extend:SI 4870 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))] 4871 "TARGET_SH1" 4872 "mov.<bw> %1,%0" 4873 [(set_attr "type" "load")]) 4874 4875(define_expand "extendqihi2" 4876 [(set (match_operand:HI 0 "arith_reg_dest") 4877 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))] 4878 "TARGET_SH1") 4879 4880(define_insn "*extendqihi2_compact_reg" 4881 [(set (match_operand:HI 0 "arith_reg_dest" "=r") 4882 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))] 4883 "TARGET_SH1" 4884 "exts.b %1,%0" 4885 [(set_attr "type" "arith")]) 4886 4887;; ------------------------------------------------------------------------- 4888;; Move instructions 4889;; ------------------------------------------------------------------------- 4890 4891(define_expand "push" 4892 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG))) 4893 (match_operand:SI 0 "register_operand"))]) 4894 4895(define_expand "pop" 4896 [(set (match_operand:SI 0 "register_operand") 4897 (mem:SI (post_inc:SI (reg:SI SP_REG))))]) 4898 4899(define_expand "push_e" 4900 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) 4901 (match_operand:SF 0 "" "")) 4902 (use (reg:SI FPSCR_MODES_REG)) 4903 (clobber (scratch:SI))])]) 4904 4905(define_insn "push_fpul" 4906 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))] 4907 "TARGET_SH2E" 4908 "sts.l fpul,@-r15" 4909 [(set_attr "type" "fstore") 4910 (set_attr "late_fp_use" "yes") 4911 (set_attr "hit_stack" "yes")]) 4912 4913;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4, 4914;; so use that. 4915(define_expand "push_4" 4916 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG))) 4917 (match_operand:DF 0 "" "")) 4918 (use (reg:SI FPSCR_MODES_REG)) 4919 (clobber (scratch:SI))])]) 4920 4921(define_expand "pop_e" 4922 [(parallel [(set (match_operand:SF 0 "" "") 4923 (mem:SF (post_inc:SI (reg:SI SP_REG)))) 4924 (use (reg:SI FPSCR_MODES_REG)) 4925 (clobber (scratch:SI))])]) 4926 4927(define_insn "pop_fpul" 4928 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))] 4929 "TARGET_SH2E" 4930 "lds.l @r15+,fpul" 4931 [(set_attr "type" "load") 4932 (set_attr "hit_stack" "yes")]) 4933 4934(define_expand "pop_4" 4935 [(parallel [(set (match_operand:DF 0 "" "") 4936 (mem:DF (post_inc:SI (reg:SI SP_REG)))) 4937 (use (reg:SI FPSCR_MODES_REG)) 4938 (clobber (scratch:SI))])]) 4939 4940(define_expand "push_fpscr" 4941 [(const_int 0)] 4942 "TARGET_SH2E" 4943{ 4944 add_reg_note ( 4945 emit_insn ( 4946 gen_sts_fpscr ( 4947 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))), 4948 REG_INC, stack_pointer_rtx); 4949 DONE; 4950}) 4951 4952(define_expand "pop_fpscr" 4953 [(const_int 0)] 4954 "TARGET_SH2E" 4955{ 4956 add_reg_note ( 4957 emit_insn ( 4958 gen_lds_fpscr ( 4959 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))), 4960 REG_INC, stack_pointer_rtx); 4961 DONE; 4962}) 4963 4964;; The clrt and sett patterns can happen as the result of optimization and 4965;; insn expansion. 4966;; Comparisons might get simplified to a move of zero or 1 into the T reg. 4967;; In this case they might not disappear completely, because the T reg is 4968;; a fixed hard reg. 4969;; When DImode operations that use the T reg as carry/borrow are split into 4970;; individual SImode operations, the T reg is usually cleared before the 4971;; first SImode insn. 4972(define_insn "clrt" 4973 [(set (reg:SI T_REG) (const_int 0))] 4974 "TARGET_SH1" 4975 "clrt" 4976 [(set_attr "type" "mt_group")]) 4977 4978(define_insn "sett" 4979 [(set (reg:SI T_REG) (const_int 1))] 4980 "TARGET_SH1" 4981 "sett" 4982 [(set_attr "type" "mt_group")]) 4983 4984;; Use the combine pass to transform sequences such as 4985;; mov r5,r0 4986;; add #1,r0 4987;; shll2 r0 4988;; mov.l @(r0,r4),r0 4989;; into 4990;; shll2 r5 4991;; add r4,r5 4992;; mov.l @(4,r5),r0 4993;; 4994;; See also PR 39423. 4995;; Notice that these patterns have a T_REG clobber, because the shift 4996;; sequence that will be split out might clobber the T_REG. Ideally, the 4997;; clobber would be added conditionally, depending on the result of 4998;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go 4999;; through the ashlsi3 expander in order to get the right shift insn -- 5000;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift. 5001;; FIXME: Combine never tries this kind of patterns for DImode. 5002(define_insn_and_split "*movsi_index_disp_load" 5003 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 5004 (match_operand:SI 1 "mem_index_disp_operand" "m")) 5005 (clobber (reg:SI T_REG))] 5006 "TARGET_SH1" 5007 "#" 5008 "&& can_create_pseudo_p ()" 5009 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3))) 5010 (set (match_dup 0) (match_dup 7))] 5011{ 5012 rtx mem = operands[1]; 5013 rtx plus0_rtx = XEXP (mem, 0); 5014 rtx plus1_rtx = XEXP (plus0_rtx, 0); 5015 rtx mult_rtx = XEXP (plus1_rtx, 0); 5016 5017 operands[1] = XEXP (mult_rtx, 0); 5018 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1)))); 5019 operands[3] = XEXP (plus1_rtx, 1); 5020 operands[4] = XEXP (plus0_rtx, 1); 5021 operands[5] = gen_reg_rtx (SImode); 5022 operands[6] = gen_reg_rtx (SImode); 5023 operands[7] = 5024 replace_equiv_address (mem, 5025 gen_rtx_PLUS (SImode, operands[6], operands[4])); 5026 5027 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2])); 5028}) 5029 5030(define_insn_and_split "*movhi_index_disp_load" 5031 [(set (match_operand:SI 0 "arith_reg_dest") 5032 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand"))) 5033 (clobber (reg:SI T_REG))] 5034 "TARGET_SH1" 5035 "#" 5036 "&& can_create_pseudo_p ()" 5037 [(const_int 0)] 5038{ 5039 rtx mem = operands[1]; 5040 rtx plus0_rtx = XEXP (mem, 0); 5041 rtx plus1_rtx = XEXP (plus0_rtx, 0); 5042 rtx mult_rtx = XEXP (plus1_rtx, 0); 5043 5044 rtx op_1 = XEXP (mult_rtx, 0); 5045 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1)))); 5046 rtx op_3 = XEXP (plus1_rtx, 1); 5047 rtx op_4 = XEXP (plus0_rtx, 1); 5048 rtx op_5 = gen_reg_rtx (SImode); 5049 rtx op_6 = gen_reg_rtx (SImode); 5050 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4)); 5051 5052 emit_insn (gen_ashlsi3 (op_5, op_1, op_2)); 5053 emit_insn (gen_addsi3 (op_6, op_5, op_3)); 5054 5055 if (<CODE> == SIGN_EXTEND) 5056 { 5057 emit_insn (gen_extendhisi2 (operands[0], op_7)); 5058 DONE; 5059 } 5060 else if (<CODE> == ZERO_EXTEND) 5061 { 5062 /* On SH2A the movu.w insn can be used for zero extending loads. */ 5063 if (TARGET_SH2A) 5064 emit_insn (gen_zero_extendhisi2 (operands[0], op_7)); 5065 else 5066 { 5067 emit_insn (gen_extendhisi2 (operands[0], op_7)); 5068 emit_insn (gen_zero_extendhisi2 (operands[0], 5069 gen_lowpart (HImode, operands[0]))); 5070 } 5071 DONE; 5072 } 5073 else 5074 FAIL; 5075}) 5076 5077(define_insn_and_split "*mov<mode>_index_disp_store" 5078 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m") 5079 (match_operand:HISI 1 "arith_reg_operand" "r")) 5080 (clobber (reg:SI T_REG))] 5081 "TARGET_SH1" 5082 "#" 5083 "&& can_create_pseudo_p ()" 5084 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3))) 5085 (set (match_dup 7) (match_dup 1))] 5086{ 5087 rtx mem = operands[0]; 5088 rtx plus0_rtx = XEXP (mem, 0); 5089 rtx plus1_rtx = XEXP (plus0_rtx, 0); 5090 rtx mult_rtx = XEXP (plus1_rtx, 0); 5091 5092 operands[0] = XEXP (mult_rtx, 0); 5093 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1)))); 5094 operands[3] = XEXP (plus1_rtx, 1); 5095 operands[4] = XEXP (plus0_rtx, 1); 5096 operands[5] = gen_reg_rtx (SImode); 5097 operands[6] = gen_reg_rtx (SImode); 5098 operands[7] = 5099 replace_equiv_address (mem, 5100 gen_rtx_PLUS (SImode, operands[6], operands[4])); 5101 5102 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2])); 5103}) 5104 5105;; t/r must come after r/r, lest reload will try to reload stuff like 5106;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0) 5107;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T. 5108;; Notice that although this pattern allows movi20 and movi20s on non-SH2A, 5109;; those alternatives will not be taken, as they will be converted into 5110;; PC-relative loads. 5111(define_insn "movsi_i" 5112 [(set (match_operand:SI 0 "general_movdst_operand" 5113 "=r,r, r, r, r, r,r,r,m,<,<,x,l,x,l,r") 5114 (match_operand:SI 1 "general_movsrc_operand" 5115 " Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,i"))] 5116 "TARGET_SH1 && !TARGET_FPU_ANY 5117 && (register_operand (operands[0], SImode) 5118 || register_operand (operands[1], SImode))" 5119 "@ 5120 mov.l %1,%0 5121 mov %1,%0 5122 mov %1,%0 5123 movi20 %1,%0 5124 movi20s %1,%0 5125 mov.l %1,%0 5126 sts %1,%0 5127 sts %1,%0 5128 mov.l %1,%0 5129 sts.l %1,%0 5130 sts.l %1,%0 5131 lds %1,%0 5132 lds %1,%0 5133 lds.l %1,%0 5134 lds.l %1,%0 5135 fake %1,%0" 5136 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store, 5137 mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si") 5138 (set_attr_alternative "length" 5139 [(const_int 2) 5140 (const_int 2) 5141 (const_int 2) 5142 (const_int 4) 5143 (const_int 4) 5144 (if_then_else (match_operand 1 "long_displacement_mem_operand") 5145 (const_int 4) (const_int 2)) 5146 (const_int 2) 5147 (const_int 2) 5148 (if_then_else (match_operand 0 "long_displacement_mem_operand") 5149 (const_int 4) (const_int 2)) 5150 (const_int 2) 5151 (const_int 2) 5152 (const_int 2) 5153 (const_int 2) 5154 (const_int 2) 5155 (const_int 2) 5156 (const_int 2)])]) 5157 5158;; t/r must come after r/r, lest reload will try to reload stuff like 5159;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2) 5160;; ??? This allows moves from macl to fpul to be recognized, but these moves 5161;; will require a reload. 5162;; ??? We can't include f/f because we need the proper FPSCR setting when 5163;; TARGET_FMOVD is in effect, and mode switching is done before reload. 5164;; Notice that although this pattern allows movi20 and movi20s on non-SH2A, 5165;; those alternatives will not be taken, as they will be converted into 5166;; PC-relative loads. 5167(define_insn "movsi_ie" 5168 [(set (match_operand:SI 0 "general_movdst_operand" 5169 "=r,r, r, r, r, r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f, y,*f,y") 5170 (match_operand:SI 1 "general_movsrc_operand" 5171 " Q,r,I08,I20,I28,mr,x,l, r,x,l,r,r,>,>,>,y,i,r,y, y,*f,*f,y"))] 5172 "TARGET_SH1 && TARGET_FPU_ANY 5173 && ((register_operand (operands[0], SImode) 5174 && !fpscr_operand (operands[0], SImode)) 5175 || (register_operand (operands[1], SImode) 5176 && !fpscr_operand (operands[1], SImode)))" 5177 "@ 5178 mov.l %1,%0 5179 mov %1,%0 5180 mov %1,%0 5181 movi20 %1,%0 5182 movi20s %1,%0 5183 mov.l %1,%0 5184 sts %1,%0 5185 sts %1,%0 5186 mov.l %1,%0 5187 sts.l %1,%0 5188 sts.l %1,%0 5189 lds %1,%0 5190 lds %1,%0 5191 lds.l %1,%0 5192 lds.l %1,%0 5193 lds.l %1,%0 5194 sts.l %1,%0 5195 fake %1,%0 5196 lds %1,%0 5197 sts %1,%0 5198 fsts fpul,%0 5199 flds %1,fpul 5200 fmov %1,%0 5201 ! move optimized away" 5202 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store, 5203 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore, 5204 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil") 5205 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*") 5206 (set_attr_alternative "length" 5207 [(const_int 2) 5208 (const_int 2) 5209 (const_int 2) 5210 (const_int 4) 5211 (const_int 4) 5212 (if_then_else (match_operand 1 "long_displacement_mem_operand") 5213 (const_int 4) (const_int 2)) 5214 (const_int 2) 5215 (const_int 2) 5216 (if_then_else (match_operand 0 "long_displacement_mem_operand") 5217 (const_int 4) (const_int 2)) 5218 (const_int 2) 5219 (const_int 2) 5220 (const_int 2) 5221 (const_int 2) 5222 (const_int 2) 5223 (const_int 2) 5224 (const_int 2) 5225 (const_int 2) 5226 (const_int 2) 5227 (const_int 2) 5228 (const_int 2) 5229 (const_int 2) 5230 (const_int 2) 5231 (const_int 2) 5232 (const_int 0)])]) 5233 5234;; Notice that although this pattern allows movi20 and movi20s on non-SH2A, 5235;; those alternatives will not be taken, as they will be converted into 5236;; PC-relative loads. 5237(define_insn "movsi_i_lowpart" 5238 [(set (strict_low_part 5239 (match_operand:SI 0 "general_movdst_operand" 5240 "+r,r, r, r, r, r,r,r,m,r")) 5241 (match_operand:SI 1 "general_movsrc_operand" 5242 " Q,r,I08,I20,I28,mr,x,l,r,i"))] 5243 "TARGET_SH1 5244 && (register_operand (operands[0], SImode) 5245 || register_operand (operands[1], SImode))" 5246 "@ 5247 mov.l %1,%0 5248 mov %1,%0 5249 mov %1,%0 5250 movi20 %1,%0 5251 movi20s %1,%0 5252 mov.l %1,%0 5253 sts %1,%0 5254 sts %1,%0 5255 mov.l %1,%0 5256 fake %1,%0" 5257 [(set_attr "type" "pcload,move,movi8,move,move,load,mac_gp,prget,store, 5258 pcload") 5259 (set_attr_alternative "length" 5260 [(const_int 2) 5261 (const_int 2) 5262 (const_int 2) 5263 (const_int 4) 5264 (const_int 4) 5265 (if_then_else (match_operand 1 "long_displacement_mem_operand") 5266 (const_int 4) (const_int 2)) 5267 (const_int 2) 5268 (const_int 2) 5269 (if_then_else (match_operand 0 "long_displacement_mem_operand") 5270 (const_int 4) (const_int 2)) 5271 (const_int 2)])]) 5272 5273(define_insn_and_split "load_ra" 5274 [(set (match_operand:SI 0 "general_movdst_operand" "") 5275 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))] 5276 "TARGET_SH1" 5277 "#" 5278 "&& ! currently_expanding_to_rtl" 5279 [(set (match_dup 0) (match_dup 1))]) 5280 5281(define_expand "movsi" 5282 [(set (match_operand:SI 0 "general_movdst_operand" "") 5283 (match_operand:SI 1 "general_movsrc_operand" ""))] 5284 "" 5285{ 5286 prepare_move_operands (operands, SImode); 5287}) 5288 5289(define_expand "ic_invalidate_line" 5290 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand") 5291 (match_dup 1)] UNSPEC_ICACHE) 5292 (clobber (scratch:SI))])] 5293 "TARGET_HARD_SH4" 5294{ 5295 emit_insn (gen_ic_invalidate_line_sh4a (operands[0])); 5296 DONE; 5297}) 5298 5299;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing 5300;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits 5301;; the requirement *1*00 for associative address writes. The alignment of 5302;; %0 implies that its least significant bit is cleared, 5303;; thus we clear the V bit of a matching entry if there is one. 5304(define_insn "ic_invalidate_line_i" 5305 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r") 5306 (match_operand:SI 1 "register_operand" "r")] 5307 UNSPEC_ICACHE) 5308 (clobber (match_scratch:SI 2 "=&r"))] 5309 "TARGET_HARD_SH4" 5310{ 5311 return "ocbwb @%0" "\n" 5312 " extu.w %0,%2" "\n" 5313 " or %1,%2" "\n" 5314 " mov.l %0,@%2"; 5315} 5316 [(set_attr "length" "8") 5317 (set_attr "type" "cwb")]) 5318 5319(define_insn "ic_invalidate_line_sh4a" 5320 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 5321 UNSPEC_ICACHE)] 5322 "TARGET_SH4A || TARGET_SH4_300" 5323{ 5324 return "ocbwb @%0" "\n" 5325 " synco" "\n" 5326 " icbi @%0"; 5327} 5328 [(set_attr "length" "6") 5329 (set_attr "type" "cwb")]) 5330 5331(define_expand "mov<mode>" 5332 [(set (match_operand:QIHI 0 "general_movdst_operand") 5333 (match_operand:QIHI 1 "general_movsrc_operand"))] 5334 "" 5335{ 5336 if (can_create_pseudo_p () && CONST_INT_P (operands[1]) 5337 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG) 5338 { 5339 rtx reg = gen_reg_rtx(SImode); 5340 emit_move_insn (reg, operands[1]); 5341 operands[1] = gen_lowpart (<MODE>mode, reg); 5342 } 5343 5344 prepare_move_operands (operands, <MODE>mode); 5345}) 5346 5347;; The pre-dec and post-inc mems must be captured by the '<' and '>' 5348;; constraints, otherwise wrong code might get generated. 5349(define_insn "*mov<mode>_load_predec" 5350 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z") 5351 (match_operand:QIHISI 1 "pre_dec_mem" "<"))] 5352 "TARGET_SH2A" 5353 "mov.<bwl> %1,%0" 5354 [(set_attr "type" "load")]) 5355 5356(define_insn "*mov<mode>_store_postinc" 5357 [(set (match_operand:QIHISI 0 "post_inc_mem" "=>") 5358 (match_operand:QIHISI 1 "arith_reg_operand" "z"))] 5359 "TARGET_SH2A" 5360 "mov.<bwl> %1,%0" 5361 [(set_attr "type" "store")]) 5362 5363;; Specifying the displacement addressing load / store patterns separately 5364;; before the generic movqi / movhi pattern allows controlling the order 5365;; in which load / store insns are selected in a more fine grained way. 5366;; FIXME: The non-SH2A and SH2A variants should be combined by adding 5367;; "enabled" attribute as it is done in other targets. 5368(define_insn "*mov<mode>_store_mem_disp04" 5369 [(set (mem:QIHI 5370 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r") 5371 (match_operand:SI 1 "const_int_operand" "<disp04>,N"))) 5372 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))] 5373 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)" 5374 "@ 5375 mov.<bw> %2,@(%O1,%0) 5376 mov.<bw> %2,@%0" 5377 [(set_attr "type" "store")]) 5378 5379(define_insn "*mov<mode>_store_mem_disp12" 5380 [(set (mem:QIHI 5381 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r") 5382 (match_operand:SI 1 "const_int_operand" "<disp12>"))) 5383 (match_operand:QIHI 2 "arith_reg_operand" "r"))] 5384 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)" 5385 "mov.<bw> %2,@(%O1,%0)" 5386 [(set_attr "type" "store") 5387 (set_attr "length" "4")]) 5388 5389(define_insn "*mov<mode>_load_mem_disp04" 5390 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r") 5391 (mem:QIHI 5392 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r") 5393 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))] 5394 "TARGET_SH1 && ! TARGET_SH2A 5395 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)" 5396 "@ 5397 mov.<bw> @(%O2,%1),%0 5398 mov.<bw> @%1,%0" 5399 [(set_attr "type" "load")]) 5400 5401(define_insn "*mov<mode>_load_mem_disp12" 5402 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r") 5403 (mem:QIHI 5404 (plus:SI 5405 (match_operand:SI 1 "arith_reg_operand" "%r,r,r") 5406 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))] 5407 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)" 5408 "@ 5409 mov.<bw> @(%O2,%1),%0 5410 mov.<bw> @%1,%0 5411 mov.<bw> @(%O2,%1),%0" 5412 [(set_attr "type" "load") 5413 (set_attr "length" "2,2,4")]) 5414 5415;; The order of the constraint alternatives is important here. 5416;; Q/r has to come first, otherwise PC relative loads might wrongly get 5417;; placed into delay slots. Since there is no QImode PC relative load, the 5418;; Q constraint and general_movsrc_operand will reject it for QImode. 5419;; The Sid/Ssd alternatives should come before Sdd in order to avoid 5420;; a preference of using r0 als the register operand for addressing modes 5421;; other than displacement addressing. 5422;; The Sdd alternatives allow only r0 as register operand, even though on 5423;; SH2A any register could be allowed by switching to a 32 bit insn. 5424;; Generally sticking to the r0 is preferrable, since it generates smaller 5425;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A. 5426(define_insn "*mov<mode>" 5427 [(set (match_operand:QIHI 0 "general_movdst_operand" 5428 "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l") 5429 (match_operand:QIHI 1 "general_movsrc_operand" 5430 "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))] 5431 "TARGET_SH1 5432 && (arith_reg_operand (operands[0], <MODE>mode) 5433 || arith_reg_operand (operands[1], <MODE>mode))" 5434 "@ 5435 mov.<bw> %1,%0 5436 mov %1,%0 5437 mov %1,%0 5438 mov.<bw> %1,%0 5439 mov.<bw> %1,%0 5440 mov.<bw> %1,%0 5441 mov.<bw> %1,%0 5442 mov.<bw> %1,%0 5443 mov.<bw> %1,%0 5444 sts %1,%0 5445 lds %1,%0" 5446 [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset") 5447 (set (attr "length") 5448 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 4) 5449 (match_operand 1 "long_displacement_mem_operand") (const_int 4)] 5450 (const_int 2)))]) 5451 5452;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c 5453;; compiled with -m2 -ml -O3 -funroll-loops 5454(define_insn "*movdi_i" 5455 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m, r,r,r,*!x") 5456 (match_operand:DI 1 "general_movsrc_operand" " Q,r,m,r,I08,i,x, r"))] 5457 "TARGET_SH1 5458 && (arith_reg_operand (operands[0], DImode) 5459 || arith_reg_operand (operands[1], DImode))" 5460{ 5461 return output_movedouble (insn, operands, DImode); 5462} 5463 [(set_attr "type" "pcload,move,load,store,move,pcload,move,move") 5464 (set (attr "length") 5465 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8) 5466 (match_operand 1 "long_displacement_mem_operand") (const_int 8)] 5467 (const_int 4)))]) 5468 5469;; If the output is a register and the input is memory or a register, we have 5470;; to be careful and see which word needs to be loaded first. 5471(define_split 5472 [(set (match_operand:DI 0 "general_movdst_operand" "") 5473 (match_operand:DI 1 "general_movsrc_operand" ""))] 5474 "TARGET_SH1 && reload_completed" 5475 [(set (match_dup 2) (match_dup 3)) 5476 (set (match_dup 4) (match_dup 5))] 5477{ 5478 int regno; 5479 5480 if ((MEM_P (operands[0]) 5481 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 5482 || (MEM_P (operands[1]) 5483 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)) 5484 FAIL; 5485 5486 switch (GET_CODE (operands[0])) 5487 { 5488 case REG: 5489 regno = REGNO (operands[0]); 5490 break; 5491 case SUBREG: 5492 regno = subreg_regno (operands[0]); 5493 break; 5494 case MEM: 5495 regno = -1; 5496 break; 5497 default: 5498 gcc_unreachable (); 5499 } 5500 5501 if (regno == -1 || ! refers_to_regno_p (regno, operands[1])) 5502 { 5503 operands[2] = operand_subword (operands[0], 0, 0, DImode); 5504 operands[3] = operand_subword (operands[1], 0, 0, DImode); 5505 operands[4] = operand_subword (operands[0], 1, 0, DImode); 5506 operands[5] = operand_subword (operands[1], 1, 0, DImode); 5507 } 5508 else 5509 { 5510 operands[2] = operand_subword (operands[0], 1, 0, DImode); 5511 operands[3] = operand_subword (operands[1], 1, 0, DImode); 5512 operands[4] = operand_subword (operands[0], 0, 0, DImode); 5513 operands[5] = operand_subword (operands[1], 0, 0, DImode); 5514 } 5515 5516 if (operands[2] == 0 || operands[3] == 0 5517 || operands[4] == 0 || operands[5] == 0) 5518 FAIL; 5519}) 5520 5521(define_expand "movdi" 5522 [(set (match_operand:DI 0 "general_movdst_operand" "") 5523 (match_operand:DI 1 "general_movsrc_operand" ""))] 5524 "" 5525{ 5526 prepare_move_operands (operands, DImode); 5527 5528 /* When the dest operand is (R0, R1) register pair, split it to 5529 two movsi of which dest is R1 and R0 so as to lower R0-register 5530 pressure on the first movsi. Apply only for simple source not 5531 to make complex rtl here. */ 5532 if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG 5533 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER) 5534 { 5535 emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG), 5536 gen_rtx_SUBREG (SImode, operands[1], 4))); 5537 emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG), 5538 gen_rtx_SUBREG (SImode, operands[1], 0))); 5539 DONE; 5540 } 5541}) 5542 5543;; FIXME: This should be a define_insn_and_split. 5544(define_insn "movdf_k" 5545 [(set (match_operand:DF 0 "general_movdst_operand" "=r, r,r,m") 5546 (match_operand:DF 1 "general_movsrc_operand" " r,FQ,m,r"))] 5547 "TARGET_SH1 5548 && (!TARGET_FPU_DOUBLE || reload_completed 5549 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */ 5550 || (REG_P (operands[0]) && REGNO (operands[0]) == 3) 5551 || (REG_P (operands[1]) && REGNO (operands[1]) == 3)) 5552 && (arith_reg_operand (operands[0], DFmode) 5553 || arith_reg_operand (operands[1], DFmode))" 5554{ 5555 return output_movedouble (insn, operands, DFmode); 5556} 5557 [(set_attr "type" "move,pcload,load,store") 5558 (set (attr "length") 5559 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8) 5560 (match_operand 1 "long_displacement_mem_operand") (const_int 8)] 5561 (const_int 4)))]) 5562 5563;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD. 5564;; However, the d/F/c/z alternative cannot be split directly; it is converted 5565;; with special code in machine_dependent_reorg into a load of the R0_REG and 5566;; the d/m/c/X alternative, which is split later into single-precision 5567;; instructions. And when not optimizing, no splits are done before fixing 5568;; up pcloads, so we need usable length information for that. 5569;; A DF constant load results in the following worst-case 8 byte sequence: 5570;; mova ...,r0 5571;; fmov.s @r0+,.. 5572;; fmov.s @r0,... 5573;; add #-4,r0 5574(define_insn "movdf_i4" 5575 [(set (match_operand:DF 0 "general_movdst_operand" 5576 "=d,r, d,d,m, r,r,m,!??r,!???d") 5577 (match_operand:DF 1 "general_movsrc_operand" 5578 " d,r, F,m,d,FQ,m,r, d, r")) 5579 (use (reg:SI FPSCR_MODES_REG)) 5580 (clobber (match_scratch:SI 2 5581 "=X,X,&z,X,X, X,X,X, X, X"))] 5582 "TARGET_FPU_DOUBLE 5583 && (arith_reg_operand (operands[0], DFmode) 5584 || arith_reg_operand (operands[1], DFmode))" 5585 { 5586 switch (which_alternative) 5587 { 5588 case 0: 5589 if (TARGET_FMOVD) 5590 return "fmov %1,%0"; 5591 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1) 5592 return "fmov %R1,%R0" "\n" 5593 " fmov %S1,%S0"; 5594 else 5595 return "fmov %S1,%S0" "\n" 5596 " fmov %R1,%R0"; 5597 case 3: 5598 case 4: 5599 return "fmov.d %1,%0"; 5600 default: 5601 return "#"; 5602 } 5603 } 5604 [(set_attr_alternative "length" 5605 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4)) 5606 (const_int 4) 5607 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8)) 5608 (if_then_else (match_operand 1 "displacement_mem_operand") 5609 (if_then_else (eq_attr "fmovd" "yes") 5610 (const_int 4) (const_int 8)) 5611 (if_then_else (eq_attr "fmovd" "yes") 5612 (const_int 2) (const_int 4))) 5613 (if_then_else (match_operand 0 "displacement_mem_operand") 5614 (if_then_else (eq_attr "fmovd" "yes") 5615 (const_int 4) (const_int 8)) 5616 (if_then_else (eq_attr "fmovd" "yes") 5617 (const_int 2) (const_int 4))) 5618 (const_int 4) 5619 (if_then_else (match_operand 1 "long_displacement_mem_operand") 5620 (const_int 8) (const_int 4)) 5621 (if_then_else (match_operand 0 "long_displacement_mem_operand") 5622 (const_int 8) (const_int 4)) 5623 (const_int 8) 5624 (const_int 8)]) 5625 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load, 5626 fload") 5627 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*") 5628 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes") 5629 (const_string "double") 5630 (const_string "none")))]) 5631 5632;; Moving DFmode between fp/general registers through memory 5633;; (the top of the stack) is faster than moving through fpul even for 5634;; little endian. Because the type of an instruction is important for its 5635;; scheduling, it is beneficial to split these operations, rather than 5636;; emitting them in one single chunk, even if this will expose a stack 5637;; use that will prevent scheduling of other stack accesses beyond this 5638;; instruction. 5639(define_split 5640 [(set (match_operand:DF 0 "register_operand") 5641 (match_operand:DF 1 "register_operand")) 5642 (use (reg:SI FPSCR_MODES_REG)) 5643 (clobber (match_scratch:SI 2))] 5644 "TARGET_FPU_DOUBLE && reload_completed 5645 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)" 5646 [(const_int 0)] 5647{ 5648 rtx insn, tos; 5649 5650 tos = gen_tmp_stack_mem (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); 5651 insn = emit_insn (gen_movdf_i4 (tos, operands[1])); 5652 add_reg_note (insn, REG_INC, stack_pointer_rtx); 5653 tos = gen_tmp_stack_mem (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)); 5654 insn = emit_insn (gen_movdf_i4 (operands[0], tos)); 5655 add_reg_note (insn, REG_INC, stack_pointer_rtx); 5656 DONE; 5657}) 5658 5659;; local-alloc sometimes allocates scratch registers even when not required, 5660;; so we must be prepared to handle these. 5661 5662;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k. 5663(define_split 5664 [(set (match_operand:DF 0 "general_movdst_operand" "") 5665 (match_operand:DF 1 "general_movsrc_operand" "")) 5666 (use (reg:SI FPSCR_MODES_REG)) 5667 (clobber (match_scratch:SI 2))] 5668 "TARGET_FPU_DOUBLE 5669 && reload_completed 5670 && true_regnum (operands[0]) < 16 5671 && true_regnum (operands[1]) < 16" 5672 [(set (match_dup 0) (match_dup 1))] 5673{ 5674 /* If this was a reg <-> mem operation with base + index reg addressing, 5675 we have to handle this in a special way. */ 5676 rtx mem = operands[0]; 5677 int store_p = 1; 5678 if (! memory_operand (mem, DFmode)) 5679 { 5680 mem = operands[1]; 5681 store_p = 0; 5682 } 5683 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0) 5684 mem = SUBREG_REG (mem); 5685 if (MEM_P (mem)) 5686 { 5687 rtx addr = XEXP (mem, 0); 5688 if (GET_CODE (addr) == PLUS 5689 && REG_P (XEXP (addr, 0)) 5690 && REG_P (XEXP (addr, 1))) 5691 { 5692 int offset; 5693 rtx reg0 = gen_rtx_REG (Pmode, 0); 5694 rtx regop = operands[store_p], word0 ,word1; 5695 5696 if (GET_CODE (regop) == SUBREG) 5697 alter_subreg (®op, true); 5698 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1))) 5699 offset = 2; 5700 else 5701 offset = 4; 5702 mem = copy_rtx (mem); 5703 PUT_MODE (mem, SImode); 5704 word0 = gen_rtx_SUBREG (SImode, regop, 0); 5705 alter_subreg (&word0, true); 5706 word1 = gen_rtx_SUBREG (SImode, regop, 4); 5707 alter_subreg (&word1, true); 5708 if (store_p || ! refers_to_regno_p (REGNO (word0), addr)) 5709 { 5710 emit_insn (store_p 5711 ? gen_movsi_ie (mem, word0) 5712 : gen_movsi_ie (word0, mem)); 5713 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset))); 5714 mem = copy_rtx (mem); 5715 emit_insn (store_p 5716 ? gen_movsi_ie (mem, word1) 5717 : gen_movsi_ie (word1, mem)); 5718 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset))); 5719 } 5720 else 5721 { 5722 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset))); 5723 emit_insn (gen_movsi_ie (word1, mem)); 5724 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset))); 5725 mem = copy_rtx (mem); 5726 emit_insn (gen_movsi_ie (word0, mem)); 5727 } 5728 DONE; 5729 } 5730 } 5731}) 5732 5733;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads. 5734(define_split 5735 [(set (match_operand:DF 0 "register_operand" "") 5736 (match_operand:DF 1 "memory_operand" "")) 5737 (use (reg:SI FPSCR_MODES_REG)) 5738 (clobber (reg:SI R0_REG))] 5739 "TARGET_FPU_DOUBLE && reload_completed" 5740 [(parallel [(set (match_dup 0) (match_dup 1)) 5741 (use (reg:SI FPSCR_MODES_REG)) 5742 (clobber (scratch:SI))])] 5743 "") 5744 5745(define_expand "reload_indf__frn" 5746 [(parallel [(set (match_operand:DF 0 "register_operand" "=a") 5747 (match_operand:DF 1 "immediate_operand" "FQ")) 5748 (use (reg:SI FPSCR_MODES_REG)) 5749 (clobber (match_operand:SI 2 "register_operand" "=&z"))])] 5750 "TARGET_SH1" 5751 "") 5752 5753(define_expand "reload_outdf__RnFRm" 5754 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f") 5755 (match_operand:DF 1 "register_operand" "af,r")) 5756 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])] 5757 "TARGET_SH1" 5758 "") 5759 5760;; Simplify no-op moves. 5761(define_split 5762 [(set (match_operand:SF 0 "register_operand" "") 5763 (match_operand:SF 1 "register_operand" "")) 5764 (use (reg:SI FPSCR_MODES_REG)) 5765 (clobber (match_scratch:SI 2))] 5766 "TARGET_SH2E && reload_completed 5767 && true_regnum (operands[0]) == true_regnum (operands[1])" 5768 [(set (match_dup 0) (match_dup 0))] 5769 "") 5770 5771;; fmovd substitute post-reload splits 5772(define_split 5773 [(set (match_operand:DF 0 "register_operand" "") 5774 (match_operand:DF 1 "register_operand" "")) 5775 (use (reg:SI FPSCR_MODES_REG)) 5776 (clobber (match_scratch:SI 2))] 5777 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed 5778 && FP_OR_XD_REGISTER_P (true_regnum (operands[0])) 5779 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))" 5780 [(const_int 0)] 5781{ 5782 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]); 5783 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst), 5784 gen_rtx_REG (SFmode, src))); 5785 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1), 5786 gen_rtx_REG (SFmode, src + 1))); 5787 DONE; 5788}) 5789 5790(define_split 5791 [(set (match_operand:DF 0 "register_operand" "") 5792 (mem:DF (match_operand:SI 1 "register_operand" ""))) 5793 (use (reg:SI FPSCR_MODES_REG)) 5794 (clobber (match_scratch:SI 2))] 5795 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed 5796 && FP_OR_XD_REGISTER_P (true_regnum (operands[0])) 5797 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))" 5798 [(const_int 0)] 5799{ 5800 int regno = true_regnum (operands[0]); 5801 rtx insn; 5802 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0)); 5803 rtx mem2 5804 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1])); 5805 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, 5806 regno + SH_REG_MSW_OFFSET), 5807 mem2)); 5808 add_reg_note (insn, REG_INC, operands[1]); 5809 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, 5810 regno + SH_REG_LSW_OFFSET), 5811 change_address (mem, SFmode, NULL_RTX))); 5812 DONE; 5813}) 5814 5815(define_split 5816 [(set (match_operand:DF 0 "register_operand" "") 5817 (match_operand:DF 1 "memory_operand" "")) 5818 (use (reg:SI FPSCR_MODES_REG)) 5819 (clobber (match_scratch:SI 2))] 5820 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed 5821 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))" 5822 [(const_int 0)] 5823{ 5824 int regno = true_regnum (operands[0]); 5825 rtx addr, insn; 5826 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX); 5827 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET); 5828 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET); 5829 5830 operands[1] = copy_rtx (mem2); 5831 addr = XEXP (mem2, 0); 5832 5833 switch (GET_CODE (addr)) 5834 { 5835 case REG: 5836 /* This is complicated. If the register is an arithmetic register 5837 we can just fall through to the REG+DISP case below. Otherwise 5838 we have to use a combination of POST_INC and REG addressing... */ 5839 if (! arith_reg_operand (operands[1], SFmode)) 5840 { 5841 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr); 5842 insn = emit_insn (gen_movsf_ie (reg0, mem2)); 5843 add_reg_note (insn, REG_INC, XEXP (addr, 0)); 5844 5845 emit_insn (gen_movsf_ie (reg1, operands[1])); 5846 5847 /* If we have modified the stack pointer, the value that we have 5848 read with post-increment might be modified by an interrupt, 5849 so write it back. */ 5850 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM) 5851 emit_insn (gen_push_e (reg0)); 5852 else 5853 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0), 5854 GEN_INT (-4))); 5855 break; 5856 } 5857 /* Fall through. */ 5858 5859 case PLUS: 5860 emit_insn (gen_movsf_ie (reg0, operands[1])); 5861 operands[1] = copy_rtx (operands[1]); 5862 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4); 5863 emit_insn (gen_movsf_ie (reg1, operands[1])); 5864 break; 5865 5866 case POST_INC: 5867 insn = emit_insn (gen_movsf_ie (reg0, operands[1])); 5868 add_reg_note (insn, REG_INC, XEXP (addr, 0)); 5869 5870 insn = emit_insn (gen_movsf_ie (reg1, operands[1])); 5871 add_reg_note (insn, REG_INC, XEXP (addr, 0)); 5872 break; 5873 5874 default: 5875 debug_rtx (addr); 5876 gcc_unreachable (); 5877 } 5878 5879 DONE; 5880}) 5881 5882(define_split 5883 [(set (match_operand:DF 0 "memory_operand" "") 5884 (match_operand:DF 1 "register_operand" "")) 5885 (use (reg:SI FPSCR_MODES_REG)) 5886 (clobber (match_scratch:SI 2))] 5887 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed 5888 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))" 5889 [(const_int 0)] 5890{ 5891 int regno = true_regnum (operands[1]); 5892 rtx insn, addr; 5893 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET); 5894 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET); 5895 5896 operands[0] = copy_rtx (operands[0]); 5897 PUT_MODE (operands[0], SFmode); 5898 addr = XEXP (operands[0], 0); 5899 5900 switch (GET_CODE (addr)) 5901 { 5902 case REG: 5903 /* This is complicated. If the register is an arithmetic register 5904 we can just fall through to the REG+DISP case below. Otherwise 5905 we have to use a combination of REG and PRE_DEC addressing... */ 5906 if (! arith_reg_operand (operands[0], SFmode)) 5907 { 5908 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4))); 5909 emit_insn (gen_movsf_ie (operands[0], reg1)); 5910 5911 operands[0] = copy_rtx (operands[0]); 5912 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr); 5913 5914 insn = emit_insn (gen_movsf_ie (operands[0], reg0)); 5915 add_reg_note (insn, REG_INC, XEXP (addr, 0)); 5916 break; 5917 } 5918 /* Fall through. */ 5919 5920 case PLUS: 5921 /* Since REG+DISP addressing has already been decided upon by gcc 5922 we can rely upon it having chosen an arithmetic register as the 5923 register component of the address. Just emit the lower numbered 5924 register first, to the lower address, then the higher numbered 5925 register to the higher address. */ 5926 emit_insn (gen_movsf_ie (operands[0], reg0)); 5927 5928 operands[0] = copy_rtx (operands[0]); 5929 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4); 5930 5931 emit_insn (gen_movsf_ie (operands[0], reg1)); 5932 break; 5933 5934 case PRE_DEC: 5935 /* This is easy. Output the word to go to the higher address 5936 first (ie the word in the higher numbered register) then the 5937 word to go to the lower address. */ 5938 5939 insn = emit_insn (gen_movsf_ie (operands[0], reg1)); 5940 add_reg_note (insn, REG_INC, XEXP (addr, 0)); 5941 5942 insn = emit_insn (gen_movsf_ie (operands[0], reg0)); 5943 add_reg_note (insn, REG_INC, XEXP (addr, 0)); 5944 break; 5945 5946 default: 5947 /* FAIL; */ 5948 debug_rtx (addr); 5949 gcc_unreachable (); 5950 } 5951 5952 DONE; 5953}) 5954 5955;; If the output is a register and the input is memory or a register, we have 5956;; to be careful and see which word needs to be loaded first. 5957(define_split 5958 [(set (match_operand:DF 0 "general_movdst_operand" "") 5959 (match_operand:DF 1 "general_movsrc_operand" ""))] 5960 "TARGET_SH1 && reload_completed" 5961 [(set (match_dup 2) (match_dup 3)) 5962 (set (match_dup 4) (match_dup 5))] 5963{ 5964 int regno; 5965 5966 if ((MEM_P (operands[0]) 5967 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 5968 || (MEM_P (operands[1]) 5969 && GET_CODE (XEXP (operands[1], 0)) == POST_INC)) 5970 FAIL; 5971 5972 switch (GET_CODE (operands[0])) 5973 { 5974 case REG: 5975 regno = REGNO (operands[0]); 5976 break; 5977 case SUBREG: 5978 regno = subreg_regno (operands[0]); 5979 break; 5980 case MEM: 5981 regno = -1; 5982 break; 5983 default: 5984 gcc_unreachable (); 5985 } 5986 5987 if (regno == -1 || ! refers_to_regno_p (regno, operands[1])) 5988 { 5989 operands[2] = operand_subword (operands[0], 0, 0, DFmode); 5990 operands[3] = operand_subword (operands[1], 0, 0, DFmode); 5991 operands[4] = operand_subword (operands[0], 1, 0, DFmode); 5992 operands[5] = operand_subword (operands[1], 1, 0, DFmode); 5993 } 5994 else 5995 { 5996 operands[2] = operand_subword (operands[0], 1, 0, DFmode); 5997 operands[3] = operand_subword (operands[1], 1, 0, DFmode); 5998 operands[4] = operand_subword (operands[0], 0, 0, DFmode); 5999 operands[5] = operand_subword (operands[1], 0, 0, DFmode); 6000 } 6001 6002 if (operands[2] == 0 || operands[3] == 0 6003 || operands[4] == 0 || operands[5] == 0) 6004 FAIL; 6005}) 6006 6007(define_expand "movdf" 6008 [(set (match_operand:DF 0 "general_movdst_operand" "") 6009 (match_operand:DF 1 "general_movsrc_operand" ""))] 6010 "" 6011{ 6012 prepare_move_operands (operands, DFmode); 6013 if (TARGET_FPU_DOUBLE) 6014 { 6015 emit_insn (gen_movdf_i4 (operands[0], operands[1])); 6016 DONE; 6017 } 6018}) 6019 6020;; FIXME Although the movsf_i pattern is not used when there's an FPU, 6021;; it somehow influences some RA choices also on FPU targets. 6022;; For non-FPU targets it's actually not needed. 6023(define_insn "movsf_i" 6024 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r, r, r,m,l,r") 6025 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))] 6026 "TARGET_SH1 6027 && (! TARGET_SH2E 6028 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */ 6029 || (REG_P (operands[0]) && REGNO (operands[0]) == 3) 6030 || (REG_P (operands[1]) && REGNO (operands[1]) == 3)) 6031 && (arith_reg_operand (operands[0], SFmode) 6032 || arith_reg_operand (operands[1], SFmode))" 6033 "@ 6034 mov %1,%0 6035 mov #0,%0 6036 mov.l %1,%0 6037 mov.l %1,%0 6038 mov.l %1,%0 6039 lds %1,%0 6040 sts %1,%0" 6041 [(set_attr "type" "move,move,pcload,load,store,move,move") 6042 (set_attr_alternative "length" 6043 [(const_int 2) 6044 (const_int 2) 6045 (if_then_else (match_operand 1 "long_displacement_mem_operand") 6046 (const_int 4) (const_int 2)) 6047 (if_then_else (match_operand 1 "long_displacement_mem_operand") 6048 (const_int 4) (const_int 2)) 6049 (if_then_else (match_operand 0 "long_displacement_mem_operand") 6050 (const_int 4) (const_int 2)) 6051 (const_int 2) 6052 (const_int 2)])]) 6053 6054;; We may not split the ry/yr/XX alternatives to movsi_ie, since 6055;; update_flow_info would not know where to put REG_EQUAL notes 6056;; when the destination changes mode. 6057(define_insn "movsf_ie" 6058 [(set (match_operand:SF 0 "general_movdst_operand" 6059 "=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y") 6060 (match_operand:SF 1 "general_movsrc_operand" 6061 " f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y")) 6062 (use (reg:SI FPSCR_MODES_REG)) 6063 (clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))] 6064 "TARGET_SH2E 6065 && (arith_reg_operand (operands[0], SFmode) 6066 || fpul_operand (operands[0], SFmode) 6067 || arith_reg_operand (operands[1], SFmode) 6068 || fpul_operand (operands[1], SFmode) 6069 || arith_reg_operand (operands[2], SImode))" 6070 "@ 6071 fmov %1,%0 6072 mov %1,%0 6073 fldi0 %0 6074 fldi1 %0 6075 # 6076 fmov.s %1,%0 6077 fmov.s %1,%0 6078 mov.l %1,%0 6079 mov.l %1,%0 6080 mov.l %1,%0 6081 fsts fpul,%0 6082 flds %1,fpul 6083 lds.l %1,%0 6084 # 6085 sts %1,%0 6086 lds %1,%0 6087 sts.l %1,%0 6088 lds.l %1,%0 6089 ! move optimized away" 6090 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load, 6091 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil") 6092 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*") 6093 (set_attr_alternative "length" 6094 [(const_int 2) 6095 (const_int 2) 6096 (const_int 2) 6097 (const_int 2) 6098 (const_int 4) 6099 (if_then_else (match_operand 1 "displacement_mem_operand") 6100 (const_int 4) (const_int 2)) 6101 (if_then_else (match_operand 0 "displacement_mem_operand") 6102 (const_int 4) (const_int 2)) 6103 (const_int 2) 6104 (if_then_else (match_operand 1 "long_displacement_mem_operand") 6105 (const_int 4) (const_int 2)) 6106 (if_then_else (match_operand 0 "long_displacement_mem_operand") 6107 (const_int 4) (const_int 2)) 6108 (const_int 2) 6109 (const_int 2) 6110 (const_int 2) 6111 (const_int 4) 6112 (const_int 2) 6113 (const_int 2) 6114 (const_int 2) 6115 (const_int 2) 6116 (const_int 0)]) 6117 (set_attr_alternative "fp_mode" 6118 [(if_then_else (eq_attr "fmovd" "yes") 6119 (const_string "single") (const_string "none")) 6120 (const_string "none") 6121 (const_string "single") 6122 (const_string "single") 6123 (const_string "none") 6124 (if_then_else (eq_attr "fmovd" "yes") 6125 (const_string "single") (const_string "none")) 6126 (if_then_else (eq_attr "fmovd" "yes") 6127 (const_string "single") (const_string "none")) 6128 (const_string "none") 6129 (const_string "none") 6130 (const_string "none") 6131 (const_string "none") 6132 (const_string "none") 6133 (const_string "none") 6134 (const_string "none") 6135 (const_string "none") 6136 (const_string "none") 6137 (const_string "none") 6138 (const_string "none") 6139 (const_string "none")])]) 6140 6141(define_insn_and_split "movsf_ie_ra" 6142 [(set (match_operand:SF 0 "general_movdst_operand" 6143 "=f,r,f,f,fy,f,m, r,r,m,f,y,y,rf,r,y,<,y,y") 6144 (match_operand:SF 1 "general_movsrc_operand" 6145 " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y")) 6146 (use (reg:SI FPSCR_MODES_REG)) 6147 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r")) 6148 (const_int 0)] 6149 "TARGET_SH2E 6150 && (arith_reg_operand (operands[0], SFmode) 6151 || fpul_operand (operands[0], SFmode) 6152 || arith_reg_operand (operands[1], SFmode) 6153 || fpul_operand (operands[1], SFmode))" 6154 "@ 6155 fmov %1,%0 6156 mov %1,%0 6157 fldi0 %0 6158 fldi1 %0 6159 # 6160 fmov.s %1,%0 6161 fmov.s %1,%0 6162 mov.l %1,%0 6163 mov.l %1,%0 6164 mov.l %1,%0 6165 fsts fpul,%0 6166 flds %1,fpul 6167 lds.l %1,%0 6168 # 6169 sts %1,%0 6170 lds %1,%0 6171 sts.l %1,%0 6172 lds.l %1,%0 6173 ! move optimized away" 6174 "reload_completed 6175 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])" 6176 [(const_int 0)] 6177{ 6178 if (! rtx_equal_p (operands[0], operands[1])) 6179 { 6180 emit_insn (gen_movsf_ie (operands[2], operands[1])); 6181 emit_insn (gen_movsf_ie (operands[0], operands[2])); 6182 } 6183} 6184 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load, 6185 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil") 6186 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*") 6187 (set_attr_alternative "length" 6188 [(const_int 2) 6189 (const_int 2) 6190 (const_int 2) 6191 (const_int 2) 6192 (const_int 4) 6193 (if_then_else (match_operand 1 "displacement_mem_operand") 6194 (const_int 4) (const_int 2)) 6195 (if_then_else (match_operand 0 "displacement_mem_operand") 6196 (const_int 4) (const_int 2)) 6197 (const_int 2) 6198 (if_then_else (match_operand 1 "long_displacement_mem_operand") 6199 (const_int 4) (const_int 2)) 6200 (if_then_else (match_operand 0 "long_displacement_mem_operand") 6201 (const_int 4) (const_int 2)) 6202 (const_int 2) 6203 (const_int 2) 6204 (const_int 2) 6205 (const_int 4) 6206 (const_int 2) 6207 (const_int 2) 6208 (const_int 2) 6209 (const_int 2) 6210 (const_int 0)]) 6211 (set_attr_alternative "fp_mode" 6212 [(if_then_else (eq_attr "fmovd" "yes") 6213 (const_string "single") (const_string "none")) 6214 (const_string "none") 6215 (const_string "single") 6216 (const_string "single") 6217 (const_string "none") 6218 (if_then_else (eq_attr "fmovd" "yes") 6219 (const_string "single") (const_string "none")) 6220 (if_then_else (eq_attr "fmovd" "yes") 6221 (const_string "single") (const_string "none")) 6222 (const_string "none") 6223 (const_string "none") 6224 (const_string "none") 6225 (const_string "none") 6226 (const_string "none") 6227 (const_string "none") 6228 (const_string "none") 6229 (const_string "none") 6230 (const_string "none") 6231 (const_string "none") 6232 (const_string "none") 6233 (const_string "none")])]) 6234 6235(define_split 6236 [(set (match_operand:SF 0 "register_operand" "") 6237 (match_operand:SF 1 "register_operand" "")) 6238 (use (reg:SI FPSCR_MODES_REG)) 6239 (clobber (reg:SI FPUL_REG))] 6240 "TARGET_SH1" 6241 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1)) 6242 (use (reg:SI FPSCR_MODES_REG)) 6243 (clobber (scratch:SI))]) 6244 (parallel [(set (match_dup 0) (reg:SF FPUL_REG)) 6245 (use (reg:SI FPSCR_MODES_REG)) 6246 (clobber (scratch:SI))])] 6247 "") 6248 6249(define_expand "movsf" 6250 [(set (match_operand:SF 0 "general_movdst_operand" "") 6251 (match_operand:SF 1 "general_movsrc_operand" ""))] 6252 "" 6253{ 6254 prepare_move_operands (operands, SFmode); 6255 if (TARGET_SH2E) 6256 { 6257 if (lra_in_progress) 6258 { 6259 if (GET_CODE (operands[0]) == SCRATCH) 6260 DONE; 6261 emit_insn (gen_movsf_ie_ra (operands[0], operands[1])); 6262 DONE; 6263 } 6264 6265 emit_insn (gen_movsf_ie (operands[0], operands[1])); 6266 DONE; 6267 } 6268}) 6269 6270(define_expand "reload_insf__frn" 6271 [(parallel [(set (match_operand:SF 0 "register_operand" "=a") 6272 (match_operand:SF 1 "immediate_operand" "FQ")) 6273 (use (reg:SI FPSCR_MODES_REG)) 6274 (clobber (match_operand:SI 2 "register_operand" "=&z"))])] 6275 "TARGET_SH1" 6276 "") 6277 6278(define_expand "reload_insi__i_fpul" 6279 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y") 6280 (match_operand:SI 1 "immediate_operand" "i")) 6281 (clobber (match_operand:SI 2 "register_operand" "=&z"))])] 6282 "TARGET_SH1" 6283 "") 6284 6285(define_insn "*movsi_y" 6286 [(set (match_operand:SI 0 "register_operand" "=y,y") 6287 (match_operand:SI 1 "immediate_operand" "Qi,I08")) 6288 (clobber (match_scratch:SI 2 "=&z,r"))] 6289 "TARGET_SH2E 6290 && (reload_in_progress || reload_completed)" 6291 "#" 6292 [(set_attr "length" "4") 6293 (set_attr "type" "pcload,move")]) 6294 6295(define_split 6296 [(set (match_operand:SI 0 "register_operand" "") 6297 (match_operand:SI 1 "immediate_operand" "")) 6298 (clobber (match_operand:SI 2 "register_operand" ""))] 6299 "TARGET_SH1" 6300 [(set (match_dup 2) (match_dup 1)) 6301 (set (match_dup 0) (match_dup 2))] 6302 "") 6303 6304;; ------------------------------------------------------------------------ 6305;; Define the real conditional branch instructions. 6306;; ------------------------------------------------------------------------ 6307 6308(define_expand "branch_true" 6309 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0)) 6310 (label_ref (match_operand 0)) 6311 (pc)))] 6312 "TARGET_SH1") 6313 6314(define_expand "branch_false" 6315 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 6316 (label_ref (match_operand 0)) 6317 (pc)))] 6318 "TARGET_SH1") 6319 6320(define_insn_and_split "*cbranch_t" 6321 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value") 6322 (label_ref (match_operand 0)) 6323 (pc)))] 6324 "TARGET_SH1" 6325{ 6326 return output_branch (sh_eval_treg_value (operands[1]), insn, operands); 6327} 6328 "&& 1" 6329 [(const_int 0)] 6330{ 6331 /* Try to canonicalize the branch condition if it is not one of: 6332 (ne (reg:SI T_REG) (const_int 0)) 6333 (eq (reg:SI T_REG) (const_int 0)) 6334 6335 Instead of splitting out a new insn, we modify the current insn's 6336 operands as needed. This preserves things such as REG_DEAD notes. */ 6337 6338 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE) 6339 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG 6340 && XEXP (operands[1], 1) == const0_rtx) 6341 DONE; 6342 6343 int branch_cond = sh_eval_treg_value (operands[1]); 6344 rtx new_cond_rtx = NULL_RTX; 6345 6346 if (branch_cond == 0) 6347 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx); 6348 else if (branch_cond == 1) 6349 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx); 6350 6351 if (new_cond_rtx != NULL_RTX) 6352 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0), 6353 new_cond_rtx, false); 6354 DONE; 6355} 6356 [(set_attr "type" "cbranch")]) 6357 6358;; Patterns to prevent reorg from re-combining a condbranch with a branch 6359;; which destination is too far away. 6360;; The const_int_operand is distinct for each branch target; it avoids 6361;; unwanted matches with redundant_insn. 6362(define_insn "block_branch_redirect" 6363 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))] 6364 "TARGET_SH1" 6365 "" 6366 [(set_attr "length" "0")]) 6367 6368;; This one has the additional purpose to record a possible scratch register 6369;; for the following branch. 6370;; ??? Unfortunately, just setting the scratch register is not good enough, 6371;; because the insn then might be deemed dead and deleted. And we can't 6372;; make the use in the jump insn explicit because that would disable 6373;; delay slot scheduling from the target. 6374(define_insn "indirect_jump_scratch" 6375 [(set (match_operand:SI 0 "register_operand" "=r") 6376 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR)) 6377 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))] 6378 "TARGET_SH1" 6379 "" 6380 [(set_attr "length" "0")]) 6381 6382;; This one is used to preemt an insn from beyond the bra / braf / jmp 6383;; being pulled into the delay slot of a condbranch that has been made to 6384;; jump around the unconditional jump because it was out of range. 6385(define_insn "stuff_delay_slot" 6386 [(set (pc) 6387 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc) 6388 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))] 6389 "TARGET_SH1" 6390 "" 6391 [(set_attr "length" "0") 6392 (set_attr "cond_delay_slot" "yes")]) 6393 6394;; Conditional branch insns 6395 6396; operand 0 is the loop count pseudo register 6397; operand 1 is the label to jump to at the top of the loop 6398(define_expand "doloop_end" 6399 [(parallel [(set (pc) 6400 (if_then_else (ne:SI (match_operand:SI 0 "" "") 6401 (const_int 1)) 6402 (label_ref (match_operand 1 "" "")) 6403 (pc))) 6404 (set (match_dup 0) 6405 (plus:SI (match_dup 0) (const_int -1))) 6406 (clobber (reg:SI T_REG))])] 6407 "TARGET_SH2" 6408{ 6409 if (GET_MODE (operands[0]) != SImode) 6410 FAIL; 6411 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0])); 6412 DONE; 6413}) 6414 6415(define_insn_and_split "doloop_end_split" 6416 [(set (pc) 6417 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0") 6418 (const_int 1)) 6419 (label_ref (match_operand 1 "" "")) 6420 (pc))) 6421 (set (match_operand:SI 0 "arith_reg_dest" "=r") 6422 (plus:SI (match_dup 2) (const_int -1))) 6423 (clobber (reg:SI T_REG))] 6424 "TARGET_SH2" 6425 "#" 6426 "" 6427 [(parallel [(set (reg:SI T_REG) 6428 (eq:SI (match_dup 2) (const_int 1))) 6429 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))]) 6430 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0)) 6431 (label_ref (match_dup 1)) 6432 (pc)))] 6433 "" 6434 [(set_attr "type" "cbranch")]) 6435 6436;; ------------------------------------------------------------------------ 6437;; Jump and linkage insns 6438;; ------------------------------------------------------------------------ 6439 6440(define_insn "jump_compact" 6441 [(set (pc) 6442 (label_ref (match_operand 0 "" "")))] 6443 "TARGET_SH1 && !CROSSING_JUMP_P (insn)" 6444{ 6445 /* The length is 16 if the delay slot is unfilled. */ 6446 if (get_attr_length(insn) > 4) 6447 return output_far_jump(insn, operands[0]); 6448 else 6449 return "bra %l0%#"; 6450} 6451 [(set_attr "type" "jump") 6452 (set_attr "needs_delay_slot" "yes")]) 6453 6454(define_insn "*jump_compact_crossing" 6455 [(set (pc) 6456 (label_ref (match_operand 0 "" "")))] 6457 "TARGET_SH1 6458 && flag_reorder_blocks_and_partition 6459 && CROSSING_JUMP_P (insn)" 6460{ 6461 /* The length is 16 if the delay slot is unfilled. */ 6462 return output_far_jump(insn, operands[0]); 6463} 6464 [(set_attr "type" "jump") 6465 (set_attr "length" "16")]) 6466 6467(define_expand "jump" 6468 [(set (pc) 6469 (label_ref (match_operand 0 "" "")))] 6470 "" 6471{ 6472 emit_jump_insn (gen_jump_compact (operands[0])); 6473 DONE; 6474}) 6475 6476(define_insn "calli" 6477 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) 6478 (match_operand 1 "" "")) 6479 (use (reg:SI FPSCR_MODES_REG)) 6480 (clobber (reg:SI PR_REG))] 6481 "TARGET_SH1 && !TARGET_FDPIC" 6482{ 6483 if (TARGET_SH2A && dbr_sequence_length () == 0) 6484 return "jsr/n @%0"; 6485 else 6486 return "jsr @%0%#"; 6487} 6488 [(set_attr "type" "call") 6489 (set (attr "fp_mode") 6490 (if_then_else (eq_attr "fpu_single" "yes") 6491 (const_string "single") (const_string "double"))) 6492 (set_attr "needs_delay_slot" "yes") 6493 (set_attr "fp_set" "unknown")]) 6494 6495(define_insn "calli_fdpic" 6496 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) 6497 (match_operand 1)) 6498 (use (reg:SI FPSCR_MODES_REG)) 6499 (use (reg:SI PIC_REG)) 6500 (clobber (reg:SI PR_REG))] 6501 "TARGET_FDPIC" 6502{ 6503 if (TARGET_SH2A && dbr_sequence_length () == 0) 6504 return "jsr/n @%0"; 6505 else 6506 return "jsr @%0%#"; 6507} 6508 [(set_attr "type" "call") 6509 (set (attr "fp_mode") 6510 (if_then_else (eq_attr "fpu_single" "yes") 6511 (const_string "single") (const_string "double"))) 6512 (set_attr "needs_delay_slot" "yes") 6513 (set_attr "fp_set" "unknown")]) 6514 6515;; This is TBR relative jump instruction for SH2A architecture. 6516;; Its use is enabled by assigning an attribute "function_vector" 6517;; and the vector number to a function during its declaration. 6518(define_insn "calli_tbr_rel" 6519 [(call (mem (match_operand:SI 0 "symbol_ref_operand" "")) 6520 (match_operand 1 "" "")) 6521 (use (reg:SI FPSCR_MODES_REG)) 6522 (use (match_scratch 2)) 6523 (clobber (reg:SI PR_REG))] 6524 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])" 6525{ 6526 unsigned HOST_WIDE_INT vect_num; 6527 vect_num = sh2a_get_function_vector_number (operands[0]); 6528 operands[2] = GEN_INT (vect_num * 4); 6529 6530 return "jsr/n @@(%O2,tbr)"; 6531} 6532 [(set_attr "type" "call") 6533 (set (attr "fp_mode") 6534 (if_then_else (eq_attr "fpu_single" "yes") 6535 (const_string "single") (const_string "double"))) 6536 (set_attr "needs_delay_slot" "no") 6537 (set_attr "fp_set" "unknown")]) 6538 6539;; This is a pc-rel call, using bsrf, for use with PIC. 6540(define_insn "calli_pcrel" 6541 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r")) 6542 (match_operand 1 "" "")) 6543 (use (reg:SI FPSCR_MODES_REG)) 6544 (use (reg:SI PIC_REG)) 6545 (use (match_operand 2 "" "")) 6546 (clobber (reg:SI PR_REG))] 6547 "TARGET_SH2" 6548{ 6549 return "bsrf %0" "\n" 6550 "%O2:%#"; 6551} 6552 [(set_attr "type" "call") 6553 (set (attr "fp_mode") 6554 (if_then_else (eq_attr "fpu_single" "yes") 6555 (const_string "single") (const_string "double"))) 6556 (set_attr "needs_delay_slot" "yes") 6557 (set_attr "fp_set" "unknown")]) 6558 6559(define_insn_and_split "call_pcrel" 6560 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "")) 6561 (match_operand 1 "" "")) 6562 (use (reg:SI FPSCR_MODES_REG)) 6563 (use (reg:SI PIC_REG)) 6564 (clobber (reg:SI PR_REG)) 6565 (clobber (match_scratch:SI 2 "=&r"))] 6566 "TARGET_SH2" 6567 "#" 6568 "reload_completed" 6569 [(const_int 0)] 6570{ 6571 rtx lab = PATTERN (gen_call_site ()); 6572 6573 sh_expand_sym_label2reg (operands[2], operands[0], lab, false); 6574 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab))); 6575 DONE; 6576} 6577 [(set_attr "type" "call") 6578 (set (attr "fp_mode") 6579 (if_then_else (eq_attr "fpu_single" "yes") 6580 (const_string "single") (const_string "double"))) 6581 (set_attr "needs_delay_slot" "yes") 6582 (set_attr "fp_set" "unknown")]) 6583 6584(define_insn "call_valuei" 6585 [(set (match_operand 0 "" "=rf") 6586 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) 6587 (match_operand 2 "" ""))) 6588 (use (reg:SI FPSCR_MODES_REG)) 6589 (clobber (reg:SI PR_REG))] 6590 "TARGET_SH1 && !TARGET_FDPIC" 6591{ 6592 if (TARGET_SH2A && dbr_sequence_length () == 0) 6593 return "jsr/n @%1"; 6594 else 6595 return "jsr @%1%#"; 6596} 6597 [(set_attr "type" "call") 6598 (set (attr "fp_mode") 6599 (if_then_else (eq_attr "fpu_single" "yes") 6600 (const_string "single") (const_string "double"))) 6601 (set_attr "needs_delay_slot" "yes") 6602 (set_attr "fp_set" "unknown")]) 6603 6604(define_insn "call_valuei_fdpic" 6605 [(set (match_operand 0 "" "=rf") 6606 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) 6607 (match_operand 2))) 6608 (use (reg:SI FPSCR_REG)) 6609 (use (reg:SI PIC_REG)) 6610 (clobber (reg:SI PR_REG))] 6611 "TARGET_FDPIC" 6612{ 6613 if (TARGET_SH2A && dbr_sequence_length () == 0) 6614 return "jsr/n @%1"; 6615 else 6616 return "jsr @%1%#"; 6617} 6618 [(set_attr "type" "call") 6619 (set (attr "fp_mode") 6620 (if_then_else (eq_attr "fpu_single" "yes") 6621 (const_string "single") (const_string "double"))) 6622 (set_attr "needs_delay_slot" "yes") 6623 (set_attr "fp_set" "unknown")]) 6624 6625;; This is TBR relative jump instruction for SH2A architecture. 6626;; Its use is enabled by assigning an attribute "function_vector" 6627;; and the vector number to a function during its declaration. 6628(define_insn "call_valuei_tbr_rel" 6629 [(set (match_operand 0 "" "=rf") 6630 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "")) 6631 (match_operand 2 "" ""))) 6632 (use (reg:SI FPSCR_MODES_REG)) 6633 (use (match_scratch 3)) 6634 (clobber (reg:SI PR_REG))] 6635 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])" 6636{ 6637 unsigned HOST_WIDE_INT vect_num; 6638 vect_num = sh2a_get_function_vector_number (operands[1]); 6639 operands[3] = GEN_INT (vect_num * 4); 6640 6641 return "jsr/n @@(%O3,tbr)"; 6642} 6643 [(set_attr "type" "call") 6644 (set (attr "fp_mode") 6645 (if_then_else (eq_attr "fpu_single" "yes") 6646 (const_string "single") (const_string "double"))) 6647 (set_attr "needs_delay_slot" "no") 6648 (set_attr "fp_set" "unknown")]) 6649 6650(define_insn "call_valuei_pcrel" 6651 [(set (match_operand 0 "" "=rf") 6652 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r")) 6653 (match_operand 2 "" ""))) 6654 (use (reg:SI FPSCR_MODES_REG)) 6655 (use (reg:SI PIC_REG)) 6656 (use (match_operand 3 "" "")) 6657 (clobber (reg:SI PR_REG))] 6658 "TARGET_SH2" 6659{ 6660 return "bsrf %1" "\n" 6661 "%O3:%#"; 6662} 6663 [(set_attr "type" "call") 6664 (set (attr "fp_mode") 6665 (if_then_else (eq_attr "fpu_single" "yes") 6666 (const_string "single") (const_string "double"))) 6667 (set_attr "needs_delay_slot" "yes") 6668 (set_attr "fp_set" "unknown")]) 6669 6670(define_insn_and_split "call_value_pcrel" 6671 [(set (match_operand 0 "" "=rf") 6672 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "")) 6673 (match_operand 2 "" ""))) 6674 (use (reg:SI FPSCR_MODES_REG)) 6675 (use (reg:SI PIC_REG)) 6676 (clobber (reg:SI PR_REG)) 6677 (clobber (match_scratch:SI 3 "=&r"))] 6678 "TARGET_SH2" 6679 "#" 6680 "reload_completed" 6681 [(const_int 0)] 6682{ 6683 rtx lab = PATTERN (gen_call_site ()); 6684 6685 sh_expand_sym_label2reg (operands[3], operands[1], lab, false); 6686 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3], 6687 operands[2], copy_rtx (lab))); 6688 DONE; 6689} 6690 [(set_attr "type" "call") 6691 (set (attr "fp_mode") 6692 (if_then_else (eq_attr "fpu_single" "yes") 6693 (const_string "single") (const_string "double"))) 6694 (set_attr "needs_delay_slot" "yes") 6695 (set_attr "fp_set" "unknown")]) 6696 6697(define_expand "call" 6698 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" "")) 6699 (match_operand 1 "" "")) 6700 (match_operand 2 "" "") 6701 (use (reg:SI FPSCR_MODES_REG)) 6702 (clobber (reg:SI PR_REG))])] 6703 "" 6704{ 6705 if (TARGET_FDPIC) 6706 { 6707 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); 6708 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); 6709 } 6710 6711 if (!flag_pic && TARGET_SH2A 6712 && MEM_P (operands[0]) 6713 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 6714 { 6715 if (sh2a_is_function_vector_call (XEXP (operands[0], 0))) 6716 { 6717 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0), 6718 operands[1])); 6719 DONE; 6720 } 6721 } 6722 if (flag_pic && TARGET_SH2 6723 && MEM_P (operands[0]) 6724 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 6725 { 6726 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1])); 6727 DONE; 6728 } 6729 else 6730 { 6731 operands[0] = force_reg (SImode, XEXP (operands[0], 0)); 6732 operands[1] = operands[2]; 6733 } 6734 6735 if (TARGET_FDPIC) 6736 { 6737 operands[0] = sh_load_function_descriptor (operands[0]); 6738 emit_call_insn (gen_calli_fdpic (operands[0], operands[1])); 6739 } 6740 else 6741 emit_call_insn (gen_calli (operands[0], operands[1])); 6742 DONE; 6743}) 6744 6745(define_expand "call_value" 6746 [(parallel [(set (match_operand 0 "arith_reg_operand" "") 6747 (call (mem:SI (match_operand 1 "arith_reg_operand" "")) 6748 (match_operand 2 "" ""))) 6749 (match_operand 3 "" "") 6750 (use (reg:SI FPSCR_MODES_REG)) 6751 (clobber (reg:SI PR_REG))])] 6752 "" 6753{ 6754 if (TARGET_FDPIC) 6755 { 6756 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); 6757 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); 6758 } 6759 6760 if (!flag_pic && TARGET_SH2A 6761 && MEM_P (operands[1]) 6762 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 6763 { 6764 if (sh2a_is_function_vector_call (XEXP (operands[1], 0))) 6765 { 6766 emit_call_insn (gen_call_valuei_tbr_rel (operands[0], 6767 XEXP (operands[1], 0), operands[2])); 6768 DONE; 6769 } 6770 } 6771 if (flag_pic && TARGET_SH2 6772 && MEM_P (operands[1]) 6773 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 6774 { 6775 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0), 6776 operands[2])); 6777 DONE; 6778 } 6779 else 6780 operands[1] = force_reg (SImode, XEXP (operands[1], 0)); 6781 6782 if (TARGET_FDPIC) 6783 { 6784 operands[1] = sh_load_function_descriptor (operands[1]); 6785 emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1], 6786 operands[2])); 6787 } 6788 else 6789 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2])); 6790 DONE; 6791}) 6792 6793(define_insn "sibcalli" 6794 [(call (mem:SI (match_operand:SI 0 "register_operand" "k")) 6795 (match_operand 1 "" "")) 6796 (use (reg:SI FPSCR_MODES_REG)) 6797 (return)] 6798 "TARGET_SH1 && !TARGET_FDPIC" 6799 "jmp @%0%#" 6800 [(set_attr "needs_delay_slot" "yes") 6801 (set (attr "fp_mode") 6802 (if_then_else (eq_attr "fpu_single" "yes") 6803 (const_string "single") (const_string "double"))) 6804 (set_attr "type" "jump_ind")]) 6805 6806(define_insn "sibcalli_fdpic" 6807 [(call (mem:SI (match_operand:SI 0 "register_operand" "k")) 6808 (match_operand 1)) 6809 (use (reg:SI FPSCR_MODES_REG)) 6810 (use (reg:SI PIC_REG)) 6811 (return)] 6812 "TARGET_FDPIC" 6813 "jmp @%0%#" 6814 [(set_attr "needs_delay_slot" "yes") 6815 (set (attr "fp_mode") 6816 (if_then_else (eq_attr "fpu_single" "yes") 6817 (const_string "single") (const_string "double"))) 6818 (set_attr "type" "jump_ind")]) 6819 6820(define_insn "sibcalli_pcrel" 6821 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k")) 6822 (match_operand 1 "" "")) 6823 (use (match_operand 2 "" "")) 6824 (use (reg:SI FPSCR_MODES_REG)) 6825 (return)] 6826 "TARGET_SH2 && !TARGET_FDPIC" 6827{ 6828 return "braf %0" "\n" 6829 "%O2:%#"; 6830} 6831 [(set_attr "needs_delay_slot" "yes") 6832 (set (attr "fp_mode") 6833 (if_then_else (eq_attr "fpu_single" "yes") 6834 (const_string "single") (const_string "double"))) 6835 (set_attr "type" "jump_ind")]) 6836 6837(define_insn "sibcalli_pcrel_fdpic" 6838 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k")) 6839 (match_operand 1)) 6840 (use (match_operand 2)) 6841 (use (reg:SI FPSCR_MODES_REG)) 6842 (use (reg:SI PIC_REG)) 6843 (return)] 6844 "TARGET_SH2 && TARGET_FDPIC" 6845{ 6846 return "braf %0" "\n" 6847 "%O2:%#"; 6848} 6849 [(set_attr "needs_delay_slot" "yes") 6850 (set (attr "fp_mode") 6851 (if_then_else (eq_attr "fpu_single" "yes") 6852 (const_string "single") (const_string "double"))) 6853 (set_attr "type" "jump_ind")]) 6854 6855;; This uses an unspec to describe that the symbol_ref is very close. 6856(define_insn "sibcalli_thunk" 6857 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")] 6858 UNSPEC_THUNK)) 6859 (match_operand 1 "" "")) 6860 (use (reg:SI FPSCR_MODES_REG)) 6861 (return)] 6862 "TARGET_SH1" 6863 "bra %O0" 6864 [(set_attr "needs_delay_slot" "yes") 6865 (set (attr "fp_mode") 6866 (if_then_else (eq_attr "fpu_single" "yes") 6867 (const_string "single") (const_string "double"))) 6868 (set_attr "type" "jump") 6869 (set_attr "length" "2")]) 6870 6871(define_insn_and_split "sibcall_pcrel" 6872 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "")) 6873 (match_operand 1 "" "")) 6874 (use (reg:SI FPSCR_MODES_REG)) 6875 (clobber (match_scratch:SI 2 "=&k")) 6876 (return)] 6877 "TARGET_SH2 && !TARGET_FDPIC" 6878 "#" 6879 "reload_completed" 6880 [(const_int 0)] 6881{ 6882 rtx lab = PATTERN (gen_call_site ()); 6883 rtx call_insn; 6884 6885 sh_expand_sym_label2reg (operands[2], operands[0], lab, true); 6886 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1], 6887 copy_rtx (lab))); 6888 SIBLING_CALL_P (call_insn) = 1; 6889 DONE; 6890} 6891 [(set_attr "needs_delay_slot" "yes") 6892 (set (attr "fp_mode") 6893 (if_then_else (eq_attr "fpu_single" "yes") 6894 (const_string "single") (const_string "double"))) 6895 (set_attr "type" "jump_ind")]) 6896 6897(define_insn_and_split "sibcall_pcrel_fdpic" 6898 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand")) 6899 (match_operand 1)) 6900 (use (reg:SI FPSCR_MODES_REG)) 6901 (use (reg:SI PIC_REG)) 6902 (clobber (match_scratch:SI 2 "=k")) 6903 (return)] 6904 "TARGET_SH2 && TARGET_FDPIC" 6905 "#" 6906 "&& reload_completed" 6907 [(const_int 0)] 6908{ 6909 rtx lab = PATTERN (gen_call_site ()); 6910 6911 sh_expand_sym_label2reg (operands[2], operands[0], lab, true); 6912 rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1], 6913 copy_rtx (lab))); 6914 SIBLING_CALL_P (i) = 1; 6915 DONE; 6916} 6917 [(set_attr "needs_delay_slot" "yes") 6918 (set (attr "fp_mode") 6919 (if_then_else (eq_attr "fpu_single" "yes") 6920 (const_string "single") (const_string "double"))) 6921 (set_attr "type" "jump_ind")]) 6922 6923(define_expand "sibcall" 6924 [(parallel 6925 [(call (mem:SI (match_operand 0 "arith_reg_operand" "")) 6926 (match_operand 1 "" "")) 6927 (match_operand 2 "" "") 6928 (use (reg:SI FPSCR_MODES_REG)) 6929 (return)])] 6930 "" 6931{ 6932 if (TARGET_FDPIC) 6933 { 6934 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); 6935 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); 6936 } 6937 6938 if (flag_pic && TARGET_SH2 6939 && MEM_P (operands[0]) 6940 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF 6941 /* The PLT needs the PIC register, but the epilogue would have 6942 to restore it, so we can only use PC-relative PIC calls for 6943 static functions. */ 6944 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0))) 6945 { 6946 if (TARGET_FDPIC) 6947 emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0), 6948 operands[1])); 6949 else 6950 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1])); 6951 DONE; 6952 } 6953 else 6954 operands[0] = force_reg (SImode, XEXP (operands[0], 0)); 6955 6956 if (TARGET_FDPIC) 6957 { 6958 operands[0] = sh_load_function_descriptor (operands[0]); 6959 emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1])); 6960 } 6961 else 6962 emit_call_insn (gen_sibcalli (operands[0], operands[1])); 6963 DONE; 6964}) 6965 6966(define_insn "sibcall_valuei" 6967 [(set (match_operand 0 "" "=rf") 6968 (call (mem:SI (match_operand:SI 1 "register_operand" "k")) 6969 (match_operand 2 "" ""))) 6970 (use (reg:SI FPSCR_MODES_REG)) 6971 (return)] 6972 "TARGET_SH1 && !TARGET_FDPIC" 6973 "jmp @%1%#" 6974 [(set_attr "needs_delay_slot" "yes") 6975 (set (attr "fp_mode") 6976 (if_then_else (eq_attr "fpu_single" "yes") 6977 (const_string "single") (const_string "double"))) 6978 (set_attr "type" "jump_ind")]) 6979 6980(define_insn "sibcall_valuei_fdpic" 6981 [(set (match_operand 0 "" "=rf") 6982 (call (mem:SI (match_operand:SI 1 "register_operand" "k")) 6983 (match_operand 2))) 6984 (use (reg:SI FPSCR_MODES_REG)) 6985 (use (reg:SI PIC_REG)) 6986 (return)] 6987 "TARGET_FDPIC" 6988 "jmp @%1%#" 6989 [(set_attr "needs_delay_slot" "yes") 6990 (set (attr "fp_mode") 6991 (if_then_else (eq_attr "fpu_single" "yes") 6992 (const_string "single") (const_string "double"))) 6993 (set_attr "type" "jump_ind")]) 6994 6995(define_insn "sibcall_valuei_pcrel" 6996 [(set (match_operand 0 "" "=rf") 6997 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k")) 6998 (match_operand 2 "" ""))) 6999 (use (match_operand 3 "" "")) 7000 (use (reg:SI FPSCR_MODES_REG)) 7001 (return)] 7002 "TARGET_SH2 && !TARGET_FDPIC" 7003{ 7004 return "braf %1" "\n" 7005 "%O3:%#"; 7006} 7007 [(set_attr "needs_delay_slot" "yes") 7008 (set (attr "fp_mode") 7009 (if_then_else (eq_attr "fpu_single" "yes") 7010 (const_string "single") (const_string "double"))) 7011 (set_attr "type" "jump_ind")]) 7012 7013(define_insn "sibcall_valuei_pcrel_fdpic" 7014 [(set (match_operand 0 "" "=rf") 7015 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k")) 7016 (match_operand 2))) 7017 (use (match_operand 3)) 7018 (use (reg:SI FPSCR_MODES_REG)) 7019 (use (reg:SI PIC_REG)) 7020 (return)] 7021 "TARGET_SH2 && TARGET_FDPIC" 7022{ 7023 return "braf %1" "\n" 7024 "%O3:%#"; 7025} 7026 [(set_attr "needs_delay_slot" "yes") 7027 (set (attr "fp_mode") 7028 (if_then_else (eq_attr "fpu_single" "yes") 7029 (const_string "single") (const_string "double"))) 7030 (set_attr "type" "jump_ind")]) 7031 7032;; sibcall_value_pcrel used to have a =&k clobber for the scratch register 7033;; that it needs for the branch address. This causes troubles when there 7034;; is a big overlap of argument and return value registers. Hence, use a 7035;; fixed call clobbered register for the address. See also PR 67260. 7036(define_insn_and_split "sibcall_value_pcrel" 7037 [(set (match_operand 0 "" "=rf") 7038 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "")) 7039 (match_operand 2 "" ""))) 7040 (use (reg:SI FPSCR_MODES_REG)) 7041 (clobber (reg:SI R1_REG)) 7042 (return)] 7043 "TARGET_SH2 && !TARGET_FDPIC" 7044 "#" 7045 "reload_completed" 7046 [(const_int 0)] 7047{ 7048 rtx lab = PATTERN (gen_call_site ()); 7049 rtx tmp = gen_rtx_REG (SImode, R1_REG); 7050 7051 sh_expand_sym_label2reg (tmp, operands[1], lab, true); 7052 rtx call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0], 7053 tmp, 7054 operands[2], 7055 copy_rtx (lab))); 7056 SIBLING_CALL_P (call_insn) = 1; 7057 DONE; 7058} 7059 [(set_attr "needs_delay_slot" "yes") 7060 (set (attr "fp_mode") 7061 (if_then_else (eq_attr "fpu_single" "yes") 7062 (const_string "single") (const_string "double"))) 7063 (set_attr "type" "jump_ind")]) 7064 7065;; Like for sibcall_value_pcrel, use a fixed call clobbered register for 7066;; the branch address. 7067(define_insn_and_split "sibcall_value_pcrel_fdpic" 7068 [(set (match_operand 0 "" "=rf") 7069 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand")) 7070 (match_operand 2))) 7071 (use (reg:SI FPSCR_MODES_REG)) 7072 (use (reg:SI PIC_REG)) 7073 (clobber (reg:SI R1_REG)) 7074 (return)] 7075 "TARGET_SH2 && TARGET_FDPIC" 7076 "#" 7077 "&& reload_completed" 7078 [(const_int 0)] 7079{ 7080 rtx lab = PATTERN (gen_call_site ()); 7081 rtx tmp = gen_rtx_REG (SImode, R1_REG); 7082 7083 sh_expand_sym_label2reg (tmp, operands[1], lab, true); 7084 rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0], 7085 tmp, 7086 operands[2], 7087 copy_rtx (lab))); 7088 SIBLING_CALL_P (i) = 1; 7089 DONE; 7090} 7091 [(set_attr "needs_delay_slot" "yes") 7092 (set (attr "fp_mode") 7093 (if_then_else (eq_attr "fpu_single" "yes") 7094 (const_string "single") (const_string "double"))) 7095 (set_attr "type" "jump_ind")]) 7096 7097(define_expand "sibcall_value" 7098 [(parallel 7099 [(set (match_operand 0 "arith_reg_operand" "") 7100 (call (mem:SI (match_operand 1 "arith_reg_operand" "")) 7101 (match_operand 2 "" ""))) 7102 (match_operand 3 "" "") 7103 (use (reg:SI FPSCR_MODES_REG)) 7104 (return)])] 7105 "" 7106{ 7107 if (TARGET_FDPIC) 7108 { 7109 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); 7110 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); 7111 } 7112 7113 if (flag_pic && TARGET_SH2 7114 && MEM_P (operands[1]) 7115 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF 7116 /* The PLT needs the PIC register, but the epilogue would have 7117 to restore it, so we can only use PC-relative PIC calls for 7118 static functions. */ 7119 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0))) 7120 { 7121 if (TARGET_FDPIC) 7122 emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0], 7123 XEXP (operands[1], 0), 7124 operands[2])); 7125 else 7126 emit_call_insn (gen_sibcall_value_pcrel (operands[0], 7127 XEXP (operands[1], 0), 7128 operands[2])); 7129 DONE; 7130 } 7131 else 7132 operands[1] = force_reg (SImode, XEXP (operands[1], 0)); 7133 7134 if (TARGET_FDPIC) 7135 { 7136 operands[1] = sh_load_function_descriptor (operands[1]); 7137 emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1], 7138 operands[2])); 7139 } 7140 else 7141 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2])); 7142 DONE; 7143}) 7144 7145(define_expand "sibcall_epilogue" 7146 [(return)] 7147 "" 7148{ 7149 sh_expand_epilogue (true); 7150 DONE; 7151}) 7152 7153(define_insn "indirect_jump_compact" 7154 [(set (pc) 7155 (match_operand:SI 0 "arith_reg_operand" "r"))] 7156 "TARGET_SH1" 7157 "jmp @%0%#" 7158 [(set_attr "needs_delay_slot" "yes") 7159 (set_attr "type" "jump_ind")]) 7160 7161(define_expand "indirect_jump" 7162 [(set (pc) 7163 (match_operand 0 "register_operand" ""))] 7164 "" 7165{ 7166 if (GET_MODE (operands[0]) != Pmode) 7167 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0); 7168}) 7169 7170;; The use of operand 1 / 2 helps us distinguish case table jumps 7171;; which can be present in structured code from indirect jumps which can not 7172;; be present in structured code. This allows -fprofile-arcs to work. 7173 7174;; For SH1 processors. 7175(define_insn "casesi_jump_1" 7176 [(set (pc) 7177 (match_operand:SI 0 "register_operand" "r")) 7178 (use (label_ref (match_operand 1 "" "")))] 7179 "TARGET_SH1" 7180 "jmp @%0%#" 7181 [(set_attr "needs_delay_slot" "yes") 7182 (set_attr "type" "jump_ind")]) 7183 7184;; For all later processors. 7185(define_insn "casesi_jump_2" 7186 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r") 7187 (label_ref (match_operand 1 "" "")))) 7188 (use (label_ref (match_operand 2 "" "")))] 7189 "TARGET_SH2 7190 && (! INSN_UID (operands[1]) 7191 || prev_real_insn (as_a<rtx_insn *> (operands[1])) == insn)" 7192 "braf %0%#" 7193 [(set_attr "needs_delay_slot" "yes") 7194 (set_attr "type" "jump_ind")]) 7195 7196;; Call subroutine returning any type. 7197;; ??? This probably doesn't work. 7198(define_expand "untyped_call" 7199 [(parallel [(call (match_operand 0 "" "") 7200 (const_int 0)) 7201 (match_operand 1 "" "") 7202 (match_operand 2 "" "")])] 7203 "TARGET_SH2E || TARGET_SH2A" 7204{ 7205 /* RA does not know that the call sets the function value registers. 7206 We avoid problems by claiming that those registers are clobbered 7207 at this point. */ 7208 for (int i = 0; i < XVECLEN (operands[2], 0); i++) 7209 emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i))); 7210 7211 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); 7212 7213 for (int i = 0; i < XVECLEN (operands[2], 0); i++) 7214 { 7215 rtx set = XVECEXP (operands[2], 0, i); 7216 emit_move_insn (SET_DEST (set), SET_SRC (set)); 7217 } 7218 7219 /* The optimizer does not know that the call sets the function value 7220 registers we stored in the result block. We avoid problems by 7221 claiming that all hard registers are used and clobbered at this 7222 point. */ 7223 emit_insn (gen_blockage ()); 7224 7225 DONE; 7226}) 7227 7228;; ------------------------------------------------------------------------ 7229;; Misc insns 7230;; ------------------------------------------------------------------------ 7231 7232(define_insn "dect" 7233 [(set (reg:SI T_REG) 7234 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1))) 7235 (set (match_operand:SI 0 "arith_reg_dest" "=r") 7236 (plus:SI (match_dup 1) (const_int -1)))] 7237 "TARGET_SH2" 7238 "dt %0" 7239 [(set_attr "type" "arith")]) 7240 7241(define_insn "nop" 7242 [(const_int 0)] 7243 "" 7244 "nop") 7245 7246;; Load address of a label. This is only generated by the casesi expand, 7247;; and by machine_dependent_reorg (fixing up fp moves). 7248;; This must use unspec, because this only works for labels that are 7249;; within range. 7250(define_insn "mova" 7251 [(set (reg:SI R0_REG) 7252 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))] 7253 "TARGET_SH1" 7254 "mova %O0,r0" 7255 [(set_attr "in_delay_slot" "no") 7256 (set_attr "type" "arith")]) 7257 7258;; machine_dependent_reorg will make this a `mova'. 7259(define_insn "mova_const" 7260 [(set (reg:SI R0_REG) 7261 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))] 7262 "TARGET_SH1" 7263 "#" 7264 [(set_attr "in_delay_slot" "no") 7265 (set_attr "type" "arith")]) 7266 7267;; Loads of the GOTPC relocation values must not be optimized away 7268;; by e.g. any kind of CSE and must stay as they are. Although there 7269;; are other various ways to ensure this, we use an artificial counter 7270;; operand to generate unique symbols. 7271(define_expand "GOTaddr2picreg" 7272 [(set (reg:SI R0_REG) 7273 (unspec:SI [(const:SI (unspec:SI [(match_dup 2) 7274 (match_operand:SI 0 "" "")] 7275 UNSPEC_PIC))] UNSPEC_MOVA)) 7276 (set (match_dup 1) 7277 (const:SI (unspec:SI [(match_dup 2) (match_dup 0)] UNSPEC_PIC))) 7278 (set (match_dup 1) (plus:SI (match_dup 1) (reg:SI R0_REG)))] 7279 "" 7280{ 7281 if (TARGET_VXWORKS_RTP) 7282 { 7283 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE); 7284 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX); 7285 emit_insn (gen_vxworks_picreg (gott_base, gott_index)); 7286 DONE; 7287 } 7288 7289 if (TARGET_FDPIC) 7290 { 7291 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG); 7292 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ()); 7293 DONE; 7294 } 7295 7296 operands[1] = gen_rtx_REG (Pmode, PIC_REG); 7297 operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); 7298}) 7299 7300;; A helper for GOTaddr2picreg to finish up the initialization of the 7301;; PIC register. 7302(define_expand "vxworks_picreg" 7303 [(set (reg:SI PIC_REG) 7304 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC))) 7305 (set (reg:SI R0_REG) 7306 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC))) 7307 (set (reg:SI PIC_REG) 7308 (mem:SI (reg:SI PIC_REG))) 7309 (set (reg:SI PIC_REG) 7310 (mem:SI (plus:SI (reg:SI PIC_REG) 7311 (reg:SI R0_REG))))] 7312 "TARGET_VXWORKS_RTP") 7313 7314(define_expand "builtin_setjmp_receiver" 7315 [(match_operand 0 "" "")] 7316 "flag_pic" 7317{ 7318 emit_insn (gen_GOTaddr2picreg (const0_rtx)); 7319 DONE; 7320}) 7321 7322(define_expand "call_site" 7323 [(unspec [(match_dup 0)] UNSPEC_CALLER)] 7324 "TARGET_SH1" 7325{ 7326 static HOST_WIDE_INT i = 0; 7327 operands[0] = GEN_INT (i); 7328 i++; 7329}) 7330 7331;; op0 = op1 + r12 but hide it before reload completed. See the comment 7332;; in symGOT_load expand. 7333(define_insn_and_split "chk_guard_add" 7334 [(set (match_operand:SI 0 "register_operand" "=&r") 7335 (unspec:SI [(match_operand:SI 1 "register_operand" "r") 7336 (reg:SI PIC_REG)] 7337 UNSPEC_CHKADD))] 7338 "TARGET_SH1" 7339 "#" 7340 "TARGET_SH1 && reload_completed" 7341 [(set (match_dup 0) (reg:SI PIC_REG)) 7342 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))] 7343 "" 7344 [(set_attr "type" "arith")]) 7345 7346(define_expand "sym_label2reg" 7347 [(set (match_operand:SI 0 "" "") 7348 (const:SI (unspec:SI [(match_operand:SI 1 "" "") 7349 (const (plus:SI (match_operand:SI 2 "" "") 7350 (const_int 2)))] 7351 UNSPEC_SYMOFF)))] 7352 "TARGET_SH1" "") 7353 7354(define_expand "symPCREL_label2reg" 7355 [(set (match_operand:SI 0 "" "") 7356 (const:SI 7357 (unspec:SI 7358 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL)) 7359 (const:SI (plus:SI (match_operand:SI 2 "" "") 7360 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))] 7361 "TARGET_SH1" 7362 "") 7363 7364(define_expand "symGOT_load" 7365 [(set (match_dup 2) (match_operand 1 "" "")) 7366 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG))) 7367 (set (match_operand 0 "" "") (mem (match_dup 3)))] 7368 "" 7369{ 7370 rtx mem; 7371 bool stack_chk_guard_p = false; 7372 7373 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val () 7374 : gen_rtx_REG (Pmode, PIC_REG); 7375 7376 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); 7377 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); 7378 7379 if (!TARGET_FDPIC 7380 && flag_stack_protect 7381 && GET_CODE (operands[1]) == CONST 7382 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC 7383 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF 7384 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0), 7385 "__stack_chk_guard") == 0) 7386 stack_chk_guard_p = true; 7387 7388 emit_move_insn (operands[2], operands[1]); 7389 7390 /* When stack protector inserts codes after the result is set to 7391 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec 7392 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A)) 7393 when rX is a GOT address for the guard symbol. Ugly but doesn't 7394 matter because this is a rare situation. */ 7395 if (stack_chk_guard_p) 7396 emit_insn (gen_chk_guard_add (operands[3], operands[2])); 7397 else 7398 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg)); 7399 7400 /* N.B. This is not constant for a GOTPLT relocation. */ 7401 mem = gen_rtx_MEM (Pmode, operands[3]); 7402 MEM_NOTRAP_P (mem) = 1; 7403 /* ??? Should we have a special alias set for the GOT? */ 7404 emit_move_insn (operands[0], mem); 7405 7406 DONE; 7407}) 7408 7409(define_expand "sym2GOT" 7410 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))] 7411 "" 7412 "") 7413 7414(define_expand "symGOT2reg" 7415 [(match_operand 0 "" "") (match_operand 1 "" "")] 7416 "" 7417{ 7418 rtx gotsym, insn; 7419 7420 gotsym = gen_sym2GOT (operands[1]); 7421 PUT_MODE (gotsym, Pmode); 7422 insn = emit_insn (gen_symGOT_load (operands[0], gotsym)); 7423 7424 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1; 7425 7426 DONE; 7427}) 7428 7429(define_expand "sym2GOTFUNCDESC" 7430 [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))] 7431 "TARGET_FDPIC") 7432 7433(define_expand "symGOTFUNCDESC2reg" 7434 [(match_operand 0) (match_operand 1)] 7435 "TARGET_FDPIC" 7436{ 7437 rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]); 7438 PUT_MODE (gotsym, Pmode); 7439 rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym)); 7440 7441 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1; 7442 7443 DONE; 7444}) 7445 7446(define_expand "symGOTPLT2reg" 7447 [(match_operand 0 "" "") (match_operand 1 "" "")] 7448 "" 7449{ 7450 rtx pltsym = gen_rtx_CONST (Pmode, 7451 gen_rtx_UNSPEC (Pmode, 7452 gen_rtvec (1, operands[1]), 7453 UNSPEC_GOTPLT)); 7454 emit_insn (gen_symGOT_load (operands[0], pltsym)); 7455 DONE; 7456}) 7457 7458(define_expand "sym2GOTOFF" 7459 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))] 7460 "" 7461 "") 7462 7463(define_expand "symGOTOFF2reg" 7464 [(match_operand 0 "" "") (match_operand 1 "" "")] 7465 "" 7466{ 7467 rtx gotoffsym; 7468 rtx t = (!can_create_pseudo_p () 7469 ? operands[0] 7470 : gen_reg_rtx (GET_MODE (operands[0]))); 7471 7472 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val () 7473 : gen_rtx_REG (Pmode, PIC_REG); 7474 7475 gotoffsym = gen_sym2GOTOFF (operands[1]); 7476 PUT_MODE (gotoffsym, Pmode); 7477 emit_move_insn (t, gotoffsym); 7478 rtx_insn *insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg)); 7479 7480 set_unique_reg_note (insn, REG_EQUAL, operands[1]); 7481 7482 DONE; 7483}) 7484 7485(define_expand "sym2GOTOFFFUNCDESC" 7486 [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))] 7487 "TARGET_FDPIC") 7488 7489(define_expand "symGOTOFFFUNCDESC2reg" 7490 [(match_operand 0) (match_operand 1)] 7491 "TARGET_FDPIC" 7492{ 7493 rtx picreg = sh_get_fdpic_reg_initial_val (); 7494 rtx t = !can_create_pseudo_p () 7495 ? operands[0] 7496 : gen_reg_rtx (GET_MODE (operands[0])); 7497 7498 rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]); 7499 PUT_MODE (gotoffsym, Pmode); 7500 emit_move_insn (t, gotoffsym); 7501 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg)); 7502 DONE; 7503}) 7504 7505(define_expand "symPLT_label2reg" 7506 [(set (match_operand:SI 0 "" "") 7507 (const:SI 7508 (unspec:SI 7509 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT)) 7510 (const:SI (plus:SI (match_operand:SI 2 "" "") 7511 (const_int 2)))] UNSPEC_PCREL_SYMOFF))) 7512 ;; Even though the PIC register is not really used by the call 7513 ;; sequence in which this is expanded, the PLT code assumes the PIC 7514 ;; register is set, so we must not skip its initialization. Since 7515 ;; we only use this expand as part of calling sequences, and never 7516 ;; to take the address of a function, this is the best point to 7517 ;; insert the (use). Using the PLT to take the address of a 7518 ;; function would be wrong, not only because the PLT entry could 7519 ;; then be called from a function that doesn't initialize the PIC 7520 ;; register to the proper GOT, but also because pointers to the 7521 ;; same function might not compare equal, should they be set by 7522 ;; different shared libraries. 7523 (use (reg:SI PIC_REG))] 7524 "TARGET_SH1" 7525 "") 7526 7527(define_expand "sym2PIC" 7528 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))] 7529 "" 7530 "") 7531 7532;; ------------------------------------------------------------------------- 7533;; TLS code generation. 7534 7535;; FIXME: The multi-insn asm blocks should be converted to use 7536;; define_insn_and_split. 7537;; See the thread [PATCH/RFA] SH TLS support on gcc-patches 7538;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html> 7539;; for details. 7540 7541(define_insn "tls_global_dynamic" 7542 [(set (match_operand:SI 0 "register_operand" "=&z") 7543 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")] 7544 UNSPEC_TLSGD)) 7545 (const_int 0))) 7546 (use (reg:SI FPSCR_MODES_REG)) 7547 (use (reg:SI PIC_REG)) 7548 (clobber (reg:SI PR_REG)) 7549 (clobber (scratch:SI))] 7550 "TARGET_SH1" 7551{ 7552 return "mov.l 1f,r4" "\n" 7553 " mova 2f,r0" "\n" 7554 " mov.l 2f,r1" "\n" 7555 " add r0,r1" "\n" 7556 " jsr @r1" "\n" 7557 " add r12,r4" "\n" 7558 " bra 3f" "\n" 7559 " nop" "\n" 7560 " .align 2" "\n" 7561 "1: .long %a1@TLSGD" "\n" 7562 "2: .long __tls_get_addr@PLT" "\n" 7563 "3:"; 7564} 7565 [(set_attr "type" "tls_load") 7566 (set_attr "length" "26")]) 7567 7568(define_insn "tls_local_dynamic" 7569 [(set (match_operand:SI 0 "register_operand" "=&z") 7570 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")] 7571 UNSPEC_TLSLDM)) 7572 (const_int 0))) 7573 (use (reg:SI FPSCR_MODES_REG)) 7574 (use (reg:SI PIC_REG)) 7575 (clobber (reg:SI PR_REG)) 7576 (clobber (scratch:SI))] 7577 "TARGET_SH1" 7578{ 7579 return "mov.l 1f,r4" "\n" 7580 " mova 2f,r0" "\n" 7581 " mov.l 2f,r1" "\n" 7582 " add r0,r1" "\n" 7583 " jsr @r1" "\n" 7584 " add r12,r4" "\n" 7585 " bra 3f" "\n" 7586 " nop" "\n" 7587 " .align 2" "\n" 7588 "1: .long %a1@TLSLDM" "\n" 7589 "2: .long __tls_get_addr@PLT" "\n" 7590 "3:"; 7591} 7592 [(set_attr "type" "tls_load") 7593 (set_attr "length" "26")]) 7594 7595(define_expand "sym2DTPOFF" 7596 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))] 7597 "" 7598 "") 7599 7600(define_expand "symDTPOFF2reg" 7601 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")] 7602 "" 7603{ 7604 rtx dtpoffsym; 7605 rtx t = (!can_create_pseudo_p () 7606 ? operands[0] 7607 : gen_reg_rtx (GET_MODE (operands[0]))); 7608 7609 dtpoffsym = gen_sym2DTPOFF (operands[1]); 7610 PUT_MODE (dtpoffsym, Pmode); 7611 emit_move_insn (t, dtpoffsym); 7612 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2])); 7613 DONE; 7614}) 7615 7616(define_expand "sym2GOTTPOFF" 7617 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))] 7618 "" 7619 "") 7620 7621(define_insn "tls_initial_exec" 7622 [(set (match_operand:SI 0 "register_operand" "=&r") 7623 (unspec:SI [(match_operand:SI 1 "" "")] 7624 UNSPEC_TLSIE)) 7625 (use (reg:SI GBR_REG)) 7626 (use (reg:SI PIC_REG)) 7627 (clobber (reg:SI R0_REG))] 7628 "" 7629{ 7630 return "mov.l 1f,r0" "\n" 7631 " stc gbr,%0" "\n" 7632 " mov.l @(r0,r12),r0" "\n" 7633 " bra 2f" "\n" 7634 " add r0,%0" "\n" 7635 " .align 2" "\n" 7636 "1: .long %a1" "\n" 7637 "2:"; 7638} 7639 [(set_attr "type" "tls_load") 7640 (set_attr "length" "16")]) 7641 7642(define_expand "sym2TPOFF" 7643 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))] 7644 "" 7645 "") 7646 7647(define_expand "symTPOFF2reg" 7648 [(match_operand 0 "" "") (match_operand 1 "" "")] 7649 "" 7650{ 7651 rtx tpoffsym; 7652 7653 tpoffsym = gen_sym2TPOFF (operands[1]); 7654 PUT_MODE (tpoffsym, Pmode); 7655 emit_move_insn (operands[0], tpoffsym); 7656 DONE; 7657}) 7658 7659;;------------------------------------------------------------------------------ 7660;; Thread pointer getter and setter. 7661;; 7662;; On SH the thread pointer is kept in the GBR. 7663;; These patterns are usually expanded from the respective built-in functions. 7664(define_expand "get_thread_pointersi" 7665 [(set (match_operand:SI 0 "arith_reg_dest") (reg:SI GBR_REG))] 7666 "TARGET_SH1") 7667 7668;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses. 7669(define_insn "store_gbr" 7670 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (reg:SI GBR_REG))] 7671 "" 7672 "stc gbr,%0" 7673 [(set_attr "type" "tls_load")]) 7674 7675(define_expand "set_thread_pointersi" 7676 [(set (reg:SI GBR_REG) 7677 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand")] 7678 UNSPECV_GBR))] 7679 "TARGET_SH1") 7680 7681(define_insn "load_gbr" 7682 [(set (reg:SI GBR_REG) 7683 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand" "r")] 7684 UNSPECV_GBR))] 7685 "TARGET_SH1" 7686 "ldc %0,gbr" 7687 [(set_attr "type" "move")]) 7688 7689;;------------------------------------------------------------------------------ 7690;; Thread pointer relative memory loads and stores. 7691;; 7692;; On SH there are GBR displacement address modes which can be utilized to 7693;; access memory behind the thread pointer. 7694;; Since we do not allow using GBR for general purpose memory accesses, these 7695;; GBR addressing modes are formed by the combine pass. 7696;; This could be done with fewer patterns than below by using a mem predicate 7697;; for the GBR mem, but then reload would try to reload addresses with a 7698;; zero displacement for some strange reason. 7699 7700(define_insn "*mov<mode>_gbr_load" 7701 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z") 7702 (mem:QIHISI (plus:SI (reg:SI GBR_REG) 7703 (match_operand:QIHISI 1 "gbr_displacement"))))] 7704 "TARGET_SH1" 7705 "mov.<bwl> @(%O1,gbr),%0" 7706 [(set_attr "type" "load")]) 7707 7708(define_insn "*mov<mode>_gbr_load" 7709 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z") 7710 (mem:QIHISI (reg:SI GBR_REG)))] 7711 "TARGET_SH1" 7712 "mov.<bwl> @(0,gbr),%0" 7713 [(set_attr "type" "load")]) 7714 7715(define_insn "*mov<mode>_gbr_load" 7716 [(set (match_operand:SI 0 "arith_reg_dest" "=z") 7717 (sign_extend:SI 7718 (mem:QIHI (plus:SI (reg:SI GBR_REG) 7719 (match_operand:QIHI 1 "gbr_displacement")))))] 7720 "TARGET_SH1" 7721 "mov.<bw> @(%O1,gbr),%0" 7722 [(set_attr "type" "load")]) 7723 7724(define_insn "*mov<mode>_gbr_load" 7725 [(set (match_operand:SI 0 "arith_reg_dest" "=z") 7726 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))] 7727 "TARGET_SH1" 7728 "mov.<bw> @(0,gbr),%0" 7729 [(set_attr "type" "load")]) 7730 7731(define_insn "*mov<mode>_gbr_store" 7732 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG) 7733 (match_operand:QIHISI 0 "gbr_displacement"))) 7734 (match_operand:QIHISI 1 "register_operand" "z"))] 7735 "TARGET_SH1" 7736 "mov.<bwl> %1,@(%O0,gbr)" 7737 [(set_attr "type" "store")]) 7738 7739(define_insn "*mov<mode>_gbr_store" 7740 [(set (mem:QIHISI (reg:SI GBR_REG)) 7741 (match_operand:QIHISI 0 "register_operand" "z"))] 7742 "TARGET_SH1" 7743 "mov.<bwl> %0,@(0,gbr)" 7744 [(set_attr "type" "store")]) 7745 7746;; DImode memory accesses have to be split in two SImode accesses. 7747;; Split them before reload, so that it gets a better chance to figure out 7748;; how to deal with the R0 restriction for the individual SImode accesses. 7749;; Do not match this insn during or after reload because it can't be split 7750;; afterwards. 7751(define_insn_and_split "*movdi_gbr_load" 7752 [(set (match_operand:DI 0 "arith_reg_dest") 7753 (match_operand:DI 1 "gbr_address_mem"))] 7754 "TARGET_SH1 && can_create_pseudo_p ()" 7755 "#" 7756 "&& 1" 7757 [(set (match_dup 3) (match_dup 5)) 7758 (set (match_dup 4) (match_dup 6))] 7759{ 7760 /* Swap low/high part load order on little endian, so that the result reg 7761 of the second load can be used better. */ 7762 int off = TARGET_LITTLE_ENDIAN ? 1 : 0; 7763 operands[3 + off] = gen_lowpart (SImode, operands[0]); 7764 operands[5 + off] = gen_lowpart (SImode, operands[1]); 7765 operands[4 - off] = gen_highpart (SImode, operands[0]); 7766 operands[6 - off] = gen_highpart (SImode, operands[1]); 7767}) 7768 7769(define_insn_and_split "*movdi_gbr_store" 7770 [(set (match_operand:DI 0 "gbr_address_mem") 7771 (match_operand:DI 1 "register_operand"))] 7772 "TARGET_SH1 && can_create_pseudo_p ()" 7773 "#" 7774 "&& 1" 7775 [(set (match_dup 3) (match_dup 5)) 7776 (set (match_dup 4) (match_dup 6))] 7777{ 7778 /* Swap low/high part store order on big endian, so that stores of function 7779 call results can save a reg copy. */ 7780 int off = TARGET_LITTLE_ENDIAN ? 0 : 1; 7781 operands[3 + off] = gen_lowpart (SImode, operands[0]); 7782 operands[5 + off] = gen_lowpart (SImode, operands[1]); 7783 operands[4 - off] = gen_highpart (SImode, operands[0]); 7784 operands[6 - off] = gen_highpart (SImode, operands[1]); 7785}) 7786 7787;; Sometimes memory accesses do not get combined with the store_gbr insn, 7788;; in particular when the displacements are in the range of the regular move 7789;; insns. Thus, in the first split pass after the combine pass we search 7790;; for missed opportunities and try to fix them up ourselves. 7791;; If an equivalent GBR address can be determined the load / store is split 7792;; into one of the GBR load / store patterns. 7793;; All of that must happen before reload (GBR address modes use R0 as the 7794;; other operand) and there's no point of doing it if the GBR is not 7795;; referenced in a function at all. 7796(define_split 7797 [(set (match_operand:QIHISIDI 0 "register_operand") 7798 (match_operand:QIHISIDI 1 "memory_operand"))] 7799 "TARGET_SH1 && !reload_in_progress && !reload_completed 7800 && df_regs_ever_live_p (GBR_REG)" 7801 [(set (match_dup 0) (match_dup 1))] 7802{ 7803 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]); 7804 if (gbr_mem != NULL_RTX) 7805 operands[1] = replace_equiv_address (operands[1], gbr_mem); 7806 else 7807 FAIL; 7808}) 7809 7810(define_split 7811 [(set (match_operand:SI 0 "register_operand") 7812 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))] 7813 "TARGET_SH1 && !reload_in_progress && !reload_completed 7814 && df_regs_ever_live_p (GBR_REG)" 7815 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))] 7816{ 7817 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]); 7818 if (gbr_mem != NULL_RTX) 7819 operands[1] = replace_equiv_address (operands[1], gbr_mem); 7820 else 7821 FAIL; 7822}) 7823 7824;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads. 7825;; Split those so that a GBR load can be used. 7826(define_split 7827 [(set (match_operand:SI 0 "register_operand") 7828 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))] 7829 "TARGET_SH2A && !reload_in_progress && !reload_completed 7830 && df_regs_ever_live_p (GBR_REG)" 7831 [(set (match_dup 2) (match_dup 1)) 7832 (set (match_dup 0) (zero_extend:SI (match_dup 2)))] 7833{ 7834 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]); 7835 if (gbr_mem != NULL_RTX) 7836 { 7837 operands[2] = gen_reg_rtx (GET_MODE (operands[1])); 7838 operands[1] = replace_equiv_address (operands[1], gbr_mem); 7839 } 7840 else 7841 FAIL; 7842}) 7843 7844(define_split 7845 [(set (match_operand:QIHISIDI 0 "memory_operand") 7846 (match_operand:QIHISIDI 1 "register_operand"))] 7847 "TARGET_SH1 && !reload_in_progress && !reload_completed 7848 && df_regs_ever_live_p (GBR_REG)" 7849 [(set (match_dup 0) (match_dup 1))] 7850{ 7851 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]); 7852 if (gbr_mem != NULL_RTX) 7853 operands[0] = replace_equiv_address (operands[0], gbr_mem); 7854 else 7855 FAIL; 7856}) 7857 7858;;------------------------------------------------------------------------------ 7859;; case instruction for switch statements. 7860 7861;; operand 0 is index 7862;; operand 1 is the minimum bound 7863;; operand 2 is the maximum bound - minimum bound + 1 7864;; operand 3 is CODE_LABEL for the table; 7865;; operand 4 is the CODE_LABEL to go to if index out of range. 7866(define_expand "casesi" 7867 [(match_operand:SI 0 "arith_reg_operand" "") 7868 (match_operand:SI 1 "arith_reg_operand" "") 7869 (match_operand:SI 2 "arith_reg_operand" "") 7870 (match_operand 3 "" "") (match_operand 4 "" "")] 7871 "" 7872{ 7873 rtx reg = gen_reg_rtx (SImode); 7874 rtx reg2 = gen_reg_rtx (SImode); 7875 7876 operands[1] = copy_to_mode_reg (SImode, operands[1]); 7877 operands[2] = copy_to_mode_reg (SImode, operands[2]); 7878 /* If optimizing, casesi_worker depends on the mode of the instruction 7879 before label it 'uses' - operands[3]. */ 7880 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4], 7881 reg)); 7882 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3])); 7883 if (TARGET_SH2) 7884 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3])); 7885 else 7886 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3])); 7887 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to 7888 operands[3], but to lab. We will fix this up in 7889 machine_dependent_reorg. */ 7890 emit_barrier (); 7891 DONE; 7892}) 7893 7894(define_expand "casesi_0" 7895 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" "")) 7896 (set (match_dup 4) (minus:SI (match_dup 4) 7897 (match_operand:SI 1 "arith_operand" ""))) 7898 (set (reg:SI T_REG) 7899 (gtu:SI (match_dup 4) 7900 (match_operand:SI 2 "arith_reg_operand" ""))) 7901 (set (pc) 7902 (if_then_else (ne (reg:SI T_REG) 7903 (const_int 0)) 7904 (label_ref (match_operand 3 "" "")) 7905 (pc)))] 7906 "TARGET_SH1" 7907 "") 7908 7909;; ??? reload might clobber r0 if we use it explicitly in the RTL before 7910;; reload; using a R0_REGS pseudo reg is likely to give poor code. 7911;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload. 7912;; 7913;; The use on the T_REG in the casesi_worker* patterns links the bounds 7914;; checking insns and the table memory access. See also PR 69713. 7915(define_insn "casesi_worker_0" 7916 [(set (match_operand:SI 0 "register_operand" "=r,r") 7917 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r") 7918 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI)) 7919 (clobber (match_scratch:SI 3 "=X,1")) 7920 (clobber (match_scratch:SI 4 "=&z,z")) 7921 (use (reg:SI T_REG))] 7922 "TARGET_SH1" 7923 "#") 7924 7925(define_split 7926 [(set (match_operand:SI 0 "register_operand" "") 7927 (unspec:SI [(match_operand:SI 1 "register_operand" "") 7928 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI)) 7929 (clobber (match_scratch:SI 3 "")) 7930 (clobber (match_scratch:SI 4)) 7931 (use (reg:SI T_REG))] 7932 "TARGET_SH1 && ! TARGET_SH2 && reload_completed" 7933 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA)) 7934 (parallel [(set (match_dup 0) 7935 (unspec:SI [(reg:SI R0_REG) (match_dup 1) 7936 (label_ref (match_dup 2))] UNSPEC_CASESI)) 7937 (clobber (match_dup 3))]) 7938 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))] 7939{ 7940 if (GET_CODE (operands[2]) == CODE_LABEL) 7941 LABEL_NUSES (operands[2])++; 7942}) 7943 7944(define_split 7945 [(set (match_operand:SI 0 "register_operand" "") 7946 (unspec:SI [(match_operand:SI 1 "register_operand" "") 7947 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI)) 7948 (clobber (match_scratch:SI 3 "")) 7949 (clobber (match_scratch:SI 4)) 7950 (use (reg:SI T_REG))] 7951 "TARGET_SH2 && reload_completed" 7952 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA)) 7953 (parallel [(set (match_dup 0) 7954 (unspec:SI [(reg:SI R0_REG) (match_dup 1) 7955 (label_ref (match_dup 2))] UNSPEC_CASESI)) 7956 (clobber (match_dup 3))])] 7957{ 7958 if (GET_CODE (operands[2]) == CODE_LABEL) 7959 LABEL_NUSES (operands[2])++; 7960}) 7961 7962;; This may be replaced with casesi_worker_2 in sh_reorg for PIC. 7963;; The insn length is set to 8 for that case. 7964(define_insn "casesi_worker_1" 7965 [(set (match_operand:SI 0 "register_operand" "=r,r") 7966 (unspec:SI [(reg:SI R0_REG) 7967 (match_operand:SI 1 "register_operand" "0,r") 7968 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI)) 7969 (clobber (match_scratch:SI 3 "=X,1"))] 7970 "TARGET_SH1" 7971{ 7972 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2]))); 7973 7974 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); 7975 7976 switch (GET_MODE (diff_vec)) 7977 { 7978 case SImode: 7979 return "shll2 %1" "\n" 7980 " mov.l @(r0,%1),%0"; 7981 case HImode: 7982 return "add %1,%1" "\n" 7983 " mov.w @(r0,%1),%0"; 7984 case QImode: 7985 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) 7986 return "mov.b @(r0,%1),%0" "\n" 7987 " extu.b %0,%0"; 7988 else 7989 return "mov.b @(r0,%1),%0"; 7990 7991 default: 7992 gcc_unreachable (); 7993 } 7994} 7995 [(set_attr_alternative "length" 7996 [(if_then_else (match_test "flag_pic") (const_int 8) (const_int 4)) 7997 (if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))])]) 7998 7999(define_insn "casesi_worker_2" 8000 [(set (match_operand:SI 0 "register_operand" "=r,r") 8001 (unspec:SI [(reg:SI R0_REG) 8002 (match_operand:SI 1 "register_operand" "0,r") 8003 (label_ref (match_operand 2 "" "")) 8004 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI)) 8005 (clobber (match_operand:SI 4 "" "=X,1"))] 8006 "TARGET_SH2 && reload_completed && flag_pic" 8007{ 8008 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2]))); 8009 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); 8010 8011 switch (GET_MODE (diff_vec)) 8012 { 8013 case SImode: 8014 return "shll2 %1" "\n" 8015 " add r0,%1" "\n" 8016 " mova %O3,r0" "\n" 8017 " mov.l @(r0,%1),%0"; 8018 case HImode: 8019 return "add %1,%1" "\n" 8020 " add r0,%1" "\n" 8021 " mova %O3,r0" "\n" 8022 " mov.w @(r0,%1),%0"; 8023 case QImode: 8024 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) 8025 return "add r0,%1" "\n" 8026 " mova %O3,r0" "\n" 8027 " mov.b @(r0,%1),%0" "\n" 8028 " extu.b %0,%0"; 8029 else 8030 return "add r0,%1" "\n" 8031 " mova %O3,r0" "\n" 8032 " mov.b @(r0,%1),%0"; 8033 default: 8034 gcc_unreachable (); 8035 } 8036} 8037 [(set_attr "length" "8")]) 8038 8039(define_expand "simple_return" 8040 [(simple_return)] 8041 "sh_can_use_simple_return_p ()") 8042 8043(define_expand "return" 8044 [(return)] 8045 "reload_completed && epilogue_completed") 8046 8047(define_insn "*<code>_i" 8048 [(any_return)] 8049 "TARGET_SH1 8050 && reload_completed 8051 && ! sh_cfun_trap_exit_p ()" 8052{ 8053 if (TARGET_SH2A && (dbr_sequence_length () == 0) 8054 && !current_function_interrupt) 8055 return "rts/n"; 8056 else 8057 return "%@ %#"; 8058} 8059 [(set_attr "type" "return") 8060 (set_attr "needs_delay_slot" "yes")]) 8061 8062;; trapa has no delay slot. 8063(define_insn "*return_trapa" 8064 [(return)] 8065 "TARGET_SH1 && reload_completed" 8066 "%@" 8067 [(set_attr "type" "return")]) 8068 8069(define_expand "prologue" 8070 [(const_int 0)] 8071 "" 8072{ 8073 sh_expand_prologue (); 8074 DONE; 8075}) 8076 8077(define_expand "epilogue" 8078 [(return)] 8079 "" 8080{ 8081 sh_expand_epilogue (false); 8082}) 8083 8084(define_expand "eh_return" 8085 [(use (match_operand 0 "register_operand" ""))] 8086 "" 8087{ 8088 emit_insn (gen_eh_set_ra_si (operands[0])); 8089 DONE; 8090}) 8091 8092;; Clobber the return address on the stack. We can't expand this 8093;; until we know where it will be put in the stack frame. 8094 8095(define_insn "eh_set_ra_si" 8096 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 8097 UNSPECV_EH_RETURN) 8098 (clobber (match_scratch:SI 1 "=&r"))] 8099 "" 8100 "#") 8101 8102(define_split 8103 [(unspec_volatile [(match_operand 0 "register_operand" "")] 8104 UNSPECV_EH_RETURN) 8105 (clobber (match_scratch 1 ""))] 8106 "reload_completed" 8107 [(const_int 0)] 8108{ 8109 sh_set_return_address (operands[0], operands[1]); 8110 DONE; 8111}) 8112 8113(define_insn "blockage" 8114 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 8115 "" 8116 "" 8117 [(set_attr "length" "0")]) 8118 8119;; Define movml instructions for SH2A target. Currently they are 8120;; used to push and pop all banked registers only. 8121 8122(define_insn "movml_push_banked" 8123 [(set (match_operand:SI 0 "register_operand" "=r") 8124 (plus (match_dup 0) (const_int -32))) 8125 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG)) 8126 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG)) 8127 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG)) 8128 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG)) 8129 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG)) 8130 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG)) 8131 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG)) 8132 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))] 8133 "TARGET_SH2A && REGNO (operands[0]) == 15" 8134 "movml.l r7,@-r15" 8135 [(set_attr "in_delay_slot" "no")]) 8136 8137(define_insn "movml_pop_banked" 8138 [(set (match_operand:SI 0 "register_operand" "=r") 8139 (plus (match_dup 0) (const_int 32))) 8140 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32)))) 8141 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28)))) 8142 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24)))) 8143 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20)))) 8144 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16)))) 8145 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12)))) 8146 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8)))) 8147 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))] 8148 "TARGET_SH2A && REGNO (operands[0]) == 15" 8149 "movml.l @r15+,r7" 8150 [(set_attr "in_delay_slot" "no")]) 8151 8152;; ------------------------------------------------------------------------ 8153;; Scc instructions 8154;; ------------------------------------------------------------------------ 8155 8156(define_insn "movt" 8157 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8158 (match_operand:SI 1 "t_reg_operand"))] 8159 "TARGET_SH1" 8160 "movt %0" 8161 [(set_attr "type" "arith")]) 8162 8163(define_insn "movrt" 8164 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8165 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))] 8166 "TARGET_SH2A" 8167 "movrt %0" 8168 [(set_attr "type" "arith")]) 8169 8170(define_expand "cstoresi4" 8171 [(set (match_operand:SI 0 "register_operand") 8172 (match_operator:SI 1 "comparison_operator" 8173 [(match_operand:SI 2 "cmpsi_operand") 8174 (match_operand:SI 3 "arith_operand")]))] 8175 "TARGET_SH1" 8176{ 8177 if (sh_expand_t_scc (operands)) 8178 DONE; 8179 8180 if (! currently_expanding_to_rtl) 8181 FAIL; 8182 8183 sh_emit_compare_and_set (operands, SImode); 8184 DONE; 8185}) 8186 8187(define_expand "cstoredi4" 8188 [(set (match_operand:SI 0 "register_operand") 8189 (match_operator:SI 1 "comparison_operator" 8190 [(match_operand:DI 2 "arith_operand") 8191 (match_operand:DI 3 "arith_operand")]))] 8192 "TARGET_SH2" 8193{ 8194 if (sh_expand_t_scc (operands)) 8195 DONE; 8196 8197 if (! currently_expanding_to_rtl) 8198 FAIL; 8199 8200 sh_emit_compare_and_set (operands, DImode); 8201 DONE; 8202}) 8203 8204;; Move the complement of the T reg to a reg. 8205;; On SH2A the movrt insn can be used. 8206;; On anything else than SH2A this has to be done with multiple instructions. 8207;; One obvious way would be: 8208;; cmp/eq ... 8209;; movt r0 8210;; xor #1,r0 8211;; 8212;; However, this puts pressure on r0 in most cases and thus the following is 8213;; more appealing: 8214;; cmp/eq ... 8215;; mov #-1,temp 8216;; negc temp,dest 8217;; 8218;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively 8219;; becomes a one instruction operation. Moreover, care must be taken that 8220;; the insn can still be combined with inverted compare and branch code 8221;; around it. On the other hand, if a function returns the complement of 8222;; a previous comparison result in the T bit, the xor #1,r0 approach might 8223;; lead to better code. 8224(define_expand "movnegt" 8225 [(set (match_operand:SI 0 "arith_reg_dest" "") 8226 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))] 8227 "TARGET_SH1" 8228{ 8229 if (TARGET_SH2A) 8230 emit_insn (gen_movrt (operands[0], operands[1])); 8231 else 8232 { 8233 rtx val = force_reg (SImode, gen_int_mode (-1, SImode)); 8234 emit_insn (gen_movrt_negc (operands[0], operands[1], val)); 8235 } 8236 DONE; 8237}) 8238 8239(define_insn_and_split "movrt_negc" 8240 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8241 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1))) 8242 (set (reg:SI T_REG) (const_int 1)) 8243 (use (match_operand:SI 2 "arith_reg_operand" "r"))] 8244 "TARGET_SH1" 8245 "negc %2,%0" 8246 "&& !sh_in_recog_treg_set_expr ()" 8247 [(const_int 0)] 8248{ 8249 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands)) 8250 DONE; 8251 else 8252 FAIL; 8253} 8254 [(set_attr "type" "arith")]) 8255 8256;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the 8257;; pattern can be used by the combine pass. Using a scratch reg for the 8258;; -1 constant results in slightly better register allocations compared to 8259;; generating a pseudo reg before reload. 8260(define_insn_and_split "*movrt_negc" 8261 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8262 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1))) 8263 (clobber (match_scratch:SI 2 "=r")) 8264 (clobber (reg:SI T_REG))] 8265 "TARGET_SH1 && ! TARGET_SH2A" 8266 "#" 8267 "&& !sh_in_recog_treg_set_expr ()" 8268 [(const_int 0)] 8269{ 8270 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands)) 8271 DONE; 8272 else if (reload_completed) 8273 { 8274 emit_move_insn (operands[2], gen_int_mode (-1, SImode)); 8275 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2])); 8276 DONE; 8277 } 8278 else 8279 FAIL; 8280}) 8281 8282;; Store the negated T bit in a reg using r0 and xor. This one doesn't 8283;; clobber the T bit, which is useful when storing the T bit and the 8284;; negated T bit in parallel. On SH2A the movrt insn can be used for that. 8285;; Usually we don't want this insn to be matched, except for cases where the 8286;; T bit clobber is really not appreciated. Hence the extra use on T_REG. 8287(define_insn_and_split "movrt_xor" 8288 [(set (match_operand:SI 0 "arith_reg_dest" "=z") 8289 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1))) 8290 (use (reg:SI T_REG))] 8291 "TARGET_SH1" 8292 "#" 8293 "&& reload_completed" 8294 [(set (match_dup 0) (reg:SI T_REG)) 8295 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))]) 8296 8297;; 0x7fffffff + T 8298;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T 8299;; 8300;; Notice that 0 - 0x80000000 = 0x80000000. 8301 8302;; Single bit tests are usually done with zero_extract. On non-SH2A this 8303;; will use a tst-negc sequence. On SH2A it will use a bld-addc sequence. 8304;; The zeroth bit requires a special pattern, otherwise we get a shlr-addc. 8305;; This is a special case of the generic treg_set_expr pattern and thus has 8306;; to come first or it will never match. 8307(define_insn_and_split "*mov_t_msb_neg" 8308 [(set (match_operand:SI 0 "arith_reg_dest") 8309 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand") 8310 (const_int 1)) 8311 (const_int 2147483647))) 8312 (clobber (reg:SI T_REG))] 8313 "TARGET_SH1" 8314 "#" 8315 "&& can_create_pseudo_p ()" 8316 [(parallel [(set (match_dup 0) 8317 (plus:SI (zero_extract:SI (match_dup 1) 8318 (const_int 1) (const_int 0)) 8319 (const_int 2147483647))) 8320 (clobber (reg:SI T_REG))])]) 8321 8322(define_insn_and_split "*mov_t_msb_neg" 8323 [(set (match_operand:SI 0 "arith_reg_dest") 8324 (plus:SI (match_operand 1 "treg_set_expr") 8325 (const_int 2147483647))) ;; 0x7fffffff 8326 (clobber (reg:SI T_REG))] 8327 "TARGET_SH1" 8328 "#" 8329 "&& can_create_pseudo_p ()" 8330 [(const_int 0)] 8331{ 8332 if (negt_reg_operand (operands[1], VOIDmode)) 8333 { 8334 emit_insn (gen_negc (operands[0], 8335 force_reg (SImode, GEN_INT (-2147483648LL)))); 8336 DONE; 8337 } 8338 8339 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn); 8340 if (ti.remove_trailing_nott ()) 8341 emit_insn (gen_negc (operands[0], 8342 force_reg (SImode, GEN_INT (-2147483648LL)))); 8343 else 8344 emit_insn (gen_addc (operands[0], 8345 force_reg (SImode, const0_rtx), 8346 force_reg (SImode, GEN_INT (2147483647)))); 8347 DONE; 8348}) 8349 8350(define_insn_and_split "*mov_t_msb_neg" 8351 [(set (match_operand:SI 0 "arith_reg_dest") 8352 (if_then_else:SI (match_operand 1 "treg_set_expr") 8353 (match_operand 2 "const_int_operand") 8354 (match_operand 3 "const_int_operand"))) 8355 (clobber (reg:SI T_REG))] 8356 "TARGET_SH1 && can_create_pseudo_p () 8357 && ((INTVAL (operands[2]) == -2147483648LL 8358 && INTVAL (operands[3]) == 2147483647LL) 8359 || (INTVAL (operands[2]) == 2147483647LL 8360 && INTVAL (operands[3]) == -2147483648LL))" 8361 "#" 8362 "&& 1" 8363 [(const_int 0)] 8364{ 8365 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn); 8366 8367 if (INTVAL (operands[2]) == -2147483648LL) 8368 { 8369 if (ti.remove_trailing_nott ()) 8370 emit_insn (gen_negc (operands[0], 8371 force_reg (SImode, GEN_INT (-2147483648LL)))); 8372 else 8373 emit_insn (gen_addc (operands[0], 8374 force_reg (SImode, const0_rtx), 8375 force_reg (SImode, operands[3]))); 8376 DONE; 8377 } 8378 else if (INTVAL (operands[2]) == 2147483647LL) 8379 { 8380 if (ti.remove_trailing_nott ()) 8381 emit_insn (gen_addc (operands[0], 8382 force_reg (SImode, const0_rtx), 8383 force_reg (SImode, GEN_INT (2147483647LL)))); 8384 else 8385 emit_insn (gen_negc (operands[0], 8386 force_reg (SImode, GEN_INT (-2147483648LL)))); 8387 DONE; 8388 } 8389 else 8390 gcc_unreachable (); 8391}) 8392 8393;; Store (negated) T bit as all zeros or ones in a reg. 8394;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T 8395;; not Rn,Rn ! Rn = 0 - Rn 8396(define_insn_and_split "mov_neg_si_t" 8397 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8398 (neg:SI (match_operand 1 "treg_set_expr")))] 8399 "TARGET_SH1" 8400{ 8401 gcc_assert (t_reg_operand (operands[1], VOIDmode)); 8402 return "subc %0,%0"; 8403} 8404 "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)" 8405 [(const_int 0)] 8406{ 8407 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn); 8408 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ())); 8409 8410 if (ti.remove_trailing_nott ()) 8411 emit_insn (gen_one_cmplsi2 (operands[0], operands[0])); 8412 8413 DONE; 8414} 8415 [(set_attr "type" "arith")]) 8416 8417;; Invert the T bit. 8418;; On SH2A we can use the nott insn. On anything else this must be done with 8419;; multiple insns like: 8420;; movt Rn 8421;; tst Rn,Rn 8422;; This requires an additional pseudo. The SH specific sh_treg_combine RTL 8423;; pass will look for this insn. Disallow using it if pseudos can't be 8424;; created. 8425;; Don't split the nott inside the splitting of a treg_set_expr, or else 8426;; surrounding insns might not see and recombine it. Defer the splitting 8427;; of the nott until after the whole insn containing the treg_set_expr 8428;; has been split. 8429(define_insn_and_split "nott" 8430 [(set (reg:SI T_REG) 8431 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))] 8432 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())" 8433{ 8434 gcc_assert (TARGET_SH2A); 8435 return "nott"; 8436} 8437 "!TARGET_SH2A && can_create_pseudo_p () && !sh_in_recog_treg_set_expr ()" 8438 [(set (match_dup 0) (reg:SI T_REG)) 8439 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))] 8440{ 8441 operands[0] = gen_reg_rtx (SImode); 8442}) 8443 8444;; Store T bit as MSB in a reg. 8445;; T = 0: 0x00000000 -> reg 8446;; T = 1: 0x80000000 -> reg 8447(define_insn_and_split "*movt_msb" 8448 [(set (match_operand:SI 0 "arith_reg_dest") 8449 (mult:SI (match_operand:SI 1 "t_reg_operand") 8450 (const_int -2147483648))) ;; 0xffffffff80000000 8451 (clobber (reg:SI T_REG))] 8452 "TARGET_SH1" 8453 "#" 8454 "&& 1" 8455 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))]) 8456 8457;; Store inverted T bit as MSB in a reg. 8458;; T = 0: 0x80000000 -> reg 8459;; T = 1: 0x00000000 -> reg 8460;; On SH2A we can get away without clobbering the T_REG using the movrt insn. 8461;; On non SH2A we resort to the following sequence: 8462;; movt Rn 8463;; tst Rn,Rn 8464;; rotcr Rn 8465;; The T bit value will be modified during the sequence, but the rotcr insn 8466;; will restore its original value. 8467(define_insn_and_split "*negt_msb" 8468 [(set (match_operand:SI 0 "arith_reg_dest") 8469 (match_operand:SI 1 "negt_reg_shl31_operand"))] 8470 "TARGET_SH1" 8471 "#" 8472 "&& can_create_pseudo_p ()" 8473 [(const_int 0)] 8474{ 8475 rtx tmp = gen_reg_rtx (SImode); 8476 8477 if (TARGET_SH2A) 8478 { 8479 emit_insn (gen_movrt (tmp, get_t_reg_rtx ())); 8480 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx)); 8481 } 8482 else 8483 { 8484 emit_move_insn (tmp, get_t_reg_rtx ()); 8485 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx)); 8486 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ())); 8487 } 8488 DONE; 8489}) 8490 8491;; The *cset_zero patterns convert optimizations such as 8492;; "if (test) x = 0;" 8493;; to 8494;; "x &= -(test == 0);" 8495;; back to conditional branch sequences if zero-displacement branches 8496;; are enabled. 8497;; FIXME: These patterns can be removed when conditional execution patterns 8498;; are implemented, since ifcvt will not perform these optimizations if 8499;; conditional execution is supported. 8500(define_insn "*cset_zero" 8501 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8502 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand") 8503 (const_int -1)) 8504 (match_operand:SI 2 "arith_reg_operand" "0")))] 8505 "TARGET_SH1 && TARGET_ZDCBRANCH" 8506{ 8507 return "bf 0f" "\n" 8508 " mov #0,%0" "\n" 8509 "0:"; 8510} 8511 [(set_attr "type" "arith") ;; poor approximation 8512 (set_attr "length" "4")]) 8513 8514(define_insn "*cset_zero" 8515 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8516 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value") 8517 (match_operand:SI 2 "arith_reg_operand" "0") 8518 (const_int 0)))] 8519 "TARGET_SH1 && TARGET_ZDCBRANCH" 8520{ 8521 int tval = sh_eval_treg_value (operands[1]); 8522 if (tval == true) 8523 return "bt 0f" "\n" 8524 " mov #0,%0" "\n" 8525 "0:"; 8526 else if (tval == false) 8527 return "bf 0f" "\n" 8528 " mov #0,%0" "\n" 8529 "0:"; 8530 else 8531 gcc_unreachable (); 8532} 8533 [(set_attr "type" "arith") ;; poor approximation 8534 (set_attr "length" "4")]) 8535 8536(define_insn_and_split "*cset_zero" 8537 [(set (match_operand:SI 0 "arith_reg_dest") 8538 (if_then_else:SI (match_operand 1 "treg_set_expr_not_const01") 8539 (match_dup 0) (const_int 0))) 8540 (clobber (reg:SI T_REG))] 8541 "TARGET_SH1 && TARGET_ZDCBRANCH && can_create_pseudo_p ()" 8542 "#" 8543 "&& 1" 8544 [(set (match_dup 0) 8545 (if_then_else:SI (match_dup 1) (match_dup 0) (const_int 0)))] 8546{ 8547 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn); 8548 if (ti.remove_trailing_nott ()) 8549 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const0_rtx); 8550 else 8551 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const1_rtx); 8552}) 8553 8554(define_expand "cstoresf4" 8555 [(set (match_operand:SI 0 "register_operand") 8556 (match_operator:SI 1 "ordered_comparison_operator" 8557 [(match_operand:SF 2 "arith_operand") 8558 (match_operand:SF 3 "arith_operand")]))] 8559 "TARGET_SH2E" 8560{ 8561 if (! currently_expanding_to_rtl) 8562 FAIL; 8563 8564 sh_emit_compare_and_set (operands, SFmode); 8565 DONE; 8566}) 8567 8568(define_expand "cstoredf4" 8569 [(set (match_operand:SI 0 "register_operand") 8570 (match_operator:SI 1 "ordered_comparison_operator" 8571 [(match_operand:DF 2 "arith_operand") 8572 (match_operand:DF 3 "arith_operand")]))] 8573 "TARGET_FPU_DOUBLE" 8574{ 8575 if (! currently_expanding_to_rtl) 8576 FAIL; 8577 8578 sh_emit_compare_and_set (operands, DFmode); 8579 DONE; 8580}) 8581 8582;; Sometimes the T bit result of insns is needed in normal registers. 8583;; Instead of open coding all the pattern variations, use the treg_set_expr 8584;; predicate to match any T bit output insn and split it out after. 8585;; This pattern should be below all other related patterns so that it is 8586;; considered as a last resort option during matching. This allows 8587;; overriding it with special case patterns. 8588(define_insn_and_split "any_treg_expr_to_reg" 8589 [(set (match_operand:SI 0 "arith_reg_dest") 8590 (match_operand 1 "treg_set_expr")) 8591 (clobber (reg:SI T_REG))] 8592 "TARGET_SH1 && can_create_pseudo_p ()" 8593 "#" 8594 "&& !sh_in_recog_treg_set_expr ()" 8595 [(const_int 0)] 8596{ 8597 if (dump_file) 8598 fprintf (dump_file, "splitting any_treg_expr_to_reg\n"); 8599 8600 if (t_reg_operand (operands[1], VOIDmode)) 8601 { 8602 if (dump_file) 8603 fprintf (dump_file, "t_reg_operand: emitting movt\n"); 8604 emit_insn (gen_movt (operands[0], get_t_reg_rtx ())); 8605 DONE; 8606 } 8607 if (negt_reg_operand (operands[1], VOIDmode)) 8608 { 8609 if (dump_file) 8610 fprintf (dump_file, "negt_reg_operand: emitting movrt\n"); 8611 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ())); 8612 DONE; 8613 } 8614 8615 /* If the split out insns ended with a nott, emit a movrt sequence, 8616 otherwise a normal movt. */ 8617 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn); 8618 rtx_insn* i = NULL; 8619 if (ti.remove_trailing_nott ()) 8620 { 8621 /* Emit this same insn_and_split again. However, the next time it 8622 is split, it will emit the actual negc/movrt insn. This gives 8623 other surrounding insns the chance to see the trailing movrt. */ 8624 if (dump_file) 8625 fprintf (dump_file, 8626 "any_treg_expr_to_reg: replacing trailing nott with movrt\n"); 8627 i = emit_insn (gen_any_treg_expr_to_reg ( 8628 operands[0], gen_rtx_XOR (SImode, get_t_reg_rtx (), 8629 const1_rtx))); 8630 } 8631 else 8632 { 8633 i = emit_insn (gen_movt (operands[0], get_t_reg_rtx ())); 8634 if (dump_file) 8635 fprintf (dump_file, "any_treg_expr_to_reg: appending movt\n"); 8636 } 8637 8638 add_reg_note (i, REG_UNUSED, get_t_reg_rtx ()); 8639 DONE; 8640}) 8641 8642;; ------------------------------------------------------------------------- 8643;; Instructions to cope with inline literal tables 8644;; ------------------------------------------------------------------------- 8645 8646;; 2 byte integer in line 8647(define_insn "consttable_2" 8648 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g") 8649 (match_operand 1 "" "")] 8650 UNSPECV_CONST2)] 8651 "" 8652{ 8653 if (operands[1] != const0_rtx) 8654 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1); 8655 return ""; 8656} 8657 [(set_attr "length" "2") 8658 (set_attr "in_delay_slot" "no")]) 8659 8660;; 4 byte integer in line 8661(define_insn "consttable_4" 8662 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g") 8663 (match_operand 1 "" "")] 8664 UNSPECV_CONST4)] 8665 "" 8666{ 8667 if (operands[1] != const0_rtx) 8668 { 8669 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1); 8670 mark_symbol_refs_as_used (operands[0]); 8671 } 8672 return ""; 8673} 8674 [(set_attr "length" "4") 8675 (set_attr "in_delay_slot" "no")]) 8676 8677;; 8 byte integer in line 8678(define_insn "consttable_8" 8679 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g") 8680 (match_operand 1 "" "")] 8681 UNSPECV_CONST8)] 8682 "" 8683{ 8684 if (operands[1] != const0_rtx) 8685 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1); 8686 return ""; 8687} 8688 [(set_attr "length" "8") 8689 (set_attr "in_delay_slot" "no")]) 8690 8691;; 4 byte floating point 8692(define_insn "consttable_sf" 8693 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g") 8694 (match_operand 1 "" "")] 8695 UNSPECV_CONST4)] 8696 "" 8697{ 8698 if (operands[1] != const0_rtx) 8699 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]), 8700 SFmode, GET_MODE_ALIGNMENT (SFmode)); 8701 return ""; 8702} 8703 [(set_attr "length" "4") 8704 (set_attr "in_delay_slot" "no")]) 8705 8706;; 8 byte floating point 8707(define_insn "consttable_df" 8708 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g") 8709 (match_operand 1 "" "")] 8710 UNSPECV_CONST8)] 8711 "" 8712{ 8713 if (operands[1] != const0_rtx) 8714 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]), 8715 DFmode, GET_MODE_ALIGNMENT (DFmode)); 8716 return ""; 8717} 8718 [(set_attr "length" "8") 8719 (set_attr "in_delay_slot" "no")]) 8720 8721;; Alignment is needed for some constant tables; it may also be added for 8722;; Instructions at the start of loops, or after unconditional branches. 8723;; ??? We would get more accurate lengths if we did instruction 8724;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used 8725;; here is too conservative. 8726 8727;; align to a two byte boundary 8728(define_expand "align_2" 8729 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)] 8730 "" 8731 "") 8732 8733;; Align to a four byte boundary. 8734;; align_4 and align_log are instructions for the starts of loops, or 8735;; after unconditional branches, which may take up extra room. 8736(define_expand "align_4" 8737 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)] 8738 "" 8739 "") 8740 8741;; Align to a cache line boundary. 8742(define_insn "align_log" 8743 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)] 8744 "" 8745 "" 8746 [(set_attr "length" "0") 8747 (set_attr "in_delay_slot" "no")]) 8748 8749;; Emitted at the end of the literal table, used to emit the 8750;; 32bit branch labels if needed. 8751(define_insn "consttable_end" 8752 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)] 8753 "" 8754{ 8755 return output_jump_label_table (); 8756} 8757 [(set_attr "in_delay_slot" "no")]) 8758 8759;; Emitted at the end of the window in the literal table. 8760(define_insn "consttable_window_end" 8761 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)] 8762 "" 8763 "" 8764 [(set_attr "length" "0") 8765 (set_attr "in_delay_slot" "no")]) 8766 8767;; ------------------------------------------------------------------------- 8768;; Minimum / maximum operations. 8769;; ------------------------------------------------------------------------- 8770 8771;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin 8772;; and smax standard name patterns are defined, they will be used during 8773;; initial expansion and combine will then be able to form the actual min-max 8774;; pattern. 8775;; The clips.b and clips.w set the SR.CS bit if the value in the register is 8776;; clipped, but there is currently no way of making use of this information. 8777;; The only way to read or reset the SR.CS bit is by accessing the SR. 8778(define_expand "<code>si3" 8779 [(parallel [(set (match_operand:SI 0 "arith_reg_dest") 8780 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand") 8781 (match_operand 2 "const_int_operand"))) 8782 (clobber (reg:SI T_REG))])] 8783 "TARGET_SH2A" 8784{ 8785 /* Force the comparison value into a register, because greater-than 8786 comparisons can work only on registers. Combine will be able to pick up 8787 the constant value from the REG_EQUAL note when trying to form a min-max 8788 pattern. */ 8789 operands[2] = force_reg (SImode, operands[2]); 8790}) 8791 8792;; Convert 8793;; smax (smin (...)) 8794;; to 8795;; smin (smax (...)) 8796(define_insn_and_split "*clips" 8797 [(set (match_operand:SI 0 "arith_reg_dest") 8798 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand") 8799 (match_operand 2 "clips_max_const_int")) 8800 (match_operand 3 "clips_min_const_int")))] 8801 "TARGET_SH2A" 8802 "#" 8803 "&& 1" 8804 [(set (match_dup 0) 8805 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))]) 8806 8807(define_insn "*clips" 8808 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8809 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0") 8810 (match_operand 2 "clips_min_const_int")) 8811 (match_operand 3 "clips_max_const_int")))] 8812 "TARGET_SH2A" 8813{ 8814 if (INTVAL (operands[3]) == 127) 8815 return "clips.b %0"; 8816 else if (INTVAL (operands[3]) == 32767) 8817 return "clips.w %0"; 8818 else 8819 gcc_unreachable (); 8820} 8821 [(set_attr "type" "arith")]) 8822 8823;; If the expanded smin or smax patterns were not combined, split them into 8824;; a compare and branch sequence, because there are no real smin or smax 8825;; insns. 8826(define_insn_and_split "*<code>si3" 8827 [(set (match_operand:SI 0 "arith_reg_dest") 8828 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand") 8829 (match_operand:SI 2 "arith_reg_or_0_or_1_operand"))) 8830 (clobber (reg:SI T_REG))] 8831 "TARGET_SH2A && can_create_pseudo_p ()" 8832 "#" 8833 "&& 1" 8834 [(const_int 0)] 8835{ 8836 rtx_code_label *skip_label = gen_label_rtx (); 8837 emit_move_insn (operands[0], operands[1]); 8838 8839 rtx cmp_val = operands[2]; 8840 if (satisfies_constraint_M (cmp_val)) 8841 cmp_val = const0_rtx; 8842 8843 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val)); 8844 emit_jump_insn (<CODE> == SMIN 8845 ? gen_branch_false (skip_label) 8846 : gen_branch_true (skip_label)); 8847 8848 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2])); 8849 DONE; 8850}) 8851 8852;; The SH2A clipu.b and clipu.w insns can be used to implement a min function 8853;; with a register and a constant. 8854;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is 8855;; clipped, but there is currently no way of making use of this information. 8856;; The only way to read or reset the SR.CS bit is by accessing the SR. 8857(define_expand "uminsi3" 8858 [(set (match_operand:SI 0 "arith_reg_dest") 8859 (umin:SI (match_operand:SI 1 "arith_reg_operand") 8860 (match_operand 2 "const_int_operand")))] 8861 "TARGET_SH2A" 8862{ 8863 if (INTVAL (operands[2]) == 1) 8864 { 8865 emit_insn (gen_clipu_one (operands[0], operands[1])); 8866 DONE; 8867 } 8868 else if (! clipu_max_const_int (operands[2], VOIDmode)) 8869 FAIL; 8870}) 8871 8872(define_insn "*clipu" 8873 [(set (match_operand:SI 0 "arith_reg_dest" "=r") 8874 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0") 8875 (match_operand 2 "clipu_max_const_int")))] 8876 "TARGET_SH2A" 8877{ 8878 if (INTVAL (operands[2]) == 255) 8879 return "clipu.b %0"; 8880 else if (INTVAL (operands[2]) == 65535) 8881 return "clipu.w %0"; 8882 else 8883 gcc_unreachable (); 8884} 8885 [(set_attr "type" "arith")]) 8886 8887(define_insn_and_split "clipu_one" 8888 [(set (match_operand:SI 0 "arith_reg_dest") 8889 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1))) 8890 (clobber (reg:SI T_REG))] 8891 "TARGET_SH2A" 8892 "#" 8893 "&& can_create_pseudo_p ()" 8894 [(const_int 0)] 8895{ 8896 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx)); 8897 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ())); 8898 DONE; 8899}) 8900 8901;; ------------------------------------------------------------------------- 8902;; Misc 8903;; ------------------------------------------------------------------------- 8904 8905;; String/block move insn. 8906 8907(define_expand "movmemsi" 8908 [(parallel [(set (mem:BLK (match_operand:BLK 0)) 8909 (mem:BLK (match_operand:BLK 1))) 8910 (use (match_operand:SI 2 "nonmemory_operand")) 8911 (use (match_operand:SI 3 "immediate_operand")) 8912 (clobber (reg:SI PR_REG)) 8913 (clobber (reg:SI R4_REG)) 8914 (clobber (reg:SI R5_REG)) 8915 (clobber (reg:SI R0_REG))])] 8916 "TARGET_SH1" 8917{ 8918 if (expand_block_move (operands)) 8919 DONE; 8920 else 8921 FAIL; 8922}) 8923 8924(define_insn "block_move_real" 8925 [(parallel [(set (mem:BLK (reg:SI R4_REG)) 8926 (mem:BLK (reg:SI R5_REG))) 8927 (use (match_operand:SI 0 "arith_reg_operand" "r,r")) 8928 (use (match_operand 1 "" "Z,Ccl")) 8929 (clobber (reg:SI PR_REG)) 8930 (clobber (reg:SI R0_REG))])] 8931 "TARGET_SH1 && ! TARGET_HARD_SH4" 8932 "@ 8933 jsr @%0%# 8934 bsrf %0\n%O1:%#" 8935 [(set_attr "type" "sfunc") 8936 (set_attr "needs_delay_slot" "yes")]) 8937 8938(define_insn "block_lump_real" 8939 [(parallel [(set (mem:BLK (reg:SI R4_REG)) 8940 (mem:BLK (reg:SI R5_REG))) 8941 (use (match_operand:SI 0 "arith_reg_operand" "r,r")) 8942 (use (match_operand 1 "" "Z,Ccl")) 8943 (use (reg:SI R6_REG)) 8944 (clobber (reg:SI PR_REG)) 8945 (clobber (reg:SI T_REG)) 8946 (clobber (reg:SI R4_REG)) 8947 (clobber (reg:SI R5_REG)) 8948 (clobber (reg:SI R6_REG)) 8949 (clobber (reg:SI R0_REG))])] 8950 "TARGET_SH1 && ! TARGET_HARD_SH4" 8951 "@ 8952 jsr @%0%# 8953 bsrf %0\n%O1:%#" 8954 [(set_attr "type" "sfunc") 8955 (set_attr "needs_delay_slot" "yes")]) 8956 8957(define_insn "block_move_real_i4" 8958 [(parallel [(set (mem:BLK (reg:SI R4_REG)) 8959 (mem:BLK (reg:SI R5_REG))) 8960 (use (match_operand:SI 0 "arith_reg_operand" "r,r")) 8961 (use (match_operand 1 "" "Z,Ccl")) 8962 (clobber (reg:SI PR_REG)) 8963 (clobber (reg:SI R0_REG)) 8964 (clobber (reg:SI R1_REG)) 8965 (clobber (reg:SI R2_REG))])] 8966 "TARGET_HARD_SH4" 8967 "@ 8968 jsr @%0%# 8969 bsrf %0\n%O1:%#" 8970 [(set_attr "type" "sfunc") 8971 (set_attr "needs_delay_slot" "yes")]) 8972 8973(define_insn "block_lump_real_i4" 8974 [(parallel [(set (mem:BLK (reg:SI R4_REG)) 8975 (mem:BLK (reg:SI R5_REG))) 8976 (use (match_operand:SI 0 "arith_reg_operand" "r,r")) 8977 (use (match_operand 1 "" "Z,Ccl")) 8978 (use (reg:SI R6_REG)) 8979 (clobber (reg:SI PR_REG)) 8980 (clobber (reg:SI T_REG)) 8981 (clobber (reg:SI R4_REG)) 8982 (clobber (reg:SI R5_REG)) 8983 (clobber (reg:SI R6_REG)) 8984 (clobber (reg:SI R0_REG)) 8985 (clobber (reg:SI R1_REG)) 8986 (clobber (reg:SI R2_REG)) 8987 (clobber (reg:SI R3_REG))])] 8988 "TARGET_HARD_SH4" 8989 "@ 8990 jsr @%0%# 8991 bsrf %0\n%O1:%#" 8992 [(set_attr "type" "sfunc") 8993 (set_attr "needs_delay_slot" "yes")]) 8994 8995;; byte compare pattern 8996;; temp = a ^ b; 8997;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F)) 8998(define_insn "cmpstr_t" 8999 [(set (reg:SI T_REG) 9000 (eq:SI (and:SI 9001 (and:SI 9002 (and:SI 9003 (zero_extract:SI 9004 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r") 9005 (match_operand:SI 1 "arith_reg_operand" "r")) 9006 (const_int 8) (const_int 0)) 9007 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1)) 9008 (const_int 8) (const_int 8))) 9009 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1)) 9010 (const_int 8) (const_int 16))) 9011 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1)) 9012 (const_int 8) (const_int 24))) 9013 (const_int 0)))] 9014 "TARGET_SH1" 9015 "cmp/str %0,%1" 9016 [(set_attr "type" "mt_group")]) 9017 9018(define_expand "cmpstrsi" 9019 [(set (match_operand:SI 0 "register_operand") 9020 (compare:SI (match_operand:BLK 1 "memory_operand") 9021 (match_operand:BLK 2 "memory_operand"))) 9022 (use (match_operand 3 "immediate_operand"))] 9023 "TARGET_SH1 && optimize" 9024{ 9025 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands)) 9026 DONE; 9027 else 9028 FAIL; 9029}) 9030 9031(define_expand "cmpstrnsi" 9032 [(set (match_operand:SI 0 "register_operand") 9033 (compare:SI (match_operand:BLK 1 "memory_operand") 9034 (match_operand:BLK 2 "memory_operand"))) 9035 (use (match_operand:SI 3 "nonmemory_operand")) 9036 (use (match_operand:SI 4 "immediate_operand"))] 9037 "TARGET_SH1 && optimize" 9038{ 9039 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands)) 9040 DONE; 9041 else 9042 FAIL; 9043}) 9044 9045(define_expand "strlensi" 9046 [(set (match_operand:SI 0 "register_operand") 9047 (unspec:SI [(match_operand:BLK 1 "memory_operand") 9048 (match_operand:SI 2 "immediate_operand") 9049 (match_operand:SI 3 "immediate_operand")] 9050 UNSPEC_BUILTIN_STRLEN))] 9051 "TARGET_SH1 && optimize" 9052{ 9053 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands)) 9054 DONE; 9055 else 9056 FAIL; 9057}) 9058 9059(define_expand "setmemqi" 9060 [(parallel [(set (match_operand:BLK 0 "memory_operand") 9061 (match_operand 2 "const_int_operand")) 9062 (use (match_operand:QI 1 "const_int_operand")) 9063 (use (match_operand:QI 3 "const_int_operand"))])] 9064 "TARGET_SH1 && optimize" 9065 { 9066 if (optimize_insn_for_size_p ()) 9067 FAIL; 9068 9069 sh_expand_setmem (operands); 9070 DONE; 9071 }) 9072 9073 9074;; ------------------------------------------------------------------------- 9075;; Floating point instructions. 9076;; ------------------------------------------------------------------------- 9077 9078;; FIXME: For now we disallow any memory operands for fpscr loads/stores, 9079;; except for post-inc loads and pre-dec stores for push/pop purposes. 9080;; This avoids problems with reload. As a consequence, user initiated fpscr 9081;; stores to memory will always be ferried through a general register. 9082;; User initiated fpscr loads always have to undergo bit masking to preserve 9083;; the current fpu mode settings for the compiler generated code. Thus such 9084;; fpscr loads will always have to go through general registers anyways. 9085(define_insn "lds_fpscr" 9086 [(set (reg:SI FPSCR_REG) 9087 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>")) 9088 (set (reg:SI FPSCR_STAT_REG) 9089 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT)) 9090 (set (reg:SI FPSCR_MODES_REG) 9091 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))] 9092 "TARGET_FPU_ANY" 9093 "@ 9094 lds %0,fpscr 9095 lds.l %0,fpscr" 9096 [(set_attr "type" "gp_fpscr,mem_fpscr")]) 9097 9098;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp 9099;; type for it. 9100(define_insn "sts_fpscr" 9101 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<") 9102 (reg:SI FPSCR_REG)) 9103 (use (reg:SI FPSCR_STAT_REG)) 9104 (use (reg:SI FPSCR_MODES_REG))] 9105 "TARGET_FPU_ANY" 9106 "@ 9107 sts fpscr,%0 9108 sts.l fpscr,%0" 9109 [(set_attr "type" "mac_gp,fstore")]) 9110 9111(define_expand "set_fpscr" 9112 [(parallel [(set (reg:SI FPSCR_REG) 9113 (match_operand:SI 0 "general_operand")) 9114 (set (reg:SI FPSCR_STAT_REG) 9115 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])] 9116 "TARGET_FPU_ANY" 9117{ 9118 /* We have to mask out the FR, SZ and PR bits. To do that, we need to 9119 get the current FPSCR value first. 9120 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */ 9121 9122 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR)); 9123 9124 rtx a = force_reg (SImode, operands[0]); 9125 9126 rtx b = gen_reg_rtx (SImode); 9127 emit_insn (gen_sts_fpscr (b)); 9128 9129 rtx a_xor_b = gen_reg_rtx (SImode); 9130 emit_insn (gen_xorsi3 (a_xor_b, a, b)); 9131 9132 rtx a_xor_b_and_mask = gen_reg_rtx (SImode); 9133 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask)); 9134 9135 rtx r = gen_reg_rtx (SImode); 9136 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a)); 9137 emit_insn (gen_lds_fpscr (r)); 9138 9139 DONE; 9140}) 9141 9142;; ??? This uses the fp unit, but has no type indicating that. 9143;; If we did that, this would either give a bogus latency or introduce 9144;; a bogus FIFO constraint. 9145;; Since this insn is currently only used for prologues/epilogues, 9146;; it is probably best to claim no function unit, which matches the 9147;; current setting. 9148(define_insn "toggle_sz" 9149 [(set (reg:SI FPSCR_REG) 9150 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ))) 9151 (set (reg:SI FPSCR_MODES_REG) 9152 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))] 9153 "TARGET_FPU_DOUBLE" 9154 "fschg" 9155 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")]) 9156 9157;; Toggle FPU precision PR mode. 9158 9159(define_insn "toggle_pr" 9160 [(set (reg:SI FPSCR_REG) 9161 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR))) 9162 (set (reg:SI FPSCR_MODES_REG) 9163 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))] 9164 "TARGET_SH4A_FP" 9165 "fpchg" 9166 [(set_attr "type" "fpscr_toggle")]) 9167 9168(define_expand "addsf3" 9169 [(set (match_operand:SF 0 "fp_arith_reg_operand") 9170 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand") 9171 (match_operand:SF 2 "fp_arith_reg_operand")))] 9172 "TARGET_SH2E" 9173{ 9174 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2])); 9175 DONE; 9176}) 9177 9178(define_insn "addsf3_i" 9179 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9180 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0") 9181 (match_operand:SF 2 "fp_arith_reg_operand" "f"))) 9182 (clobber (reg:SI FPSCR_STAT_REG)) 9183 (use (reg:SI FPSCR_MODES_REG))] 9184 "TARGET_SH2E" 9185 "fadd %2,%0" 9186 [(set_attr "type" "fp") 9187 (set_attr "fp_mode" "single")]) 9188 9189(define_expand "subsf3" 9190 [(set (match_operand:SF 0 "fp_arith_reg_operand" "") 9191 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "") 9192 (match_operand:SF 2 "fp_arith_reg_operand" "")))] 9193 "TARGET_SH2E" 9194{ 9195 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2])); 9196 DONE; 9197}) 9198 9199(define_insn "subsf3_i" 9200 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9201 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0") 9202 (match_operand:SF 2 "fp_arith_reg_operand" "f"))) 9203 (clobber (reg:SI FPSCR_STAT_REG)) 9204 (use (reg:SI FPSCR_MODES_REG))] 9205 "TARGET_SH2E" 9206 "fsub %2,%0" 9207 [(set_attr "type" "fp") 9208 (set_attr "fp_mode" "single")]) 9209 9210(define_expand "mulsf3" 9211 [(set (match_operand:SF 0 "fp_arith_reg_operand" "") 9212 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "") 9213 (match_operand:SF 2 "fp_arith_reg_operand" "")))] 9214 "TARGET_SH2E" 9215{ 9216 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2])); 9217 DONE; 9218}) 9219 9220(define_insn "mulsf3_i" 9221 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9222 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0") 9223 (match_operand:SF 2 "fp_arith_reg_operand" "f"))) 9224 (clobber (reg:SI FPSCR_STAT_REG)) 9225 (use (reg:SI FPSCR_MODES_REG))] 9226 "TARGET_SH2E" 9227 "fmul %2,%0" 9228 [(set_attr "type" "fp") 9229 (set_attr "fp_mode" "single")]) 9230 9231;; FMA (fused multiply-add) patterns 9232(define_expand "fmasf4" 9233 [(set (match_operand:SF 0 "fp_arith_reg_operand") 9234 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand") 9235 (match_operand:SF 2 "fp_arith_reg_operand") 9236 (match_operand:SF 3 "fp_arith_reg_operand")))] 9237 "TARGET_SH2E" 9238{ 9239 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], operands[3])); 9240 DONE; 9241}) 9242 9243(define_insn "fmasf4_i" 9244 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9245 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w") 9246 (match_operand:SF 2 "fp_arith_reg_operand" "f") 9247 (match_operand:SF 3 "fp_arith_reg_operand" "0"))) 9248 (clobber (reg:SI FPSCR_STAT_REG)) 9249 (use (reg:SI FPSCR_MODES_REG))] 9250 "TARGET_SH2E" 9251 "fmac %1,%2,%0" 9252 [(set_attr "type" "fp") 9253 (set_attr "fp_mode" "single")]) 9254 9255;; For some cases such as 'a * b + a' the FMA pattern is not generated by 9256;; previous transformations. If FMA is generally allowed, let the combine 9257;; pass utilize it. 9258(define_insn_and_split "*fmasf4" 9259 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9260 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w") 9261 (match_operand:SF 2 "fp_arith_reg_operand" "f")) 9262 (match_operand:SF 3 "arith_reg_operand" "0"))) 9263 (clobber (reg:SI FPSCR_STAT_REG)) 9264 (use (reg:SI FPSCR_MODES_REG))] 9265 "TARGET_SH2E && flag_fp_contract_mode != FP_CONTRACT_OFF" 9266 "fmac %1,%2,%0" 9267 "&& can_create_pseudo_p ()" 9268 [(parallel [(set (match_dup 0) 9269 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3))) 9270 (clobber (reg:SI FPSCR_STAT_REG)) 9271 (use (reg:SI FPSCR_MODES_REG))])] 9272{ 9273 /* Change 'b * a + a' into 'a * b + a'. 9274 This is better for register allocation. */ 9275 if (REGNO (operands[2]) == REGNO (operands[3])) 9276 std::swap (operands[1], operands[2]); 9277} 9278 [(set_attr "type" "fp") 9279 (set_attr "fp_mode" "single")]) 9280 9281(define_expand "divsf3" 9282 [(set (match_operand:SF 0 "fp_arith_reg_operand") 9283 (div:SF (match_operand:SF 1 "fp_arith_reg_operand") 9284 (match_operand:SF 2 "fp_arith_reg_operand")))] 9285 "TARGET_SH2E" 9286{ 9287 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2])); 9288 DONE; 9289}) 9290 9291(define_insn "divsf3_i" 9292 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9293 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0") 9294 (match_operand:SF 2 "fp_arith_reg_operand" "f"))) 9295 (clobber (reg:SI FPSCR_STAT_REG)) 9296 (use (reg:SI FPSCR_MODES_REG))] 9297 "TARGET_SH2E" 9298 "fdiv %2,%0" 9299 [(set_attr "type" "fdiv") 9300 (set_attr "fp_mode" "single")]) 9301 9302(define_expand "floatsisf2" 9303 [(set (match_operand:SF 0 "fp_arith_reg_operand" "") 9304 (float:SF (match_operand:SI 1 "fpul_operand" "")))] 9305 "TARGET_SH2E" 9306{ 9307 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1])); 9308 DONE; 9309}) 9310 9311(define_insn "floatsisf2_i4" 9312 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9313 (float:SF (match_operand:SI 1 "fpul_operand" "y"))) 9314 (clobber (reg:SI FPSCR_STAT_REG)) 9315 (use (reg:SI FPSCR_MODES_REG))] 9316 "TARGET_SH2E" 9317 "float %1,%0" 9318 [(set_attr "type" "fp") 9319 (set_attr "fp_mode" "single")]) 9320 9321(define_expand "fix_truncsfsi2" 9322 [(set (match_operand:SI 0 "fpul_operand") 9323 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand")))] 9324 "TARGET_SH2E" 9325{ 9326 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1])); 9327 DONE; 9328}) 9329 9330(define_insn "fix_truncsfsi2_i4" 9331 [(set (match_operand:SI 0 "fpul_operand" "=y") 9332 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f"))) 9333 (clobber (reg:SI FPSCR_STAT_REG)) 9334 (use (reg:SI FPSCR_MODES_REG))] 9335 "TARGET_SH2E" 9336 "ftrc %1,%0" 9337 [(set_attr "type" "ftrc_s") 9338 (set_attr "fp_mode" "single")]) 9339 9340(define_insn "cmpgtsf_t" 9341 [(set (reg:SI T_REG) 9342 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f") 9343 (match_operand:SF 1 "fp_arith_reg_operand" "f"))) 9344 (clobber (reg:SI FPSCR_STAT_REG)) 9345 (use (reg:SI FPSCR_MODES_REG))] 9346 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE" 9347 "fcmp/gt %1,%0" 9348 [(set_attr "type" "fp_cmp") 9349 (set_attr "fp_mode" "single")]) 9350 9351(define_insn "cmpeqsf_t" 9352 [(set (reg:SI T_REG) 9353 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f") 9354 (match_operand:SF 1 "fp_arith_reg_operand" "f"))) 9355 (clobber (reg:SI FPSCR_STAT_REG)) 9356 (use (reg:SI FPSCR_MODES_REG))] 9357 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE" 9358 "fcmp/eq %1,%0" 9359 [(set_attr "type" "fp_cmp") 9360 (set_attr "fp_mode" "single")]) 9361 9362(define_insn "ieee_ccmpeqsf_t" 9363 [(set (reg:SI T_REG) 9364 (ior:SI (reg:SI T_REG) 9365 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f") 9366 (match_operand:SF 1 "fp_arith_reg_operand" "f")))) 9367 (clobber (reg:SI FPSCR_STAT_REG)) 9368 (use (reg:SI FPSCR_MODES_REG))] 9369 "TARGET_IEEE && TARGET_SH2E" 9370{ 9371 return output_ieee_ccmpeq (insn, operands); 9372} 9373 [(set_attr "length" "4") 9374 (set_attr "fp_mode" "single")]) 9375 9376(define_expand "cbranchsf4" 9377 [(set (pc) 9378 (if_then_else (match_operator 0 "ordered_comparison_operator" 9379 [(match_operand:SF 1 "arith_operand" "") 9380 (match_operand:SF 2 "arith_operand" "")]) 9381 (match_operand 3 "" "") 9382 (pc)))] 9383 "TARGET_SH2E" 9384{ 9385 sh_emit_compare_and_branch (operands, SFmode); 9386 DONE; 9387}) 9388 9389(define_expand "negsf2" 9390 [(set (match_operand:SF 0 "fp_arith_reg_operand") 9391 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))] 9392 "TARGET_SH2E") 9393 9394(define_insn "*negsf2_i" 9395 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9396 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))] 9397 "TARGET_SH2E" 9398 "fneg %0" 9399 [(set_attr "type" "fmove")]) 9400 9401(define_expand "sqrtsf2" 9402 [(set (match_operand:SF 0 "fp_arith_reg_operand" "") 9403 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))] 9404 "TARGET_SH3E" 9405{ 9406 emit_insn (gen_sqrtsf2_i (operands[0], operands[1])); 9407 DONE; 9408}) 9409 9410(define_insn "sqrtsf2_i" 9411 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9412 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0"))) 9413 (clobber (reg:SI FPSCR_STAT_REG)) 9414 (use (reg:SI FPSCR_MODES_REG))] 9415 "TARGET_SH3E" 9416 "fsqrt %0" 9417 [(set_attr "type" "fdiv") 9418 (set_attr "fp_mode" "single")]) 9419 9420(define_insn "rsqrtsf2" 9421 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9422 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "0")] 9423 UNSPEC_FSRRA)) 9424 (clobber (reg:SI FPSCR_STAT_REG)) 9425 (use (reg:SI FPSCR_MODES_REG))] 9426 "TARGET_FPU_ANY && TARGET_FSRRA" 9427 "fsrra %0" 9428 [(set_attr "type" "fsrra") 9429 (set_attr "fp_mode" "single")]) 9430 9431;; When the sincos pattern is defined, the builtin functions sin and cos 9432;; will be expanded to the sincos pattern and one of the output values will 9433;; remain unused. 9434(define_expand "sincossf3" 9435 [(set (match_operand:SF 0 "nonimmediate_operand") 9436 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA)) 9437 (set (match_operand:SF 1 "nonimmediate_operand") 9438 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))] 9439 "TARGET_FPU_ANY && TARGET_FSCA" 9440{ 9441 rtx scaled = gen_reg_rtx (SFmode); 9442 rtx truncated = gen_reg_rtx (SImode); 9443 rtx fsca = gen_reg_rtx (V2SFmode); 9444 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ()); 9445 9446 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg)); 9447 emit_insn (gen_fix_truncsfsi2 (truncated, scaled)); 9448 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ())); 9449 9450 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4)); 9451 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0)); 9452 DONE; 9453}) 9454 9455(define_insn_and_split "fsca" 9456 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f") 9457 (vec_concat:V2SF 9458 (unspec:SF [(mult:SF 9459 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y")) 9460 (match_operand:SF 2 "fsca_scale_factor" "i")) 9461 ] UNSPEC_FSINA) 9462 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2)) 9463 ] UNSPEC_FCOSA))) 9464 (clobber (reg:SI FPSCR_STAT_REG)) 9465 (use (reg:SI FPSCR_MODES_REG))] 9466 "TARGET_FPU_ANY && TARGET_FSCA" 9467 "fsca fpul,%d0" 9468 "&& !fpul_operand (operands[1], SImode)" 9469 [(const_int 0)] 9470{ 9471 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it 9472 to a simple reg, otherwise reload will have trouble reloading the 9473 pseudo into fpul. */ 9474 rtx x = XEXP (operands[1], 0); 9475 while (x != NULL_RTX && !fpul_operand (x, SImode)) 9476 { 9477 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT); 9478 x = XEXP (x, 0); 9479 } 9480 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode)); 9481 emit_insn (gen_fsca (operands[0], x, operands[2])); 9482 DONE; 9483} 9484 [(set_attr "type" "fsca") 9485 (set_attr "fp_mode" "single")]) 9486 9487(define_expand "abssf2" 9488 [(set (match_operand:SF 0 "fp_arith_reg_operand") 9489 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))] 9490 "TARGET_SH2E") 9491 9492(define_insn "*abssf2_i" 9493 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") 9494 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))] 9495 "TARGET_SH2E" 9496 "fabs %0" 9497 [(set_attr "type" "fmove")]) 9498 9499(define_expand "adddf3" 9500 [(set (match_operand:DF 0 "fp_arith_reg_operand" "") 9501 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "") 9502 (match_operand:DF 2 "fp_arith_reg_operand" "")))] 9503 "TARGET_FPU_DOUBLE" 9504{ 9505 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2])); 9506 DONE; 9507}) 9508 9509(define_insn "adddf3_i" 9510 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9511 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0") 9512 (match_operand:DF 2 "fp_arith_reg_operand" "f"))) 9513 (clobber (reg:SI FPSCR_STAT_REG)) 9514 (use (reg:SI FPSCR_MODES_REG))] 9515 "TARGET_FPU_DOUBLE" 9516 "fadd %2,%0" 9517 [(set_attr "type" "dfp_arith") 9518 (set_attr "fp_mode" "double")]) 9519 9520(define_expand "subdf3" 9521 [(set (match_operand:DF 0 "fp_arith_reg_operand" "") 9522 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "") 9523 (match_operand:DF 2 "fp_arith_reg_operand" "")))] 9524 "TARGET_FPU_DOUBLE" 9525{ 9526 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2])); 9527 DONE; 9528}) 9529 9530(define_insn "subdf3_i" 9531 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9532 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0") 9533 (match_operand:DF 2 "fp_arith_reg_operand" "f"))) 9534 (clobber (reg:SI FPSCR_STAT_REG)) 9535 (use (reg:SI FPSCR_MODES_REG))] 9536 "TARGET_FPU_DOUBLE" 9537 "fsub %2,%0" 9538 [(set_attr "type" "dfp_arith") 9539 (set_attr "fp_mode" "double")]) 9540 9541(define_expand "muldf3" 9542 [(set (match_operand:DF 0 "fp_arith_reg_operand" "") 9543 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "") 9544 (match_operand:DF 2 "fp_arith_reg_operand" "")))] 9545 "TARGET_FPU_DOUBLE" 9546{ 9547 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2])); 9548 DONE; 9549}) 9550 9551(define_insn "muldf3_i" 9552 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9553 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0") 9554 (match_operand:DF 2 "fp_arith_reg_operand" "f"))) 9555 (clobber (reg:SI FPSCR_STAT_REG)) 9556 (use (reg:SI FPSCR_MODES_REG))] 9557 "TARGET_FPU_DOUBLE" 9558 "fmul %2,%0" 9559 [(set_attr "type" "dfp_mul") 9560 (set_attr "fp_mode" "double")]) 9561 9562(define_expand "divdf3" 9563 [(set (match_operand:DF 0 "fp_arith_reg_operand" "") 9564 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "") 9565 (match_operand:DF 2 "fp_arith_reg_operand" "")))] 9566 "TARGET_FPU_DOUBLE" 9567{ 9568 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2])); 9569 DONE; 9570}) 9571 9572(define_insn "divdf3_i" 9573 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9574 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0") 9575 (match_operand:DF 2 "fp_arith_reg_operand" "f"))) 9576 (clobber (reg:SI FPSCR_STAT_REG)) 9577 (use (reg:SI FPSCR_MODES_REG))] 9578 "TARGET_FPU_DOUBLE" 9579 "fdiv %2,%0" 9580 [(set_attr "type" "dfdiv") 9581 (set_attr "fp_mode" "double")]) 9582 9583(define_expand "floatsidf2" 9584 [(set (match_operand:DF 0 "fp_arith_reg_operand" "") 9585 (float:DF (match_operand:SI 1 "fpul_operand" "")))] 9586 "TARGET_FPU_DOUBLE" 9587{ 9588 emit_insn (gen_floatsidf2_i (operands[0], operands[1])); 9589 DONE; 9590}) 9591 9592(define_insn "floatsidf2_i" 9593 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9594 (float:DF (match_operand:SI 1 "fpul_operand" "y"))) 9595 (clobber (reg:SI FPSCR_STAT_REG)) 9596 (use (reg:SI FPSCR_MODES_REG))] 9597 "TARGET_FPU_DOUBLE" 9598 "float %1,%0" 9599 [(set_attr "type" "dfp_conv") 9600 (set_attr "fp_mode" "double")]) 9601 9602(define_expand "fix_truncdfsi2" 9603 [(set (match_operand:SI 0 "fpul_operand" "") 9604 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))] 9605 "TARGET_FPU_DOUBLE" 9606{ 9607 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1])); 9608 DONE; 9609}) 9610 9611(define_insn "fix_truncdfsi2_i" 9612 [(set (match_operand:SI 0 "fpul_operand" "=y") 9613 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f"))) 9614 (clobber (reg:SI FPSCR_STAT_REG)) 9615 (use (reg:SI FPSCR_MODES_REG))] 9616 "TARGET_FPU_DOUBLE" 9617 "ftrc %1,%0" 9618 [(set_attr "type" "dfp_conv") 9619 (set_attr "dfp_comp" "no") 9620 (set_attr "fp_mode" "double")]) 9621 9622(define_insn "cmpgtdf_t" 9623 [(set (reg:SI T_REG) 9624 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f") 9625 (match_operand:DF 1 "fp_arith_reg_operand" "f"))) 9626 (clobber (reg:SI FPSCR_STAT_REG)) 9627 (use (reg:SI FPSCR_MODES_REG))] 9628 "TARGET_FPU_DOUBLE" 9629 "fcmp/gt %1,%0" 9630 [(set_attr "type" "dfp_cmp") 9631 (set_attr "fp_mode" "double")]) 9632 9633(define_insn "cmpeqdf_t" 9634 [(set (reg:SI T_REG) 9635 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f") 9636 (match_operand:DF 1 "fp_arith_reg_operand" "f"))) 9637 (clobber (reg:SI FPSCR_STAT_REG)) 9638 (use (reg:SI FPSCR_MODES_REG))] 9639 "TARGET_FPU_DOUBLE" 9640 "fcmp/eq %1,%0" 9641 [(set_attr "type" "dfp_cmp") 9642 (set_attr "fp_mode" "double")]) 9643 9644(define_insn "*ieee_ccmpeqdf_t" 9645 [(set (reg:SI T_REG) 9646 (ior:SI (reg:SI T_REG) 9647 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f") 9648 (match_operand:DF 1 "fp_arith_reg_operand" "f")))) 9649 (clobber (reg:SI FPSCR_STAT_REG)) 9650 (use (reg:SI FPSCR_MODES_REG))] 9651 "TARGET_IEEE && TARGET_FPU_DOUBLE" 9652{ 9653 return output_ieee_ccmpeq (insn, operands); 9654} 9655 [(set_attr "length" "4") 9656 (set_attr "fp_mode" "double")]) 9657 9658(define_expand "cbranchdf4" 9659 [(set (pc) 9660 (if_then_else (match_operator 0 "ordered_comparison_operator" 9661 [(match_operand:DF 1 "arith_operand" "") 9662 (match_operand:DF 2 "arith_operand" "")]) 9663 (match_operand 3 "" "") 9664 (pc)))] 9665 "TARGET_FPU_DOUBLE" 9666{ 9667 sh_emit_compare_and_branch (operands, DFmode); 9668 DONE; 9669}) 9670 9671(define_expand "negdf2" 9672 [(set (match_operand:DF 0 "fp_arith_reg_operand") 9673 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))] 9674 "TARGET_FPU_DOUBLE") 9675 9676(define_insn "*negdf2_i" 9677 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9678 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))] 9679 "TARGET_FPU_DOUBLE" 9680 "fneg %0" 9681 [(set_attr "type" "fmove")]) 9682 9683(define_expand "sqrtdf2" 9684 [(set (match_operand:DF 0 "fp_arith_reg_operand") 9685 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))] 9686 "TARGET_FPU_DOUBLE" 9687{ 9688 emit_insn (gen_sqrtdf2_i (operands[0], operands[1])); 9689 DONE; 9690}) 9691 9692(define_insn "sqrtdf2_i" 9693 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9694 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0"))) 9695 (clobber (reg:SI FPSCR_STAT_REG)) 9696 (use (reg:SI FPSCR_MODES_REG))] 9697 "TARGET_FPU_DOUBLE" 9698 "fsqrt %0" 9699 [(set_attr "type" "dfdiv") 9700 (set_attr "fp_mode" "double")]) 9701 9702(define_expand "absdf2" 9703 [(set (match_operand:DF 0 "fp_arith_reg_operand") 9704 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))] 9705 "TARGET_FPU_DOUBLE") 9706 9707(define_insn "*absdf2_i" 9708 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9709 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))] 9710 "TARGET_FPU_DOUBLE" 9711 "fabs %0" 9712 [(set_attr "type" "fmove")]) 9713 9714(define_expand "extendsfdf2" 9715 [(set (match_operand:DF 0 "fp_arith_reg_operand" "") 9716 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))] 9717 "TARGET_FPU_DOUBLE" 9718{ 9719 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1])); 9720 DONE; 9721}) 9722 9723(define_insn "extendsfdf2_i4" 9724 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") 9725 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y"))) 9726 (clobber (reg:SI FPSCR_STAT_REG)) 9727 (use (reg:SI FPSCR_MODES_REG))] 9728 "TARGET_FPU_DOUBLE" 9729 "fcnvsd %1,%0" 9730 [(set_attr "type" "fp") 9731 (set_attr "fp_mode" "double")]) 9732 9733(define_expand "truncdfsf2" 9734 [(set (match_operand:SF 0 "fpul_operand" "") 9735 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))] 9736 "TARGET_FPU_DOUBLE" 9737{ 9738 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1])); 9739 DONE; 9740}) 9741 9742(define_insn "truncdfsf2_i4" 9743 [(set (match_operand:SF 0 "fpul_operand" "=y") 9744 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f"))) 9745 (clobber (reg:SI FPSCR_STAT_REG)) 9746 (use (reg:SI FPSCR_MODES_REG))] 9747 "TARGET_FPU_DOUBLE" 9748 "fcnvds %1,%0" 9749 [(set_attr "type" "fp") 9750 (set_attr "fp_mode" "double")]) 9751 9752;; ------------------------------------------------------------------------- 9753;; Bit field extract patterns. 9754;; ------------------------------------------------------------------------- 9755 9756;; These give better code for packed bitfields, because they allow 9757;; auto-increment addresses to be generated. 9758 9759(define_expand "insv" 9760 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "") 9761 (match_operand:SI 1 "immediate_operand" "") 9762 (match_operand:SI 2 "immediate_operand" "")) 9763 (match_operand:SI 3 "general_operand" ""))] 9764 "TARGET_SH1 && TARGET_BIG_ENDIAN" 9765{ 9766 rtx addr_target, orig_address, shift_reg, qi_val; 9767 HOST_WIDE_INT bitsize, size, v = 0; 9768 rtx x = operands[3]; 9769 9770 if (TARGET_SH2A && TARGET_BITOPS 9771 && (satisfies_constraint_Sbw (operands[0]) 9772 || satisfies_constraint_Sbv (operands[0])) 9773 && satisfies_constraint_M (operands[1]) 9774 && satisfies_constraint_K03 (operands[2])) 9775 { 9776 if (satisfies_constraint_N (operands[3])) 9777 { 9778 emit_insn (gen_bclr_m2a (operands[0], operands[2])); 9779 DONE; 9780 } 9781 else if (satisfies_constraint_M (operands[3])) 9782 { 9783 emit_insn (gen_bset_m2a (operands[0], operands[2])); 9784 DONE; 9785 } 9786 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG) 9787 && satisfies_constraint_M (operands[1])) 9788 { 9789 emit_insn (gen_bst_m2a (operands[0], operands[2])); 9790 DONE; 9791 } 9792 else if (REG_P (operands[3]) 9793 && satisfies_constraint_M (operands[1])) 9794 { 9795 emit_insn (gen_bldsi_reg (operands[3], const0_rtx)); 9796 emit_insn (gen_bst_m2a (operands[0], operands[2])); 9797 DONE; 9798 } 9799 } 9800 /* ??? expmed doesn't care for non-register predicates. */ 9801 if (! memory_operand (operands[0], VOIDmode) 9802 || ! immediate_operand (operands[1], VOIDmode) 9803 || ! immediate_operand (operands[2], VOIDmode) 9804 || ! general_operand (x, VOIDmode)) 9805 FAIL; 9806 /* If this isn't a 16 / 24 / 32 bit field, or if 9807 it doesn't start on a byte boundary, then fail. */ 9808 bitsize = INTVAL (operands[1]); 9809 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0 9810 || (INTVAL (operands[2]) % 8) != 0) 9811 FAIL; 9812 9813 size = bitsize / 8; 9814 orig_address = XEXP (operands[0], 0); 9815 shift_reg = gen_reg_rtx (SImode); 9816 if (CONST_INT_P (x)) 9817 { 9818 v = INTVAL (x); 9819 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode))); 9820 } 9821 else 9822 { 9823 emit_insn (gen_movsi (shift_reg, operands[3])); 9824 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3); 9825 } 9826 addr_target = copy_addr_to_reg (plus_constant (Pmode, 9827 orig_address, size - 1)); 9828 9829 operands[0] = replace_equiv_address (operands[0], addr_target); 9830 emit_insn (gen_movqi (operands[0], qi_val)); 9831 9832 while (size -= 1) 9833 { 9834 if (CONST_INT_P (x)) 9835 qi_val 9836 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode))); 9837 else 9838 { 9839 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8))); 9840 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3); 9841 } 9842 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx)); 9843 emit_insn (gen_movqi (operands[0], qi_val)); 9844 } 9845 9846 DONE; 9847}) 9848 9849(define_insn "movua" 9850 [(set (match_operand:SI 0 "register_operand" "=z") 9851 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")] 9852 UNSPEC_MOVUA))] 9853 "TARGET_SH4A" 9854 "movua.l %1,%0" 9855 [(set_attr "type" "movua")]) 9856 9857;; We shouldn't need this, but cse replaces increments with references 9858;; to other regs before flow has a chance to create post_inc 9859;; addressing modes, and only postreload's cse_move2add brings the 9860;; increments back to a usable form. 9861(define_peephole2 9862 [(set (match_operand:SI 0 "register_operand" "") 9863 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" "")) 9864 (const_int 32) (const_int 0))) 9865 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))] 9866 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])" 9867 [(set (match_operand:SI 0 "register_operand" "") 9868 (sign_extract:SI (mem:SI (post_inc:SI 9869 (match_operand:SI 1 "register_operand" ""))) 9870 (const_int 32) (const_int 0)))] 9871 "") 9872 9873(define_expand "extv" 9874 [(set (match_operand:SI 0 "register_operand" "") 9875 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "") 9876 (match_operand 2 "const_int_operand" "") 9877 (match_operand 3 "const_int_operand" "")))] 9878 "TARGET_SH4A || TARGET_SH2A" 9879{ 9880 if (TARGET_SH2A && TARGET_BITOPS 9881 && (satisfies_constraint_Sbw (operands[1]) 9882 || satisfies_constraint_Sbv (operands[1])) 9883 && satisfies_constraint_M (operands[2]) 9884 && satisfies_constraint_K03 (operands[3])) 9885 { 9886 emit_insn (gen_bldsign_m2a (operands[1], operands[3])); 9887 if (REGNO (operands[0]) != T_REG) 9888 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG))); 9889 DONE; 9890 } 9891 if (TARGET_SH4A 9892 && INTVAL (operands[2]) == 32 9893 && INTVAL (operands[3]) == 0 9894 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32) 9895 { 9896 rtx src = adjust_address (operands[1], BLKmode, 0); 9897 set_mem_size (src, 4); 9898 emit_insn (gen_movua (operands[0], src)); 9899 DONE; 9900 } 9901 9902 FAIL; 9903}) 9904 9905(define_expand "extzv" 9906 [(set (match_operand:SI 0 "register_operand" "") 9907 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "") 9908 (match_operand 2 "const_int_operand" "") 9909 (match_operand 3 "const_int_operand" "")))] 9910 "TARGET_SH4A || TARGET_SH2A" 9911{ 9912 if (TARGET_SH2A && TARGET_BITOPS 9913 && (satisfies_constraint_Sbw (operands[1]) 9914 || satisfies_constraint_Sbv (operands[1])) 9915 && satisfies_constraint_M (operands[2]) 9916 && satisfies_constraint_K03 (operands[3])) 9917 { 9918 emit_insn (gen_bld_m2a (operands[1], operands[3])); 9919 if (REGNO (operands[0]) != T_REG) 9920 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG))); 9921 DONE; 9922 } 9923 if (TARGET_SH4A 9924 && INTVAL (operands[2]) == 32 9925 && INTVAL (operands[3]) == 0 9926 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32) 9927 { 9928 rtx src = adjust_address (operands[1], BLKmode, 0); 9929 set_mem_size (src, 4); 9930 emit_insn (gen_movua (operands[0], src)); 9931 DONE; 9932 } 9933 9934 FAIL; 9935}) 9936 9937;; ------------------------------------------------------------------------- 9938;; Extract negated single bit and zero extend it. 9939;; Generally we don't care about the exact xor const_int value, as long 9940;; as it contains the extracted bit. For simplicity, the pattern variations 9941;; that convert everything into the primary '*neg_zero_extract_0' pattern use 9942;; a xor const_int -1 value. 9943 9944(define_insn_and_split "*neg_zero_extract_0" 9945 [(set (reg:SI T_REG) 9946 (zero_extract:SI (xor:QIHISI (match_operand:QIHISI 0 "arith_reg_operand") 9947 (match_operand 1 "const_int_operand")) 9948 (const_int 1) 9949 (match_operand 2 "const_int_operand")))] 9950 "TARGET_SH1 && can_create_pseudo_p () 9951 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))" 9952 "#" 9953 "&& 1" 9954 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 2)) 9955 (const_int 0)))] 9956{ 9957 if (INTVAL (operands[2]) == 31 && <MODE>mode == SImode) 9958 { 9959 /* Use cmp/pz to extract bit 31 into the T bit. */ 9960 emit_insn (gen_cmpgesi_t (operands[0], const0_rtx)); 9961 DONE; 9962 } 9963 9964 operands[2] = GEN_INT ((1 << INTVAL (operands[2]))); 9965 if (GET_MODE (operands[0]) != SImode) 9966 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0); 9967}) 9968 9969(define_insn_and_split "*neg_zero_extract_1" 9970 [(set (reg:SI T_REG) 9971 (and:SI (not:SI (match_operand:SI 0 "arith_reg_operand")) 9972 (const_int 1)))] 9973 "TARGET_SH1" 9974 "#" 9975 "&& 1" 9976 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1)) 9977 (const_int 1) (const_int 0)))]) 9978 9979;; x & (1 << n) == 0: 0x00000000 + 1 = 1 9980;; x & (1 << n) != 0: 0xFFFFFFFF + 1 = 0 9981(define_insn_and_split "*neg_zero_extract_2" 9982 [(set (reg:SI T_REG) 9983 (plus:SI (sign_extract:SI (match_operand:QIHISI 0 "arith_reg_operand") 9984 (const_int 1) 9985 (match_operand 1 "const_int_operand")) 9986 (const_int 1)))] 9987 "TARGET_SH1 && can_create_pseudo_p ()" 9988 "#" 9989 "&& 1" 9990 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1)) 9991 (const_int 1) (match_dup 1)))]) 9992 9993;; (signed)x >> 31 + 1 = (x >= 0) ^ 1 9994(define_insn_and_split "*neg_zero_extract_3" 9995 [(set (reg:SI T_REG) 9996 (plus:SI (ashiftrt:SI (match_operand:SI 0 "arith_reg_operand") 9997 (const_int 31)) 9998 (const_int 1)))] 9999 "TARGET_SH1 && can_create_pseudo_p ()" 10000 "#" 10001 "&& 1" 10002 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1)) 10003 (const_int 1) (const_int 31)))]) 10004 10005;; This is required for some bit patterns of DImode subregs. 10006;; It looks like combine gets confused by the DImode right shift and fails 10007;; to simplify things. 10008(define_insn_and_split "*neg_zero_extract_4" 10009 [(set (reg:SI T_REG) 10010 (and:SI (and:SI 10011 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand") 10012 (match_operand 1 "const_int_operand")) 10013 (match_operand 2 "const_int_operand")) 10014 (not:SI (ashift:SI (match_operand:SI 3 "arith_reg_operand") 10015 (match_operand 4 "const_int_operand")))) 10016 (const_int 1)))] 10017 "TARGET_SH1 && can_create_pseudo_p () 10018 && INTVAL (operands[4]) > 0 10019 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))" 10020 "#" 10021 "&& 1" 10022 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1)) 10023 (const_int 1) (match_dup 2)))]) 10024 10025(define_insn_and_split "*neg_zero_extract_5" 10026 [(set (reg:SI T_REG) 10027 (and:SI (not:SI (subreg:SI 10028 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand") 10029 (match_operand 1 "const_int_operand")) 10030 0)) 10031 (const_int 1)))] 10032 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p () 10033 && INTVAL (operands[1]) < 32" 10034 "#" 10035 "&& 1" 10036 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1)) 10037 (const_int 1) (match_dup 1)))] 10038{ 10039 operands[0] = gen_lowpart (SImode, operands[0]); 10040}) 10041 10042(define_insn_and_split "*neg_zero_extract_6" 10043 [(set (reg:SI T_REG) 10044 (and:SI (not:SI (subreg:SI 10045 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand") 10046 (match_operand 1 "const_int_operand")) 10047 4)) 10048 (const_int 1)))] 10049 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p () 10050 && INTVAL (operands[1]) < 32" 10051 "#" 10052 "&& 1" 10053 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1)) 10054 (const_int 1) (match_dup 1)))] 10055{ 10056 operands[0] = gen_lowpart (SImode, operands[0]); 10057}) 10058 10059;; ------------------------------------------------------------------------- 10060;; Extract single bit and zero extend it. 10061;; All patterns store the result bit in the T bit, although that is not 10062;; always possible to do with a single insn and a nott must be appended. 10063;; The trailing nott will be optimized away in most cases. E.g. if the 10064;; extracted bit is fed into a branch condition, the condition can be 10065;; inverted and the nott will be eliminated. 10066;; FIXME: In cases where the trailing nott can't be eliminated, try to 10067;; convert it into a (not, tst) sequence, which could be better on non-SH2A. 10068 10069;; On SH2A the 'bld<mode>_reg' insn will be used if the bit position fits. 10070(define_insn_and_split "*zero_extract_0" 10071 [(set (reg:SI T_REG) 10072 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand") 10073 (const_int 1) 10074 (match_operand 1 "const_int_operand")))] 10075 "TARGET_SH1 && can_create_pseudo_p () 10076 && !(TARGET_SH2A && satisfies_constraint_K03 (operands[1]))" 10077 "#" 10078 "&& 1" 10079 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 1)) 10080 (const_int 0))) 10081 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))] 10082{ 10083 if (INTVAL (operands[1]) == 31 && <MODE>mode == SImode) 10084 { 10085 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0])); 10086 DONE; 10087 } 10088 10089 operands[1] = GEN_INT (1 << INTVAL (operands[1])); 10090 if (GET_MODE (operands[0]) != SImode) 10091 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0); 10092}) 10093 10094;; This is required for some bit patterns of DImode subregs. 10095;; It looks like combine gets confused by the DImode right shift and fails 10096;; to simplify things. 10097(define_insn_and_split "*zero_extract_1" 10098 [(set (reg:SI T_REG) 10099 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand") 10100 (const_int 1) 10101 (match_operand 1 "const_int_operand")) 10102 0))] 10103 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p () 10104 && INTVAL (operands[1]) < 32" 10105 "#" 10106 "&& 1" 10107 [(set (reg:SI T_REG) 10108 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))]) 10109 10110(define_insn_and_split "*zero_extract_2" 10111 [(set (reg:SI T_REG) 10112 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand") 10113 (const_int 1) 10114 (match_operand 1 "const_int_operand")) 10115 4))] 10116 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p () 10117 && INTVAL (operands[1]) < 32" 10118 "#" 10119 "&& 1" 10120 [(set (reg:SI T_REG) 10121 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))]) 10122 10123(define_insn_and_split "*zero_extract_3" 10124 [(set (match_operand:SI 0 "arith_reg_dest") 10125 (and:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand") 10126 (match_operand 2 "const_int_operand")) 10127 (match_operand 3 "const_int_operand"))) 10128 (clobber (reg:SI T_REG))] 10129 "TARGET_SH1 && can_create_pseudo_p () 10130 && exact_log2 (INTVAL (operands[3])) >= 0" 10131 "#" 10132 "&& 1" 10133 [(const_int 0)] 10134{ 10135 int rshift = INTVAL (operands[2]); 10136 int lshift = exact_log2 (INTVAL (operands[3])); 10137 10138 rtx tmp = gen_reg_rtx (SImode); 10139 emit_insn (gen_rtx_PARALLEL (VOIDmode, 10140 gen_rtvec (2, 10141 gen_rtx_SET (tmp, 10142 gen_rtx_ZERO_EXTRACT (SImode, operands[1], const1_rtx, 10143 GEN_INT (rshift + lshift))), 10144 gen_rtx_CLOBBER (VOIDmode, get_t_reg_rtx ())))); 10145 emit_insn (gen_ashlsi3 (operands[0], tmp, GEN_INT (lshift))); 10146}) 10147 10148;; ------------------------------------------------------------------------- 10149;; SH2A instructions for bitwise operations. 10150;; FIXME: Convert multiple instruction insns to insn_and_split. 10151;; FIXME: Use iterators to fold at least and,xor,or insn variations. 10152 10153;; Clear a bit in a memory location. 10154(define_insn "bclr_m2a" 10155 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv") 10156 (and:QI 10157 (not:QI (ashift:QI (const_int 1) 10158 (match_operand:QI 1 "const_int_operand" "K03,K03"))) 10159 (match_dup 0)))] 10160 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10161 "@ 10162 bclr.b %1,%0 10163 bclr.b %1,@(0,%t0)" 10164[(set_attr "length" "4,4")]) 10165 10166(define_insn "bclrmem_m2a" 10167 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv") 10168 (and:QI (match_dup 0) 10169 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))] 10170 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS" 10171 "@ 10172 bclr.b %W1,%0 10173 bclr.b %W1,@(0,%t0)" 10174 [(set_attr "length" "4,4")]) 10175 10176;; Set a bit in a memory location. 10177(define_insn "bset_m2a" 10178 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv") 10179 (ior:QI 10180 (ashift:QI (const_int 1) 10181 (match_operand:QI 1 "const_int_operand" "K03,K03")) 10182 (match_dup 0)))] 10183 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10184 "@ 10185 bset.b %1,%0 10186 bset.b %1,@(0,%t0)" 10187 [(set_attr "length" "4,4")]) 10188 10189(define_insn "bsetmem_m2a" 10190 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv") 10191 (ior:QI (match_dup 0) 10192 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))] 10193 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS" 10194 "@ 10195 bset.b %V1,%0 10196 bset.b %V1,@(0,%t0)" 10197 [(set_attr "length" "4,4")]) 10198 10199;;; Transfer the contents of the T bit to a specified bit of memory. 10200(define_insn "bst_m2a" 10201 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m") 10202 (if_then_else (eq (reg:SI T_REG) (const_int 0)) 10203 (and:QI 10204 (not:QI (ashift:QI (const_int 1) 10205 (match_operand:QI 1 "const_int_operand" "K03,K03"))) 10206 (match_dup 0)) 10207 (ior:QI 10208 (ashift:QI (const_int 1) (match_dup 1)) 10209 (match_dup 0))))] 10210 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10211 "@ 10212 bst.b %1,%0 10213 bst.b %1,@(0,%t0)" 10214 [(set_attr "length" "4")]) 10215 10216;; Store a specified bit of memory in the T bit. 10217(define_insn "bld_m2a" 10218 [(set (reg:SI T_REG) 10219 (zero_extract:SI 10220 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv") 10221 (const_int 1) 10222 (match_operand 1 "const_int_operand" "K03,K03")))] 10223 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10224 "@ 10225 bld.b %1,%0 10226 bld.b %1,@(0,%t0)" 10227 [(set_attr "length" "4,4")]) 10228 10229;; Store a specified bit of memory in the T bit. 10230(define_insn "bldsign_m2a" 10231 [(set (reg:SI T_REG) 10232 (sign_extract:SI 10233 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m") 10234 (const_int 1) 10235 (match_operand 1 "const_int_operand" "K03,K03")))] 10236 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10237 "@ 10238 bld.b %1,%0 10239 bld.b %1,@(0,%t0)" 10240 [(set_attr "length" "4,4")]) 10241 10242;; Store a specified bit of the LSB 8 bits of a register in the T bit. 10243(define_insn "bld<mode>_reg" 10244 [(set (reg:SI T_REG) 10245 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand" "r") 10246 (const_int 1) 10247 (match_operand 1 "const_int_operand" "K03")))] 10248 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])" 10249 "bld %1,%0") 10250 10251;; Take logical and of a specified bit of memory with the T bit and 10252;; store its result in the T bit. 10253(define_insn "band_m2a" 10254 [(set (reg:SI T_REG) 10255 (and:SI (reg:SI T_REG) 10256 (zero_extract:SI 10257 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m") 10258 (const_int 1) 10259 (match_operand 1 "const_int_operand" "K03,K03"))))] 10260 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10261 "@ 10262 band.b %1,%0 10263 band.b %1,@(0,%t0)" 10264 [(set_attr "length" "4,4")]) 10265 10266(define_insn "bandreg_m2a" 10267 [(set (match_operand:SI 0 "register_operand" "=r,r") 10268 (and:SI (zero_extract:SI 10269 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv") 10270 (const_int 1) 10271 (match_operand 2 "const_int_operand" "K03,K03")) 10272 (match_operand:SI 3 "register_operand" "r,r")))] 10273 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])" 10274{ 10275 static const char* alt[] = 10276 { 10277 "band.b %2,%1" "\n" 10278 " movt %0", 10279 10280 "band.b %2,@(0,%t1)" "\n" 10281 " movt %0" 10282 }; 10283 return alt[which_alternative]; 10284} 10285 [(set_attr "length" "6,6")]) 10286 10287;; Take logical or of a specified bit of memory with the T bit and 10288;; store its result in the T bit. 10289(define_insn "bor_m2a" 10290 [(set (reg:SI T_REG) 10291 (ior:SI (reg:SI T_REG) 10292 (zero_extract:SI 10293 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m") 10294 (const_int 1) 10295 (match_operand 1 "const_int_operand" "K03,K03"))))] 10296 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10297 "@ 10298 bor.b %1,%0 10299 bor.b %1,@(0,%t0)" 10300 [(set_attr "length" "4,4")]) 10301 10302(define_insn "borreg_m2a" 10303 [(set (match_operand:SI 0 "register_operand" "=r,r") 10304 (ior:SI (zero_extract:SI 10305 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv") 10306 (const_int 1) 10307 (match_operand 2 "const_int_operand" "K03,K03")) 10308 (match_operand:SI 3 "register_operand" "=r,r")))] 10309 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])" 10310{ 10311 static const char* alt[] = 10312 { 10313 "bor.b %2,%1" "\n" 10314 " movt %0", 10315 10316 "bor.b %2,@(0,%t1)" "\n" 10317 " movt %0" 10318 }; 10319 return alt[which_alternative]; 10320} 10321 [(set_attr "length" "6,6")]) 10322 10323;; Take exclusive or of a specified bit of memory with the T bit and 10324;; store its result in the T bit. 10325(define_insn "bxor_m2a" 10326 [(set (reg:SI T_REG) 10327 (xor:SI (reg:SI T_REG) 10328 (zero_extract:SI 10329 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m") 10330 (const_int 1) 10331 (match_operand 1 "const_int_operand" "K03,K03"))))] 10332 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])" 10333 "@ 10334 bxor.b %1,%0 10335 bxor.b %1,@(0,%t0)" 10336 [(set_attr "length" "4,4")]) 10337 10338(define_insn "bxorreg_m2a" 10339 [(set (match_operand:SI 0 "register_operand" "=r,r") 10340 (xor:SI (zero_extract:SI 10341 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv") 10342 (const_int 1) 10343 (match_operand 2 "const_int_operand" "K03,K03")) 10344 (match_operand:SI 3 "register_operand" "=r,r")))] 10345 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])" 10346{ 10347 static const char* alt[] = 10348 { 10349 "bxor.b %2,%1" "\n" 10350 " movt %0", 10351 10352 "bxor.b %2,@(0,%t1)" "\n" 10353 " movt %0" 10354 }; 10355 return alt[which_alternative]; 10356} 10357 [(set_attr "length" "6,6")]) 10358 10359;; ------------------------------------------------------------------------- 10360;; Peepholes 10361;; ------------------------------------------------------------------------- 10362;; This matches cases where the bit in a memory location is set. 10363(define_peephole2 10364 [(set (match_operand:SI 0 "register_operand") 10365 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand"))) 10366 (set (match_dup 0) 10367 (ior:SI (match_dup 0) 10368 (match_operand:SI 2 "const_int_operand"))) 10369 (set (match_dup 1) 10370 (match_operand 3 "arith_reg_operand"))] 10371 "TARGET_SH2A && TARGET_BITOPS 10372 && satisfies_constraint_Pso (operands[2]) 10373 && REGNO (operands[0]) == REGNO (operands[3])" 10374 [(set (match_dup 1) 10375 (ior:QI (match_dup 1) (match_dup 2)))] 10376 "") 10377 10378;; This matches cases where the bit in a memory location is cleared. 10379(define_peephole2 10380 [(set (match_operand:SI 0 "register_operand") 10381 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand"))) 10382 (set (match_dup 0) 10383 (and:SI (match_dup 0) 10384 (match_operand:SI 2 "const_int_operand"))) 10385 (set (match_dup 1) 10386 (match_operand 3 "arith_reg_operand"))] 10387 "TARGET_SH2A && TARGET_BITOPS 10388 && satisfies_constraint_Psz (operands[2]) 10389 && REGNO (operands[0]) == REGNO (operands[3])" 10390 [(set (match_dup 1) 10391 (and:QI (match_dup 1) (match_dup 2)))] 10392 "") 10393 10394;; This matches cases where a stack pointer increment at the start of the 10395;; epilogue combines with a stack slot read loading the return value. 10396(define_peephole 10397 [(set (match_operand:SI 0 "arith_reg_operand" "") 10398 (mem:SI (match_operand:SI 1 "arith_reg_operand" ""))) 10399 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))] 10400 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])" 10401 "mov.l @%1+,%0") 10402 10403;; See the comment on the dt combiner pattern above. 10404(define_peephole 10405 [(set (match_operand:SI 0 "arith_reg_operand" "=r") 10406 (plus:SI (match_dup 0) 10407 (const_int -1))) 10408 (set (reg:SI T_REG) 10409 (eq:SI (match_dup 0) (const_int 0)))] 10410 "TARGET_SH2" 10411 "dt %0") 10412 10413;; The following peepholes fold load sequences for which reload was not 10414;; able to generate a displacement addressing move insn. 10415;; This can happen when reload has to transform a move insn 10416;; without displacement into one with displacement. Or when reload can't 10417;; fit a displacement into the insn's constraints. In the latter case, the 10418;; load destination reg remains at r0, which reload compensates by inserting 10419;; another mov insn. 10420 10421;; Fold sequence: 10422;; mov #54,r0 10423;; mov.{b,w} @(r0,r15),r0 10424;; mov r0,r3 10425;; into: 10426;; mov.{b,w} @(54,r15),r3 10427;; 10428(define_peephole2 10429 [(set (match_operand:SI 0 "arith_reg_dest" "") 10430 (match_operand:SI 1 "const_int_operand" "")) 10431 (set (match_operand:SI 2 "arith_reg_dest" "") 10432 (sign_extend:SI 10433 (mem:QI (plus:SI (match_dup 0) 10434 (match_operand:SI 3 "arith_reg_operand" ""))))) 10435 (set (match_operand:QI 4 "arith_reg_dest" "") 10436 (match_operand:QI 5 "arith_reg_operand" ""))] 10437 "TARGET_SH2A 10438 && sh_legitimate_index_p (QImode, operands[1], true, true) 10439 && REGNO (operands[2]) == REGNO (operands[5]) 10440 && peep2_reg_dead_p (3, operands[5])" 10441 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))] 10442 "") 10443 10444(define_peephole2 10445 [(set (match_operand:SI 0 "arith_reg_dest" "") 10446 (match_operand:SI 1 "const_int_operand" "")) 10447 (set (match_operand:SI 2 "arith_reg_dest" "") 10448 (sign_extend:SI 10449 (mem:HI (plus:SI (match_dup 0) 10450 (match_operand:SI 3 "arith_reg_operand" ""))))) 10451 (set (match_operand:HI 4 "arith_reg_dest" "") 10452 (match_operand:HI 5 "arith_reg_operand" ""))] 10453 "TARGET_SH2A 10454 && sh_legitimate_index_p (HImode, operands[1], true, true) 10455 && REGNO (operands[2]) == REGNO (operands[5]) 10456 && peep2_reg_dead_p (3, operands[5])" 10457 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))] 10458 "") 10459 10460;; Fold sequence: 10461;; mov #54,r0 10462;; mov.{b,w} @(r0,r15),r1 10463;; into: 10464;; mov.{b,w} @(54,r15),r1 10465;; 10466(define_peephole2 10467 [(set (match_operand:SI 0 "arith_reg_dest" "") 10468 (match_operand:SI 1 "const_int_operand" "")) 10469 (set (match_operand:SI 2 "arith_reg_dest" "") 10470 (sign_extend:SI 10471 (mem:QI (plus:SI (match_dup 0) 10472 (match_operand:SI 3 "arith_reg_operand" "")))))] 10473 "TARGET_SH2A 10474 && sh_legitimate_index_p (QImode, operands[1], true, true) 10475 && (peep2_reg_dead_p (2, operands[0]) 10476 || REGNO (operands[0]) == REGNO (operands[2]))" 10477 [(set (match_dup 2) 10478 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))] 10479 "") 10480 10481(define_peephole2 10482 [(set (match_operand:SI 0 "arith_reg_dest" "") 10483 (match_operand:SI 1 "const_int_operand" "")) 10484 (set (match_operand:SI 2 "arith_reg_dest" "") 10485 (sign_extend:SI 10486 (mem:HI (plus:SI (match_dup 0) 10487 (match_operand:SI 3 "arith_reg_operand" "")))))] 10488 "TARGET_SH2A 10489 && sh_legitimate_index_p (HImode, operands[1], true, true) 10490 && (peep2_reg_dead_p (2, operands[0]) 10491 || REGNO (operands[0]) == REGNO (operands[2]))" 10492 [(set (match_dup 2) 10493 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))] 10494 "") 10495 10496;; Fold sequence: 10497;; mov.{b,w} @(r0,r15),r0 10498;; mov r0,r3 10499;; into: 10500;; mov.{b,w} @(r0,r15),r3 10501;; 10502;; This can happen when initially a displacement address is picked, where 10503;; the destination reg is fixed to r0, and then the address is transformed 10504;; into 'r0 + reg'. 10505(define_peephole2 10506 [(set (match_operand:SI 0 "arith_reg_dest" "") 10507 (sign_extend:SI 10508 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "") 10509 (match_operand:SI 2 "arith_reg_operand" ""))))) 10510 (set (match_operand:QI 3 "arith_reg_dest" "") 10511 (match_operand:QI 4 "arith_reg_operand" ""))] 10512 "TARGET_SH1 10513 && REGNO (operands[0]) == REGNO (operands[4]) 10514 && peep2_reg_dead_p (2, operands[0])" 10515 [(set (match_dup 3) 10516 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))] 10517 "") 10518 10519(define_peephole2 10520 [(set (match_operand:SI 0 "arith_reg_dest" "") 10521 (sign_extend:SI 10522 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "") 10523 (match_operand:SI 2 "arith_reg_operand" ""))))) 10524 (set (match_operand:HI 3 "arith_reg_dest" "") 10525 (match_operand:HI 4 "arith_reg_operand" ""))] 10526 "TARGET_SH1 10527 && REGNO (operands[0]) == REGNO (operands[4]) 10528 && peep2_reg_dead_p (2, operands[0])" 10529 [(set (match_dup 3) 10530 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))] 10531 "") 10532 10533;; extu.bw a,b 10534;; mov b,c -> extu.bw a,c 10535(define_peephole2 10536 [(set (match_operand:SI 0 "arith_reg_dest") 10537 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand"))) 10538 (set (match_operand:SI 2 "arith_reg_dest") 10539 (match_dup 0))] 10540 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])" 10541 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))]) 10542 10543;; mov r0,r1 10544;; extu.bw r1,r1 -> extu.bw r0,r1 10545(define_peephole2 10546 [(set (match_operand 0 "arith_reg_dest") 10547 (match_operand 1 "arith_reg_operand")) 10548 (set (match_operand:SI 2 "arith_reg_dest") 10549 (zero_extend:SI (match_operand:QIHI 3 "arith_reg_operand")))] 10550 "TARGET_SH1 10551 && REGNO (operands[0]) == REGNO (operands[3]) 10552 && (REGNO (operands[0]) == REGNO (operands[2]) 10553 || peep2_reg_dead_p (2, operands[0]))" 10554 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))] 10555{ 10556 operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1])); 10557}) 10558 10559;; mov a,b 10560;; mov b,a -> < nop > 10561(define_peephole2 10562 [(set (match_operand 0 "register_operand") 10563 (match_operand 1 "register_operand")) 10564 (set (match_operand 2 "register_operand") 10565 (match_operand 3 "register_operand"))] 10566 "TARGET_SH1 10567 && REGNO (operands[0]) == REGNO (operands[3]) 10568 && REGNO (operands[1]) == REGNO (operands[2]) 10569 && peep2_reg_dead_p (2, operands[3])" 10570 [(const_int 0)]) 10571 10572;; mov #3,r4 10573;; and r4,r1 -> mov r1,r0 10574;; mov r1,r0 and #3,r0 10575(define_code_iterator ANDIORXOR [and ior xor]) 10576(define_peephole2 10577 [(set (match_operand:SI 0 "register_operand") 10578 (match_operand:SI 1 "const_logical_operand")) 10579 (set (match_operand:SI 2) (ANDIORXOR:SI (match_dup 2) (match_dup 0))) 10580 (set (reg:SI R0_REG) (match_dup 2))] 10581 "TARGET_SH1 10582 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])" 10583 [(set (reg:SI R0_REG) (match_dup 2)) 10584 (set (reg:SI R0_REG) (ANDIORXOR:SI (reg:SI R0_REG) (match_dup 1)))]) 10585 10586;; ... r2,r0 ... r2,r0 10587;; or r1,r0 -> or r0,r1 10588;; mov r0,r1 10589;; (r0 dead) 10590(define_code_iterator ANDIORXORPLUS [and ior xor plus]) 10591(define_peephole2 10592 [(set (match_operand:SI 0 "arith_reg_dest") 10593 (ANDIORXORPLUS:SI (match_dup 0) (match_operand:SI 1 "arith_reg_dest"))) 10594 (set (match_dup 1) (match_dup 0))] 10595 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])" 10596 [(set (match_dup 1) (ANDIORXORPLUS:SI (match_dup 1) (match_dup 0)))]) 10597 10598;; mov r12,r0 10599;; add #-48,r0 -> add #-48,r12 10600;; mov.l r0,@(4,r10) mov.l r12,@(4,r10) 10601;; (r12 dead) 10602(define_peephole2 10603 [(set (match_operand:SI 0 "arith_reg_dest") 10604 (match_operand:SI 1 "arith_reg_dest")) 10605 (set (match_dup 0) (plus:SI (match_dup 0) 10606 (match_operand:SI 2 "const_int_operand"))) 10607 (set (match_operand:SI 3 "general_movdst_operand") (match_dup 0))] 10608 "TARGET_SH1 10609 && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])" 10610 [(const_int 0)] 10611{ 10612 emit_insn (gen_addsi3 (operands[1], operands[1], operands[2])); 10613 sh_peephole_emit_move_insn (operands[3], operands[1]); 10614}) 10615 10616;; mov.l @(r0,r9),r1 10617;; mov r1,r0 -> mov @(r0,r9),r0 10618(define_peephole2 10619 [(set (match_operand:SI 0 "arith_reg_dest") 10620 (match_operand:SI 1 "general_movsrc_operand")) 10621 (set (match_operand:SI 2 "arith_reg_dest") 10622 (match_dup 0))] 10623 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])" 10624 [(const_int 0)] 10625{ 10626 sh_peephole_emit_move_insn (operands[2], operands[1]); 10627}) 10628 10629(define_peephole2 10630 [(set (match_operand:QIHI 0 "register_operand") 10631 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand")) 10632 (set (match_operand:QIHI 2 "register_operand") 10633 (match_dup 0))] 10634 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])" 10635 [(const_int 0)] 10636{ 10637 sh_peephole_emit_move_insn (operands[2], operands[1]); 10638}) 10639 10640(define_peephole2 10641 [(set (match_operand:SI 0 "arith_reg_dest") 10642 (sign_extend:SI (match_operand:QIHI 1 "movsrc_no_disp_mem_operand"))) 10643 (set (match_operand:SI 2 "arith_reg_dest") 10644 (match_dup 0))] 10645 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])" 10646 [(const_int 0)] 10647{ 10648 sh_check_add_incdec_notes (emit_insn (gen_extend<mode>si2 (operands[2], 10649 sh_remove_overlapping_post_inc (operands[2], operands[1])))); 10650}) 10651 10652;; mov.w @(18,r1),r0 (r0 = HImode) 10653;; mov r0,r1 (r0 = r1 = HImode) mov.w @(18,r1),r0 10654;; ... ..,r13 (r13 = SImode) -> ... ..,r13 10655;; tst r1,r13 tst r0,r13 10656(define_peephole2 10657 [(set (match_operand 0 "arith_reg_dest") 10658 (match_operand 1 "arith_reg_dest")) 10659 (set (match_operand:SI 2 "arith_reg_dest") 10660 (match_operand:SI 3)) 10661 (set (reg:SI T_REG) 10662 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand") 10663 (match_operand:SI 5 "arith_reg_operand")) 10664 (const_int 0)))] 10665 "TARGET_SH1 10666 && peep2_reg_dead_p (3, operands[0]) 10667 && !reg_overlap_mentioned_p (operands[0], operands[3]) 10668 && (REGNO (operands[0]) == REGNO (operands[4]) 10669 || REGNO (operands[0]) == REGNO (operands[5])) 10670 && (REGNO (operands[2]) == REGNO (operands[4]) 10671 || REGNO (operands[2]) == REGNO (operands[5]))" 10672 [(const_int 0)] 10673{ 10674 if (REGNO (operands[1]) == REGNO (operands[2])) 10675 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0])); 10676 10677 // We don't know what the new set insn will be in detail. Just make sure 10678 // that it still can be recognized and the constraints are satisfied. 10679 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2], 10680 sh_remove_overlapping_post_inc (operands[2], operands[3]))); 10681 10682 recog_data_d prev_recog_data = recog_data; 10683 bool i_invalid = insn_invalid_p (i, false); 10684 recog_data = prev_recog_data; 10685 10686 if (i_invalid) 10687 FAIL; 10688 10689 sh_check_add_incdec_notes (i); 10690 10691 emit_insn (gen_tstsi_t (operands[2], 10692 gen_rtx_REG (SImode, (REGNO (operands[1]))))); 10693}) 10694 10695;; mov.w @(18,r1),r0 (r0 = HImode) 10696;; ... ..,r13 (r13 = SImode) mov.w @(18,r1),r0 10697;; mov r0,r1 (r0 = r1 = HImode) -> ... ..,r13 10698;; tst r1,r13 tst r0,r13 10699(define_peephole2 10700 [(set (match_operand:SI 2 "arith_reg_dest") 10701 (match_operand:SI 3)) 10702 (set (match_operand 0 "arith_reg_dest") 10703 (match_operand 1 "arith_reg_operand")) 10704 (set (reg:SI T_REG) 10705 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand") 10706 (match_operand:SI 5 "arith_reg_operand")) 10707 (const_int 0)))] 10708 "TARGET_SH1 10709 && peep2_reg_dead_p (3, operands[0]) 10710 && !reg_overlap_mentioned_p (operands[0], operands[3]) 10711 && (REGNO (operands[0]) == REGNO (operands[4]) 10712 || REGNO (operands[0]) == REGNO (operands[5])) 10713 && (REGNO (operands[2]) == REGNO (operands[4]) 10714 || REGNO (operands[2]) == REGNO (operands[5]))" 10715 [(const_int 0)] 10716{ 10717 // We don't know what the new set insn will be in detail. Just make sure 10718 // that it still can be recognized and the constraints are satisfied. 10719 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2], 10720 sh_remove_overlapping_post_inc (operands[2], operands[3]))); 10721 10722 recog_data_d prev_recog_data = recog_data; 10723 bool i_invalid = insn_invalid_p (i, false); 10724 recog_data = prev_recog_data; 10725 10726 if (i_invalid) 10727 FAIL; 10728 10729 sh_check_add_incdec_notes (i); 10730 10731 emit_insn (gen_tstsi_t (operands[2], 10732 gen_rtx_REG (SImode, (REGNO (operands[1]))))); 10733}) 10734 10735;; This is not a peephole, but it's here because it's actually supposed 10736;; to be one. It tries to convert a sequence such as 10737;; movt r2 -> movt r2 10738;; movt r13 mov r2,r13 10739;; This gives the schduler a bit more freedom to hoist a following 10740;; comparison insn. Moreover, it the reg-reg mov insn is MT group which has 10741;; better chances for parallel execution. 10742;; We can do this with a peephole2 pattern, but then the cprop_hardreg 10743;; pass will revert the change. See also PR 64331. 10744;; Thus do it manually in one of the split passes after register allocation. 10745;; Sometimes the cprop_hardreg pass might also eliminate the reg-reg copy. 10746(define_split 10747 [(set (match_operand:SI 0 "arith_reg_dest") 10748 (match_operand:SI 1 "t_reg_operand"))] 10749 "TARGET_SH1 && reload_completed" 10750 [(set (match_dup 0) (match_dup 1))] 10751{ 10752 rtx t_reg = get_t_reg_rtx (); 10753 10754 for (rtx_insn* i = prev_nonnote_insn_bb (curr_insn); i != NULL; 10755 i = prev_nonnote_insn_bb (i)) 10756 { 10757 if (!INSN_P (i) || DEBUG_INSN_P (i)) 10758 continue; 10759 10760 if (modified_in_p (t_reg, i) || BARRIER_P (i)) 10761 FAIL; 10762 10763 if (sh_is_movt_insn (i)) 10764 { 10765 rtx r = sh_movt_set_dest (i); 10766 if (!modified_between_p (r, i, curr_insn)) 10767 { 10768 operands[1] = r; 10769 break; 10770 } 10771 } 10772 } 10773}) 10774 10775(define_peephole 10776 [(set (match_operand:SI 0 "register_operand" "=r") 10777 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) 10778 (set (mem:SF (match_dup 0)) 10779 (match_operand:SF 2 "general_movsrc_operand" ""))] 10780 "TARGET_SH1 && REGNO (operands[0]) == 0 10781 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16) 10782 || (GET_CODE (operands[2]) == SUBREG 10783 && REGNO (SUBREG_REG (operands[2])) < 16)) 10784 && reg_unused_after (operands[0], insn)" 10785 "mov.l %2,@(%0,%1)") 10786 10787(define_peephole 10788 [(set (match_operand:SI 0 "register_operand" "=r") 10789 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) 10790 (set (match_operand:SF 2 "general_movdst_operand" "") 10791 10792 (mem:SF (match_dup 0)))] 10793 "TARGET_SH1 && REGNO (operands[0]) == 0 10794 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16) 10795 || (GET_CODE (operands[2]) == SUBREG 10796 && REGNO (SUBREG_REG (operands[2])) < 16)) 10797 && reg_unused_after (operands[0], insn)" 10798 "mov.l @(%0,%1),%2") 10799 10800(define_peephole 10801 [(set (match_operand:SI 0 "register_operand" "=r") 10802 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) 10803 (set (mem:SF (match_dup 0)) 10804 (match_operand:SF 2 "general_movsrc_operand" ""))] 10805 "TARGET_SH2E && REGNO (operands[0]) == 0 10806 && ((REG_P (operands[2]) 10807 && FP_OR_XD_REGISTER_P (REGNO (operands[2]))) 10808 || (GET_CODE (operands[2]) == SUBREG 10809 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2]))))) 10810 && reg_unused_after (operands[0], insn)" 10811 "fmov{.s|} %2,@(%0,%1)") 10812 10813(define_peephole 10814 [(set (match_operand:SI 0 "register_operand" "=r") 10815 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r"))) 10816 (set (match_operand:SF 2 "general_movdst_operand" "") 10817 10818 (mem:SF (match_dup 0)))] 10819 "TARGET_SH2E && REGNO (operands[0]) == 0 10820 && ((REG_P (operands[2]) 10821 && FP_OR_XD_REGISTER_P (REGNO (operands[2]))) 10822 || (GET_CODE (operands[2]) == SUBREG 10823 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2]))))) 10824 && reg_unused_after (operands[0], insn)" 10825 "fmov{.s|} @(%0,%1),%2") 10826 10827;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). 10828(define_insn "sp_switch_1" 10829 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")] 10830 UNSPECV_SP_SWITCH_B))] 10831 "TARGET_SH1" 10832{ 10833 return "mov.l r0,@-r15" "\n" 10834 " mov.l %0,r0" "\n" 10835 " mov.l @r0,r0" "\n" 10836 " mov.l r15,@-r0" "\n" 10837 " mov r0,r15"; 10838} 10839 [(set_attr "length" "10")]) 10840 10841;; Switch back to the original stack for interrupt functions with the 10842;; sp_switch attribute. 10843(define_insn "sp_switch_2" 10844 [(unspec_volatile [(const_int 0)] 10845 UNSPECV_SP_SWITCH_E)] 10846 "TARGET_SH1" 10847{ 10848 return "mov.l @r15,r15" "\n" 10849 " mov.l @r15+,r0"; 10850} 10851 [(set_attr "length" "4")]) 10852 10853 10854;; In user mode, the "pref" instruction will raise a RADDERR exception 10855;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable 10856;; implementation of __builtin_prefetch for VxWorks RTPs. 10857(define_expand "prefetch" 10858 [(prefetch (match_operand 0 "address_operand" "") 10859 (match_operand:SI 1 "const_int_operand" "") 10860 (match_operand:SI 2 "const_int_operand" ""))] 10861 "(TARGET_SH2A || TARGET_SH3) && !TARGET_VXWORKS_RTP") 10862 10863(define_insn "*prefetch" 10864 [(prefetch (match_operand:SI 0 "register_operand" "r") 10865 (match_operand:SI 1 "const_int_operand" "n") 10866 (match_operand:SI 2 "const_int_operand" "n"))] 10867 "(TARGET_SH2A || TARGET_SH3) && ! TARGET_VXWORKS_RTP" 10868 "pref @%0" 10869 [(set_attr "type" "other")]) 10870 10871;; ------------------------------------------------------------------------- 10872;; Stack Protector Patterns 10873;; ------------------------------------------------------------------------- 10874 10875(define_expand "stack_protect_set" 10876 [(set (match_operand 0 "memory_operand" "") 10877 (match_operand 1 "memory_operand" ""))] 10878 "" 10879{ 10880 emit_insn (gen_stack_protect_set_si (operands[0], operands[1])); 10881 DONE; 10882}) 10883 10884(define_insn "stack_protect_set_si" 10885 [(set (match_operand:SI 0 "memory_operand" "=m") 10886 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) 10887 (set (match_scratch:SI 2 "=&r") (const_int 0))] 10888 "" 10889{ 10890 return "mov.l %1,%2" "\n" 10891 " mov.l %2,%0" "\n" 10892 " mov #0,%2"; 10893} 10894 [(set_attr "type" "other") 10895 (set_attr "length" "6")]) 10896 10897(define_expand "stack_protect_test" 10898 [(match_operand 0 "memory_operand" "") 10899 (match_operand 1 "memory_operand" "") 10900 (match_operand 2 "" "")] 10901 "" 10902{ 10903 emit_insn (gen_stack_protect_test_si (operands[0], operands[1])); 10904 emit_jump_insn (gen_branch_true (operands[2])); 10905 DONE; 10906}) 10907 10908(define_insn "stack_protect_test_si" 10909 [(set (reg:SI T_REG) 10910 (unspec:SI [(match_operand:SI 0 "memory_operand" "m") 10911 (match_operand:SI 1 "memory_operand" "m")] 10912 UNSPEC_SP_TEST)) 10913 (set (match_scratch:SI 2 "=&r") (const_int 0)) 10914 (set (match_scratch:SI 3 "=&r") (const_int 0))] 10915 "" 10916{ 10917 return "mov.l %0,%2" "\n" 10918 " mov.l %1,%3" "\n" 10919 " cmp/eq %2,%3" "\n" 10920 " mov #0,%2" "\n" 10921 " mov #0,%3"; 10922} 10923 [(set_attr "type" "other") 10924 (set_attr "length" "10")]) 10925 10926;; ------------------------------------------------------------------------- 10927;; Atomic operations 10928;; ------------------------------------------------------------------------- 10929 10930(include "sync.md") 10931