1;; Scheduling description for z196 (cpu 2817).
2;;   Copyright (C) 2010-2020 Free Software Foundation, Inc.
3;;   Contributed by Christian Borntraeger (Christian.Borntraeger@de.ibm.com)
4;;                  Andreas Krebbel (Andreas.Krebbel@de.ibm.com)
5
6;; This file is part of GCC.
7
8;; GCC is free software; you can redistribute it and/or modify it under
9;; the terms of the GNU General Public License as published by the Free
10;; Software Foundation; either version 3, or (at your option) any later
11;; version.
12
13;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
15;; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
16;; for more details.
17
18;; You should have received a copy of the GNU General Public License
19;; along with GCC; see the file COPYING3.  If not see
20;; <http://www.gnu.org/licenses/>.
21
22(define_automaton "z196_ipu")
23
24;; Fetch + Decoder
25(define_cpu_unit "z196_g1" "z196_ipu")
26(define_cpu_unit "z196_g2" "z196_ipu")
27(define_cpu_unit "z196_g3" "z196_ipu")
28(define_cpu_unit "z196_cr1" "z196_ipu")
29(define_cpu_unit "z196_cr2" "z196_ipu")
30(define_cpu_unit "z196_cr3" "z196_ipu")
31
32(final_presence_set "z196_g2" "z196_g1")
33(final_presence_set "z196_g3" "z196_g2")
34(final_presence_set "z196_cr2" "z196_cr1")
35(final_presence_set "z196_cr3" "z196_cr2")
36(exclusion_set "z196_g1" "z196_cr1")
37
38;; Instructions can be groupable, end a group, or be alone in a group.
39(define_reservation "z196_simple" "( z196_g1 | z196_g2 | z196_g3 )")
40(define_reservation "z196_ends" "( z196_g3 | ( z196_g2 + z196_g3 ) | ( z196_g1 + z196_g2 + z196_g3 ) )")
41
42;; Try to keep cracked and alone insns together in a clump.  This will also
43;; improve the clumping of "normal" insns.  We also allow crackes insns
44;; to go as a last instruction together with normal ones.
45(define_reservation "z196_crack"  "( z196_cr1 | z196_cr2 | z196_cr3 | z196_g3)")
46(define_reservation "z196_alone"  "( z196_cr1 | z196_cr2 | z196_cr3 )")
47
48;; Most simple instruction a fast enough to be handled by OOO even with
49;; latency == 0.  This reduces life ranges and spilling. We want to increase
50;; life range for longer running ops, though, thats why we do not use
51;; -fno-schedule-insns.
52(define_insn_reservation "z196_simple_LSU" 0
53  (and (eq_attr "cpu" "z196")
54       (and (eq_attr "type" "load,store,lr")
55            (eq_attr "z196prop" "none")))
56  "z196_simple")
57
58(define_insn_reservation "z196_simple_FXU" 0
59  (and (eq_attr "cpu" "z196")
60       (and (eq_attr "type" "integer,la,larl,other")
61            (and (eq_attr "z196prop" "none")
62                 (eq_attr "op_type" "RR"))))
63  "z196_simple")
64
65(define_insn_reservation "z196_simple_DUAL" 0
66  (and (eq_attr "cpu" "z196")
67       (and (eq_attr "type" "integer,la,larl,other")
68            (and (eq_attr "z196prop" "none")
69                 (eq_attr "op_type" "!RR"))))
70  "z196_simple")
71
72(define_insn_reservation "z196_cracked" 0
73  (and (eq_attr "cpu" "z196")
74       (and (eq_attr "type" "integer,la,larl,load,lr,store,other")
75            (eq_attr "z196prop" "z196_cracked")))
76  "z196_crack")
77
78(define_insn_reservation "z196_alone" 0
79  (and (eq_attr "cpu" "z196")
80       (and (eq_attr "type" "integer,la,larl,load,lr,store,other")
81            (eq_attr "z196prop" "z196_alone")))
82  "z196_alone")
83
84(define_insn_reservation "z196_ends" 0
85  (and (eq_attr "cpu" "z196")
86       (and (eq_attr "type" "integer,la,larl,load,lr,store,other")
87            (eq_attr "z196prop" "z196_ends")))
88  "z196_ends")
89
90(define_insn_reservation "z196_branch" 0
91  (and (eq_attr "cpu" "z196")
92       (eq_attr "type" "branch"))
93  "z196_ends")
94
95(define_insn_reservation "z196_call" 0
96  (and (eq_attr "cpu" "z196")
97       (eq_attr "type" "jsr"))
98  "z196_ends")
99
100(define_insn_reservation "z196_mul_hi" 10
101  (and (eq_attr "cpu" "z196")
102       (eq_attr "type" "imulhi"))
103  "z196_simple")
104
105(define_insn_reservation "z196_mul_si" 12
106  (and (eq_attr "cpu" "z196")
107       (eq_attr "type" "imulsi"))
108  "z196_simple")
109
110(define_insn_reservation "z196_mul_di" 14
111  (and (eq_attr "cpu" "z196")
112       (eq_attr "type" "imuldi"))
113  "z196_simple")
114
115(define_insn_reservation "z196_div" 73
116  (and (eq_attr "cpu" "z196")
117       (eq_attr "type" "idiv"))
118  "z196_alone")
119
120(define_insn_reservation "z196_sem" 0
121  (and (eq_attr "cpu" "z196")
122       (eq_attr "type" "sem"))
123  "z196_crack")
124
125(define_insn_reservation "z196_cs" 0
126  (and (eq_attr "cpu" "z196")
127       (eq_attr "type" "cs"))
128  "z196_crack")
129
130(define_insn_reservation "z196_vs" 0
131  (and (eq_attr "cpu" "z196")
132       (eq_attr "type" "vs"))
133  "z196_alone")
134
135(define_insn_reservation "z196_lm_stm" 0
136  (and (eq_attr "cpu" "z196")
137       (eq_attr "type" "stm,lm"))
138  "z196_crack")
139
140
141;;
142;; Binary Floating Point
143;;
144
145(define_insn_reservation "z196_fsimptf" 18
146  (and (eq_attr "cpu" "z196")
147       (eq_attr "type" "fsimptf,fhex"))
148  "z196_alone")
149
150(define_insn_reservation "z196_fmultf" 47
151  (and (eq_attr "cpu" "z196")
152       (eq_attr "type" "fmultf"))
153  "z196_alone")
154
155(define_insn_reservation "z196_fsimpdf" 7
156  (and (eq_attr "cpu" "z196")
157       (eq_attr "type" "fsimpdf,fmuldf,fhex"))
158  "z196_simple")
159
160(define_insn_reservation "z196_fmadddf" 7
161  (and (eq_attr "cpu" "z196")
162       (eq_attr "type" "fmadddf"))
163  "z196_alone")
164
165(define_insn_reservation "z196_fsimpsf" 7
166  (and (eq_attr "cpu" "z196")
167       (eq_attr "type" "fsimpsf,fmulsf,fhex"))
168  "z196_simple")
169
170(define_insn_reservation "z196_fmaddsf" 7
171  (and (eq_attr "cpu" "z196")
172       (eq_attr "type" "fmaddsf"))
173  "z196_alone")
174
175(define_insn_reservation "z196_fdivtf" 108
176  (and (eq_attr "cpu" "z196")
177       (eq_attr "type" "fdivtf,fsqrttf"))
178  "z196_alone")
179
180(define_insn_reservation "z196_fdivdf" 36
181  (and (eq_attr "cpu" "z196")
182       (eq_attr "type" "fdivdf,fsqrtdf"))
183  "z196_simple")
184
185(define_insn_reservation "z196_fdivsf" 29
186  (and (eq_attr "cpu" "z196")
187       (eq_attr "type" "fdivsf,fsqrtsf"))
188  "z196_simple")
189
190
191;; Loads and stores are cheap as well.
192(define_insn_reservation "z196_floaddf" 0
193  (and (eq_attr "cpu" "z196")
194       (eq_attr "type" "floaddf"))
195  "z196_simple")
196
197(define_insn_reservation "z196_floadsf" 0
198  (and (eq_attr "cpu" "z196")
199       (eq_attr "type" "floadsf"))
200  "z196_simple")
201
202(define_insn_reservation "z196_fstoredf" 0
203  (and (eq_attr "cpu" "z196")
204       (eq_attr "type" "fstoredf"))
205  "z196_simple")
206
207(define_insn_reservation "z196_fstoresf" 0
208  (and (eq_attr "cpu" "z196")
209       (eq_attr "type" "fstoresf"))
210  "z196_simple")
211
212
213(define_insn_reservation "z196_ftrunctf" 9
214  (and (eq_attr "cpu" "z196")
215       (eq_attr "type" "ftrunctf"))
216  "z196_simple")
217
218(define_insn_reservation "z196_ftruncdf" 7
219  (and (eq_attr "cpu" "z196")
220       (eq_attr "type" "ftruncdf"))
221  "z196_simple")
222
223
224(define_insn_reservation "z196_ftoi" 7
225  (and (eq_attr "cpu" "z196")
226       (eq_attr "type" "ftoi"))
227  "z196_crack")
228
229(define_insn_reservation "z196_itof" 7
230  (and (eq_attr "cpu" "z196")
231       (eq_attr "type" "itoftf,itofdf,itofsf"))
232  "z196_crack")
233
234;;
235;; Decimal Floating Point
236;;
237
238;; DDTR
239(define_insn_reservation "z196_fdivdd" 33
240  (and (eq_attr "cpu" "z196")
241       (eq_attr "type" "fdivdd"))
242  "z196_simple")
243
244;; DXTR
245(define_insn_reservation "z196_fdivtd" 35
246  (and (eq_attr "cpu" "z196")
247       (eq_attr "type" "fdivtd"))
248  "z196_alone")
249
250;; LEDTR
251(define_insn_reservation "z196_ftruncsd" 34
252  (and (eq_attr "cpu" "z196")
253       (eq_attr "type" "ftruncsd"))
254  "z196_simple")
255
256;; LDXTR
257(define_insn_reservation "z196_ftruncdd" 36
258  (and (eq_attr "cpu" "z196")
259       (eq_attr "type" "ftruncdd"))
260  "z196_simple")
261
262;; These are normal fp loads/stores - which are cheap.
263(define_insn_reservation "z196_floadsddd" 0
264  (and (eq_attr "cpu" "z196")
265       (eq_attr "type" "floadsd,floaddd,fstoredd,fstoresd"))
266  "z196_simple")
267
268;; MDTR
269(define_insn_reservation "z196_fmuldd" 23
270  (and (eq_attr "cpu" "z196")
271       (eq_attr "type" "fmuldd"))
272  "z196_simple")
273
274;; MXTR
275(define_insn_reservation "z196_fmultd" 25
276  (and (eq_attr "cpu" "z196")
277       (eq_attr "type" "fmultd"))
278  "z196_alone")
279
280;; multiple different isns like add, sub etc.
281;; Just use the same defaults as z10.
282(define_insn_reservation "z196_fsimpsd" 17
283  (and (eq_attr "cpu" "z196")
284       (eq_attr "type" "fsimpsd"))
285  "z196_simple")
286(define_insn_reservation "z196_fsimpdd" 17
287  (and (eq_attr "cpu" "z196")
288       (eq_attr "type" "fsimpdd"))
289  "z196_simple")
290(define_insn_reservation "z196_fsimptd" 18
291  (and (eq_attr "cpu" "z196")
292       (eq_attr "type" "fsimptd"))
293  "z196_alone")
294
295;; CDGTR
296(define_insn_reservation "z196_itofdd" 45
297  (and (eq_attr "cpu" "z196")
298       (eq_attr "type" "itofdd"))
299  "z196_crack")
300
301;; CXGTR
302(define_insn_reservation "z196_itoftd" 33
303  (and (eq_attr "cpu" "z196")
304       (eq_attr "type" "itoftd"))
305  "z196_crack")
306
307;; CGXTR, CGDTR
308(define_insn_reservation "z196_ftoidfp" 33
309  (and (eq_attr "cpu" "z196")
310       (eq_attr "type" "ftoidfp"))
311  "z196_crack")
312
313
314
315