rs6000.h revision 1.5
10Sstevel@tonic-gate/* Definitions of target machine for GNU compiler, for IBM RS/6000. 20Sstevel@tonic-gate Copyright (C) 1992-2015 Free Software Foundation, Inc. 30Sstevel@tonic-gate Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 40Sstevel@tonic-gate 51865Sdilpreet This file is part of GCC. 61865Sdilpreet 70Sstevel@tonic-gate GCC is free software; you can redistribute it and/or modify it 80Sstevel@tonic-gate under the terms of the GNU General Public License as published 90Sstevel@tonic-gate by the Free Software Foundation; either version 3, or (at your 100Sstevel@tonic-gate option) any later version. 110Sstevel@tonic-gate 120Sstevel@tonic-gate GCC is distributed in the hope that it will be useful, but WITHOUT 130Sstevel@tonic-gate ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 140Sstevel@tonic-gate or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 150Sstevel@tonic-gate License for more details. 160Sstevel@tonic-gate 170Sstevel@tonic-gate Under Section 7 of GPL version 3, you are granted additional 180Sstevel@tonic-gate permissions described in the GCC Runtime Library Exception, version 190Sstevel@tonic-gate 3.1, as published by the Free Software Foundation. 200Sstevel@tonic-gate 210Sstevel@tonic-gate You should have received a copy of the GNU General Public License and 221865Sdilpreet a copy of the GCC Runtime Library Exception along with this program; 230Sstevel@tonic-gate see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 240Sstevel@tonic-gate <http://www.gnu.org/licenses/>. */ 250Sstevel@tonic-gate 260Sstevel@tonic-gate/* Note that some other tm.h files include this one and then override 270Sstevel@tonic-gate many of the definitions. */ 280Sstevel@tonic-gate 290Sstevel@tonic-gate#ifndef RS6000_OPTS_H 300Sstevel@tonic-gate#include "config/rs6000/rs6000-opts.h" 310Sstevel@tonic-gate#endif 320Sstevel@tonic-gate 330Sstevel@tonic-gate/* Definitions for the object file format. These are set at 340Sstevel@tonic-gate compile-time. */ 350Sstevel@tonic-gate 360Sstevel@tonic-gate#define OBJECT_XCOFF 1 370Sstevel@tonic-gate#define OBJECT_ELF 2 380Sstevel@tonic-gate#define OBJECT_PEF 3 390Sstevel@tonic-gate#define OBJECT_MACHO 4 400Sstevel@tonic-gate 410Sstevel@tonic-gate#define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 420Sstevel@tonic-gate#define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 430Sstevel@tonic-gate#define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 440Sstevel@tonic-gate#define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 450Sstevel@tonic-gate 460Sstevel@tonic-gate#ifndef TARGET_AIX 470Sstevel@tonic-gate#define TARGET_AIX 0 480Sstevel@tonic-gate#endif 490Sstevel@tonic-gate 500Sstevel@tonic-gate#ifndef TARGET_AIX_OS 510Sstevel@tonic-gate#define TARGET_AIX_OS 0 520Sstevel@tonic-gate#endif 530Sstevel@tonic-gate 540Sstevel@tonic-gate/* Control whether function entry points use a "dot" symbol when 550Sstevel@tonic-gate ABI_AIX. */ 560Sstevel@tonic-gate#define DOT_SYMBOLS 1 570Sstevel@tonic-gate 580Sstevel@tonic-gate/* Default string to use for cpu if not specified. */ 590Sstevel@tonic-gate#ifndef TARGET_CPU_DEFAULT 600Sstevel@tonic-gate#define TARGET_CPU_DEFAULT ((char *)0) 610Sstevel@tonic-gate#endif 620Sstevel@tonic-gate 630Sstevel@tonic-gate/* If configured for PPC405, support PPC405CR Erratum77. */ 640Sstevel@tonic-gate#ifdef CONFIG_PPC405CR 650Sstevel@tonic-gate#define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 660Sstevel@tonic-gate#else 670Sstevel@tonic-gate#define PPC405_ERRATUM77 0 680Sstevel@tonic-gate#endif 690Sstevel@tonic-gate 700Sstevel@tonic-gate#ifndef TARGET_PAIRED_FLOAT 710Sstevel@tonic-gate#define TARGET_PAIRED_FLOAT 0 720Sstevel@tonic-gate#endif 730Sstevel@tonic-gate 740Sstevel@tonic-gate#ifdef HAVE_AS_POPCNTB 750Sstevel@tonic-gate#define ASM_CPU_POWER5_SPEC "-mpower5" 760Sstevel@tonic-gate#else 770Sstevel@tonic-gate#define ASM_CPU_POWER5_SPEC "-mpower4" 780Sstevel@tonic-gate#endif 790Sstevel@tonic-gate 800Sstevel@tonic-gate#ifdef HAVE_AS_DFP 810Sstevel@tonic-gate#define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" 820Sstevel@tonic-gate#else 830Sstevel@tonic-gate#define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" 840Sstevel@tonic-gate#endif 850Sstevel@tonic-gate 860Sstevel@tonic-gate#ifdef HAVE_AS_POPCNTD 870Sstevel@tonic-gate#define ASM_CPU_POWER7_SPEC "-mpower7" 880Sstevel@tonic-gate#else 890Sstevel@tonic-gate#define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" 900Sstevel@tonic-gate#endif 910Sstevel@tonic-gate 920Sstevel@tonic-gate#ifdef HAVE_AS_POWER8 930Sstevel@tonic-gate#define ASM_CPU_POWER8_SPEC "-mpower8" 940Sstevel@tonic-gate#else 950Sstevel@tonic-gate#define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC 960Sstevel@tonic-gate#endif 970Sstevel@tonic-gate 980Sstevel@tonic-gate#ifdef HAVE_AS_DCI 990Sstevel@tonic-gate#define ASM_CPU_476_SPEC "-m476" 1000Sstevel@tonic-gate#else 1010Sstevel@tonic-gate#define ASM_CPU_476_SPEC "-mpower4" 1020Sstevel@tonic-gate#endif 1030Sstevel@tonic-gate 1040Sstevel@tonic-gate/* Common ASM definitions used by ASM_SPEC among the various targets for 1050Sstevel@tonic-gate handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 1060Sstevel@tonic-gate provide the default assembler options if the user uses -mcpu=native, so if 1070Sstevel@tonic-gate you make changes here, make them also there. */ 1080Sstevel@tonic-gate#define ASM_CPU_SPEC \ 1090Sstevel@tonic-gate"%{!mcpu*: \ 1100Sstevel@tonic-gate %{mpowerpc64*: -mppc64} \ 1110Sstevel@tonic-gate %{!mpowerpc64*: %(asm_default)}} \ 1120Sstevel@tonic-gate%{mcpu=native: %(asm_cpu_native)} \ 1130Sstevel@tonic-gate%{mcpu=cell: -mcell} \ 1140Sstevel@tonic-gate%{mcpu=power3: -mppc64} \ 1150Sstevel@tonic-gate%{mcpu=power4: -mpower4} \ 1160Sstevel@tonic-gate%{mcpu=power5: %(asm_cpu_power5)} \ 1170Sstevel@tonic-gate%{mcpu=power5+: %(asm_cpu_power5)} \ 1180Sstevel@tonic-gate%{mcpu=power6: %(asm_cpu_power6) -maltivec} \ 1190Sstevel@tonic-gate%{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ 1200Sstevel@tonic-gate%{mcpu=power7: %(asm_cpu_power7)} \ 1210Sstevel@tonic-gate%{mcpu=power8: %(asm_cpu_power8)} \ 1220Sstevel@tonic-gate%{mcpu=a2: -ma2} \ 1230Sstevel@tonic-gate%{mcpu=powerpc: -mppc} \ 1240Sstevel@tonic-gate%{mcpu=powerpc64le: %(asm_cpu_power8)} \ 1250Sstevel@tonic-gate%{mcpu=rs64a: -mppc64} \ 1260Sstevel@tonic-gate%{mcpu=401: -mppc} \ 1270Sstevel@tonic-gate%{mcpu=403: -m403} \ 1280Sstevel@tonic-gate%{mcpu=405: -m405} \ 1290Sstevel@tonic-gate%{mcpu=405fp: -m405} \ 1300Sstevel@tonic-gate%{mcpu=440: -m440} \ 1310Sstevel@tonic-gate%{mcpu=440fp: -m440} \ 1320Sstevel@tonic-gate%{mcpu=464: -m440} \ 1330Sstevel@tonic-gate%{mcpu=464fp: -m440} \ 1340Sstevel@tonic-gate%{mcpu=476: %(asm_cpu_476)} \ 1350Sstevel@tonic-gate%{mcpu=476fp: %(asm_cpu_476)} \ 1360Sstevel@tonic-gate%{mcpu=505: -mppc} \ 1370Sstevel@tonic-gate%{mcpu=601: -m601} \ 1380Sstevel@tonic-gate%{mcpu=602: -mppc} \ 1390Sstevel@tonic-gate%{mcpu=603: -mppc} \ 1400Sstevel@tonic-gate%{mcpu=603e: -mppc} \ 1410Sstevel@tonic-gate%{mcpu=ec603e: -mppc} \ 1420Sstevel@tonic-gate%{mcpu=604: -mppc} \ 1430Sstevel@tonic-gate%{mcpu=604e: -mppc} \ 1440Sstevel@tonic-gate%{mcpu=620: -mppc64} \ 1450Sstevel@tonic-gate%{mcpu=630: -mppc64} \ 1460Sstevel@tonic-gate%{mcpu=740: -mppc} \ 1470Sstevel@tonic-gate%{mcpu=750: -mppc} \ 1480Sstevel@tonic-gate%{mcpu=G3: -mppc} \ 1490Sstevel@tonic-gate%{mcpu=7400: -mppc -maltivec} \ 1500Sstevel@tonic-gate%{mcpu=7450: -mppc -maltivec} \ 1510Sstevel@tonic-gate%{mcpu=G4: -mppc -maltivec} \ 1520Sstevel@tonic-gate%{mcpu=801: -mppc} \ 1530Sstevel@tonic-gate%{mcpu=821: -mppc} \ 1540Sstevel@tonic-gate%{mcpu=823: -mppc} \ 1550Sstevel@tonic-gate%{mcpu=860: -mppc} \ 1560Sstevel@tonic-gate%{mcpu=970: -mpower4 -maltivec} \ 1570Sstevel@tonic-gate%{mcpu=G5: -mpower4 -maltivec} \ 1580Sstevel@tonic-gate%{mcpu=8540: -me500} \ 1590Sstevel@tonic-gate%{mcpu=8548: -me500} \ 1600Sstevel@tonic-gate%{mcpu=e300c2: -me300} \ 1610Sstevel@tonic-gate%{mcpu=e300c3: -me300} \ 1620Sstevel@tonic-gate%{mcpu=e500mc: -me500mc} \ 1630Sstevel@tonic-gate%{mcpu=e500mc64: -me500mc64} \ 1640Sstevel@tonic-gate%{mcpu=e5500: -me5500} \ 1650Sstevel@tonic-gate%{mcpu=e6500: -me6500} \ 1660Sstevel@tonic-gate%{maltivec: -maltivec} \ 1670Sstevel@tonic-gate%{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ 1680Sstevel@tonic-gate%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ 1690Sstevel@tonic-gate-many" 1700Sstevel@tonic-gate 1710Sstevel@tonic-gate#define CPP_DEFAULT_SPEC "" 1720Sstevel@tonic-gate 1730Sstevel@tonic-gate#define ASM_DEFAULT_SPEC "" 1740Sstevel@tonic-gate 1750Sstevel@tonic-gate/* This macro defines names of additional specifications to put in the specs 1760Sstevel@tonic-gate that can be used in various specifications like CC1_SPEC. Its definition 1770Sstevel@tonic-gate is an initializer with a subgrouping for each command option. 1780Sstevel@tonic-gate 1790Sstevel@tonic-gate Each subgrouping contains a string constant, that defines the 1800Sstevel@tonic-gate specification name, and a string constant that used by the GCC driver 1810Sstevel@tonic-gate program. 1820Sstevel@tonic-gate 1832889Sjj156685 Do not define this macro if it does not need to do anything. */ 1842889Sjj156685 1852889Sjj156685#define SUBTARGET_EXTRA_SPECS 1862889Sjj156685 1872889Sjj156685#define EXTRA_SPECS \ 1882889Sjj156685 { "cpp_default", CPP_DEFAULT_SPEC }, \ 1892889Sjj156685 { "asm_cpu", ASM_CPU_SPEC }, \ 1900Sstevel@tonic-gate { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 1910Sstevel@tonic-gate { "asm_default", ASM_DEFAULT_SPEC }, \ 1920Sstevel@tonic-gate { "cc1_cpu", CC1_CPU_SPEC }, \ 1932889Sjj156685 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ 1942889Sjj156685 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ 1952889Sjj156685 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ 1962889Sjj156685 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \ 1972889Sjj156685 { "asm_cpu_476", ASM_CPU_476_SPEC }, \ 1982889Sjj156685 SUBTARGET_EXTRA_SPECS 1990Sstevel@tonic-gate 2000Sstevel@tonic-gate/* -mcpu=native handling only makes sense with compiler running on 2010Sstevel@tonic-gate an PowerPC chip. If changing this condition, also change 2020Sstevel@tonic-gate the condition in driver-rs6000.c. */ 2030Sstevel@tonic-gate#if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 2040Sstevel@tonic-gate/* In driver-rs6000.c. */ 2050Sstevel@tonic-gateextern const char *host_detect_local_cpu (int argc, const char **argv); 2060Sstevel@tonic-gate#define EXTRA_SPEC_FUNCTIONS \ 2070Sstevel@tonic-gate { "local_cpu_detect", host_detect_local_cpu }, 2080Sstevel@tonic-gate#define HAVE_LOCAL_CPU_DETECT 2090Sstevel@tonic-gate#define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 2100Sstevel@tonic-gate 2110Sstevel@tonic-gate#else 2120Sstevel@tonic-gate#define ASM_CPU_NATIVE_SPEC "%(asm_default)" 2130Sstevel@tonic-gate#endif 2140Sstevel@tonic-gate 2150Sstevel@tonic-gate#ifndef CC1_CPU_SPEC 2160Sstevel@tonic-gate#ifdef HAVE_LOCAL_CPU_DETECT 2170Sstevel@tonic-gate#define CC1_CPU_SPEC \ 2180Sstevel@tonic-gate"%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 2190Sstevel@tonic-gate %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2200Sstevel@tonic-gate#else 2210Sstevel@tonic-gate#define CC1_CPU_SPEC "" 2220Sstevel@tonic-gate#endif 2230Sstevel@tonic-gate#endif 2240Sstevel@tonic-gate 2250Sstevel@tonic-gate/* Architecture type. */ 2260Sstevel@tonic-gate 2270Sstevel@tonic-gate/* Define TARGET_MFCRF if the target assembler does not support the 2280Sstevel@tonic-gate optional field operand for mfcr. */ 2290Sstevel@tonic-gate 2300Sstevel@tonic-gate#ifndef HAVE_AS_MFCRF 2310Sstevel@tonic-gate#undef TARGET_MFCRF 2320Sstevel@tonic-gate#define TARGET_MFCRF 0 2330Sstevel@tonic-gate#endif 2340Sstevel@tonic-gate 2350Sstevel@tonic-gate/* Define TARGET_POPCNTB if the target assembler does not support the 2360Sstevel@tonic-gate popcount byte instruction. */ 2370Sstevel@tonic-gate 2380Sstevel@tonic-gate#ifndef HAVE_AS_POPCNTB 2390Sstevel@tonic-gate#undef TARGET_POPCNTB 2400Sstevel@tonic-gate#define TARGET_POPCNTB 0 2410Sstevel@tonic-gate#endif 2420Sstevel@tonic-gate 2430Sstevel@tonic-gate/* Define TARGET_FPRND if the target assembler does not support the 2440Sstevel@tonic-gate fp rounding instructions. */ 2450Sstevel@tonic-gate 2460Sstevel@tonic-gate#ifndef HAVE_AS_FPRND 2470Sstevel@tonic-gate#undef TARGET_FPRND 2480Sstevel@tonic-gate#define TARGET_FPRND 0 2490Sstevel@tonic-gate#endif 2500Sstevel@tonic-gate 2510Sstevel@tonic-gate/* Define TARGET_CMPB if the target assembler does not support the 2520Sstevel@tonic-gate cmpb instruction. */ 2530Sstevel@tonic-gate 2540Sstevel@tonic-gate#ifndef HAVE_AS_CMPB 2550Sstevel@tonic-gate#undef TARGET_CMPB 2560Sstevel@tonic-gate#define TARGET_CMPB 0 2570Sstevel@tonic-gate#endif 2580Sstevel@tonic-gate 2590Sstevel@tonic-gate/* Define TARGET_MFPGPR if the target assembler does not support the 2600Sstevel@tonic-gate mffpr and mftgpr instructions. */ 2610Sstevel@tonic-gate 2620Sstevel@tonic-gate#ifndef HAVE_AS_MFPGPR 2630Sstevel@tonic-gate#undef TARGET_MFPGPR 2640Sstevel@tonic-gate#define TARGET_MFPGPR 0 2650Sstevel@tonic-gate#endif 2660Sstevel@tonic-gate 2670Sstevel@tonic-gate/* Define TARGET_DFP if the target assembler does not support decimal 2680Sstevel@tonic-gate floating point instructions. */ 2690Sstevel@tonic-gate#ifndef HAVE_AS_DFP 2700Sstevel@tonic-gate#undef TARGET_DFP 2710Sstevel@tonic-gate#define TARGET_DFP 0 2720Sstevel@tonic-gate#endif 2730Sstevel@tonic-gate 2740Sstevel@tonic-gate/* Define TARGET_POPCNTD if the target assembler does not support the 2750Sstevel@tonic-gate popcount word and double word instructions. */ 2760Sstevel@tonic-gate 2770Sstevel@tonic-gate#ifndef HAVE_AS_POPCNTD 2780Sstevel@tonic-gate#undef TARGET_POPCNTD 2790Sstevel@tonic-gate#define TARGET_POPCNTD 0 2800Sstevel@tonic-gate#endif 2810Sstevel@tonic-gate 2820Sstevel@tonic-gate/* Define the ISA 2.07 flags as 0 if the target assembler does not support the 2830Sstevel@tonic-gate waitasecond instruction. Allow -mpower8-fusion, since it does not add new 2840Sstevel@tonic-gate instructions. */ 2850Sstevel@tonic-gate 2860Sstevel@tonic-gate#ifndef HAVE_AS_POWER8 2870Sstevel@tonic-gate#undef TARGET_DIRECT_MOVE 2880Sstevel@tonic-gate#undef TARGET_CRYPTO 2890Sstevel@tonic-gate#undef TARGET_HTM 2900Sstevel@tonic-gate#undef TARGET_P8_VECTOR 2910Sstevel@tonic-gate#define TARGET_DIRECT_MOVE 0 2920Sstevel@tonic-gate#define TARGET_CRYPTO 0 2930Sstevel@tonic-gate#define TARGET_HTM 0 2940Sstevel@tonic-gate#define TARGET_P8_VECTOR 0 2950Sstevel@tonic-gate#endif 2960Sstevel@tonic-gate 2970Sstevel@tonic-gate/* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If 2980Sstevel@tonic-gate not, generate the lwsync code as an integer constant. */ 2990Sstevel@tonic-gate#ifdef HAVE_AS_LWSYNC 3000Sstevel@tonic-gate#define TARGET_LWSYNC_INSTRUCTION 1 3010Sstevel@tonic-gate#else 3020Sstevel@tonic-gate#define TARGET_LWSYNC_INSTRUCTION 0 3030Sstevel@tonic-gate#endif 3040Sstevel@tonic-gate 3050Sstevel@tonic-gate/* Define TARGET_TLS_MARKERS if the target assembler does not support 3060Sstevel@tonic-gate arg markers for __tls_get_addr calls. */ 3070Sstevel@tonic-gate#ifndef HAVE_AS_TLS_MARKERS 3080Sstevel@tonic-gate#undef TARGET_TLS_MARKERS 3090Sstevel@tonic-gate#define TARGET_TLS_MARKERS 0 3100Sstevel@tonic-gate#else 3110Sstevel@tonic-gate#define TARGET_TLS_MARKERS tls_markers 3120Sstevel@tonic-gate#endif 3130Sstevel@tonic-gate 3140Sstevel@tonic-gate#ifndef TARGET_SECURE_PLT 3150Sstevel@tonic-gate#define TARGET_SECURE_PLT 0 3160Sstevel@tonic-gate#endif 3170Sstevel@tonic-gate 3180Sstevel@tonic-gate#ifndef TARGET_CMODEL 3190Sstevel@tonic-gate#define TARGET_CMODEL CMODEL_SMALL 3200Sstevel@tonic-gate#endif 3210Sstevel@tonic-gate 3220Sstevel@tonic-gate#define TARGET_32BIT (! TARGET_64BIT) 3230Sstevel@tonic-gate 3240Sstevel@tonic-gate#ifndef HAVE_AS_TLS 3250Sstevel@tonic-gate#define HAVE_AS_TLS 0 3260Sstevel@tonic-gate#endif 3270Sstevel@tonic-gate 3280Sstevel@tonic-gate#ifndef TARGET_LINK_STACK 3290Sstevel@tonic-gate#define TARGET_LINK_STACK 0 3300Sstevel@tonic-gate#endif 3310Sstevel@tonic-gate 3320Sstevel@tonic-gate#ifndef SET_TARGET_LINK_STACK 3330Sstevel@tonic-gate#define SET_TARGET_LINK_STACK(X) do { } while (0) 3340Sstevel@tonic-gate#endif 3350Sstevel@tonic-gate 3360Sstevel@tonic-gate/* Return 1 for a symbol ref for a thread-local storage symbol. */ 3370Sstevel@tonic-gate#define RS6000_SYMBOL_REF_TLS_P(RTX) \ 3380Sstevel@tonic-gate (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 3390Sstevel@tonic-gate 3400Sstevel@tonic-gate#ifdef IN_LIBGCC2 3410Sstevel@tonic-gate/* For libgcc2 we make sure this is a compile time constant */ 3420Sstevel@tonic-gate#if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 3430Sstevel@tonic-gate#undef TARGET_POWERPC64 3440Sstevel@tonic-gate#define TARGET_POWERPC64 1 3450Sstevel@tonic-gate#else 3460Sstevel@tonic-gate#undef TARGET_POWERPC64 3470Sstevel@tonic-gate#define TARGET_POWERPC64 0 3480Sstevel@tonic-gate#endif 3490Sstevel@tonic-gate#else 3500Sstevel@tonic-gate /* The option machinery will define this. */ 3510Sstevel@tonic-gate#endif 3520Sstevel@tonic-gate 3530Sstevel@tonic-gate#define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING) 3540Sstevel@tonic-gate 3550Sstevel@tonic-gate/* FPU operations supported. 3560Sstevel@tonic-gate Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must 3570Sstevel@tonic-gate also test TARGET_HARD_FLOAT. */ 3580Sstevel@tonic-gate#define TARGET_SINGLE_FLOAT 1 3590Sstevel@tonic-gate#define TARGET_DOUBLE_FLOAT 1 3600Sstevel@tonic-gate#define TARGET_SINGLE_FPU 0 3610Sstevel@tonic-gate#define TARGET_SIMPLE_FPU 0 3620Sstevel@tonic-gate#define TARGET_XILINX_FPU 0 3630Sstevel@tonic-gate 3640Sstevel@tonic-gate/* Recast the processor type to the cpu attribute. */ 3650Sstevel@tonic-gate#define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 3660Sstevel@tonic-gate 3670Sstevel@tonic-gate/* Define generic processor types based upon current deployment. */ 3680Sstevel@tonic-gate#define PROCESSOR_COMMON PROCESSOR_PPC601 3690Sstevel@tonic-gate#define PROCESSOR_POWERPC PROCESSOR_PPC604 3700Sstevel@tonic-gate#define PROCESSOR_POWERPC64 PROCESSOR_RS64A 3710Sstevel@tonic-gate 3720Sstevel@tonic-gate/* Define the default processor. This is overridden by other tm.h files. */ 3730Sstevel@tonic-gate#define PROCESSOR_DEFAULT PROCESSOR_PPC603 3740Sstevel@tonic-gate#define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 3750Sstevel@tonic-gate 3760Sstevel@tonic-gate/* Specify the dialect of assembler to use. Only new mnemonics are supported 3770Sstevel@tonic-gate starting with GCC 4.8, i.e. just one dialect, but for backwards 3780Sstevel@tonic-gate compatibility with older inline asm ASSEMBLER_DIALECT needs to be 3790Sstevel@tonic-gate defined. */ 3800Sstevel@tonic-gate#define ASSEMBLER_DIALECT 1 3810Sstevel@tonic-gate 3820Sstevel@tonic-gate/* Debug support */ 3830Sstevel@tonic-gate#define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 3840Sstevel@tonic-gate#define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 3850Sstevel@tonic-gate#define MASK_DEBUG_REG 0x04 /* debug register handling */ 3860Sstevel@tonic-gate#define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 3870Sstevel@tonic-gate#define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 3880Sstevel@tonic-gate#define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 3890Sstevel@tonic-gate#define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 3900Sstevel@tonic-gate#define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 3910Sstevel@tonic-gate | MASK_DEBUG_ARG \ 3920Sstevel@tonic-gate | MASK_DEBUG_REG \ 3930Sstevel@tonic-gate | MASK_DEBUG_ADDR \ 3940Sstevel@tonic-gate | MASK_DEBUG_COST \ 3950Sstevel@tonic-gate | MASK_DEBUG_TARGET \ 3960Sstevel@tonic-gate | MASK_DEBUG_BUILTIN) 3970Sstevel@tonic-gate 3980Sstevel@tonic-gate#define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 3990Sstevel@tonic-gate#define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 4000Sstevel@tonic-gate#define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 4010Sstevel@tonic-gate#define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 4020Sstevel@tonic-gate#define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 4030Sstevel@tonic-gate#define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 4040Sstevel@tonic-gate#define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 4050Sstevel@tonic-gate 4060Sstevel@tonic-gate/* Describe the vector unit used for arithmetic operations. */ 4070Sstevel@tonic-gateextern enum rs6000_vector rs6000_vector_unit[]; 4080Sstevel@tonic-gate 4090Sstevel@tonic-gate#define VECTOR_UNIT_NONE_P(MODE) \ 4100Sstevel@tonic-gate (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 4110Sstevel@tonic-gate 4120Sstevel@tonic-gate#define VECTOR_UNIT_VSX_P(MODE) \ 4130Sstevel@tonic-gate (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 4140Sstevel@tonic-gate 4150Sstevel@tonic-gate#define VECTOR_UNIT_P8_VECTOR_P(MODE) \ 4160Sstevel@tonic-gate (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) 4170Sstevel@tonic-gate 4180Sstevel@tonic-gate#define VECTOR_UNIT_ALTIVEC_P(MODE) \ 4190Sstevel@tonic-gate (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 4200Sstevel@tonic-gate 4210Sstevel@tonic-gate#define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ 4220Sstevel@tonic-gate (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 4230Sstevel@tonic-gate (int)VECTOR_VSX, \ 4240Sstevel@tonic-gate (int)VECTOR_P8_VECTOR)) 4250Sstevel@tonic-gate 4260Sstevel@tonic-gate/* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either 4270Sstevel@tonic-gate altivec (VMX) or VSX vector instructions. P8 vector support is upwards 4280Sstevel@tonic-gate compatible, so allow it as well, rather than changing all of the uses of the 4290Sstevel@tonic-gate macro. */ 4300Sstevel@tonic-gate#define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 4310Sstevel@tonic-gate (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 4320Sstevel@tonic-gate (int)VECTOR_ALTIVEC, \ 4330Sstevel@tonic-gate (int)VECTOR_P8_VECTOR)) 4340Sstevel@tonic-gate 4350Sstevel@tonic-gate/* Describe whether to use VSX loads or Altivec loads. For now, just use the 4360Sstevel@tonic-gate same unit as the vector unit we are using, but we may want to migrate to 4370Sstevel@tonic-gate using VSX style loads even for types handled by altivec. */ 4380Sstevel@tonic-gateextern enum rs6000_vector rs6000_vector_mem[]; 4390Sstevel@tonic-gate 4400Sstevel@tonic-gate#define VECTOR_MEM_NONE_P(MODE) \ 4410Sstevel@tonic-gate (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 4420Sstevel@tonic-gate 4430Sstevel@tonic-gate#define VECTOR_MEM_VSX_P(MODE) \ 4440Sstevel@tonic-gate (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 4450Sstevel@tonic-gate 4460Sstevel@tonic-gate#define VECTOR_MEM_P8_VECTOR_P(MODE) \ 4470Sstevel@tonic-gate (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 4480Sstevel@tonic-gate 4490Sstevel@tonic-gate#define VECTOR_MEM_ALTIVEC_P(MODE) \ 4500Sstevel@tonic-gate (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 4510Sstevel@tonic-gate 4520Sstevel@tonic-gate#define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ 4530Sstevel@tonic-gate (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 4540Sstevel@tonic-gate (int)VECTOR_VSX, \ 4550Sstevel@tonic-gate (int)VECTOR_P8_VECTOR)) 4560Sstevel@tonic-gate 4570Sstevel@tonic-gate#define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 4580Sstevel@tonic-gate (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 4590Sstevel@tonic-gate (int)VECTOR_ALTIVEC, \ 4600Sstevel@tonic-gate (int)VECTOR_P8_VECTOR)) 4610Sstevel@tonic-gate 4620Sstevel@tonic-gate/* Return the alignment of a given vector type, which is set based on the 4630Sstevel@tonic-gate vector unit use. VSX for instance can load 32 or 64 bit aligned words 4640Sstevel@tonic-gate without problems, while Altivec requires 128-bit aligned vectors. */ 4650Sstevel@tonic-gateextern int rs6000_vector_align[]; 4660Sstevel@tonic-gate 4670Sstevel@tonic-gate#define VECTOR_ALIGN(MODE) \ 4680Sstevel@tonic-gate ((rs6000_vector_align[(MODE)] != 0) \ 4690Sstevel@tonic-gate ? rs6000_vector_align[(MODE)] \ 4700Sstevel@tonic-gate : (int)GET_MODE_BITSIZE ((MODE))) 4710Sstevel@tonic-gate 4720Sstevel@tonic-gate/* Determine the element order to use for vector instructions. By 4730Sstevel@tonic-gate default we use big-endian element order when targeting big-endian, 4740Sstevel@tonic-gate and little-endian element order when targeting little-endian. For 4750Sstevel@tonic-gate programs being ported from BE Power to LE Power, it can sometimes 4760Sstevel@tonic-gate be useful to use big-endian element order when targeting little-endian. 4770Sstevel@tonic-gate This is set via -maltivec=be, for example. */ 4780Sstevel@tonic-gate#define VECTOR_ELT_ORDER_BIG \ 4790Sstevel@tonic-gate (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) 4800Sstevel@tonic-gate 4810Sstevel@tonic-gate/* Element number of the 64-bit value in a 128-bit vector that can be accessed 4820Sstevel@tonic-gate with scalar instructions. */ 4830Sstevel@tonic-gate#define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 4840Sstevel@tonic-gate 4850Sstevel@tonic-gate/* Alignment options for fields in structures for sub-targets following 4860Sstevel@tonic-gate AIX-like ABI. 4870Sstevel@tonic-gate ALIGN_POWER word-aligns FP doubles (default AIX ABI). 4880Sstevel@tonic-gate ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 4890Sstevel@tonic-gate 4900Sstevel@tonic-gate Override the macro definitions when compiling libobjc to avoid undefined 4910Sstevel@tonic-gate reference to rs6000_alignment_flags due to library's use of GCC alignment 4920Sstevel@tonic-gate macros which use the macros below. */ 4930Sstevel@tonic-gate 4940Sstevel@tonic-gate#ifndef IN_TARGET_LIBS 4950Sstevel@tonic-gate#define MASK_ALIGN_POWER 0x00000000 4960Sstevel@tonic-gate#define MASK_ALIGN_NATURAL 0x00000001 4970Sstevel@tonic-gate#define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 4980Sstevel@tonic-gate#else 4990Sstevel@tonic-gate#define TARGET_ALIGN_NATURAL 0 5000Sstevel@tonic-gate#endif 5010Sstevel@tonic-gate 5020Sstevel@tonic-gate#define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 5030Sstevel@tonic-gate#define TARGET_IEEEQUAD rs6000_ieeequad 5040Sstevel@tonic-gate#define TARGET_ALTIVEC_ABI rs6000_altivec_abi 5050Sstevel@tonic-gate#define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 5060Sstevel@tonic-gate 5070Sstevel@tonic-gate#define TARGET_SPE_ABI 0 5080Sstevel@tonic-gate#define TARGET_SPE 0 5090Sstevel@tonic-gate#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) 5100Sstevel@tonic-gate#define TARGET_FPRS 1 5110Sstevel@tonic-gate#define TARGET_E500_SINGLE 0 5120Sstevel@tonic-gate#define TARGET_E500_DOUBLE 0 5130Sstevel@tonic-gate#define CHECK_E500_OPTIONS do { } while (0) 5140Sstevel@tonic-gate 5150Sstevel@tonic-gate/* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 5160Sstevel@tonic-gate Enable 32-bit fcfid's on any of the switches for newer ISA machines or 5170Sstevel@tonic-gate XILINX. */ 5180Sstevel@tonic-gate#define TARGET_FCFID (TARGET_POWERPC64 \ 5190Sstevel@tonic-gate || TARGET_PPC_GPOPT /* 970/power4 */ \ 5200Sstevel@tonic-gate || TARGET_POPCNTB /* ISA 2.02 */ \ 5210Sstevel@tonic-gate || TARGET_CMPB /* ISA 2.05 */ \ 5220Sstevel@tonic-gate || TARGET_POPCNTD /* ISA 2.06 */ \ 5230Sstevel@tonic-gate || TARGET_XILINX_FPU) 5240Sstevel@tonic-gate 5250Sstevel@tonic-gate#define TARGET_FCTIDZ TARGET_FCFID 5260Sstevel@tonic-gate#define TARGET_STFIWX TARGET_PPC_GFXOPT 5270Sstevel@tonic-gate#define TARGET_LFIWAX TARGET_CMPB 5280Sstevel@tonic-gate#define TARGET_LFIWZX TARGET_POPCNTD 5290Sstevel@tonic-gate#define TARGET_FCFIDS TARGET_POPCNTD 5300Sstevel@tonic-gate#define TARGET_FCFIDU TARGET_POPCNTD 5310Sstevel@tonic-gate#define TARGET_FCFIDUS TARGET_POPCNTD 5320Sstevel@tonic-gate#define TARGET_FCTIDUZ TARGET_POPCNTD 5330Sstevel@tonic-gate#define TARGET_FCTIWUZ TARGET_POPCNTD 5340Sstevel@tonic-gate 5350Sstevel@tonic-gate#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 5360Sstevel@tonic-gate#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 5370Sstevel@tonic-gate#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) 5380Sstevel@tonic-gate 5390Sstevel@tonic-gate/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present 5400Sstevel@tonic-gate in power7, so conditionalize them on p8 features. TImode syncs need quad 5410Sstevel@tonic-gate memory support. */ 5420Sstevel@tonic-gate#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ 5430Sstevel@tonic-gate || TARGET_QUAD_MEMORY_ATOMIC \ 5440Sstevel@tonic-gate || TARGET_DIRECT_MOVE) 5450Sstevel@tonic-gate 5460Sstevel@tonic-gate#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC 5470Sstevel@tonic-gate 5480Sstevel@tonic-gate/* Power7 has both 32-bit load and store integer for the FPRs, so we don't need 5490Sstevel@tonic-gate to allocate the SDmode stack slot to get the value into the proper location 5500Sstevel@tonic-gate in the register. */ 5510Sstevel@tonic-gate#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 5520Sstevel@tonic-gate 5530Sstevel@tonic-gate/* In switching from using target_flags to using rs6000_isa_flags, the options 5540Sstevel@tonic-gate machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 5550Sstevel@tonic-gate OPTION_MASK_<xxx> back into MASK_<xxx>. */ 5560Sstevel@tonic-gate#define MASK_ALTIVEC OPTION_MASK_ALTIVEC 5570Sstevel@tonic-gate#define MASK_CMPB OPTION_MASK_CMPB 5580Sstevel@tonic-gate#define MASK_CRYPTO OPTION_MASK_CRYPTO 5590Sstevel@tonic-gate#define MASK_DFP OPTION_MASK_DFP 5600Sstevel@tonic-gate#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE 5610Sstevel@tonic-gate#define MASK_DLMZB OPTION_MASK_DLMZB 5620Sstevel@tonic-gate#define MASK_EABI OPTION_MASK_EABI 5630Sstevel@tonic-gate#define MASK_FPRND OPTION_MASK_FPRND 5640Sstevel@tonic-gate#define MASK_P8_FUSION OPTION_MASK_P8_FUSION 5650Sstevel@tonic-gate#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 5660Sstevel@tonic-gate#define MASK_HTM OPTION_MASK_HTM 5670Sstevel@tonic-gate#define MASK_ISEL OPTION_MASK_ISEL 5680Sstevel@tonic-gate#define MASK_MFCRF OPTION_MASK_MFCRF 5690Sstevel@tonic-gate#define MASK_MFPGPR OPTION_MASK_MFPGPR 5700Sstevel@tonic-gate#define MASK_MULHW OPTION_MASK_MULHW 5710Sstevel@tonic-gate#define MASK_MULTIPLE OPTION_MASK_MULTIPLE 5720Sstevel@tonic-gate#define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 5730Sstevel@tonic-gate#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR 5740Sstevel@tonic-gate#define MASK_POPCNTB OPTION_MASK_POPCNTB 5750Sstevel@tonic-gate#define MASK_POPCNTD OPTION_MASK_POPCNTD 5760Sstevel@tonic-gate#define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 5770Sstevel@tonic-gate#define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 5780Sstevel@tonic-gate#define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 5790Sstevel@tonic-gate#define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 5800Sstevel@tonic-gate#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 5810Sstevel@tonic-gate#define MASK_STRING OPTION_MASK_STRING 5820Sstevel@tonic-gate#define MASK_UPDATE OPTION_MASK_UPDATE 5830Sstevel@tonic-gate#define MASK_VSX OPTION_MASK_VSX 5840Sstevel@tonic-gate#define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE 5850Sstevel@tonic-gate 5860Sstevel@tonic-gate#ifndef IN_LIBGCC2 5870Sstevel@tonic-gate#define MASK_POWERPC64 OPTION_MASK_POWERPC64 5880Sstevel@tonic-gate#endif 5890Sstevel@tonic-gate 5900Sstevel@tonic-gate#ifdef TARGET_64BIT 5910Sstevel@tonic-gate#define MASK_64BIT OPTION_MASK_64BIT 5920Sstevel@tonic-gate#endif 5930Sstevel@tonic-gate 5940Sstevel@tonic-gate#ifdef TARGET_RELOCATABLE 5950Sstevel@tonic-gate#define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE 5960Sstevel@tonic-gate#endif 5970Sstevel@tonic-gate 5980Sstevel@tonic-gate#ifdef TARGET_LITTLE_ENDIAN 5990Sstevel@tonic-gate#define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 6000Sstevel@tonic-gate#endif 6010Sstevel@tonic-gate 6020Sstevel@tonic-gate#ifdef TARGET_MINIMAL_TOC 6030Sstevel@tonic-gate#define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC 6040Sstevel@tonic-gate#endif 6050Sstevel@tonic-gate 6060Sstevel@tonic-gate#ifdef TARGET_REGNAMES 6070Sstevel@tonic-gate#define MASK_REGNAMES OPTION_MASK_REGNAMES 6080Sstevel@tonic-gate#endif 6090Sstevel@tonic-gate 6100Sstevel@tonic-gate#ifdef TARGET_PROTOTYPE 6110Sstevel@tonic-gate#define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 6120Sstevel@tonic-gate#endif 6130Sstevel@tonic-gate 6140Sstevel@tonic-gate/* For power systems, we want to enable Altivec and VSX builtins even if the 6150Sstevel@tonic-gate user did not use -maltivec or -mvsx to allow the builtins to be used inside 6160Sstevel@tonic-gate of #pragma GCC target or the target attribute to change the code level for a 6170Sstevel@tonic-gate given system. The SPE and Paired builtins are only enabled if you configure 6180Sstevel@tonic-gate the compiler for those builtins, and those machines don't support altivec or 6190Sstevel@tonic-gate VSX. */ 6200Sstevel@tonic-gate 6210Sstevel@tonic-gate#define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \ 6220Sstevel@tonic-gate && ((TARGET_POWERPC64 \ 6230Sstevel@tonic-gate || TARGET_PPC_GPOPT /* 970/power4 */ \ 6240Sstevel@tonic-gate || TARGET_POPCNTB /* ISA 2.02 */ \ 6250Sstevel@tonic-gate || TARGET_CMPB /* ISA 2.05 */ \ 6260Sstevel@tonic-gate || TARGET_POPCNTD /* ISA 2.06 */ \ 6270Sstevel@tonic-gate || TARGET_ALTIVEC \ 6280Sstevel@tonic-gate || TARGET_VSX \ 6290Sstevel@tonic-gate || TARGET_HARD_FLOAT))) 6300Sstevel@tonic-gate 6310Sstevel@tonic-gate/* E500 cores only support plain "sync", not lwsync. */ 6320Sstevel@tonic-gate#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 6330Sstevel@tonic-gate || rs6000_cpu == PROCESSOR_PPC8548) 6340Sstevel@tonic-gate 6350Sstevel@tonic-gate 6360Sstevel@tonic-gate/* Whether SF/DF operations are supported on the E500. */ 6370Sstevel@tonic-gate#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \ 6380Sstevel@tonic-gate && !TARGET_FPRS) 6390Sstevel@tonic-gate 6400Sstevel@tonic-gate#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ 6410Sstevel@tonic-gate && !TARGET_FPRS && TARGET_E500_DOUBLE) 6420Sstevel@tonic-gate 6430Sstevel@tonic-gate/* Whether SF/DF operations are supported by by the normal floating point unit 6440Sstevel@tonic-gate (or the vector/scalar unit). */ 6450Sstevel@tonic-gate#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ 6460Sstevel@tonic-gate && TARGET_SINGLE_FLOAT) 6470Sstevel@tonic-gate 6480Sstevel@tonic-gate#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ 6490Sstevel@tonic-gate && TARGET_DOUBLE_FLOAT) 6500Sstevel@tonic-gate 6510Sstevel@tonic-gate/* Whether SF/DF operations are supported by any hardware. */ 6520Sstevel@tonic-gate#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE) 6530Sstevel@tonic-gate#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE) 6540Sstevel@tonic-gate 6550Sstevel@tonic-gate/* Which machine supports the various reciprocal estimate instructions. */ 6560Sstevel@tonic-gate#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 6570Sstevel@tonic-gate && TARGET_FPRS && TARGET_SINGLE_FLOAT) 6580Sstevel@tonic-gate 6590Sstevel@tonic-gate#define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \ 6600Sstevel@tonic-gate && TARGET_DOUBLE_FLOAT \ 6610Sstevel@tonic-gate && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 6620Sstevel@tonic-gate 6630Sstevel@tonic-gate#define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 6640Sstevel@tonic-gate && TARGET_FPRS && TARGET_SINGLE_FLOAT) 6650Sstevel@tonic-gate 6660Sstevel@tonic-gate#define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \ 6670Sstevel@tonic-gate && TARGET_DOUBLE_FLOAT \ 6680Sstevel@tonic-gate && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 6690Sstevel@tonic-gate 6700Sstevel@tonic-gate/* Whether the various reciprocal divide/square root estimate instructions 6710Sstevel@tonic-gate exist, and whether we should automatically generate code for the instruction 6720Sstevel@tonic-gate by default. */ 6730Sstevel@tonic-gate#define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 6740Sstevel@tonic-gate#define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 6750Sstevel@tonic-gate#define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 6760Sstevel@tonic-gate#define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 6770Sstevel@tonic-gate 6780Sstevel@tonic-gateextern unsigned char rs6000_recip_bits[]; 6790Sstevel@tonic-gate 6800Sstevel@tonic-gate#define RS6000_RECIP_HAVE_RE_P(MODE) \ 6810Sstevel@tonic-gate (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 6820Sstevel@tonic-gate 6830Sstevel@tonic-gate#define RS6000_RECIP_AUTO_RE_P(MODE) \ 6840Sstevel@tonic-gate (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 6850Sstevel@tonic-gate 6860Sstevel@tonic-gate#define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 6870Sstevel@tonic-gate (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 6880Sstevel@tonic-gate 6890Sstevel@tonic-gate#define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 6900Sstevel@tonic-gate (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 6910Sstevel@tonic-gate 6920Sstevel@tonic-gate/* The default CPU for TARGET_OPTION_OVERRIDE. */ 6930Sstevel@tonic-gate#define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 6940Sstevel@tonic-gate 6950Sstevel@tonic-gate/* Target pragma. */ 6960Sstevel@tonic-gate#define REGISTER_TARGET_PRAGMAS() do { \ 6970Sstevel@tonic-gate c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 6980Sstevel@tonic-gate targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 6990Sstevel@tonic-gate targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 7000Sstevel@tonic-gate rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 7010Sstevel@tonic-gate} while (0) 7020Sstevel@tonic-gate 7030Sstevel@tonic-gate/* Target #defines. */ 7040Sstevel@tonic-gate#define TARGET_CPU_CPP_BUILTINS() \ 7050Sstevel@tonic-gate rs6000_cpu_cpp_builtins (pfile) 7060Sstevel@tonic-gate 7070Sstevel@tonic-gate/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 7080Sstevel@tonic-gate we're compiling for. Some configurations may need to override it. */ 7090Sstevel@tonic-gate#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 7100Sstevel@tonic-gate do \ 711946Smathue { \ 7120Sstevel@tonic-gate if (BYTES_BIG_ENDIAN) \ 7130Sstevel@tonic-gate { \ 7140Sstevel@tonic-gate builtin_define ("__BIG_ENDIAN__"); \ 7150Sstevel@tonic-gate builtin_define ("_BIG_ENDIAN"); \ 7160Sstevel@tonic-gate builtin_assert ("machine=bigendian"); \ 7170Sstevel@tonic-gate } \ 7180Sstevel@tonic-gate else \ 7190Sstevel@tonic-gate { \ 7200Sstevel@tonic-gate builtin_define ("__LITTLE_ENDIAN__"); \ 7210Sstevel@tonic-gate builtin_define ("_LITTLE_ENDIAN"); \ 7220Sstevel@tonic-gate builtin_assert ("machine=littleendian"); \ 7230Sstevel@tonic-gate } \ 7240Sstevel@tonic-gate } \ 7250Sstevel@tonic-gate while (0) 7260Sstevel@tonic-gate 7270Sstevel@tonic-gate/* Target machine storage layout. */ 7280Sstevel@tonic-gate 7290Sstevel@tonic-gate/* Define this macro if it is advisable to hold scalars in registers 7300Sstevel@tonic-gate in a wider mode than that declared by the program. In such cases, 7310Sstevel@tonic-gate the value is constrained to be within the bounds of the declared 7320Sstevel@tonic-gate type, but kept valid in the wider mode. The signedness of the 7330Sstevel@tonic-gate extension may differ from that of the type. */ 7340Sstevel@tonic-gate 7350Sstevel@tonic-gate#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 7360Sstevel@tonic-gate if (GET_MODE_CLASS (MODE) == MODE_INT \ 7370Sstevel@tonic-gate && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \ 7380Sstevel@tonic-gate (MODE) = TARGET_32BIT ? SImode : DImode; 7390Sstevel@tonic-gate 7400Sstevel@tonic-gate/* Define this if most significant bit is lowest numbered 7410Sstevel@tonic-gate in instructions that operate on numbered bit-fields. */ 7420Sstevel@tonic-gate/* That is true on RS/6000. */ 7430Sstevel@tonic-gate#define BITS_BIG_ENDIAN 1 7440Sstevel@tonic-gate 7450Sstevel@tonic-gate/* Define this if most significant byte of a word is the lowest numbered. */ 7460Sstevel@tonic-gate/* That is true on RS/6000. */ 7470Sstevel@tonic-gate#define BYTES_BIG_ENDIAN 1 7480Sstevel@tonic-gate 7490Sstevel@tonic-gate/* Define this if most significant word of a multiword number is lowest 7500Sstevel@tonic-gate numbered. 7510Sstevel@tonic-gate 7520Sstevel@tonic-gate For RS/6000 we can decide arbitrarily since there are no machine 7530Sstevel@tonic-gate instructions for them. Might as well be consistent with bits and bytes. */ 7540Sstevel@tonic-gate#define WORDS_BIG_ENDIAN 1 7550Sstevel@tonic-gate 7560Sstevel@tonic-gate/* This says that for the IBM long double the larger magnitude double 7570Sstevel@tonic-gate comes first. It's really a two element double array, and arrays 7580Sstevel@tonic-gate don't index differently between little- and big-endian. */ 7590Sstevel@tonic-gate#define LONG_DOUBLE_LARGE_FIRST 1 7600Sstevel@tonic-gate 7610Sstevel@tonic-gate#define MAX_BITS_PER_WORD 64 7620Sstevel@tonic-gate 7630Sstevel@tonic-gate/* Width of a word, in units (bytes). */ 7640Sstevel@tonic-gate#define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 7650Sstevel@tonic-gate#ifdef IN_LIBGCC2 7660Sstevel@tonic-gate#define MIN_UNITS_PER_WORD UNITS_PER_WORD 7670Sstevel@tonic-gate#else 7680Sstevel@tonic-gate#define MIN_UNITS_PER_WORD 4 7690Sstevel@tonic-gate#endif 7700Sstevel@tonic-gate#define UNITS_PER_FP_WORD 8 7710Sstevel@tonic-gate#define UNITS_PER_ALTIVEC_WORD 16 7720Sstevel@tonic-gate#define UNITS_PER_VSX_WORD 16 7730Sstevel@tonic-gate#define UNITS_PER_SPE_WORD 8 7740Sstevel@tonic-gate#define UNITS_PER_PAIRED_WORD 8 7750Sstevel@tonic-gate 7760Sstevel@tonic-gate/* Type used for ptrdiff_t, as a string used in a declaration. */ 7770Sstevel@tonic-gate#define PTRDIFF_TYPE "int" 7780Sstevel@tonic-gate 7791865Sdilpreet/* Type used for size_t, as a string used in a declaration. */ 7801865Sdilpreet#define SIZE_TYPE "long unsigned int" 7811865Sdilpreet 7821865Sdilpreet/* Type used for wchar_t, as a string used in a declaration. */ 7830Sstevel@tonic-gate#define WCHAR_TYPE "short unsigned int" 7840Sstevel@tonic-gate 7850Sstevel@tonic-gate/* Width of wchar_t in bits. */ 7860Sstevel@tonic-gate#define WCHAR_TYPE_SIZE 16 7870Sstevel@tonic-gate 7880Sstevel@tonic-gate/* A C expression for the size in bits of the type `short' on the 7890Sstevel@tonic-gate target machine. If you don't define this, the default is half a 7900Sstevel@tonic-gate word. (If this would be less than one storage unit, it is 7910Sstevel@tonic-gate rounded up to one unit.) */ 7920Sstevel@tonic-gate#define SHORT_TYPE_SIZE 16 7930Sstevel@tonic-gate 7940Sstevel@tonic-gate/* A C expression for the size in bits of the type `int' on the 7950Sstevel@tonic-gate target machine. If you don't define this, the default is one 7960Sstevel@tonic-gate word. */ 7970Sstevel@tonic-gate#define INT_TYPE_SIZE 32 7980Sstevel@tonic-gate 7990Sstevel@tonic-gate/* A C expression for the size in bits of the type `long' on the 8000Sstevel@tonic-gate target machine. If you don't define this, the default is one 8010Sstevel@tonic-gate word. */ 8020Sstevel@tonic-gate#define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 8030Sstevel@tonic-gate 8040Sstevel@tonic-gate/* A C expression for the size in bits of the type `long long' on the 8050Sstevel@tonic-gate target machine. If you don't define this, the default is two 8060Sstevel@tonic-gate words. */ 8070Sstevel@tonic-gate#define LONG_LONG_TYPE_SIZE 64 8080Sstevel@tonic-gate 8090Sstevel@tonic-gate/* A C expression for the size in bits of the type `float' on the 8100Sstevel@tonic-gate target machine. If you don't define this, the default is one 8110Sstevel@tonic-gate word. */ 8120Sstevel@tonic-gate#define FLOAT_TYPE_SIZE 32 8130Sstevel@tonic-gate 8140Sstevel@tonic-gate/* A C expression for the size in bits of the type `double' on the 8150Sstevel@tonic-gate target machine. If you don't define this, the default is two 8160Sstevel@tonic-gate words. */ 8170Sstevel@tonic-gate#define DOUBLE_TYPE_SIZE 64 8180Sstevel@tonic-gate 8190Sstevel@tonic-gate/* A C expression for the size in bits of the type `long double' on 8200Sstevel@tonic-gate the target machine. If you don't define this, the default is two 8210Sstevel@tonic-gate words. */ 8220Sstevel@tonic-gate#define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 8230Sstevel@tonic-gate 8240Sstevel@tonic-gate/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 8250Sstevel@tonic-gate#define WIDEST_HARDWARE_FP_SIZE 64 8260Sstevel@tonic-gate 8270Sstevel@tonic-gate/* Width in bits of a pointer. 8280Sstevel@tonic-gate See also the macro `Pmode' defined below. */ 8290Sstevel@tonic-gateextern unsigned rs6000_pointer_size; 8300Sstevel@tonic-gate#define POINTER_SIZE rs6000_pointer_size 8310Sstevel@tonic-gate 8320Sstevel@tonic-gate/* Allocation boundary (in *bits*) for storing arguments in argument list. */ 8330Sstevel@tonic-gate#define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 8340Sstevel@tonic-gate 8350Sstevel@tonic-gate/* Boundary (in *bits*) on which stack pointer should be aligned. */ 8360Sstevel@tonic-gate#define STACK_BOUNDARY \ 8370Sstevel@tonic-gate ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 8380Sstevel@tonic-gate ? 64 : 128) 8390Sstevel@tonic-gate 8400Sstevel@tonic-gate/* Allocation boundary (in *bits*) for the code of a function. */ 8410Sstevel@tonic-gate#define FUNCTION_BOUNDARY 32 8420Sstevel@tonic-gate 8430Sstevel@tonic-gate/* No data type wants to be aligned rounder than this. */ 8440Sstevel@tonic-gate#define BIGGEST_ALIGNMENT 128 8450Sstevel@tonic-gate 8460Sstevel@tonic-gate/* Alignment of field after `int : 0' in a structure. */ 8470Sstevel@tonic-gate#define EMPTY_FIELD_BOUNDARY 32 8480Sstevel@tonic-gate 8490Sstevel@tonic-gate/* Every structure's size must be a multiple of this. */ 8500Sstevel@tonic-gate#define STRUCTURE_SIZE_BOUNDARY 8 8510Sstevel@tonic-gate 8520Sstevel@tonic-gate/* A bit-field declared as `int' forces `int' alignment for the struct. */ 8530Sstevel@tonic-gate#define PCC_BITFIELD_TYPE_MATTERS 1 8540Sstevel@tonic-gate 8550Sstevel@tonic-gateenum data_align { align_abi, align_opt, align_both }; 8560Sstevel@tonic-gate 8570Sstevel@tonic-gate/* A C expression to compute the alignment for a variables in the 8580Sstevel@tonic-gate local store. TYPE is the data type, and ALIGN is the alignment 8590Sstevel@tonic-gate that the object would ordinarily have. */ 8600Sstevel@tonic-gate#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 8610Sstevel@tonic-gate rs6000_data_alignment (TYPE, ALIGN, align_both) 8620Sstevel@tonic-gate 8630Sstevel@tonic-gate/* Make strings word-aligned so strcpy from constants will be faster. */ 8640Sstevel@tonic-gate#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 8650Sstevel@tonic-gate (TREE_CODE (EXP) == STRING_CST \ 8660Sstevel@tonic-gate && (STRICT_ALIGNMENT || !optimize_size) \ 8670Sstevel@tonic-gate && (ALIGN) < BITS_PER_WORD \ 8680Sstevel@tonic-gate ? BITS_PER_WORD \ 8690Sstevel@tonic-gate : (ALIGN)) 8700Sstevel@tonic-gate 8710Sstevel@tonic-gate/* Make arrays of chars word-aligned for the same reasons. */ 8720Sstevel@tonic-gate#define DATA_ALIGNMENT(TYPE, ALIGN) \ 8730Sstevel@tonic-gate rs6000_data_alignment (TYPE, ALIGN, align_opt) 8740Sstevel@tonic-gate 8750Sstevel@tonic-gate/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to 8760Sstevel@tonic-gate 64 bits. */ 8770Sstevel@tonic-gate#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 8780Sstevel@tonic-gate rs6000_data_alignment (TYPE, ALIGN, align_abi) 8790Sstevel@tonic-gate 8800Sstevel@tonic-gate/* Nonzero if move instructions will actually fail to work 8810Sstevel@tonic-gate when given unaligned data. */ 8820Sstevel@tonic-gate#define STRICT_ALIGNMENT 0 8830Sstevel@tonic-gate 8840Sstevel@tonic-gate/* Define this macro to be the value 1 if unaligned accesses have a cost 8850Sstevel@tonic-gate many times greater than aligned accesses, for example if they are 8860Sstevel@tonic-gate emulated in a trap handler. */ 8870Sstevel@tonic-gate/* Altivec vector memory instructions simply ignore the low bits; SPE vector 8880Sstevel@tonic-gate memory instructions trap on unaligned accesses; VSX memory instructions are 8890Sstevel@tonic-gate aligned to 4 or 8 bytes. */ 8900Sstevel@tonic-gate#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 8910Sstevel@tonic-gate (STRICT_ALIGNMENT \ 8920Sstevel@tonic-gate || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 8930Sstevel@tonic-gate || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \ 8940Sstevel@tonic-gate && (ALIGN) < 32) \ 8950Sstevel@tonic-gate || (!TARGET_EFFICIENT_UNALIGNED_VSX \ 8960Sstevel@tonic-gate && (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))) 8970Sstevel@tonic-gate 8980Sstevel@tonic-gate 8990Sstevel@tonic-gate/* Standard register usage. */ 900 901/* Number of actual hardware registers. 902 The hardware registers are assigned numbers for the compiler 903 from 0 to just below FIRST_PSEUDO_REGISTER. 904 All registers that the compiler knows about must be given numbers, 905 even those that are not normally considered general registers. 906 907 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 908 a count register, a link register, and 8 condition register fields, 909 which we view here as separate registers. AltiVec adds 32 vector 910 registers and a VRsave register. 911 912 In addition, the difference between the frame and argument pointers is 913 a function of the number of registers saved, so we need to have a 914 register for AP that will later be eliminated in favor of SP or FP. 915 This is a normal register, but it is fixed. 916 917 We also create a pseudo register for float/int conversions, that will 918 really represent the memory location used. It is represented here as 919 a register, in order to work around problems in allocating stack storage 920 in inline functions. 921 922 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 923 pointer, which is eventually eliminated in favor of SP or FP. 924 925 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ 926 927#define FIRST_PSEUDO_REGISTER 149 928 929/* This must be included for pre gcc 3.0 glibc compatibility. */ 930#define PRE_GCC3_DWARF_FRAME_REGISTERS 77 931 932/* True if register is an SPE High register. */ 933#define SPE_HIGH_REGNO_P(N) \ 934 ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) 935 936/* SPE high registers added as hard regs. 937 The sfp register and 3 HTM registers 938 aren't included in DWARF_FRAME_REGISTERS. */ 939#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) 940 941/* The SPE has an additional 32 synthetic registers, with DWARF debug 942 info numbering for these registers starting at 1200. While eh_frame 943 register numbering need not be the same as the debug info numbering, 944 we choose to number these regs for eh_frame at 1200 too. 945 946 We must map them here to avoid huge unwinder tables mostly consisting 947 of unused space. */ 948#define DWARF_REG_TO_UNWIND_COLUMN(r) \ 949 ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) 950 951/* Use standard DWARF numbering for DWARF debugging information. */ 952#define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) 953 954/* Use gcc hard register numbering for eh_frame. */ 955#define DWARF_FRAME_REGNUM(REGNO) (REGNO) 956 957/* Map register numbers held in the call frame info that gcc has 958 collected using DWARF_FRAME_REGNUM to those that should be output in 959 .debug_frame and .eh_frame. */ 960#define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 961 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1) 962 963/* 1 for registers that have pervasive standard uses 964 and are not available for the register allocator. 965 966 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 967 as a local register; for all other OS's r2 is the TOC pointer. 968 969 On System V implementations, r13 is fixed and not available for use. */ 970 971#define FIXED_REGISTERS \ 972 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 973 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 974 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 975 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 976 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ 977 /* AltiVec registers. */ \ 978 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 979 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 980 1, 1 \ 981 , 1, 1, 1, 1, 1, 1, \ 982 /* SPE High registers. */ \ 983 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 984 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 985} 986 987/* 1 for registers not available across function calls. 988 These must include the FIXED_REGISTERS and also any 989 registers that can be used without being saved. 990 The latter must include the registers where values are returned 991 and the register where structure-value addresses are passed. 992 Aside from that, you can include as many other registers as you like. */ 993 994#define CALL_USED_REGISTERS \ 995 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 996 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 997 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 998 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 999 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 1000 /* AltiVec registers. */ \ 1001 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1002 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1003 1, 1 \ 1004 , 1, 1, 1, 1, 1, 1, \ 1005 /* SPE High registers. */ \ 1006 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 1007 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ 1008} 1009 1010/* Like `CALL_USED_REGISTERS' except this macro doesn't require that 1011 the entire set of `FIXED_REGISTERS' be included. 1012 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 1013 This macro is optional. If not specified, it defaults to the value 1014 of `CALL_USED_REGISTERS'. */ 1015 1016#define CALL_REALLY_USED_REGISTERS \ 1017 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 1018 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1019 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 1020 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1021 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 1022 /* AltiVec registers. */ \ 1023 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1024 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1025 0, 0 \ 1026 , 0, 0, 0, 0, 0, 0, \ 1027 /* SPE High registers. */ \ 1028 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1029 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ 1030} 1031 1032#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 1033 1034#define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 1035#define FIRST_SAVED_FP_REGNO (14+32) 1036#define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 1037 1038/* List the order in which to allocate registers. Each register must be 1039 listed once, even those in FIXED_REGISTERS. 1040 1041 We allocate in the following order: 1042 fp0 (not saved or used for anything) 1043 fp13 - fp2 (not saved; incoming fp arg registers) 1044 fp1 (not saved; return value) 1045 fp31 - fp14 (saved; order given to save least number) 1046 cr7, cr5 (not saved or special) 1047 cr6 (not saved, but used for vector operations) 1048 cr1 (not saved, but used for FP operations) 1049 cr0 (not saved, but used for arithmetic operations) 1050 cr4, cr3, cr2 (saved) 1051 r9 (not saved; best for TImode) 1052 r10, r8-r4 (not saved; highest first for less conflict with params) 1053 r3 (not saved; return value register) 1054 r11 (not saved; later alloc to help shrink-wrap) 1055 r0 (not saved; cannot be base reg) 1056 r31 - r13 (saved; order given to save least number) 1057 r12 (not saved; if used for DImode or DFmode would use r13) 1058 ctr (not saved; when we have the choice ctr is better) 1059 lr (saved) 1060 r1, r2, ap, ca (fixed) 1061 v0 - v1 (not saved or used for anything) 1062 v13 - v3 (not saved; incoming vector arg registers) 1063 v2 (not saved; incoming vector arg reg; return value) 1064 v19 - v14 (not saved or used for anything) 1065 v31 - v20 (saved; order given to save least number) 1066 vrsave, vscr (fixed) 1067 spe_acc, spefscr (fixed) 1068 sfp (fixed) 1069 tfhar (fixed) 1070 tfiar (fixed) 1071 texasr (fixed) 1072*/ 1073 1074#if FIXED_R2 == 1 1075#define MAYBE_R2_AVAILABLE 1076#define MAYBE_R2_FIXED 2, 1077#else 1078#define MAYBE_R2_AVAILABLE 2, 1079#define MAYBE_R2_FIXED 1080#endif 1081 1082#if FIXED_R13 == 1 1083#define EARLY_R12 12, 1084#define LATE_R12 1085#else 1086#define EARLY_R12 1087#define LATE_R12 12, 1088#endif 1089 1090#define REG_ALLOC_ORDER \ 1091 {32, \ 1092 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ 1093 /* not use fr14 which is a saved register. */ \ 1094 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 1095 33, \ 1096 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 1097 50, 49, 48, 47, 46, \ 1098 75, 73, 74, 69, 68, 72, 71, 70, \ 1099 MAYBE_R2_AVAILABLE \ 1100 9, 10, 8, 7, 6, 5, 4, \ 1101 3, EARLY_R12 11, 0, \ 1102 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 1103 18, 17, 16, 15, 14, 13, LATE_R12 \ 1104 66, 65, \ 1105 1, MAYBE_R2_FIXED 67, 76, \ 1106 /* AltiVec registers. */ \ 1107 77, 78, \ 1108 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 1109 79, \ 1110 96, 95, 94, 93, 92, 91, \ 1111 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 1112 109, 110, \ 1113 111, 112, 113, 114, 115, 116, \ 1114 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \ 1115 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ 1116 141, 142, 143, 144, 145, 146, 147, 148 \ 1117} 1118 1119/* True if register is floating-point. */ 1120#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1121 1122/* True if register is a condition register. */ 1123#define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 1124 1125/* True if register is a condition register, but not cr0. */ 1126#define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 1127 1128/* True if register is an integer register. */ 1129#define INT_REGNO_P(N) \ 1130 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 1131 1132/* SPE SIMD registers are just the GPRs. */ 1133#define SPE_SIMD_REGNO_P(N) ((N) <= 31) 1134 1135/* PAIRED SIMD registers are just the FPRs. */ 1136#define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1137 1138/* True if register is the CA register. */ 1139#define CA_REGNO_P(N) ((N) == CA_REGNO) 1140 1141/* True if register is an AltiVec register. */ 1142#define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1143 1144/* True if register is a VSX register. */ 1145#define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1146 1147/* Alternate name for any vector register supporting floating point, no matter 1148 which instruction set(s) are available. */ 1149#define VFLOAT_REGNO_P(N) \ 1150 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1151 1152/* Alternate name for any vector register supporting integer, no matter which 1153 instruction set(s) are available. */ 1154#define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1155 1156/* Alternate name for any vector register supporting logical operations, no 1157 matter which instruction set(s) are available. Allow GPRs as well as the 1158 vector registers. */ 1159#define VLOGICAL_REGNO_P(N) \ 1160 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ 1161 || (TARGET_VSX && FP_REGNO_P (N))) \ 1162 1163/* Return number of consecutive hard regs needed starting at reg REGNO 1164 to hold something of mode MODE. */ 1165 1166#define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] 1167 1168/* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1169 enough space to account for vectors in FP regs. However, TFmode/TDmode 1170 should not use VSX instructions to do a caller save. */ 1171#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1172 (TARGET_VSX \ 1173 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1174 && FP_REGNO_P (REGNO) \ 1175 ? V2DFmode \ 1176 : TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode) \ 1177 ? DFmode \ 1178 : !TARGET_E500_DOUBLE && (MODE) == TFmode && FP_REGNO_P (REGNO) \ 1179 ? DFmode \ 1180 : !TARGET_E500_DOUBLE && (MODE) == TDmode && FP_REGNO_P (REGNO) \ 1181 ? DImode \ 1182 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 1183 1184#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1185 (((TARGET_32BIT && TARGET_POWERPC64 \ 1186 && (GET_MODE_SIZE (MODE) > 4) \ 1187 && INT_REGNO_P (REGNO)) ? 1 : 0) \ 1188 || (TARGET_VSX && FP_REGNO_P (REGNO) \ 1189 && GET_MODE_SIZE (MODE) > 8 && ((MODE) != TDmode) \ 1190 && ((MODE) != TFmode))) 1191 1192#define VSX_VECTOR_MODE(MODE) \ 1193 ((MODE) == V4SFmode \ 1194 || (MODE) == V2DFmode) \ 1195 1196#define ALTIVEC_VECTOR_MODE(MODE) \ 1197 ((MODE) == V16QImode \ 1198 || (MODE) == V8HImode \ 1199 || (MODE) == V4SFmode \ 1200 || (MODE) == V4SImode) 1201 1202#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1203 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1204 || (MODE) == V2DImode || (MODE) == V1TImode) 1205 1206#define SPE_VECTOR_MODE(MODE) \ 1207 ((MODE) == V4HImode \ 1208 || (MODE) == V2SFmode \ 1209 || (MODE) == V1DImode \ 1210 || (MODE) == V2SImode) 1211 1212#define PAIRED_VECTOR_MODE(MODE) \ 1213 ((MODE) == V2SFmode) 1214 1215/* Value is TRUE if hard register REGNO can hold a value of 1216 machine-mode MODE. */ 1217#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1218 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] 1219 1220/* Value is 1 if it is a good idea to tie two pseudo registers 1221 when one has mode MODE1 and one has mode MODE2. 1222 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1223 for any hard reg, then this must be 0 for correct output. 1224 1225 PTImode cannot tie with other modes because PTImode is restricted to even 1226 GPR registers, and TImode can go in any GPR as well as VSX registers (PR 1227 57744). */ 1228#define MODES_TIEABLE_P(MODE1, MODE2) \ 1229 ((MODE1) == PTImode \ 1230 ? (MODE2) == PTImode \ 1231 : (MODE2) == PTImode \ 1232 ? 0 \ 1233 : SCALAR_FLOAT_MODE_P (MODE1) \ 1234 ? SCALAR_FLOAT_MODE_P (MODE2) \ 1235 : SCALAR_FLOAT_MODE_P (MODE2) \ 1236 ? 0 \ 1237 : GET_MODE_CLASS (MODE1) == MODE_CC \ 1238 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 1239 : GET_MODE_CLASS (MODE2) == MODE_CC \ 1240 ? 0 \ 1241 : SPE_VECTOR_MODE (MODE1) \ 1242 ? SPE_VECTOR_MODE (MODE2) \ 1243 : SPE_VECTOR_MODE (MODE2) \ 1244 ? 0 \ 1245 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ 1246 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1247 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1248 ? 0 \ 1249 : 1) 1250 1251/* Post-reload, we can't use any new AltiVec registers, as we already 1252 emitted the vrsave mask. */ 1253 1254#define HARD_REGNO_RENAME_OK(SRC, DST) \ 1255 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1256 1257/* Specify the cost of a branch insn; roughly the number of extra insns that 1258 should be added to avoid a branch. 1259 1260 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1261 unscheduled conditional branch. */ 1262 1263#define BRANCH_COST(speed_p, predictable_p) 3 1264 1265/* Override BRANCH_COST heuristic which empirically produces worse 1266 performance for removing short circuiting from the logical ops. */ 1267 1268#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1269 1270/* A fixed register used at epilogue generation to address SPE registers 1271 with negative offsets. The 64-bit load/store instructions on the SPE 1272 only take positive offsets (and small ones at that), so we need to 1273 reserve a register for consing up negative offsets. */ 1274 1275#define FIXED_SCRATCH 0 1276 1277/* Specify the registers used for certain standard purposes. 1278 The values of these macros are register numbers. */ 1279 1280/* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1281/* #define PC_REGNUM */ 1282 1283/* Register to use for pushing function arguments. */ 1284#define STACK_POINTER_REGNUM 1 1285 1286/* Base register for access to local variables of the function. */ 1287#define HARD_FRAME_POINTER_REGNUM 31 1288 1289/* Base register for access to local variables of the function. */ 1290#define FRAME_POINTER_REGNUM 113 1291 1292/* Base register for access to arguments of the function. */ 1293#define ARG_POINTER_REGNUM 67 1294 1295/* Place to put static chain when calling a function that requires it. */ 1296#define STATIC_CHAIN_REGNUM 11 1297 1298 1299/* Define the classes of registers for register constraints in the 1300 machine description. Also define ranges of constants. 1301 1302 One of the classes must always be named ALL_REGS and include all hard regs. 1303 If there is more than one class, another class must be named NO_REGS 1304 and contain no registers. 1305 1306 The name GENERAL_REGS must be the name of a class (or an alias for 1307 another name such as ALL_REGS). This is the class of registers 1308 that is allowed by "g" or "r" in a register constraint. 1309 Also, registers outside this class are allocated only when 1310 instructions express preferences for them. 1311 1312 The classes must be numbered in nondecreasing order; that is, 1313 a larger-numbered class must never be contained completely 1314 in a smaller-numbered class. 1315 1316 For any two classes, it is very desirable that there be another 1317 class that represents their union. */ 1318 1319/* The RS/6000 has three types of registers, fixed-point, floating-point, and 1320 condition registers, plus three special registers, CTR, and the link 1321 register. AltiVec adds a vector register class. VSX registers overlap the 1322 FPR registers and the Altivec registers. 1323 1324 However, r0 is special in that it cannot be used as a base register. 1325 So make a class for registers valid as base registers. 1326 1327 Also, cr0 is the only condition code register that can be used in 1328 arithmetic insns, so make a separate class for it. */ 1329 1330enum reg_class 1331{ 1332 NO_REGS, 1333 BASE_REGS, 1334 GENERAL_REGS, 1335 FLOAT_REGS, 1336 ALTIVEC_REGS, 1337 VSX_REGS, 1338 VRSAVE_REGS, 1339 VSCR_REGS, 1340 SPE_ACC_REGS, 1341 SPEFSCR_REGS, 1342 SPR_REGS, 1343 NON_SPECIAL_REGS, 1344 LINK_REGS, 1345 CTR_REGS, 1346 LINK_OR_CTR_REGS, 1347 SPECIAL_REGS, 1348 SPEC_OR_GEN_REGS, 1349 CR0_REGS, 1350 CR_REGS, 1351 NON_FLOAT_REGS, 1352 CA_REGS, 1353 SPE_HIGH_REGS, 1354 ALL_REGS, 1355 LIM_REG_CLASSES 1356}; 1357 1358#define N_REG_CLASSES (int) LIM_REG_CLASSES 1359 1360/* Give names of register classes as strings for dump file. */ 1361 1362#define REG_CLASS_NAMES \ 1363{ \ 1364 "NO_REGS", \ 1365 "BASE_REGS", \ 1366 "GENERAL_REGS", \ 1367 "FLOAT_REGS", \ 1368 "ALTIVEC_REGS", \ 1369 "VSX_REGS", \ 1370 "VRSAVE_REGS", \ 1371 "VSCR_REGS", \ 1372 "SPE_ACC_REGS", \ 1373 "SPEFSCR_REGS", \ 1374 "SPR_REGS", \ 1375 "NON_SPECIAL_REGS", \ 1376 "LINK_REGS", \ 1377 "CTR_REGS", \ 1378 "LINK_OR_CTR_REGS", \ 1379 "SPECIAL_REGS", \ 1380 "SPEC_OR_GEN_REGS", \ 1381 "CR0_REGS", \ 1382 "CR_REGS", \ 1383 "NON_FLOAT_REGS", \ 1384 "CA_REGS", \ 1385 "SPE_HIGH_REGS", \ 1386 "ALL_REGS" \ 1387} 1388 1389/* Define which registers fit in which classes. 1390 This is an initializer for a vector of HARD_REG_SET 1391 of length N_REG_CLASSES. */ 1392 1393#define REG_CLASS_CONTENTS \ 1394{ \ 1395 /* NO_REGS. */ \ 1396 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1397 /* BASE_REGS. */ \ 1398 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ 1399 /* GENERAL_REGS. */ \ 1400 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ 1401 /* FLOAT_REGS. */ \ 1402 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \ 1403 /* ALTIVEC_REGS. */ \ 1404 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \ 1405 /* VSX_REGS. */ \ 1406 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \ 1407 /* VRSAVE_REGS. */ \ 1408 { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \ 1409 /* VSCR_REGS. */ \ 1410 { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \ 1411 /* SPE_ACC_REGS. */ \ 1412 { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \ 1413 /* SPEFSCR_REGS. */ \ 1414 { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \ 1415 /* SPR_REGS. */ \ 1416 { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \ 1417 /* NON_SPECIAL_REGS. */ \ 1418 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \ 1419 /* LINK_REGS. */ \ 1420 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \ 1421 /* CTR_REGS. */ \ 1422 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \ 1423 /* LINK_OR_CTR_REGS. */ \ 1424 { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \ 1425 /* SPECIAL_REGS. */ \ 1426 { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \ 1427 /* SPEC_OR_GEN_REGS. */ \ 1428 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \ 1429 /* CR0_REGS. */ \ 1430 { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \ 1431 /* CR_REGS. */ \ 1432 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \ 1433 /* NON_FLOAT_REGS. */ \ 1434 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \ 1435 /* CA_REGS. */ \ 1436 { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \ 1437 /* SPE_HIGH_REGS. */ \ 1438 { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \ 1439 /* ALL_REGS. */ \ 1440 { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \ 1441} 1442 1443/* The same information, inverted: 1444 Return the class number of the smallest class containing 1445 reg number REGNO. This could be a conditional expression 1446 or could index an array. */ 1447 1448extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1449 1450#if ENABLE_CHECKING 1451#define REGNO_REG_CLASS(REGNO) \ 1452 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ 1453 rs6000_regno_regclass[(REGNO)]) 1454 1455#else 1456#define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] 1457#endif 1458 1459/* Register classes for various constraints that are based on the target 1460 switches. */ 1461enum r6000_reg_class_enum { 1462 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1463 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1464 RS6000_CONSTRAINT_v, /* Altivec registers */ 1465 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1466 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ 1467 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ 1468 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ 1469 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ 1470 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ 1471 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ 1472 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ 1473 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ 1474 RS6000_CONSTRAINT_wm, /* VSX register for direct move */ 1475 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ 1476 RS6000_CONSTRAINT_ws, /* VSX register for DF */ 1477 RS6000_CONSTRAINT_wt, /* VSX register for TImode */ 1478 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ 1479 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ 1480 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ 1481 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ 1482 RS6000_CONSTRAINT_wy, /* VSX register for SF */ 1483 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ 1484 RS6000_CONSTRAINT_MAX 1485}; 1486 1487extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1488 1489/* The class value for index registers, and the one for base regs. */ 1490#define INDEX_REG_CLASS GENERAL_REGS 1491#define BASE_REG_CLASS BASE_REGS 1492 1493/* Return whether a given register class can hold VSX objects. */ 1494#define VSX_REG_CLASS_P(CLASS) \ 1495 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1496 1497/* Return whether a given register class targets general purpose registers. */ 1498#define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) 1499 1500/* Given an rtx X being reloaded into a reg required to be 1501 in class CLASS, return the class of reg to actually use. 1502 In general this is just CLASS; but on some machines 1503 in some cases it is preferable to use a more restrictive class. 1504 1505 On the RS/6000, we have to return NO_REGS when we want to reload a 1506 floating-point CONST_DOUBLE to force it to be copied to memory. 1507 1508 We also don't want to reload integer values into floating-point 1509 registers if we can at all help it. In fact, this can 1510 cause reload to die, if it tries to generate a reload of CTR 1511 into a FP register and discovers it doesn't have the memory location 1512 required. 1513 1514 ??? Would it be a good idea to have reload do the converse, that is 1515 try to reload floating modes into FP registers if possible? 1516 */ 1517 1518#define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1519 rs6000_preferred_reload_class_ptr (X, CLASS) 1520 1521/* Return the register class of a scratch register needed to copy IN into 1522 or out of a register in CLASS in MODE. If it can be done directly, 1523 NO_REGS is returned. */ 1524 1525#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1526 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1527 1528/* If we are copying between FP or AltiVec registers and anything 1529 else, we need a memory location. The exception is when we are 1530 targeting ppc64 and the move to/from fpr to gpr instructions 1531 are available.*/ 1532 1533#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1534 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) 1535 1536/* For cpus that cannot load/store SDmode values from the 64-bit 1537 FP registers without using a full 64-bit load/store, we need 1538 to allocate a full 64-bit stack slot for them. */ 1539 1540#define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1541 rs6000_secondary_memory_needed_rtx (MODE) 1542 1543/* Specify the mode to be used for memory when a secondary memory 1544 location is needed. For cpus that cannot load/store SDmode values 1545 from the 64-bit FP registers without using a full 64-bit 1546 load/store, we need a wider mode. */ 1547#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1548 rs6000_secondary_memory_needed_mode (MODE) 1549 1550/* Return the maximum number of consecutive registers 1551 needed to represent mode MODE in a register of class CLASS. 1552 1553 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1554 a single reg is enough for two words, unless we have VSX, where the FP 1555 registers can hold 128 bits. */ 1556#define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1557 1558/* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ 1559 1560#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1561 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) 1562 1563/* Stack layout; function entry, exit and calling. */ 1564 1565/* Define this if pushing a word on the stack 1566 makes the stack pointer a smaller address. */ 1567#define STACK_GROWS_DOWNWARD 1568 1569/* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1570#define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1571 1572/* Define this to nonzero if the nominal address of the stack frame 1573 is at the high-address end of the local variables; 1574 that is, each additional local variable allocated 1575 goes at a more negative offset in the frame. 1576 1577 On the RS/6000, we grow upwards, from the area after the outgoing 1578 arguments. */ 1579#define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 1580 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 1581 1582/* Size of the fixed area on the stack */ 1583#define RS6000_SAVE_AREA \ 1584 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ 1585 << (TARGET_64BIT ? 1 : 0)) 1586 1587/* Stack offset for toc save slot. */ 1588#define RS6000_TOC_SAVE_SLOT \ 1589 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) 1590 1591/* Align an address */ 1592#define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1593 1594/* Offset within stack frame to start allocating local variables at. 1595 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1596 first local allocated. Otherwise, it is the offset to the BEGINNING 1597 of the first local allocated. 1598 1599 On the RS/6000, the frame pointer is the same as the stack pointer, 1600 except for dynamic allocations. So we start after the fixed area and 1601 outgoing parameter area. */ 1602 1603#define STARTING_FRAME_OFFSET \ 1604 (FRAME_GROWS_DOWNWARD \ 1605 ? 0 \ 1606 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1607 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1608 + RS6000_SAVE_AREA)) 1609 1610/* Offset from the stack pointer register to an item dynamically 1611 allocated on the stack, e.g., by `alloca'. 1612 1613 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1614 length of the outgoing arguments. The default is correct for most 1615 machines. See `function.c' for details. */ 1616#define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1617 (RS6000_ALIGN (crtl->outgoing_args_size, \ 1618 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1619 + (STACK_POINTER_OFFSET)) 1620 1621/* If we generate an insn to push BYTES bytes, 1622 this says how many the stack pointer really advances by. 1623 On RS/6000, don't define this because there are no push insns. */ 1624/* #define PUSH_ROUNDING(BYTES) */ 1625 1626/* Offset of first parameter from the argument pointer register value. 1627 On the RS/6000, we define the argument pointer to the start of the fixed 1628 area. */ 1629#define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1630 1631/* Offset from the argument pointer register value to the top of 1632 stack. This is different from FIRST_PARM_OFFSET because of the 1633 register save area. */ 1634#define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1635 1636/* Define this if stack space is still allocated for a parameter passed 1637 in a register. The value is the number of bytes allocated to this 1638 area. */ 1639#define REG_PARM_STACK_SPACE(FNDECL) \ 1640 rs6000_reg_parm_stack_space ((FNDECL), false) 1641 1642/* Define this macro if space guaranteed when compiling a function body 1643 is different to space required when making a call, a situation that 1644 can arise with K&R style function definitions. */ 1645#define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ 1646 rs6000_reg_parm_stack_space ((FNDECL), true) 1647 1648/* Define this if the above stack space is to be considered part of the 1649 space allocated by the caller. */ 1650#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1651 1652/* This is the difference between the logical top of stack and the actual sp. 1653 1654 For the RS/6000, sp points past the fixed area. */ 1655#define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1656 1657/* Define this if the maximum size of all the outgoing args is to be 1658 accumulated and pushed during the prologue. The amount can be 1659 found in the variable crtl->outgoing_args_size. */ 1660#define ACCUMULATE_OUTGOING_ARGS 1 1661 1662/* Define how to find the value returned by a library function 1663 assuming the value has mode MODE. */ 1664 1665#define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1666 1667/* DRAFT_V4_STRUCT_RET defaults off. */ 1668#define DRAFT_V4_STRUCT_RET 0 1669 1670/* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1671#define DEFAULT_PCC_STRUCT_RETURN 0 1672 1673/* Mode of stack savearea. 1674 FUNCTION is VOIDmode because calling convention maintains SP. 1675 BLOCK needs Pmode for SP. 1676 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1677#define STACK_SAVEAREA_MODE(LEVEL) \ 1678 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1679 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) 1680 1681/* Minimum and maximum general purpose registers used to hold arguments. */ 1682#define GP_ARG_MIN_REG 3 1683#define GP_ARG_MAX_REG 10 1684#define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1685 1686/* Minimum and maximum floating point registers used to hold arguments. */ 1687#define FP_ARG_MIN_REG 33 1688#define FP_ARG_AIX_MAX_REG 45 1689#define FP_ARG_V4_MAX_REG 40 1690#define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ 1691 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) 1692#define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1693 1694/* Minimum and maximum AltiVec registers used to hold arguments. */ 1695#define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1696#define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1697#define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1698 1699/* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ 1700#define AGGR_ARG_NUM_REG 8 1701 1702/* Return registers */ 1703#define GP_ARG_RETURN GP_ARG_MIN_REG 1704#define FP_ARG_RETURN FP_ARG_MIN_REG 1705#define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1706#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ 1707 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1708#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \ 1709 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1710 1711/* Flags for the call/call_value rtl operations set up by function_arg */ 1712#define CALL_NORMAL 0x00000000 /* no special processing */ 1713/* Bits in 0x00000001 are unused. */ 1714#define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1715#define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1716#define CALL_LONG 0x00000008 /* always call indirect */ 1717#define CALL_LIBCALL 0x00000010 /* libcall */ 1718 1719/* We don't have prologue and epilogue functions to save/restore 1720 everything for most ABIs. */ 1721#define WORLD_SAVE_P(INFO) 0 1722 1723/* 1 if N is a possible register number for a function value 1724 as seen by the caller. 1725 1726 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1727#define FUNCTION_VALUE_REGNO_P(N) \ 1728 ((N) == GP_ARG_RETURN \ 1729 || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \ 1730 && TARGET_HARD_FLOAT && TARGET_FPRS) \ 1731 || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \ 1732 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1733 1734/* 1 if N is a possible register number for function argument passing. 1735 On RS/6000, these are r3-r10 and fp1-fp13. 1736 On AltiVec, v2 - v13 are used for passing vectors. */ 1737#define FUNCTION_ARG_REGNO_P(N) \ 1738 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1739 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1740 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1741 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1742 && TARGET_HARD_FLOAT && TARGET_FPRS)) 1743 1744/* Define a data type for recording info about an argument list 1745 during the scan of that argument list. This data type should 1746 hold all necessary information about the function itself 1747 and about the args processed so far, enough to enable macros 1748 such as FUNCTION_ARG to determine where the next arg should go. 1749 1750 On the RS/6000, this is a structure. The first element is the number of 1751 total argument words, the second is used to store the next 1752 floating-point register number, and the third says how many more args we 1753 have prototype types for. 1754 1755 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1756 the next available GP register, `fregno' is the next available FP 1757 register, and `words' is the number of words used on the stack. 1758 1759 The varargs/stdarg support requires that this structure's size 1760 be a multiple of sizeof(int). */ 1761 1762typedef struct rs6000_args 1763{ 1764 int words; /* # words used for passing GP registers */ 1765 int fregno; /* next available FP register */ 1766 int vregno; /* next available AltiVec register */ 1767 int nargs_prototype; /* # args left in the current prototype */ 1768 int prototype; /* Whether a prototype was defined */ 1769 int stdarg; /* Whether function is a stdarg function. */ 1770 int call_cookie; /* Do special things for this call */ 1771 int sysv_gregno; /* next available GP register */ 1772 int intoffset; /* running offset in struct (darwin64) */ 1773 int use_stack; /* any part of struct on stack (darwin64) */ 1774 int floats_in_gpr; /* count of SFmode floats taking up 1775 GPR space (darwin64) */ 1776 int named; /* false for varargs params */ 1777 int escapes; /* if function visible outside tu */ 1778} CUMULATIVE_ARGS; 1779 1780/* Initialize a variable CUM of type CUMULATIVE_ARGS 1781 for a call to a function whose data type is FNTYPE. 1782 For a library call, FNTYPE is 0. */ 1783 1784#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1785 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1786 N_NAMED_ARGS, FNDECL, VOIDmode) 1787 1788/* Similar, but when scanning the definition of a procedure. We always 1789 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1790 1791#define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1792 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1793 1000, current_function_decl, VOIDmode) 1794 1795/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1796 1797#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1798 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1799 0, NULL_TREE, MODE) 1800 1801/* If defined, a C expression which determines whether, and in which 1802 direction, to pad out an argument with extra space. The value 1803 should be of type `enum direction': either `upward' to pad above 1804 the argument, `downward' to pad below, or `none' to inhibit 1805 padding. */ 1806 1807#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1808 1809#define PAD_VARARGS_DOWN \ 1810 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1811 1812/* Output assembler code to FILE to increment profiler label # LABELNO 1813 for profiling a function entry. */ 1814 1815#define FUNCTION_PROFILER(FILE, LABELNO) \ 1816 output_function_profiler ((FILE), (LABELNO)); 1817 1818/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1819 the stack pointer does not matter. No definition is equivalent to 1820 always zero. 1821 1822 On the RS/6000, this is nonzero because we can restore the stack from 1823 its backpointer, which we maintain. */ 1824#define EXIT_IGNORE_STACK 1 1825 1826/* Define this macro as a C expression that is nonzero for registers 1827 that are used by the epilogue or the return' pattern. The stack 1828 and frame pointer registers are already be assumed to be used as 1829 needed. */ 1830 1831#define EPILOGUE_USES(REGNO) \ 1832 ((reload_completed && (REGNO) == LR_REGNO) \ 1833 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1834 || (crtl->calls_eh_return \ 1835 && TARGET_AIX \ 1836 && (REGNO) == 2)) 1837 1838 1839/* Length in units of the trampoline for entering a nested function. */ 1840 1841#define TRAMPOLINE_SIZE rs6000_trampoline_size () 1842 1843/* Definitions for __builtin_return_address and __builtin_frame_address. 1844 __builtin_return_address (0) should give link register (65), enable 1845 this. */ 1846/* This should be uncommented, so that the link register is used, but 1847 currently this would result in unmatched insns and spilling fixed 1848 registers so we'll leave it for another day. When these problems are 1849 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1850 (mrs) */ 1851/* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1852 1853/* Number of bytes into the frame return addresses can be found. See 1854 rs6000_stack_info in rs6000.c for more information on how the different 1855 abi's store the return address. */ 1856#define RETURN_ADDRESS_OFFSET \ 1857 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) 1858 1859/* The current return address is in link register (65). The return address 1860 of anything farther back is accessed normally at an offset of 8 from the 1861 frame pointer. */ 1862#define RETURN_ADDR_RTX(COUNT, FRAME) \ 1863 (rs6000_return_addr (COUNT, FRAME)) 1864 1865 1866/* Definitions for register eliminations. 1867 1868 We have two registers that can be eliminated on the RS/6000. First, the 1869 frame pointer register can often be eliminated in favor of the stack 1870 pointer register. Secondly, the argument pointer register can always be 1871 eliminated; it is replaced with either the stack or frame pointer. 1872 1873 In addition, we use the elimination mechanism to see if r30 is needed 1874 Initially we assume that it isn't. If it is, we spill it. This is done 1875 by making it an eliminable register. We replace it with itself so that 1876 if it isn't needed, then existing uses won't be modified. */ 1877 1878/* This is an array of structures. Each structure initializes one pair 1879 of eliminable registers. The "from" register number is given first, 1880 followed by "to". Eliminations of the same "from" register are listed 1881 in order of preference. */ 1882#define ELIMINABLE_REGS \ 1883{{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1884 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1885 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1886 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1887 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1888 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1889 1890/* Define the offset between two registers, one to be eliminated, and the other 1891 its replacement, at the start of a routine. */ 1892#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1893 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1894 1895/* Addressing modes, and classification of registers for them. */ 1896 1897#define HAVE_PRE_DECREMENT 1 1898#define HAVE_PRE_INCREMENT 1 1899#define HAVE_PRE_MODIFY_DISP 1 1900#define HAVE_PRE_MODIFY_REG 1 1901 1902/* Macros to check register numbers against specific register classes. */ 1903 1904/* These assume that REGNO is a hard or pseudo reg number. 1905 They give nonzero only if REGNO is a hard reg of the suitable class 1906 or a pseudo reg currently allocated to a suitable hard reg. 1907 Since they use reg_renumber, they are safe only once reg_renumber 1908 has been allocated, which happens in reginfo.c during register 1909 allocation. */ 1910 1911#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1912((REGNO) < FIRST_PSEUDO_REGISTER \ 1913 ? (REGNO) <= 31 || (REGNO) == 67 \ 1914 || (REGNO) == FRAME_POINTER_REGNUM \ 1915 : (reg_renumber[REGNO] >= 0 \ 1916 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1917 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1918 1919#define REGNO_OK_FOR_BASE_P(REGNO) \ 1920((REGNO) < FIRST_PSEUDO_REGISTER \ 1921 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1922 || (REGNO) == FRAME_POINTER_REGNUM \ 1923 : (reg_renumber[REGNO] > 0 \ 1924 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1925 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1926 1927/* Nonzero if X is a hard reg that can be used as an index 1928 or if it is a pseudo reg in the non-strict case. */ 1929#define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1930 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1931 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1932 1933/* Nonzero if X is a hard reg that can be used as a base reg 1934 or if it is a pseudo reg in the non-strict case. */ 1935#define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1936 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1937 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1938 1939 1940/* Maximum number of registers that can appear in a valid memory address. */ 1941 1942#define MAX_REGS_PER_ADDRESS 2 1943 1944/* Recognize any constant value that is a valid address. */ 1945 1946#define CONSTANT_ADDRESS_P(X) \ 1947 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1948 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1949 || GET_CODE (X) == HIGH) 1950 1951#define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1952#define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1953 && EASY_VECTOR_15((n) >> 1) \ 1954 && ((n) & 1) == 0) 1955 1956#define EASY_VECTOR_MSB(n,mode) \ 1957 (((unsigned HOST_WIDE_INT)n) == \ 1958 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1959 1960 1961/* Try a machine-dependent way of reloading an illegitimate address 1962 operand. If we find one, push the reload and jump to WIN. This 1963 macro is used in only one place: `find_reloads_address' in reload.c. 1964 1965 Implemented on rs6000 by rs6000_legitimize_reload_address. 1966 Note that (X) is evaluated twice; this is safe in current usage. */ 1967 1968#define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1969do { \ 1970 int win; \ 1971 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ 1972 (int)(TYPE), (IND_LEVELS), &win); \ 1973 if ( win ) \ 1974 goto WIN; \ 1975} while (0) 1976 1977#define FIND_BASE_TERM rs6000_find_base_term 1978 1979/* The register number of the register used to address a table of 1980 static data addresses in memory. In some cases this register is 1981 defined by a processor's "application binary interface" (ABI). 1982 When this macro is defined, RTL is generated for this register 1983 once, as with the stack pointer and frame pointer registers. If 1984 this macro is not defined, it is up to the machine-dependent files 1985 to allocate such a register (if necessary). */ 1986 1987#define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1988#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 1989 1990#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1991 1992/* Define this macro if the register defined by 1993 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1994 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1995 1996/* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1997 1998/* A C expression that is nonzero if X is a legitimate immediate 1999 operand on the target machine when generating position independent 2000 code. You can assume that X satisfies `CONSTANT_P', so you need 2001 not check this. You can also assume FLAG_PIC is true, so you need 2002 not check it either. You need not define this macro if all 2003 constants (including `SYMBOL_REF') can be immediate operands when 2004 generating position independent code. */ 2005 2006/* #define LEGITIMATE_PIC_OPERAND_P (X) */ 2007 2008/* Define this if some processing needs to be done immediately before 2009 emitting code for an insn. */ 2010 2011#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ 2012 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) 2013 2014/* Specify the machine mode that this machine uses 2015 for the index in the tablejump instruction. */ 2016#define CASE_VECTOR_MODE SImode 2017 2018/* Define as C expression which evaluates to nonzero if the tablejump 2019 instruction expects the table to contain offsets from the address of the 2020 table. 2021 Do not define this if the table should contain absolute addresses. */ 2022#define CASE_VECTOR_PC_RELATIVE 1 2023 2024/* Define this as 1 if `char' should by default be signed; else as 0. */ 2025#define DEFAULT_SIGNED_CHAR 0 2026 2027/* An integer expression for the size in bits of the largest integer machine 2028 mode that should actually be used. */ 2029 2030/* Allow pairs of registers to be used, which is the intent of the default. */ 2031#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 2032 2033/* Max number of bytes we can move from memory to memory 2034 in one reasonably fast instruction. */ 2035#define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 2036#define MAX_MOVE_MAX 8 2037 2038/* Nonzero if access to memory by bytes is no faster than for words. 2039 Also nonzero if doing byte operations (specifically shifts) in registers 2040 is undesirable. */ 2041#define SLOW_BYTE_ACCESS 1 2042 2043/* Define if operations between registers always perform the operation 2044 on the full register even if a narrower mode is specified. */ 2045#define WORD_REGISTER_OPERATIONS 2046 2047/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2048 will either zero-extend or sign-extend. The value of this macro should 2049 be the code that says which one of the two operations is implicitly 2050 done, UNKNOWN if none. */ 2051#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2052 2053/* Define if loading short immediate values into registers sign extends. */ 2054#define SHORT_IMMEDIATES_SIGN_EXTEND 2055 2056/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 2057 is done just by pretending it is already truncated. */ 2058#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2059 2060/* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 2061#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2062 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 2063 2064/* The CTZ patterns return -1 for input of zero. */ 2065#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) 2066 2067/* Specify the machine mode that pointers have. 2068 After generation of rtl, the compiler makes no further distinction 2069 between pointers and any other objects of this machine mode. */ 2070extern unsigned rs6000_pmode; 2071#define Pmode ((machine_mode)rs6000_pmode) 2072 2073/* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 2074#define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 2075 2076/* Mode of a function address in a call instruction (for indexing purposes). 2077 Doesn't matter on RS/6000. */ 2078#define FUNCTION_MODE SImode 2079 2080/* Define this if addresses of constant functions 2081 shouldn't be put through pseudo regs where they can be cse'd. 2082 Desirable on machines where ordinary constants are expensive 2083 but a CALL with constant address is cheap. */ 2084#define NO_FUNCTION_CSE 2085 2086/* Define this to be nonzero if shift instructions ignore all but the low-order 2087 few bits. 2088 2089 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 2090 have been dropped from the PowerPC architecture. */ 2091#define SHIFT_COUNT_TRUNCATED 0 2092 2093/* Adjust the length of an INSN. LENGTH is the currently-computed length and 2094 should be adjusted to reflect any required changes. This macro is used when 2095 there is some systematic length adjustment required that would be difficult 2096 to express in the length attribute. */ 2097 2098/* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 2099 2100/* Given a comparison code (EQ, NE, etc.) and the first operand of a 2101 COMPARE, return the mode to be used for the comparison. For 2102 floating-point, CCFPmode should be used. CCUNSmode should be used 2103 for unsigned comparisons. CCEQmode should be used when we are 2104 doing an inequality comparison on the result of a 2105 comparison. CCmode should be used in all other cases. */ 2106 2107#define SELECT_CC_MODE(OP,X,Y) \ 2108 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 2109 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 2110 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 2111 ? CCEQmode : CCmode)) 2112 2113/* Can the condition code MODE be safely reversed? This is safe in 2114 all cases on this port, because at present it doesn't use the 2115 trapping FP comparisons (fcmpo). */ 2116#define REVERSIBLE_CC_MODE(MODE) 1 2117 2118/* Given a condition code and a mode, return the inverse condition. */ 2119#define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 2120 2121 2122/* Control the assembler format that we output. */ 2123 2124/* A C string constant describing how to begin a comment in the target 2125 assembler language. The compiler assumes that the comment will end at 2126 the end of the line. */ 2127#define ASM_COMMENT_START " #" 2128 2129/* Flag to say the TOC is initialized */ 2130extern int toc_initialized; 2131 2132/* Macro to output a special constant pool entry. Go to WIN if we output 2133 it. Otherwise, it is written the usual way. 2134 2135 On the RS/6000, toc entries are handled this way. */ 2136 2137#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 2138{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 2139 { \ 2140 output_toc (FILE, X, LABELNO, MODE); \ 2141 goto WIN; \ 2142 } \ 2143} 2144 2145#ifdef HAVE_GAS_WEAK 2146#define RS6000_WEAK 1 2147#else 2148#define RS6000_WEAK 0 2149#endif 2150 2151#if RS6000_WEAK 2152/* Used in lieu of ASM_WEAKEN_LABEL. */ 2153#define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 2154 do \ 2155 { \ 2156 fputs ("\t.weak\t", (FILE)); \ 2157 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2158 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2159 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2160 { \ 2161 if (TARGET_XCOFF) \ 2162 fputs ("[DS]", (FILE)); \ 2163 fputs ("\n\t.weak\t.", (FILE)); \ 2164 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2165 } \ 2166 fputc ('\n', (FILE)); \ 2167 if (VAL) \ 2168 { \ 2169 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 2170 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2171 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2172 { \ 2173 fputs ("\t.set\t.", (FILE)); \ 2174 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2175 fputs (",.", (FILE)); \ 2176 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 2177 fputc ('\n', (FILE)); \ 2178 } \ 2179 } \ 2180 } \ 2181 while (0) 2182#endif 2183 2184#if HAVE_GAS_WEAKREF 2185#define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 2186 do \ 2187 { \ 2188 fputs ("\t.weakref\t", (FILE)); \ 2189 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2190 fputs (", ", (FILE)); \ 2191 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2192 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2193 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2194 { \ 2195 fputs ("\n\t.weakref\t.", (FILE)); \ 2196 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2197 fputs (", .", (FILE)); \ 2198 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2199 } \ 2200 fputc ('\n', (FILE)); \ 2201 } while (0) 2202#endif 2203 2204/* This implements the `alias' attribute. */ 2205#undef ASM_OUTPUT_DEF_FROM_DECLS 2206#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2207 do \ 2208 { \ 2209 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2210 const char *name = IDENTIFIER_POINTER (TARGET); \ 2211 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2212 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2213 { \ 2214 if (TREE_PUBLIC (DECL)) \ 2215 { \ 2216 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2217 { \ 2218 fputs ("\t.globl\t.", FILE); \ 2219 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2220 putc ('\n', FILE); \ 2221 } \ 2222 } \ 2223 else if (TARGET_XCOFF) \ 2224 { \ 2225 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2226 { \ 2227 fputs ("\t.lglobl\t.", FILE); \ 2228 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2229 putc ('\n', FILE); \ 2230 fputs ("\t.lglobl\t", FILE); \ 2231 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2232 putc ('\n', FILE); \ 2233 } \ 2234 } \ 2235 fputs ("\t.set\t.", FILE); \ 2236 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2237 fputs (",.", FILE); \ 2238 RS6000_OUTPUT_BASENAME (FILE, name); \ 2239 fputc ('\n', FILE); \ 2240 } \ 2241 ASM_OUTPUT_DEF (FILE, alias, name); \ 2242 } \ 2243 while (0) 2244 2245#define TARGET_ASM_FILE_START rs6000_file_start 2246 2247/* Output to assembler file text saying following lines 2248 may contain character constants, extra white space, comments, etc. */ 2249 2250#define ASM_APP_ON "" 2251 2252/* Output to assembler file text saying following lines 2253 no longer contain unusual constructs. */ 2254 2255#define ASM_APP_OFF "" 2256 2257/* How to refer to registers in assembler output. 2258 This sequence is indexed by compiler's hard-register-number (see above). */ 2259 2260extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2261 2262#define REGISTER_NAMES \ 2263{ \ 2264 &rs6000_reg_names[ 0][0], /* r0 */ \ 2265 &rs6000_reg_names[ 1][0], /* r1 */ \ 2266 &rs6000_reg_names[ 2][0], /* r2 */ \ 2267 &rs6000_reg_names[ 3][0], /* r3 */ \ 2268 &rs6000_reg_names[ 4][0], /* r4 */ \ 2269 &rs6000_reg_names[ 5][0], /* r5 */ \ 2270 &rs6000_reg_names[ 6][0], /* r6 */ \ 2271 &rs6000_reg_names[ 7][0], /* r7 */ \ 2272 &rs6000_reg_names[ 8][0], /* r8 */ \ 2273 &rs6000_reg_names[ 9][0], /* r9 */ \ 2274 &rs6000_reg_names[10][0], /* r10 */ \ 2275 &rs6000_reg_names[11][0], /* r11 */ \ 2276 &rs6000_reg_names[12][0], /* r12 */ \ 2277 &rs6000_reg_names[13][0], /* r13 */ \ 2278 &rs6000_reg_names[14][0], /* r14 */ \ 2279 &rs6000_reg_names[15][0], /* r15 */ \ 2280 &rs6000_reg_names[16][0], /* r16 */ \ 2281 &rs6000_reg_names[17][0], /* r17 */ \ 2282 &rs6000_reg_names[18][0], /* r18 */ \ 2283 &rs6000_reg_names[19][0], /* r19 */ \ 2284 &rs6000_reg_names[20][0], /* r20 */ \ 2285 &rs6000_reg_names[21][0], /* r21 */ \ 2286 &rs6000_reg_names[22][0], /* r22 */ \ 2287 &rs6000_reg_names[23][0], /* r23 */ \ 2288 &rs6000_reg_names[24][0], /* r24 */ \ 2289 &rs6000_reg_names[25][0], /* r25 */ \ 2290 &rs6000_reg_names[26][0], /* r26 */ \ 2291 &rs6000_reg_names[27][0], /* r27 */ \ 2292 &rs6000_reg_names[28][0], /* r28 */ \ 2293 &rs6000_reg_names[29][0], /* r29 */ \ 2294 &rs6000_reg_names[30][0], /* r30 */ \ 2295 &rs6000_reg_names[31][0], /* r31 */ \ 2296 \ 2297 &rs6000_reg_names[32][0], /* fr0 */ \ 2298 &rs6000_reg_names[33][0], /* fr1 */ \ 2299 &rs6000_reg_names[34][0], /* fr2 */ \ 2300 &rs6000_reg_names[35][0], /* fr3 */ \ 2301 &rs6000_reg_names[36][0], /* fr4 */ \ 2302 &rs6000_reg_names[37][0], /* fr5 */ \ 2303 &rs6000_reg_names[38][0], /* fr6 */ \ 2304 &rs6000_reg_names[39][0], /* fr7 */ \ 2305 &rs6000_reg_names[40][0], /* fr8 */ \ 2306 &rs6000_reg_names[41][0], /* fr9 */ \ 2307 &rs6000_reg_names[42][0], /* fr10 */ \ 2308 &rs6000_reg_names[43][0], /* fr11 */ \ 2309 &rs6000_reg_names[44][0], /* fr12 */ \ 2310 &rs6000_reg_names[45][0], /* fr13 */ \ 2311 &rs6000_reg_names[46][0], /* fr14 */ \ 2312 &rs6000_reg_names[47][0], /* fr15 */ \ 2313 &rs6000_reg_names[48][0], /* fr16 */ \ 2314 &rs6000_reg_names[49][0], /* fr17 */ \ 2315 &rs6000_reg_names[50][0], /* fr18 */ \ 2316 &rs6000_reg_names[51][0], /* fr19 */ \ 2317 &rs6000_reg_names[52][0], /* fr20 */ \ 2318 &rs6000_reg_names[53][0], /* fr21 */ \ 2319 &rs6000_reg_names[54][0], /* fr22 */ \ 2320 &rs6000_reg_names[55][0], /* fr23 */ \ 2321 &rs6000_reg_names[56][0], /* fr24 */ \ 2322 &rs6000_reg_names[57][0], /* fr25 */ \ 2323 &rs6000_reg_names[58][0], /* fr26 */ \ 2324 &rs6000_reg_names[59][0], /* fr27 */ \ 2325 &rs6000_reg_names[60][0], /* fr28 */ \ 2326 &rs6000_reg_names[61][0], /* fr29 */ \ 2327 &rs6000_reg_names[62][0], /* fr30 */ \ 2328 &rs6000_reg_names[63][0], /* fr31 */ \ 2329 \ 2330 &rs6000_reg_names[64][0], /* was mq */ \ 2331 &rs6000_reg_names[65][0], /* lr */ \ 2332 &rs6000_reg_names[66][0], /* ctr */ \ 2333 &rs6000_reg_names[67][0], /* ap */ \ 2334 \ 2335 &rs6000_reg_names[68][0], /* cr0 */ \ 2336 &rs6000_reg_names[69][0], /* cr1 */ \ 2337 &rs6000_reg_names[70][0], /* cr2 */ \ 2338 &rs6000_reg_names[71][0], /* cr3 */ \ 2339 &rs6000_reg_names[72][0], /* cr4 */ \ 2340 &rs6000_reg_names[73][0], /* cr5 */ \ 2341 &rs6000_reg_names[74][0], /* cr6 */ \ 2342 &rs6000_reg_names[75][0], /* cr7 */ \ 2343 \ 2344 &rs6000_reg_names[76][0], /* ca */ \ 2345 \ 2346 &rs6000_reg_names[77][0], /* v0 */ \ 2347 &rs6000_reg_names[78][0], /* v1 */ \ 2348 &rs6000_reg_names[79][0], /* v2 */ \ 2349 &rs6000_reg_names[80][0], /* v3 */ \ 2350 &rs6000_reg_names[81][0], /* v4 */ \ 2351 &rs6000_reg_names[82][0], /* v5 */ \ 2352 &rs6000_reg_names[83][0], /* v6 */ \ 2353 &rs6000_reg_names[84][0], /* v7 */ \ 2354 &rs6000_reg_names[85][0], /* v8 */ \ 2355 &rs6000_reg_names[86][0], /* v9 */ \ 2356 &rs6000_reg_names[87][0], /* v10 */ \ 2357 &rs6000_reg_names[88][0], /* v11 */ \ 2358 &rs6000_reg_names[89][0], /* v12 */ \ 2359 &rs6000_reg_names[90][0], /* v13 */ \ 2360 &rs6000_reg_names[91][0], /* v14 */ \ 2361 &rs6000_reg_names[92][0], /* v15 */ \ 2362 &rs6000_reg_names[93][0], /* v16 */ \ 2363 &rs6000_reg_names[94][0], /* v17 */ \ 2364 &rs6000_reg_names[95][0], /* v18 */ \ 2365 &rs6000_reg_names[96][0], /* v19 */ \ 2366 &rs6000_reg_names[97][0], /* v20 */ \ 2367 &rs6000_reg_names[98][0], /* v21 */ \ 2368 &rs6000_reg_names[99][0], /* v22 */ \ 2369 &rs6000_reg_names[100][0], /* v23 */ \ 2370 &rs6000_reg_names[101][0], /* v24 */ \ 2371 &rs6000_reg_names[102][0], /* v25 */ \ 2372 &rs6000_reg_names[103][0], /* v26 */ \ 2373 &rs6000_reg_names[104][0], /* v27 */ \ 2374 &rs6000_reg_names[105][0], /* v28 */ \ 2375 &rs6000_reg_names[106][0], /* v29 */ \ 2376 &rs6000_reg_names[107][0], /* v30 */ \ 2377 &rs6000_reg_names[108][0], /* v31 */ \ 2378 &rs6000_reg_names[109][0], /* vrsave */ \ 2379 &rs6000_reg_names[110][0], /* vscr */ \ 2380 &rs6000_reg_names[111][0], /* spe_acc */ \ 2381 &rs6000_reg_names[112][0], /* spefscr */ \ 2382 &rs6000_reg_names[113][0], /* sfp */ \ 2383 &rs6000_reg_names[114][0], /* tfhar */ \ 2384 &rs6000_reg_names[115][0], /* tfiar */ \ 2385 &rs6000_reg_names[116][0], /* texasr */ \ 2386 \ 2387 &rs6000_reg_names[117][0], /* SPE rh0. */ \ 2388 &rs6000_reg_names[118][0], /* SPE rh1. */ \ 2389 &rs6000_reg_names[119][0], /* SPE rh2. */ \ 2390 &rs6000_reg_names[120][0], /* SPE rh3. */ \ 2391 &rs6000_reg_names[121][0], /* SPE rh4. */ \ 2392 &rs6000_reg_names[122][0], /* SPE rh5. */ \ 2393 &rs6000_reg_names[123][0], /* SPE rh6. */ \ 2394 &rs6000_reg_names[124][0], /* SPE rh7. */ \ 2395 &rs6000_reg_names[125][0], /* SPE rh8. */ \ 2396 &rs6000_reg_names[126][0], /* SPE rh9. */ \ 2397 &rs6000_reg_names[127][0], /* SPE rh10. */ \ 2398 &rs6000_reg_names[128][0], /* SPE rh11. */ \ 2399 &rs6000_reg_names[129][0], /* SPE rh12. */ \ 2400 &rs6000_reg_names[130][0], /* SPE rh13. */ \ 2401 &rs6000_reg_names[131][0], /* SPE rh14. */ \ 2402 &rs6000_reg_names[132][0], /* SPE rh15. */ \ 2403 &rs6000_reg_names[133][0], /* SPE rh16. */ \ 2404 &rs6000_reg_names[134][0], /* SPE rh17. */ \ 2405 &rs6000_reg_names[135][0], /* SPE rh18. */ \ 2406 &rs6000_reg_names[136][0], /* SPE rh19. */ \ 2407 &rs6000_reg_names[137][0], /* SPE rh20. */ \ 2408 &rs6000_reg_names[138][0], /* SPE rh21. */ \ 2409 &rs6000_reg_names[139][0], /* SPE rh22. */ \ 2410 &rs6000_reg_names[140][0], /* SPE rh22. */ \ 2411 &rs6000_reg_names[141][0], /* SPE rh24. */ \ 2412 &rs6000_reg_names[142][0], /* SPE rh25. */ \ 2413 &rs6000_reg_names[143][0], /* SPE rh26. */ \ 2414 &rs6000_reg_names[144][0], /* SPE rh27. */ \ 2415 &rs6000_reg_names[145][0], /* SPE rh28. */ \ 2416 &rs6000_reg_names[146][0], /* SPE rh29. */ \ 2417 &rs6000_reg_names[147][0], /* SPE rh30. */ \ 2418 &rs6000_reg_names[148][0], /* SPE rh31. */ \ 2419} 2420 2421/* Table of additional register names to use in user input. */ 2422 2423#define ADDITIONAL_REGISTER_NAMES \ 2424 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2425 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2426 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2427 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2428 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2429 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2430 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2431 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2432 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2433 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2434 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2435 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2436 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2437 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2438 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2439 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2440 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2441 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2442 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2443 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2444 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2445 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2446 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2447 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2448 {"vrsave", 109}, {"vscr", 110}, \ 2449 {"spe_acc", 111}, {"spefscr", 112}, \ 2450 /* no additional names for: lr, ctr, ap */ \ 2451 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2452 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2453 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ 2454 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2455 {"xer", 76}, \ 2456 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2457 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2458 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2459 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2460 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2461 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2462 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2463 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2464 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2465 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ 2466 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ 2467 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ 2468 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ 2469 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ 2470 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ 2471 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ 2472 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ 2473 /* Transactional Memory Facility (HTM) Registers. */ \ 2474 {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \ 2475 /* SPE high registers. */ \ 2476 {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \ 2477 {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \ 2478 {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \ 2479 {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \ 2480 {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \ 2481 {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \ 2482 {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \ 2483 {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \ 2484} 2485 2486/* This is how to output an element of a case-vector that is relative. */ 2487 2488#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2489 do { char buf[100]; \ 2490 fputs ("\t.long ", FILE); \ 2491 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2492 assemble_name (FILE, buf); \ 2493 putc ('-', FILE); \ 2494 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2495 assemble_name (FILE, buf); \ 2496 putc ('\n', FILE); \ 2497 } while (0) 2498 2499/* This is how to output an assembler line 2500 that says to advance the location counter 2501 to a multiple of 2**LOG bytes. */ 2502 2503#define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2504 if ((LOG) != 0) \ 2505 fprintf (FILE, "\t.align %d\n", (LOG)) 2506 2507/* How to align the given loop. */ 2508#define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2509 2510/* Alignment guaranteed by __builtin_malloc. */ 2511/* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. 2512 However, specifying the stronger guarantee currently leads to 2513 a regression in SPEC CPU2006 437.leslie3d. The stronger 2514 guarantee should be implemented here once that's fixed. */ 2515#define MALLOC_ABI_ALIGNMENT (64) 2516 2517/* Pick up the return address upon entry to a procedure. Used for 2518 dwarf2 unwind information. This also enables the table driven 2519 mechanism. */ 2520 2521#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2522#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2523 2524/* Describe how we implement __builtin_eh_return. */ 2525#define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2526#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2527 2528/* Print operand X (an rtx) in assembler syntax to file FILE. 2529 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2530 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2531 2532#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2533 2534/* Define which CODE values are valid. */ 2535 2536#define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2537 2538/* Print a memory address as an operand to reference that memory location. */ 2539 2540#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2541 2542/* For switching between functions with different target attributes. */ 2543#define SWITCHABLE_TARGET 1 2544 2545/* uncomment for disabling the corresponding default options */ 2546/* #define MACHINE_no_sched_interblock */ 2547/* #define MACHINE_no_sched_speculative */ 2548/* #define MACHINE_no_sched_speculative_load */ 2549 2550/* General flags. */ 2551extern int frame_pointer_needed; 2552 2553/* Classification of the builtin functions as to which switches enable the 2554 builtin, and what attributes it should have. We used to use the target 2555 flags macros, but we've run out of bits, so we now map the options into new 2556 settings used here. */ 2557 2558/* Builtin attributes. */ 2559#define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2560#define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2561#define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2562#define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2563#define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */ 2564#define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */ 2565#define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */ 2566#define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */ 2567#define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */ 2568 2569#define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2570#define RS6000_BTC_CONST 0x00000100 /* uses no global state. */ 2571#define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */ 2572#define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2573#define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ 2574 2575/* Miscellaneous information. */ 2576#define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ 2577#define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ 2578#define RS6000_BTC_CR 0x04000000 /* function references a CR. */ 2579#define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ 2580#define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ 2581 2582/* Convenience macros to document the instruction type. */ 2583#define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2584#define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2585 2586/* Builtin targets. For now, we reuse the masks for those options that are in 2587 target flags, and pick three random bits for SPE, paired and ldbl128 which 2588 aren't in target_flags. */ 2589#define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2590#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2591#define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2592#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2593#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2594#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2595#define RS6000_BTM_SPE MASK_STRING /* E500 */ 2596#define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ 2597#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2598#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2599#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2600#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2601#define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2602#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2603#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2604#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2605#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2606 2607#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2608 | RS6000_BTM_VSX \ 2609 | RS6000_BTM_P8_VECTOR \ 2610 | RS6000_BTM_CRYPTO \ 2611 | RS6000_BTM_FRE \ 2612 | RS6000_BTM_FRES \ 2613 | RS6000_BTM_FRSQRTE \ 2614 | RS6000_BTM_FRSQRTES \ 2615 | RS6000_BTM_HTM \ 2616 | RS6000_BTM_POPCNTD \ 2617 | RS6000_BTM_CELL \ 2618 | RS6000_BTM_DFP \ 2619 | RS6000_BTM_HARD_FLOAT \ 2620 | RS6000_BTM_LDBL128) 2621 2622/* Define builtin enum index. */ 2623 2624#undef RS6000_BUILTIN_1 2625#undef RS6000_BUILTIN_2 2626#undef RS6000_BUILTIN_3 2627#undef RS6000_BUILTIN_A 2628#undef RS6000_BUILTIN_D 2629#undef RS6000_BUILTIN_E 2630#undef RS6000_BUILTIN_H 2631#undef RS6000_BUILTIN_P 2632#undef RS6000_BUILTIN_Q 2633#undef RS6000_BUILTIN_S 2634#undef RS6000_BUILTIN_X 2635 2636#define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2637#define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2638#define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2639#define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2640#define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2641#define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2642#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2643#define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2644#define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2645#define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2646#define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM, 2647 2648enum rs6000_builtins 2649{ 2650#include "rs6000-builtin.def" 2651 2652 RS6000_BUILTIN_COUNT 2653}; 2654 2655#undef RS6000_BUILTIN_1 2656#undef RS6000_BUILTIN_2 2657#undef RS6000_BUILTIN_3 2658#undef RS6000_BUILTIN_A 2659#undef RS6000_BUILTIN_D 2660#undef RS6000_BUILTIN_E 2661#undef RS6000_BUILTIN_H 2662#undef RS6000_BUILTIN_P 2663#undef RS6000_BUILTIN_Q 2664#undef RS6000_BUILTIN_S 2665#undef RS6000_BUILTIN_X 2666 2667enum rs6000_builtin_type_index 2668{ 2669 RS6000_BTI_NOT_OPAQUE, 2670 RS6000_BTI_opaque_V2SI, 2671 RS6000_BTI_opaque_V2SF, 2672 RS6000_BTI_opaque_p_V2SI, 2673 RS6000_BTI_opaque_V4SI, 2674 RS6000_BTI_V16QI, 2675 RS6000_BTI_V1TI, 2676 RS6000_BTI_V2SI, 2677 RS6000_BTI_V2SF, 2678 RS6000_BTI_V2DI, 2679 RS6000_BTI_V2DF, 2680 RS6000_BTI_V4HI, 2681 RS6000_BTI_V4SI, 2682 RS6000_BTI_V4SF, 2683 RS6000_BTI_V8HI, 2684 RS6000_BTI_unsigned_V16QI, 2685 RS6000_BTI_unsigned_V1TI, 2686 RS6000_BTI_unsigned_V8HI, 2687 RS6000_BTI_unsigned_V4SI, 2688 RS6000_BTI_unsigned_V2DI, 2689 RS6000_BTI_bool_char, /* __bool char */ 2690 RS6000_BTI_bool_short, /* __bool short */ 2691 RS6000_BTI_bool_int, /* __bool int */ 2692 RS6000_BTI_bool_long, /* __bool long */ 2693 RS6000_BTI_pixel, /* __pixel */ 2694 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2695 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2696 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2697 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2698 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2699 RS6000_BTI_long, /* long_integer_type_node */ 2700 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2701 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2702 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2703 RS6000_BTI_INTQI, /* intQI_type_node */ 2704 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2705 RS6000_BTI_INTHI, /* intHI_type_node */ 2706 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2707 RS6000_BTI_INTSI, /* intSI_type_node */ 2708 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2709 RS6000_BTI_INTDI, /* intDI_type_node */ 2710 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2711 RS6000_BTI_INTTI, /* intTI_type_node */ 2712 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2713 RS6000_BTI_float, /* float_type_node */ 2714 RS6000_BTI_double, /* double_type_node */ 2715 RS6000_BTI_long_double, /* long_double_type_node */ 2716 RS6000_BTI_dfloat64, /* dfloat64_type_node */ 2717 RS6000_BTI_dfloat128, /* dfloat128_type_node */ 2718 RS6000_BTI_void, /* void_type_node */ 2719 RS6000_BTI_MAX 2720}; 2721 2722 2723#define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) 2724#define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) 2725#define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) 2726#define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2727#define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2728#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2729#define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2730#define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2731#define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) 2732#define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) 2733#define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2734#define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2735#define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2736#define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2737#define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2738#define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) 2739#define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2740#define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2741#define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2742#define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2743#define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2744#define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2745#define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) 2746#define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2747#define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2748#define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2749#define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2750#define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2751#define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2752 2753#define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2754#define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2755#define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2756#define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2757#define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2758#define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2759#define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2760#define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2761#define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2762#define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2763#define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2764#define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2765#define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) 2766#define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) 2767#define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2768#define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2769#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) 2770#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) 2771#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) 2772#define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2773 2774extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2775extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2776 2777#define TARGET_SUPPORTS_WIDE_INT 1 2778