1/* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 2002-2020 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21/* We order the 3 128-bit floating point types so that IFmode (IBM 128-bit 22 floating point) is the 128-bit floating point type with the highest 23 precision (128 bits). This so that machine independent parts of the 24 compiler do not try to widen IFmode to TFmode on ISA 3.0 (power9) that has 25 hardware support for IEEE 128-bit. We set TFmode (long double mode) in 26 between, and KFmode (explicit __float128) below it. 27 28 Previously, IFmode and KFmode were defined to be fractional modes and TFmode 29 was the standard mode. Since IFmode does not define the normal arithmetic 30 insns (other than neg/abs), on a ISA 3.0 system, the machine independent 31 parts of the compiler would see that TFmode has the necessary hardware 32 support, and widen the operation from IFmode to TFmode. However, IEEE 33 128-bit is not strictly a super-set of IBM extended double and the 34 conversion to/from IEEE 128-bit was a function call. 35 36 We now make IFmode the highest fractional mode, which means its values are 37 not considered for widening. Since we don't define insns for IFmode, the 38 IEEE 128-bit modes would not widen to IFmode. */ 39 40#ifndef RS6000_MODES_H 41#include "config/rs6000/rs6000-modes.h" 42#endif 43 44/* IBM 128-bit floating point. */ 45FRACTIONAL_FLOAT_MODE (IF, FLOAT_PRECISION_IFmode, 16, ibm_extended_format); 46 47/* Explicit IEEE 128-bit floating point. */ 48FRACTIONAL_FLOAT_MODE (KF, FLOAT_PRECISION_KFmode, 16, ieee_quad_format); 49 50/* 128-bit floating point, either IBM 128-bit or IEEE 128-bit. This is 51 adjusted in rs6000_option_override_internal to be the appropriate floating 52 point type. */ 53FRACTIONAL_FLOAT_MODE (TF, FLOAT_PRECISION_TFmode, 16, ieee_quad_format); 54 55/* Add any extra modes needed to represent the condition code. 56 57 For the RS/6000, we need separate modes when unsigned (logical) comparisons 58 are being done and we need a separate mode for floating-point. We also 59 use a mode for the case when we are comparing the results of two 60 comparisons, as then only the EQ bit is valid in the register. */ 61 62CC_MODE (CCUNS); 63CC_MODE (CCFP); 64CC_MODE (CCEQ); 65 66/* Vector modes. */ 67 68/* VMX/VSX. */ 69VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */ 70VECTOR_MODE (INT, TI, 1); /* V1TI */ 71VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ 72 73/* Two VMX/VSX vectors (for permute, select, concat, etc.) */ 74VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ 75VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ 76 77/* Half VMX/VSX vector (for internal use) */ 78VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ 79VECTOR_MODE (INT, SI, 2); /* V2SI */ 80 81/* Replacement for TImode that only is allowed in GPRs. We also use PTImode 82 for quad memory atomic operations to force getting an even/odd register 83 combination. */ 84PARTIAL_INT_MODE (TI, 128, PTI); 85 86/* Define, but don't use the larger integer modes. We need an integer mode 87 defined that is the same size as the vector pair and vector quad modes. */ 88 89INT_MODE (OI, 32); 90INT_MODE (XI, 64); 91 92/* Modes used by __vector_pair and __vector_quad. */ 93PARTIAL_INT_MODE (OI, 256, POI); /* __vector_pair. */ 94PARTIAL_INT_MODE (XI, 512, PXI); /* __vector_quad. */ 95