rs6000-c.c revision 1.6
1/* Subroutines for the C front end on the PowerPC architecture. 2 Copyright (C) 2002-2015 Free Software Foundation, Inc. 3 4 Contributed by Zack Weinberg <zack@codesourcery.com> 5 and Paolo Bonzini <bonzini@gnu.org> 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it 10 under the terms of the GNU General Public License as published 11 by the Free Software Foundation; either version 3, or (at your 12 option) any later version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23#include "config.h" 24#include "system.h" 25#include "coretypes.h" 26#include "tm.h" 27#include "cpplib.h" 28#include "hash-set.h" 29#include "machmode.h" 30#include "vec.h" 31#include "double-int.h" 32#include "input.h" 33#include "alias.h" 34#include "symtab.h" 35#include "wide-int.h" 36#include "inchash.h" 37#include "tree.h" 38#include "fold-const.h" 39#include "stor-layout.h" 40#include "stringpool.h" 41#include "wide-int.h" 42#include "c-family/c-common.h" 43#include "c-family/c-pragma.h" 44#include "diagnostic-core.h" 45#include "tm_p.h" 46#include "target.h" 47#include "langhooks.h" 48 49 50 51/* Handle the machine specific pragma longcall. Its syntax is 52 53 # pragma longcall ( TOGGLE ) 54 55 where TOGGLE is either 0 or 1. 56 57 rs6000_default_long_calls is set to the value of TOGGLE, changing 58 whether or not new function declarations receive a longcall 59 attribute by default. */ 60 61#define SYNTAX_ERROR(gmsgid) do { \ 62 warning (OPT_Wpragmas, gmsgid); \ 63 warning (OPT_Wpragmas, "ignoring malformed #pragma longcall"); \ 64 return; \ 65} while (0) 66 67void 68rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED) 69{ 70 tree x, n; 71 72 /* If we get here, generic code has already scanned the directive 73 leader and the word "longcall". */ 74 75 if (pragma_lex (&x) != CPP_OPEN_PAREN) 76 SYNTAX_ERROR ("missing open paren"); 77 if (pragma_lex (&n) != CPP_NUMBER) 78 SYNTAX_ERROR ("missing number"); 79 if (pragma_lex (&x) != CPP_CLOSE_PAREN) 80 SYNTAX_ERROR ("missing close paren"); 81 82 if (n != integer_zero_node && n != integer_one_node) 83 SYNTAX_ERROR ("number must be 0 or 1"); 84 85 if (pragma_lex (&x) != CPP_EOF) 86 warning (OPT_Wpragmas, "junk at end of #pragma longcall"); 87 88 rs6000_default_long_calls = (n == integer_one_node); 89} 90 91/* Handle defining many CPP flags based on TARGET_xxx. As a general 92 policy, rather than trying to guess what flags a user might want a 93 #define for, it's better to define a flag for everything. */ 94 95#define builtin_define(TXT) cpp_define (pfile, TXT) 96#define builtin_assert(TXT) cpp_assert (pfile, TXT) 97 98/* Keep the AltiVec keywords handy for fast comparisons. */ 99static GTY(()) tree __vector_keyword; 100static GTY(()) tree vector_keyword; 101static GTY(()) tree __pixel_keyword; 102static GTY(()) tree pixel_keyword; 103static GTY(()) tree __bool_keyword; 104static GTY(()) tree bool_keyword; 105static GTY(()) tree _Bool_keyword; 106static GTY(()) tree __int128_type; 107static GTY(()) tree __uint128_type; 108 109/* Preserved across calls. */ 110static tree expand_bool_pixel; 111 112static cpp_hashnode * 113altivec_categorize_keyword (const cpp_token *tok) 114{ 115 if (tok->type == CPP_NAME) 116 { 117 cpp_hashnode *ident = tok->val.node.node; 118 119 if (ident == C_CPP_HASHNODE (vector_keyword)) 120 return C_CPP_HASHNODE (__vector_keyword); 121 122 if (ident == C_CPP_HASHNODE (pixel_keyword)) 123 return C_CPP_HASHNODE (__pixel_keyword); 124 125 if (ident == C_CPP_HASHNODE (bool_keyword)) 126 return C_CPP_HASHNODE (__bool_keyword); 127 128 if (ident == C_CPP_HASHNODE (_Bool_keyword)) 129 return C_CPP_HASHNODE (__bool_keyword); 130 131 return ident; 132 } 133 134 return 0; 135} 136 137static void 138init_vector_keywords (void) 139{ 140 /* Keywords without two leading underscores are context-sensitive, and hence 141 implemented as conditional macros, controlled by the 142 rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit 143 support, record the __int128_t and __uint128_t types. */ 144 145 __vector_keyword = get_identifier ("__vector"); 146 C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL; 147 148 __pixel_keyword = get_identifier ("__pixel"); 149 C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL; 150 151 __bool_keyword = get_identifier ("__bool"); 152 C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL; 153 154 vector_keyword = get_identifier ("vector"); 155 C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL; 156 157 pixel_keyword = get_identifier ("pixel"); 158 C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL; 159 160 bool_keyword = get_identifier ("bool"); 161 C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL; 162 163 _Bool_keyword = get_identifier ("_Bool"); 164 C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL; 165 166 if (TARGET_VADDUQM) 167 { 168 __int128_type = get_identifier ("__int128_t"); 169 __uint128_type = get_identifier ("__uint128_t"); 170 } 171} 172 173/* Helper function to find out which RID_INT_N_* code is the one for 174 __int128, if any. Returns RID_MAX+1 if none apply, which is safe 175 (for our purposes, since we always expect to have __int128) to 176 compare against. */ 177static int 178rid_int128(void) 179{ 180 int i; 181 182 for (i = 0; i < NUM_INT_N_ENTS; i ++) 183 if (int_n_enabled_p[i] 184 && int_n_data[i].bitsize == 128) 185 return RID_INT_N_0 + i; 186 187 return RID_MAX + 1; 188} 189 190/* Called to decide whether a conditional macro should be expanded. 191 Since we have exactly one such macro (i.e, 'vector'), we do not 192 need to examine the 'tok' parameter. */ 193 194static cpp_hashnode * 195rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) 196{ 197 cpp_hashnode *expand_this = tok->val.node.node; 198 cpp_hashnode *ident; 199 200 /* If the current machine does not have altivec, don't look for the 201 keywords. */ 202 if (!TARGET_ALTIVEC) 203 return NULL; 204 205 ident = altivec_categorize_keyword (tok); 206 207 if (ident != expand_this) 208 expand_this = NULL; 209 210 if (ident == C_CPP_HASHNODE (__vector_keyword)) 211 { 212 int idx = 0; 213 do 214 tok = cpp_peek_token (pfile, idx++); 215 while (tok->type == CPP_PADDING); 216 ident = altivec_categorize_keyword (tok); 217 218 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 219 { 220 expand_this = C_CPP_HASHNODE (__vector_keyword); 221 expand_bool_pixel = __pixel_keyword; 222 } 223 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 224 { 225 expand_this = C_CPP_HASHNODE (__vector_keyword); 226 expand_bool_pixel = __bool_keyword; 227 } 228 /* The boost libraries have code with Iterator::vector vector in it. If 229 we allow the normal handling, this module will be called recursively, 230 and the vector will be skipped.; */ 231 else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword))) 232 { 233 enum rid rid_code = (enum rid)(ident->rid_code); 234 enum node_type itype = ident->type; 235 /* If there is a function-like macro, check if it is going to be 236 invoked with or without arguments. Without following ( treat 237 it like non-macro, otherwise the following cpp_get_token eats 238 what should be preserved. */ 239 if (itype == NT_MACRO && cpp_fun_like_macro_p (ident)) 240 { 241 int idx2 = idx; 242 do 243 tok = cpp_peek_token (pfile, idx2++); 244 while (tok->type == CPP_PADDING); 245 if (tok->type != CPP_OPEN_PAREN) 246 itype = NT_VOID; 247 } 248 if (itype == NT_MACRO) 249 { 250 do 251 (void) cpp_get_token (pfile); 252 while (--idx > 0); 253 do 254 tok = cpp_peek_token (pfile, idx++); 255 while (tok->type == CPP_PADDING); 256 ident = altivec_categorize_keyword (tok); 257 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 258 { 259 expand_this = C_CPP_HASHNODE (__vector_keyword); 260 expand_bool_pixel = __pixel_keyword; 261 rid_code = RID_MAX; 262 } 263 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 264 { 265 expand_this = C_CPP_HASHNODE (__vector_keyword); 266 expand_bool_pixel = __bool_keyword; 267 rid_code = RID_MAX; 268 } 269 else if (ident) 270 rid_code = (enum rid)(ident->rid_code); 271 } 272 273 if (rid_code == RID_UNSIGNED || rid_code == RID_LONG 274 || rid_code == RID_SHORT || rid_code == RID_SIGNED 275 || rid_code == RID_INT || rid_code == RID_CHAR 276 || rid_code == RID_FLOAT 277 || (rid_code == RID_DOUBLE && TARGET_VSX) 278 || (rid_code == rid_int128 () && TARGET_VADDUQM)) 279 { 280 expand_this = C_CPP_HASHNODE (__vector_keyword); 281 /* If the next keyword is bool or pixel, it 282 will need to be expanded as well. */ 283 do 284 tok = cpp_peek_token (pfile, idx++); 285 while (tok->type == CPP_PADDING); 286 ident = altivec_categorize_keyword (tok); 287 288 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 289 expand_bool_pixel = __pixel_keyword; 290 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 291 expand_bool_pixel = __bool_keyword; 292 else 293 { 294 /* Try two tokens down, too. */ 295 do 296 tok = cpp_peek_token (pfile, idx++); 297 while (tok->type == CPP_PADDING); 298 ident = altivec_categorize_keyword (tok); 299 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 300 expand_bool_pixel = __pixel_keyword; 301 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 302 expand_bool_pixel = __bool_keyword; 303 } 304 } 305 306 /* Support vector __int128_t, but we don't need to worry about bool 307 or pixel on this type. */ 308 else if (TARGET_VADDUQM 309 && (ident == C_CPP_HASHNODE (__int128_type) 310 || ident == C_CPP_HASHNODE (__uint128_type))) 311 expand_this = C_CPP_HASHNODE (__vector_keyword); 312 } 313 } 314 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword)) 315 { 316 expand_this = C_CPP_HASHNODE (__pixel_keyword); 317 expand_bool_pixel = 0; 318 } 319 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword)) 320 { 321 expand_this = C_CPP_HASHNODE (__bool_keyword); 322 expand_bool_pixel = 0; 323 } 324 325 return expand_this; 326} 327 328 329/* Define or undefine a single macro. */ 330 331static void 332rs6000_define_or_undefine_macro (bool define_p, const char *name) 333{ 334 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) 335 fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name); 336 337 if (define_p) 338 cpp_define (parse_in, name); 339 else 340 cpp_undef (parse_in, name); 341} 342 343/* Define or undefine macros based on the current target. If the user does 344 #pragma GCC target, we need to adjust the macros dynamically. Note, some of 345 the options needed for builtins have been moved to separate variables, so 346 have both the target flags and the builtin flags as arguments. */ 347 348void 349rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, 350 HOST_WIDE_INT bu_mask) 351{ 352 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) 353 fprintf (stderr, 354 "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX 355 ", " HOST_WIDE_INT_PRINT_HEX ")\n", 356 (define_p) ? "define" : "undef", 357 flags, bu_mask); 358 359 /* rs6000_isa_flags based options. */ 360 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); 361 if ((flags & OPTION_MASK_PPC_GPOPT) != 0) 362 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); 363 if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) 364 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); 365 if ((flags & OPTION_MASK_POWERPC64) != 0) 366 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); 367 if ((flags & OPTION_MASK_MFCRF) != 0) 368 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); 369 if ((flags & OPTION_MASK_POPCNTB) != 0) 370 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); 371 if ((flags & OPTION_MASK_FPRND) != 0) 372 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); 373 if ((flags & OPTION_MASK_CMPB) != 0) 374 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); 375 if ((flags & OPTION_MASK_MFPGPR) != 0) 376 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); 377 if ((flags & OPTION_MASK_POPCNTD) != 0) 378 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); 379 if ((flags & OPTION_MASK_DIRECT_MOVE) != 0) 380 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); 381 if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) 382 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); 383 if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) 384 rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); 385 if ((flags & OPTION_MASK_ALTIVEC) != 0) 386 { 387 const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; 388 rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); 389 rs6000_define_or_undefine_macro (define_p, vec_str); 390 391 /* Define this when supporting context-sensitive keywords. */ 392 if (!flag_iso) 393 rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); 394 } 395 if ((flags & OPTION_MASK_VSX) != 0) 396 rs6000_define_or_undefine_macro (define_p, "__VSX__"); 397 if ((flags & OPTION_MASK_HTM) != 0) 398 { 399 rs6000_define_or_undefine_macro (define_p, "__HTM__"); 400 /* Tell the user that our HTM insn patterns act as memory barriers. */ 401 rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__"); 402 } 403 if ((flags & OPTION_MASK_P8_VECTOR) != 0) 404 rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__"); 405 if ((flags & OPTION_MASK_QUAD_MEMORY) != 0) 406 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__"); 407 if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0) 408 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__"); 409 if ((flags & OPTION_MASK_CRYPTO) != 0) 410 rs6000_define_or_undefine_macro (define_p, "__CRYPTO__"); 411 if ((flags & OPTION_MASK_UPPER_REGS_DF) != 0) 412 rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_DF__"); 413 if ((flags & OPTION_MASK_UPPER_REGS_SF) != 0) 414 rs6000_define_or_undefine_macro (define_p, "__UPPER_REGS_SF__"); 415 416 /* options from the builtin masks. */ 417 if ((bu_mask & RS6000_BTM_SPE) != 0) 418 rs6000_define_or_undefine_macro (define_p, "__SPE__"); 419 if ((bu_mask & RS6000_BTM_PAIRED) != 0) 420 rs6000_define_or_undefine_macro (define_p, "__PAIRED__"); 421 if ((bu_mask & RS6000_BTM_CELL) != 0) 422 rs6000_define_or_undefine_macro (define_p, "__PPU__"); 423} 424 425void 426rs6000_cpu_cpp_builtins (cpp_reader *pfile) 427{ 428 /* Define all of the common macros. */ 429 rs6000_target_modify_macros (true, rs6000_isa_flags, 430 rs6000_builtin_mask_calculate ()); 431 432 if (TARGET_FRE) 433 builtin_define ("__RECIP__"); 434 if (TARGET_FRES) 435 builtin_define ("__RECIPF__"); 436 if (TARGET_FRSQRTE) 437 builtin_define ("__RSQRTE__"); 438 if (TARGET_FRSQRTES) 439 builtin_define ("__RSQRTEF__"); 440 441 if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM) 442 { 443 /* Define the AltiVec syntactic elements. */ 444 builtin_define ("__vector=__attribute__((altivec(vector__)))"); 445 builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short"); 446 builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned"); 447 448 if (!flag_iso) 449 { 450 builtin_define ("vector=vector"); 451 builtin_define ("pixel=pixel"); 452 builtin_define ("bool=bool"); 453 builtin_define ("_Bool=_Bool"); 454 init_vector_keywords (); 455 456 /* Enable context-sensitive macros. */ 457 cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; 458 } 459 } 460 if ((!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE))) 461 ||(TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_DOUBLE_FLOAT)) 462 builtin_define ("_SOFT_DOUBLE"); 463 /* Used by lwarx/stwcx. errata work-around. */ 464 if (rs6000_cpu == PROCESSOR_PPC405) 465 builtin_define ("__PPC405__"); 466 /* Used by libstdc++. */ 467 if (TARGET_NO_LWSYNC) 468 builtin_define ("__NO_LWSYNC__"); 469 470 if (TARGET_EXTRA_BUILTINS) 471 { 472 /* For the VSX builtin functions identical to Altivec functions, just map 473 the altivec builtin into the vsx version (the altivec functions 474 generate VSX code if -mvsx). */ 475 builtin_define ("__builtin_vsx_xxland=__builtin_vec_and"); 476 builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc"); 477 builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor"); 478 builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or"); 479 builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor"); 480 builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel"); 481 builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm"); 482 483 /* Also map the a and m versions of the multiply/add instructions to the 484 builtin for people blindly going off the instruction manual. */ 485 builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp"); 486 builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp"); 487 builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp"); 488 builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp"); 489 builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp"); 490 builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp"); 491 builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp"); 492 builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp"); 493 builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp"); 494 builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp"); 495 builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp"); 496 builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp"); 497 builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp"); 498 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp"); 499 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp"); 500 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp"); 501 } 502 503 /* Tell users they can use __builtin_bswap{16,64}. */ 504 builtin_define ("__HAVE_BSWAP__"); 505 506 /* May be overridden by target configuration. */ 507 RS6000_CPU_CPP_ENDIAN_BUILTINS(); 508 509 if (TARGET_LONG_DOUBLE_128) 510 { 511 builtin_define ("__LONG_DOUBLE_128__"); 512 builtin_define ("__LONGDOUBLE128"); 513 } 514 515 switch (TARGET_CMODEL) 516 { 517 /* Deliberately omit __CMODEL_SMALL__ since that was the default 518 before --mcmodel support was added. */ 519 case CMODEL_MEDIUM: 520 builtin_define ("__CMODEL_MEDIUM__"); 521 break; 522 case CMODEL_LARGE: 523 builtin_define ("__CMODEL_LARGE__"); 524 break; 525 default: 526 break; 527 } 528 529 switch (rs6000_current_abi) 530 { 531 case ABI_V4: 532 builtin_define ("_CALL_SYSV"); 533 break; 534 case ABI_AIX: 535 builtin_define ("_CALL_AIXDESC"); 536 builtin_define ("_CALL_AIX"); 537 builtin_define ("_CALL_ELF=1"); 538 break; 539 case ABI_ELFv2: 540 builtin_define ("_CALL_ELF=2"); 541 break; 542 case ABI_DARWIN: 543 builtin_define ("_CALL_DARWIN"); 544 break; 545 default: 546 break; 547 } 548 549 /* Vector element order. */ 550 if (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) 551 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__"); 552 else 553 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__"); 554 555 /* Let the compiled code know if 'f' class registers will not be available. */ 556 if (TARGET_SOFT_FLOAT || !TARGET_FPRS) 557 builtin_define ("__NO_FPRS__"); 558 559 /* Whether aggregates passed by value are aligned to a 16 byte boundary 560 if their alignment is 16 bytes or larger. */ 561 if ((TARGET_MACHO && rs6000_darwin64_abi) 562 || DEFAULT_ABI == ABI_ELFv2 563 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) 564 builtin_define ("__STRUCT_PARM_ALIGN__=16"); 565 566 /* Generate defines for Xilinx FPU. */ 567 if (rs6000_xilinx_fpu) 568 { 569 builtin_define ("_XFPU"); 570 if (rs6000_single_float && ! rs6000_double_float) 571 { 572 if (rs6000_simple_fpu) 573 builtin_define ("_XFPU_SP_LITE"); 574 else 575 builtin_define ("_XFPU_SP_FULL"); 576 } 577 if (rs6000_double_float) 578 { 579 if (rs6000_simple_fpu) 580 builtin_define ("_XFPU_DP_LITE"); 581 else 582 builtin_define ("_XFPU_DP_FULL"); 583 } 584 } 585} 586 587 588struct altivec_builtin_types 589{ 590 enum rs6000_builtins code; 591 enum rs6000_builtins overloaded_code; 592 signed char ret_type; 593 signed char op1; 594 signed char op2; 595 signed char op3; 596}; 597 598const struct altivec_builtin_types altivec_overloaded_builtins[] = { 599 /* Unary AltiVec/VSX builtins. */ 600 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI, 601 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 602 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI, 603 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 604 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, 605 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 606 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, 607 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 608 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, 609 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 610 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, 611 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 612 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI, 613 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 614 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI, 615 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 616 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI, 617 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 618 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP, 619 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 620 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP, 621 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 622 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP, 623 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 624 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM, 625 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 626 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM, 627 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 628 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP, 629 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 630 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 631 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 }, 632 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 633 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 }, 634 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 635 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 }, 636 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 637 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 }, 638 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 639 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 }, 640 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 641 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 }, 642 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 643 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 }, 644 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 645 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 }, 646 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 647 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 }, 648 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 649 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 }, 650 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP, 651 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 652 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP, 653 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 654 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, 655 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 656 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, 657 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 658 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, 659 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 660 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, 661 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 662 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP, 663 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 664 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF, 665 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 666 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP, 667 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 668 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP, 669 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 670 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ, 671 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 672 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ, 673 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 674 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, 675 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 676 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, 677 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 678 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, 679 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 680 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, 681 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 682 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, 683 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 684 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, 685 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 686 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, 687 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 688 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 689 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 690 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 691 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 692 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, 693 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 694 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, 695 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 696 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, 697 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 698 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, 699 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 700 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, 701 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 702 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, 703 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 704 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, 705 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 706 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, 707 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 708 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX, 709 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 710 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, 711 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 712 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, 713 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 714 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 715 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 716 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 717 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 718 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 719 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 720 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 721 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 722 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, 723 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 724 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, 725 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 726 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, 727 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 728 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, 729 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 730 731 /* Binary AltiVec/VSX builtins. */ 732 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 733 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 734 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 735 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 736 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 737 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 738 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 739 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 740 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 741 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 742 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 743 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 744 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 745 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 746 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 747 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 748 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 749 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 750 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 751 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 752 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 753 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 754 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 755 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 756 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 757 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 758 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 759 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 760 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 761 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 762 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 763 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 764 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 765 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 766 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 767 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 768 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 769 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 770 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 771 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 772 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 773 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 774 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 775 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 776 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 777 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 778 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 779 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 780 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, 781 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 782 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, 783 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 784 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, 785 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 786 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, 787 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 788 RS6000_BTI_unsigned_V1TI, 0 }, 789 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP, 790 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 791 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 792 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 793 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 794 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 795 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 796 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 797 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 798 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 799 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 800 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 801 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 802 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 803 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 804 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 805 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 806 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 807 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 808 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 809 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 810 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 811 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 812 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 813 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 814 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 815 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 816 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 817 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 818 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 819 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 820 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 821 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 822 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 823 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 824 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 825 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 826 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 827 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 828 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 829 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 830 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 831 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 832 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 833 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 834 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 835 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 836 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 837 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 838 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 839 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, 840 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 841 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 842 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 843 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 844 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 845 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 846 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 847 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 848 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 849 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 850 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 851 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 852 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 853 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 854 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 855 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 856 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 857 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 858 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 859 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 860 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 861 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 862 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 863 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 864 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 865 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 866 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 867 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 868 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 869 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 870 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 871 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 872 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 873 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 874 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 875 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 876 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 877 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 878 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 879 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 880 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 881 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 882 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 883 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 884 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 885 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 886 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 887 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 888 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 889 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 890 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 891 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 892 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 893 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 894 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 895 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 896 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 897 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 898 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 899 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 900 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 901 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 902 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 903 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 904 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 905 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 906 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 907 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 908 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 909 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 910 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 911 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 912 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 913 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 914 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 915 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 916 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 917 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 918 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 919 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 920 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 921 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 922 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 923 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 924 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 925 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 926 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 927 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 928 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 929 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 930 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 931 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 932 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 933 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 934 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 935 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 936 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 937 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 938 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 939 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 940 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 941 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 942 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 943 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 944 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 945 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 946 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 947 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 948 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 949 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 950 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 951 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 952 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 953 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 954 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 955 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 956 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 957 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 958 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 959 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 960 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 961 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 962 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 963 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 964 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 965 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 966 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 967 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 968 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 969 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 970 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 971 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 972 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 973 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 974 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 975 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 976 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 977 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 978 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 979 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 980 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 981 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 982 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 983 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 984 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 985 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 986 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 987 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 988 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 989 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 990 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 991 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 992 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 993 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 994 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 995 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 996 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 997 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 998 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 999 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1000 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 1001 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1002 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 1003 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1004 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1005 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1006 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1007 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1008 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1009 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1010 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1011 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1012 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1013 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1014 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1015 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1016 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1017 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1018 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1019 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1020 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1021 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1022 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1023 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1024 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1025 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1026 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1027 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1028 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1029 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1030 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1031 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1032 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1033 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1034 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1035 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1036 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1037 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1038 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1039 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1040 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1041 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1042 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1043 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1044 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1045 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1046 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1047 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1048 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1049 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1050 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1051 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1052 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1053 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1054 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1055 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1056 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1057 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB, 1058 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1059 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB, 1060 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1061 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH, 1062 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1063 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH, 1064 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1065 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW, 1066 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1067 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW, 1068 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1069 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW, 1070 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1071 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW, 1072 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1073 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH, 1074 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1075 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH, 1076 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1077 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB, 1078 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1079 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB, 1080 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1081 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP, 1082 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1083 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 1084 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1085 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 1086 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1087 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 1088 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1089 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 1090 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1091 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 1092 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1093 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 1094 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1095 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 1096 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1097 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 1098 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1099 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, 1100 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1101 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, 1102 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1103 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP, 1104 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1105 1106 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, 1107 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1108 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, 1109 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1110 1111 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, 1112 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1113 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, 1114 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1115 1116 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, 1117 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1118 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, 1119 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1120 1121 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP, 1122 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1123 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP, 1124 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1125 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB, 1126 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1127 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB, 1128 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1129 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH, 1130 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1131 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH, 1132 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1133 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW, 1134 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1135 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, 1136 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1137 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, 1138 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1139 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, 1140 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1141 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, 1142 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1143 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, 1144 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1145 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP, 1146 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1147 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, 1148 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1149 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, 1150 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1151 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, 1152 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1153 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, 1154 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1155 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, 1156 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1157 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, 1158 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1159 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, 1160 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1161 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, 1162 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1163 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, 1164 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1165 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, 1166 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1167 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, 1168 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1169 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, 1170 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1171 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP, 1172 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1173 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP, 1174 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1175 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB, 1176 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1177 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB, 1178 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1179 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH, 1180 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1181 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH, 1182 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1183 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW, 1184 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1185 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, 1186 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1187 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, 1188 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1189 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, 1190 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1191 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, 1192 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1193 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, 1194 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1195 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP, 1196 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1197 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF, 1198 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1199 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX, 1200 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 1201 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, 1202 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 1203 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, 1204 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, 1205 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, 1206 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, 1207 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, 1208 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 1209 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, 1210 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 1211 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, 1212 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 1213 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, 1214 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 1215 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, 1216 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 1217 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, 1218 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 1219 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, 1220 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1221 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, 1222 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1223 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, 1224 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1225 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, 1226 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1227 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, 1228 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1229 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1230 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1231 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1232 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1233 ~RS6000_BTI_unsigned_V2DI, 0 }, 1234 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1235 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 1236 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, 1237 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1238 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, 1239 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1240 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1241 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1242 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1243 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1244 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1245 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1246 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1247 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1248 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1249 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1250 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1251 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1252 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1253 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1254 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1255 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1256 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1257 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1258 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1259 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1260 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1261 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1262 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1263 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1264 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1265 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1266 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1267 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1268 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1269 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1270 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1271 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1272 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1273 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1274 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1275 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1276 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, 1277 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1278 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, 1279 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1280 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, 1281 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1282 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, 1283 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1284 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1285 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1286 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1287 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1288 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1289 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1290 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1291 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1292 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1293 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1294 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1295 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1296 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1297 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1298 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1299 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1300 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1301 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1302 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1303 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1304 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, 1305 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1306 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, 1307 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1308 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1309 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1310 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1311 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1312 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1313 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1314 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1315 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1316 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1317 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1318 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1319 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1320 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1321 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1322 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1323 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1324 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1325 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1326 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1327 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1328 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1329 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1330 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1331 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1332 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1333 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1334 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1335 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1336 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1337 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1338 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1339 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1340 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1341 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1342 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1343 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1344 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1345 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1346 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1347 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1348 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1349 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1350 ~RS6000_BTI_unsigned_V16QI, 0 }, 1351 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1352 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1353 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, 1354 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1355 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1356 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1357 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1358 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1359 ~RS6000_BTI_unsigned_V2DI, 0 }, 1360 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1361 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 1362 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1363 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1364 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1365 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1366 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1367 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1368 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1369 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1370 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1371 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1372 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1373 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1374 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1375 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1376 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1377 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1378 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1379 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1380 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1381 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1382 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1383 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 1384 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1385 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 1386 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1387 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1388 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1389 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1390 ~RS6000_BTI_unsigned_long_long, 0 }, 1391 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1392 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1393 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1394 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1395 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1396 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1397 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1398 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1399 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1400 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1401 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1402 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1403 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1404 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1405 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1406 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1407 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1408 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1409 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1410 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1411 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1412 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 1413 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1414 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 1415 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1416 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1417 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1418 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1419 ~RS6000_BTI_unsigned_long_long, 0 }, 1420 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1421 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1422 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1423 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1424 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1425 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1426 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1427 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1428 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1429 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1430 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1431 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1432 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1433 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1434 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1435 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1436 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1437 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1438 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1439 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1440 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1441 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1442 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1443 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1444 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1445 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1446 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1447 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1448 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1449 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1450 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1451 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1452 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1453 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1454 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1455 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1456 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1457 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1458 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1459 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1460 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1461 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1462 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1463 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1464 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1465 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1466 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1467 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1468 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1469 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1470 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1471 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1472 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1473 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1474 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1475 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1476 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1477 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1478 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1479 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1480 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1481 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1482 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1483 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1484 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1485 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1486 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1487 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1488 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1489 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1490 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1491 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1492 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1493 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1494 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1495 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1496 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1497 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1498 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1499 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1500 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1501 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1502 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1503 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1504 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1505 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1506 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1507 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1508 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1509 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1510 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1511 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1512 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1513 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1514 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1515 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1516 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1517 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1518 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1519 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1520 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1521 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1522 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1523 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1524 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1525 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1526 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1527 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1528 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1529 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1530 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1531 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1532 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1533 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1534 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1535 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1536 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1537 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1538 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1539 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1540 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1541 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1542 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1543 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1544 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1545 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1546 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1547 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1548 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1549 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1550 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1551 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1552 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1553 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1554 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1555 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1556 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1557 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1558 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1559 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1560 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1561 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1562 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1563 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1564 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1565 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1566 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1567 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1568 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1569 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1570 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1571 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1572 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1573 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1574 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1575 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1576 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1577 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1578 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1579 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1580 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1581 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1582 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1583 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1584 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1585 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1586 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1587 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1588 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1589 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1590 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1591 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1592 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1593 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1594 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1595 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1596 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1597 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1598 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1599 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1600 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1601 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1602 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1603 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1604 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1605 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1606 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1607 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1608 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1609 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1610 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1611 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1612 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, 1613 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1614 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, 1615 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1616 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP, 1617 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1618 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1619 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1620 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1621 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1622 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1623 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1624 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1625 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1626 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1627 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 1628 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1629 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1630 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1631 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1632 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1633 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1634 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1635 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1636 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1637 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1638 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1639 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1640 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1641 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1642 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1643 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 1644 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1645 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1646 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1647 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1648 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 1649 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1650 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 1651 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1652 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 1653 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1654 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 1655 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1656 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1657 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1658 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1659 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 1660 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1661 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1662 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1663 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1664 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 1665 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1666 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 1667 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1668 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 1669 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1670 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 1671 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1672 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1673 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1674 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1675 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1676 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1677 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1678 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 1679 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1680 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1681 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1682 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1683 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1684 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1685 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1686 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 1687 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1688 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF, 1689 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1690 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1691 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1692 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1693 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1694 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1695 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1696 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1697 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1698 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1699 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1700 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 1701 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1702 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1703 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1704 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1705 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1706 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1707 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1708 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 1709 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1710 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1711 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1712 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1713 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1714 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1715 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1716 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 1717 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1718 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 1719 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1720 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 1721 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1722 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 1723 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1724 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 1725 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1726 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 1727 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1728 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 1729 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1730 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1731 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1732 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1733 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1734 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1735 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1736 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 1737 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1738 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1739 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1740 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1741 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1742 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1743 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1744 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 1745 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1746 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF, 1747 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1748 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1749 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1750 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1751 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1752 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1753 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1754 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1755 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1756 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1757 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1758 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 1759 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1760 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1761 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1762 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1763 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1764 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1765 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1766 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 1767 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1768 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1769 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1770 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1771 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 1772 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1773 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1774 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 1775 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1776 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 1777 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1778 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 1779 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1780 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 1781 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1782 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 1783 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1784 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 1785 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1786 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 1787 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1788 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 1789 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1790 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 1791 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1792 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 1793 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1794 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 1795 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1796 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 1797 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1798 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 1799 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1800 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 1801 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1802 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 1803 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1804 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 1805 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1806 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 1807 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1808 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 1809 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1810 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 1811 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1812 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 1813 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1814 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 1815 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1816 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 1817 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1818 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 1819 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1820 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 1821 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1822 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 1823 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1824 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 1825 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1826 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 1827 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1828 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 1829 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1830 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, 1831 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1832 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, 1833 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1834 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP, 1835 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1836 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 1837 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1838 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 1839 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1840 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 1841 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1842 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1843 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1844 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1845 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 1846 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1847 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1848 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1849 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1850 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 1851 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1852 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 1853 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1854 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 1855 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1856 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 1857 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1858 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 1859 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1860 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 1861 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1862 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 1863 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1864 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1865 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1866 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1867 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 1868 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1869 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1870 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1871 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1872 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 1873 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1874 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1875 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1876 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1877 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 1878 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1879 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1880 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1881 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1882 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 1883 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1884 { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_XVMULSP, 1885 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1886 { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_XVMULDP, 1887 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1888 { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, 1889 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1890 { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, 1891 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1892 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, 1893 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1894 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, 1895 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1896 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH, 1897 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1898 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, 1899 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1900 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB, 1901 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1902 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB, 1903 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1904 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH, 1905 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1906 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH, 1907 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1908 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB, 1909 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1910 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB, 1911 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1912 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, 1913 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1914 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, 1915 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1916 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH, 1917 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1918 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH, 1919 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1920 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB, 1921 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1922 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB, 1923 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1924 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI, 1925 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 1926 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, 1927 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 1928 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1929 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1930 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1931 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1932 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1933 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1934 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1935 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1936 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1937 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1938 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1939 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1940 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1941 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1942 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1943 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1944 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1945 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1946 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1947 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1948 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1949 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1950 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1951 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1952 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1953 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1954 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1955 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1956 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1957 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1958 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1959 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1960 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 1961 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1962 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1963 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1964 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1965 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 1966 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1967 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 1968 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1969 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1970 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1971 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 1972 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1973 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 1974 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1975 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1976 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1977 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1978 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1979 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1980 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1981 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1982 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1983 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1984 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1985 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1986 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1987 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1988 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1989 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1990 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1991 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1992 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1993 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1994 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1995 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1996 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1997 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1998 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 1999 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2000 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2001 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2002 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2003 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2004 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2005 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2006 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2007 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2008 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2009 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2010 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2011 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2012 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2013 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2014 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2015 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2016 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2017 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2018 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2019 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2020 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2021 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2022 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2023 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2024 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2025 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2026 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2027 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2028 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 2029 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2030 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 2031 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2032 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 2033 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2034 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 2035 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2036 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 2037 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2038 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 2039 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2040 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2041 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2042 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2043 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2044 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2045 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2046 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2047 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2048 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2049 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2050 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2051 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2052 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2053 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2054 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2055 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2056 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2057 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2058 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX, 2059 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2060 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS, 2061 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2062 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS, 2063 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2064 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS, 2065 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2066 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS, 2067 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2068 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, 2069 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2070 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, 2071 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2072 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS, 2073 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2074 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, 2075 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2076 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, 2077 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2078 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, 2079 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2080 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS, 2081 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2082 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS, 2083 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2084 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS, 2085 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2086 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, 2087 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2088 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, 2089 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2090 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, 2091 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2092 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, 2093 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2094 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, 2095 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2096 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC, 2097 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2098 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC, 2099 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2100 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, 2101 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2102 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, 2103 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2104 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, 2105 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2106 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, 2107 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2108 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, 2109 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2110 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, 2111 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2112 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, 2113 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2114 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, 2115 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2116 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, 2117 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2118 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, 2119 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2120 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, 2121 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2122 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, 2123 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2124 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, 2125 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2126 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, 2127 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2128 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, 2129 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2130 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, 2131 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2132 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, 2133 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2134 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, 2135 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2136 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, 2137 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2138 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, 2139 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2140 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, 2141 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2142 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, 2143 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2144 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, 2145 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2146 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, 2147 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2148 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, 2149 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2150 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, 2151 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2152 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, 2153 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2154 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, 2155 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2156 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, 2157 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2158 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, 2159 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2160 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2161 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2162 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2163 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2164 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2165 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2166 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2167 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2168 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2169 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2170 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2171 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2172 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2173 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2174 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2175 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2176 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2177 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2178 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2179 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2180 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2181 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2182 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2183 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2184 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2185 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2186 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2187 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2188 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2189 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2190 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2191 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2192 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2193 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2194 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2195 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2196 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2197 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2198 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2199 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2200 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2201 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2202 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2203 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2204 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2205 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2206 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2207 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2208 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2209 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2210 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2211 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2212 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2213 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2214 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2215 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2216 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2217 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2218 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2219 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2220 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2221 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2222 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2223 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2224 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2225 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, 2226 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2227 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2228 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2229 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, 2230 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2231 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2232 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2233 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, 2234 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2235 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2236 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2237 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, 2238 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2239 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2240 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2241 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, 2242 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2243 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2244 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2245 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2246 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2247 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2248 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2249 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2250 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2251 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2252 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2253 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, 2254 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2255 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 2256 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2257 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, 2258 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2259 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, 2260 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2261 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, 2262 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2263 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, 2264 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2265 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, 2266 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2267 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 2268 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2269 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 2270 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2271 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 2272 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2273 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, 2274 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF, 2275 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 2276 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2277 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 }, 2278 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2279 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, 2280 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2281 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 }, 2282 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2283 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 2284 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2285 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 2286 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2287 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 2288 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2289 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, 2290 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2291 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, 2292 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2293 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, 2294 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2295 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, 2296 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2297 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, 2298 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2299 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, 2300 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2301 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 2302 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2303 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, 2304 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, 2305 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2306 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, 2307 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2308 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, 2309 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2310 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, 2311 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2312 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, 2313 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2314 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, 2315 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2316 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, 2317 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2318 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, 2319 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2320 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, 2321 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2322 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, 2323 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2324 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, 2325 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2326 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, 2327 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2328 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, 2329 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2330 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, 2331 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2332 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, 2333 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2334 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, 2335 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2336 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, 2337 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2338 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, 2339 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2340 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, 2341 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2342 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, 2343 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2344 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, 2345 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2346 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, 2347 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2348 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, 2349 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2350 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, 2351 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2352 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, 2353 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2354 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, 2355 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2356 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, 2357 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2358 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, 2359 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2360 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2361 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2362 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2363 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2364 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2365 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2366 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2367 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2368 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2369 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2370 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2371 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2372 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2373 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2374 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2375 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2376 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2377 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2378 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2379 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2380 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2381 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2382 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2383 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2384 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2385 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2386 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2387 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2388 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2389 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2390 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2391 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2392 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2393 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2394 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2395 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2396 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2397 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2398 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2399 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2400 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2401 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2402 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2403 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2404 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2405 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2406 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2407 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2408 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2409 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2410 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2411 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2412 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2413 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2414 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2415 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2416 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2417 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2418 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2419 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2420 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2421 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2422 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2423 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2424 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2425 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, 2426 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2427 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2428 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2429 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, 2430 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2431 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2432 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2433 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, 2434 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2435 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2436 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2437 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, 2438 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2439 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2440 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2441 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, 2442 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2443 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2444 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2445 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2446 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2447 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2448 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2449 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2450 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2451 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2452 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2453 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2454 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2455 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2456 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2457 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2458 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2459 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2460 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2461 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2462 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2463 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2464 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2465 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2466 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2467 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2468 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2469 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2470 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2471 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2472 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2473 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2474 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2475 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2476 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2477 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2478 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2479 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2480 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2481 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2482 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2483 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2484 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2485 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2486 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2487 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2488 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2489 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2490 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2491 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2492 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2493 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2494 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2495 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2496 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2497 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2498 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 2499 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2500 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, 2501 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2502 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, 2503 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2504 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, 2505 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 2506 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, 2507 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 2508 RS6000_BTI_unsigned_V1TI, 0 }, 2509 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP, 2510 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2511 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2512 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2513 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2514 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2515 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2516 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2517 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2518 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2519 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2520 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2521 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2522 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2523 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2524 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 2525 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 2526 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2527 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2528 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2529 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2530 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2531 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2532 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 2533 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2534 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2535 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2536 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2537 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2538 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2539 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2540 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2541 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 2542 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2543 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2544 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2545 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2546 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2547 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2548 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2549 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2550 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2551 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2552 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2553 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2554 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2555 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2556 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2557 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 2558 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2559 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW, 2560 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2561 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 2562 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2563 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 2564 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2565 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 2566 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2567 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 2568 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2569 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 2570 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2571 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 2572 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2573 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 2574 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2575 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 2576 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2577 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 2578 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2579 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 2580 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2581 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 2582 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2583 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 2584 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2585 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 2586 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2587 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 2588 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2589 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 2590 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2591 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 2592 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2593 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 2594 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2595 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 2596 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2597 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 2598 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2599 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 2600 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2601 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 2602 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2603 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2604 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2605 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2606 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 2607 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2608 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2609 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2610 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2611 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 2612 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2613 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 2614 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2615 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 2616 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2617 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 2618 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2619 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2620 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2621 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2622 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 2623 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2624 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2625 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2626 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2627 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 2628 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2629 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 2630 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2631 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 2632 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2633 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 2634 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2635 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2636 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2637 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2638 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2639 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2640 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2641 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2642 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2643 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 2644 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2645 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS, 2646 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2647 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS, 2648 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, 2649 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS, 2650 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, 2651 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS, 2652 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, 2653 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS, 2654 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, 2655 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS, 2656 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2657 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS, 2658 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2659 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS, 2660 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2661 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2662 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2663 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2664 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 2665 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2666 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 2667 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2668 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2669 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2670 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 2671 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2672 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 2673 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2674 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2675 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2676 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2677 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2678 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2679 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2680 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2681 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2682 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2683 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2684 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2685 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2686 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2687 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2688 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2689 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2690 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2691 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2692 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2693 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2694 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2695 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2696 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2697 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2698 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2699 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2700 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2701 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2702 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2703 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2704 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2705 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2706 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2707 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2708 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2709 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2710 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2711 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2712 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2713 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2714 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2715 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2716 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2717 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2718 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2719 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2720 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2721 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2722 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2723 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2724 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2725 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 2726 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2727 2728 /* Ternary AltiVec/VSX builtins. */ 2729 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2730 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2731 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2732 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2733 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2734 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2735 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2736 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2737 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2738 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2739 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2740 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2741 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2742 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2743 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2744 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2745 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2746 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2747 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2748 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2749 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2750 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2751 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2752 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2753 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2754 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2755 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2756 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2757 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2758 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2759 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2760 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2761 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2762 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2763 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2764 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2765 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2766 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2767 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 2768 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2769 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2770 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2771 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2772 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2773 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2774 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2775 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2776 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2777 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2778 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2779 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2780 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2781 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2782 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2783 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2784 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2785 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2786 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2787 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2788 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2789 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2790 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2791 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2792 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2793 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2794 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2795 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2796 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2797 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2798 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2799 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2800 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2801 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2802 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2803 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2804 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2805 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2806 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2807 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 2808 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2809 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2810 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2811 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2812 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2813 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2814 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2815 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2816 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2817 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2818 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2819 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2820 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2821 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2822 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2823 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2824 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2825 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2826 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2827 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2828 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2829 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2830 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2831 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2832 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2833 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2834 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2835 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2836 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2837 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2838 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2839 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2840 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2841 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2842 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2843 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2844 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2845 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2846 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2847 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 2848 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2849 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2850 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2851 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2852 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2853 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2854 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2855 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2856 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2857 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2858 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2859 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2860 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2861 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2862 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2863 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2864 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2865 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2866 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2867 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2868 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2869 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2870 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2871 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2872 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2873 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2874 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2875 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2876 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2877 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2878 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2879 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2880 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2881 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2882 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2883 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2884 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2885 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2886 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2887 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 2888 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 2889 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP, 2890 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 2891 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP, 2892 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 2893 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS, 2894 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 2895 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 2896 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 2897 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 2898 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 2899 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 2900 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 2901 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 2902 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 2903 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS, 2904 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 2905 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP, 2906 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 2907 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP, 2908 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 2909 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM, 2910 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, 2911 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM, 2912 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, 2913 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM, 2914 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 2915 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM, 2916 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 2917 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM, 2918 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 2919 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM, 2920 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 2921 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM, 2922 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, 2923 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM, 2924 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, 2925 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS, 2926 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 2927 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS, 2928 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 2929 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS, 2930 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 2931 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS, 2932 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 2933 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP, 2934 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 2935 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP, 2936 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 2937 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP, 2938 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 2939 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP, 2940 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 2941 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF, 2942 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI }, 2943 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 2944 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, 2945 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 2946 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, 2947 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, 2948 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, 2949 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 2950 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI }, 2951 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 2952 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI }, 2953 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 2954 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI }, 2955 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 2956 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI }, 2957 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 2958 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI }, 2959 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 2960 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI }, 2961 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 2962 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI }, 2963 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 2964 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, 2965 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 2966 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 2967 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 2968 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 2969 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 2970 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 2971 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 2972 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 2973 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 2974 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI }, 2975 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 2976 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI }, 2977 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 2978 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI }, 2979 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 2980 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 2981 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 2982 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 2983 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 2984 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, 2985 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 2986 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 2987 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 2988 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 2989 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 2990 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 2991 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 2992 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, 2993 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, 2994 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, 2995 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, 2996 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI }, 2997 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 2998 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 2999 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3000 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI }, 3001 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3002 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 3003 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3004 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI }, 3005 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3006 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 3007 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3008 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 3009 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3010 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, 3011 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3012 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 3013 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3014 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 3015 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3016 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI }, 3017 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3018 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 3019 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3020 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3021 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3022 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, 3023 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3024 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 3025 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3026 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 3027 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3028 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, 3029 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3030 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3031 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3032 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3033 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3034 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3035 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3036 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3037 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF, 3038 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, 3039 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3040 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, 3041 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3042 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_NOT_OPAQUE }, 3043 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3044 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_NOT_OPAQUE }, 3045 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3046 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, 3047 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3048 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_NOT_OPAQUE }, 3049 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3050 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_NOT_OPAQUE }, 3051 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3052 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_NOT_OPAQUE }, 3053 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3054 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, 3055 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3056 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_NOT_OPAQUE }, 3057 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3058 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_NOT_OPAQUE }, 3059 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, 3060 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3061 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3062 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3063 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3064 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3065 ~RS6000_BTI_unsigned_V2DI }, 3066 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3067 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3068 ~RS6000_BTI_bool_V2DI }, 3069 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, 3070 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3071 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, 3072 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3073 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3074 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3075 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3076 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3077 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3078 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3079 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3080 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3081 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3082 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3083 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3084 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3085 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3086 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3087 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3088 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3089 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3090 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3091 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3092 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3093 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3094 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3095 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3096 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3097 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3098 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3099 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3100 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3101 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3102 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3103 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3104 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3105 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3106 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3107 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3108 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3109 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3110 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3111 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3112 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3113 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3114 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3115 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3116 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3117 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3118 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3119 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3120 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3121 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3122 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3123 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3124 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3125 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3126 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3127 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3128 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3129 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3130 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3131 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3132 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3133 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3134 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3135 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3136 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3137 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3138 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3139 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3140 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3141 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3142 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3143 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3144 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3145 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3146 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3147 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3148 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3149 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3150 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3151 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3152 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3153 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3154 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3155 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3156 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3157 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3158 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3159 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3160 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3161 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3162 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3163 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3164 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3165 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3166 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3167 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3168 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3169 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3170 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3171 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3172 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3173 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3174 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3175 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3176 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3177 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3178 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3179 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3180 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3181 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3182 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3183 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3184 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3185 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3186 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3187 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, 3188 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3189 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, 3190 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3191 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3192 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3193 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3194 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3195 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3196 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3197 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3198 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3199 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3200 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3201 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3202 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3203 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3204 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3205 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3206 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3207 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3208 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3209 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3210 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3211 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3212 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3213 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3214 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3215 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3216 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3217 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3218 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3219 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3220 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3221 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3222 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3223 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3224 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3225 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3226 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3227 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3228 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3229 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3230 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3231 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3232 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3233 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3234 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3235 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, 3236 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3237 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, 3238 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3239 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3240 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3241 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3242 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3243 ~RS6000_BTI_unsigned_V2DI }, 3244 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3245 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3246 ~RS6000_BTI_bool_V2DI }, 3247 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3248 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3249 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3250 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3251 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3252 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3253 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3254 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3255 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3256 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3257 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3258 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3259 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3260 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3261 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3262 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3263 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3264 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3265 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3266 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3267 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3268 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3269 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3270 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3271 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3272 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3273 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3274 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3275 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3276 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3277 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3278 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3279 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3280 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3281 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3282 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3283 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3284 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3285 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3286 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3287 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3288 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3289 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3290 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3291 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3292 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3293 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3294 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3295 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3296 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3297 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3298 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3299 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3300 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3301 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3302 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3303 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3304 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3305 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3306 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3307 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3308 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3309 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3310 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3311 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3312 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3313 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3314 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3315 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3316 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3317 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3318 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3319 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3320 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3321 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3322 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3323 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3324 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3325 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3326 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3327 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3328 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3329 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3330 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3331 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3332 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3333 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3334 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3335 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3336 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3337 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3338 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3339 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3340 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3341 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3342 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3343 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3344 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3345 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3346 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3347 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3348 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3349 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3350 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3351 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3352 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3353 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 3354 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3355 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3356 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3357 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3358 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3359 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3360 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3361 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3362 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3363 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3364 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3365 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3366 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3367 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3368 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3369 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3370 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3371 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3372 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3373 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3374 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3375 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3376 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3377 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3378 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3379 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3380 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3381 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3382 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3383 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3384 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3385 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3386 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3387 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3388 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3389 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 3390 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3391 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 3392 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, 3393 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 3394 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3395 RS6000_BTI_NOT_OPAQUE }, 3396 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 3397 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, 3398 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 3399 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3400 RS6000_BTI_NOT_OPAQUE }, 3401 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 3402 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, 3403 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 3404 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3405 RS6000_BTI_NOT_OPAQUE }, 3406 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 3407 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, 3408 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 3409 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3410 RS6000_BTI_NOT_OPAQUE }, 3411 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF, 3412 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, 3413 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF, 3414 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, 3415 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF, 3416 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_NOT_OPAQUE }, 3417 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 3418 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_NOT_OPAQUE }, 3419 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 3420 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3421 RS6000_BTI_NOT_OPAQUE }, 3422 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF, 3423 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_NOT_OPAQUE }, 3424 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 3425 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_NOT_OPAQUE }, 3426 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 3427 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3428 RS6000_BTI_NOT_OPAQUE }, 3429 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 3430 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_NOT_OPAQUE }, 3431 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 3432 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3433 RS6000_BTI_NOT_OPAQUE }, 3434 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 3435 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_NOT_OPAQUE }, 3436 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 3437 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3438 RS6000_BTI_NOT_OPAQUE }, 3439 3440 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 3441 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 3442 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 3443 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 3444 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3445 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 3446 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3447 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3448 ~RS6000_BTI_unsigned_V2DI, 0 }, 3449 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 3450 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 3451 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 3452 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 3453 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 3454 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 3455 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3456 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 3457 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3458 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 3459 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3460 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 3461 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3462 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 3463 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3464 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3465 ~RS6000_BTI_unsigned_V4SI, 0 }, 3466 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3467 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 3468 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 3469 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3470 ~RS6000_BTI_unsigned_long, 0 }, 3471 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3472 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 3473 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3474 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 3475 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3476 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 3477 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3478 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 3479 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3480 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3481 ~RS6000_BTI_unsigned_V8HI, 0 }, 3482 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 3483 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 3484 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3485 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 3486 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3487 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 3488 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3489 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 3490 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3491 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3492 ~RS6000_BTI_unsigned_V16QI, 0 }, 3493 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 3494 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 3495 3496 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 3497 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3498 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 3499 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3500 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3501 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3502 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3503 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3504 ~RS6000_BTI_unsigned_V2DI }, 3505 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 3506 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3507 ~RS6000_BTI_bool_V2DI }, 3508 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, 3509 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3510 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, 3511 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3512 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3513 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3514 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3515 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3516 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3517 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3518 ~RS6000_BTI_unsigned_V4SI }, 3519 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3520 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 3521 ~RS6000_BTI_UINTSI }, 3522 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3523 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 3524 ~RS6000_BTI_bool_V4SI }, 3525 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3526 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 3527 ~RS6000_BTI_UINTSI }, 3528 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 3529 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 3530 ~RS6000_BTI_INTSI }, 3531 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3532 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3533 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3534 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3535 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3536 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3537 ~RS6000_BTI_unsigned_V8HI }, 3538 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3539 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 3540 ~RS6000_BTI_UINTHI }, 3541 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3542 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 3543 ~RS6000_BTI_bool_V8HI }, 3544 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3545 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 3546 ~RS6000_BTI_UINTHI }, 3547 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 3548 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 3549 ~RS6000_BTI_INTHI }, 3550 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3551 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3552 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3553 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3554 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3555 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3556 ~RS6000_BTI_unsigned_V16QI }, 3557 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3558 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3559 ~RS6000_BTI_UINTQI }, 3560 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3561 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 3562 ~RS6000_BTI_bool_V16QI }, 3563 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3564 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 3565 ~RS6000_BTI_UINTQI }, 3566 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3567 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 3568 ~RS6000_BTI_INTQI }, 3569 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 3570 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 3571 ~RS6000_BTI_pixel_V8HI }, 3572 3573 /* Predicates. */ 3574 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3575 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3576 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3577 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3578 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3579 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3580 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3581 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 3582 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3583 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 3584 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3585 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 3586 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3587 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 3588 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3589 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 3590 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3591 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3592 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3593 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3594 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3595 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 3596 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3597 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 3598 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3599 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 3600 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3601 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 3602 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3603 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 3604 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3605 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 3606 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3607 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 3608 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3609 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 3610 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 3611 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 3612 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 3613 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 3614 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 3615 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 3616 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 3617 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 3618 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 3619 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 3620 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 3621 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 3622 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P, 3623 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3624 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P, 3625 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3626 3627 3628 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 3629 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3630 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 3631 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3632 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 3633 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3634 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 3635 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 3636 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 3637 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 3638 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 3639 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 3640 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 3641 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3642 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3643 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 3644 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3645 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 3646 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3647 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3648 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3649 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3650 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3651 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 3652 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3653 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 3654 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3655 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, 3656 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 3657 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI }, 3658 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 3659 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 3660 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 3661 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 3662 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 3663 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 3664 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 3665 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 3666 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 3667 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 3668 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 3669 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 3670 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 3671 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, 3672 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 3673 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 3674 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 3675 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 3676 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 3677 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 3678 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 3679 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 3680 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 3681 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 3682 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 3683 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 3684 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 3685 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, 3686 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, 3687 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3688 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, 3689 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3690 3691 3692 /* cmpge is the same as cmpgt for all cases except floating point. 3693 There is further code to deal with this special case in 3694 altivec_build_resolved_builtin. */ 3695 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3696 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3697 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3698 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3699 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 3700 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3701 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3702 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 3703 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3704 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 3705 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 3706 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 3707 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3708 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 3709 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3710 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 3711 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 3712 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3713 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3714 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3715 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3716 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 3717 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 3718 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 3719 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3720 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 3721 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3722 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 3723 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 3724 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 3725 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3726 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 3727 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3728 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 3729 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 3730 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 3731 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 3732 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 3733 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 3734 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 3735 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 3736 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 3737 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 3738 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 3739 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 3740 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 3741 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 3742 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 3743 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, 3744 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3745 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, 3746 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3747 3748 /* Power8 vector overloaded functions. */ 3749 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 3750 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 3751 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 3752 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3753 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 3754 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3755 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 3756 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 3757 RS6000_BTI_unsigned_V16QI, 0 }, 3758 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 3759 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3760 RS6000_BTI_bool_V16QI, 0 }, 3761 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 3762 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3763 RS6000_BTI_unsigned_V16QI, 0 }, 3764 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 3765 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 3766 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 3767 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3768 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 3769 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 3770 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 3771 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 3772 RS6000_BTI_unsigned_V8HI, 0 }, 3773 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 3774 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3775 RS6000_BTI_bool_V8HI, 0 }, 3776 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 3777 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3778 RS6000_BTI_unsigned_V8HI, 0 }, 3779 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 3780 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 3781 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 3782 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3783 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 3784 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3785 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 3786 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 3787 RS6000_BTI_unsigned_V4SI, 0 }, 3788 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 3789 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3790 RS6000_BTI_bool_V4SI, 0 }, 3791 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 3792 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3793 RS6000_BTI_unsigned_V4SI, 0 }, 3794 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 3795 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 3796 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 3797 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3798 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 3799 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 3800 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 3801 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 3802 RS6000_BTI_unsigned_V2DI, 0 }, 3803 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 3804 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3805 RS6000_BTI_bool_V2DI, 0 }, 3806 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 3807 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3808 RS6000_BTI_unsigned_V2DI, 0 }, 3809 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, 3810 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 3811 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF, 3812 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 3813 3814 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 3815 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 3816 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 3817 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3818 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 3819 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3820 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 3821 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 3822 RS6000_BTI_unsigned_V16QI, 0 }, 3823 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 3824 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3825 RS6000_BTI_bool_V16QI, 0 }, 3826 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 3827 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3828 RS6000_BTI_unsigned_V16QI, 0 }, 3829 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 3830 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 3831 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 3832 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3833 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 3834 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 3835 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 3836 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 3837 RS6000_BTI_unsigned_V8HI, 0 }, 3838 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 3839 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3840 RS6000_BTI_bool_V8HI, 0 }, 3841 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 3842 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3843 RS6000_BTI_unsigned_V8HI, 0 }, 3844 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 3845 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 3846 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 3847 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3848 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 3849 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3850 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 3851 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 3852 RS6000_BTI_unsigned_V4SI, 0 }, 3853 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 3854 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3855 RS6000_BTI_bool_V4SI, 0 }, 3856 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 3857 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3858 RS6000_BTI_unsigned_V4SI, 0 }, 3859 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 3860 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 3861 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 3862 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3863 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 3864 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 3865 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 3866 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 3867 RS6000_BTI_unsigned_V2DI, 0 }, 3868 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 3869 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3870 RS6000_BTI_bool_V2DI, 0 }, 3871 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 3872 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3873 RS6000_BTI_unsigned_V2DI, 0 }, 3874 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, 3875 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 3876 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, 3877 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 3878 3879 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 3880 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 3881 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 3882 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3883 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 3884 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3885 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 3886 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 3887 RS6000_BTI_unsigned_V16QI, 0 }, 3888 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 3889 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3890 RS6000_BTI_bool_V16QI, 0 }, 3891 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 3892 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3893 RS6000_BTI_unsigned_V16QI, 0 }, 3894 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 3895 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 3896 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 3897 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3898 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 3899 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 3900 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 3901 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 3902 RS6000_BTI_unsigned_V8HI, 0 }, 3903 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 3904 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3905 RS6000_BTI_bool_V8HI, 0 }, 3906 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 3907 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3908 RS6000_BTI_unsigned_V8HI, 0 }, 3909 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 3910 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 3911 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 3912 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3913 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 3914 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3915 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 3916 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 3917 RS6000_BTI_unsigned_V4SI, 0 }, 3918 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 3919 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3920 RS6000_BTI_bool_V4SI, 0 }, 3921 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 3922 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3923 RS6000_BTI_unsigned_V4SI, 0 }, 3924 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 3925 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 3926 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 3927 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3928 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 3929 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 3930 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 3931 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 3932 RS6000_BTI_unsigned_V2DI, 0 }, 3933 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 3934 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3935 RS6000_BTI_bool_V2DI, 0 }, 3936 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 3937 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3938 RS6000_BTI_unsigned_V2DI, 0 }, 3939 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, 3940 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 3941 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, 3942 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 3943 3944 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, 3945 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 3946 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, 3947 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 3948 RS6000_BTI_unsigned_V1TI, 0 }, 3949 3950 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 3951 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 3952 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 3953 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3954 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 3955 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 3956 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 3957 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 3958 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 3959 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3960 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 3961 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 3962 3963 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, 3964 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 3965 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, 3966 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 3967 RS6000_BTI_unsigned_V1TI, 0 }, 3968 3969 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 3970 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3971 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 3972 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 3973 RS6000_BTI_unsigned_V16QI, 0 }, 3974 3975 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, 3976 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 3977 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, 3978 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 3979 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, 3980 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 3981 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, 3982 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 3983 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, 3984 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 3985 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, 3986 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 3987 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, 3988 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 3989 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, 3990 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 3991 3992 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, 3993 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 3994 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, 3995 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 3996 3997 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, 3998 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 3999 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, 4000 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4001 4002 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, 4003 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4004 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, 4005 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4006 4007 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, 4008 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4009 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, 4010 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4011 4012 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 4013 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4014 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 4015 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4016 4017 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 4018 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 4019 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 4020 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4021 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 4022 4023 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, 4024 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 4025 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, 4026 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4027 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 4028 4029 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, 4030 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 4031 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, 4032 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4033 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 4034 4035 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, 4036 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 4037 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, 4038 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4039 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 4040 4041 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 4042 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4043 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 4044 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4045 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 4046 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4047 4048 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 4049 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4050 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 4051 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4052 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 4053 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4054 4055 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 4056 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4057 RS6000_BTI_unsigned_V2DI, 0 }, 4058 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 4059 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4060 RS6000_BTI_bool_V2DI, 0 }, 4061 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 4062 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4063 RS6000_BTI_unsigned_V2DI, 0 }, 4064 4065 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 4066 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4067 RS6000_BTI_unsigned_V2DI, 0 }, 4068 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 4069 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4070 RS6000_BTI_bool_V2DI, 0 }, 4071 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 4072 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4073 RS6000_BTI_unsigned_V2DI, 0 }, 4074 4075 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, 4076 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4077 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, 4078 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4079 RS6000_BTI_unsigned_V4SI, 0 }, 4080 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, 4081 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4082 4083 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, 4084 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4085 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, 4086 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4087 RS6000_BTI_unsigned_V4SI, 0 }, 4088 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, 4089 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4090 4091 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, 4092 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4093 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, 4094 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4095 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, 4096 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4097 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, 4098 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4099 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, 4100 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4101 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, 4102 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4103 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, 4104 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4105 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, 4106 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4107 4108 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, 4109 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4110 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, 4111 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4112 4113 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, 4114 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4115 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, 4116 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4117 4118 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, 4119 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4120 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, 4121 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4122 4123 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, 4124 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4125 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, 4126 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4127 4128 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 4129 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4130 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 4131 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4132 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 4133 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4134 4135 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS, 4136 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4137 4138 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS, 4139 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4140 4141 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS, 4142 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4143 4144 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, 4145 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4146 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, 4147 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4148 4149 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, 4150 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4151 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, 4152 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4153 4154 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, 4155 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4156 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, 4157 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4158 4159 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, 4160 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4161 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, 4162 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4163 4164 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, 4165 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 4166 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, 4167 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4168 RS6000_BTI_unsigned_V1TI, 0 }, 4169 4170 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 4171 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4172 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 4173 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4174 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 4175 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4176 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 4177 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4178 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 4179 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4180 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 4181 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4182 4183 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, 4184 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 4185 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, 4186 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4187 RS6000_BTI_unsigned_V1TI, 0 }, 4188 4189 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, 4190 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 4191 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, 4192 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 4193 4194 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, 4195 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 4196 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, 4197 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 4198 4199 /* Crypto builtins. */ 4200 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, 4201 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4202 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 4203 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI, 4204 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4205 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 4206 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI, 4207 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4208 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 4209 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI, 4210 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4211 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 4212 4213 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB, 4214 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4215 RS6000_BTI_unsigned_V16QI, 0 }, 4216 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH, 4217 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4218 RS6000_BTI_unsigned_V8HI, 0 }, 4219 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW, 4220 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4221 RS6000_BTI_unsigned_V4SI, 0 }, 4222 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD, 4223 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4224 RS6000_BTI_unsigned_V2DI, 0 }, 4225 4226 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW, 4227 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4228 RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 4229 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD, 4230 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4231 RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 4232 4233 { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 } 4234}; 4235 4236 4237/* Convert a type stored into a struct altivec_builtin_types as ID, 4238 into a tree. The types are in rs6000_builtin_types: negative values 4239 create a pointer type for the type associated to ~ID. Note it is 4240 a logical NOT, rather than a negation, otherwise you cannot represent 4241 a pointer type for ID 0. */ 4242 4243static inline tree 4244rs6000_builtin_type (int id) 4245{ 4246 tree t; 4247 t = rs6000_builtin_types[id < 0 ? ~id : id]; 4248 return id < 0 ? build_pointer_type (t) : t; 4249} 4250 4251/* Check whether the type of an argument, T, is compatible with a 4252 type ID stored into a struct altivec_builtin_types. Integer 4253 types are considered compatible; otherwise, the language hook 4254 lang_hooks.types_compatible_p makes the decision. */ 4255 4256static inline bool 4257rs6000_builtin_type_compatible (tree t, int id) 4258{ 4259 tree builtin_type; 4260 builtin_type = rs6000_builtin_type (id); 4261 if (t == error_mark_node) 4262 return false; 4263 if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type)) 4264 return true; 4265 else 4266 return lang_hooks.types_compatible_p (t, builtin_type); 4267} 4268 4269 4270/* In addition to calling fold_convert for EXPR of type TYPE, also 4271 call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be 4272 hiding there (PR47197). */ 4273 4274static tree 4275fully_fold_convert (tree type, tree expr) 4276{ 4277 tree result = fold_convert (type, expr); 4278 bool maybe_const = true; 4279 4280 if (!c_dialect_cxx ()) 4281 result = c_fully_fold (result, false, &maybe_const); 4282 4283 return result; 4284} 4285 4286/* Build a tree for a function call to an Altivec non-overloaded builtin. 4287 The overloaded builtin that matched the types and args is described 4288 by DESC. The N arguments are given in ARGS, respectively. 4289 4290 Actually the only thing it does is calling fold_convert on ARGS, with 4291 a small exception for vec_{all,any}_{ge,le} predicates. */ 4292 4293static tree 4294altivec_build_resolved_builtin (tree *args, int n, 4295 const struct altivec_builtin_types *desc) 4296{ 4297 tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code]; 4298 tree ret_type = rs6000_builtin_type (desc->ret_type); 4299 tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl)); 4300 tree arg_type[3]; 4301 tree call; 4302 4303 int i; 4304 for (i = 0; i < n; i++) 4305 arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes); 4306 4307 /* The AltiVec overloading implementation is overall gross, but this 4308 is particularly disgusting. The vec_{all,any}_{ge,le} builtins 4309 are completely different for floating-point vs. integer vector 4310 types, because the former has vcmpgefp, but the latter should use 4311 vcmpgtXX. 4312 4313 In practice, the second and third arguments are swapped, and the 4314 condition (LT vs. EQ, which is recognizable by bit 1 of the first 4315 argument) is reversed. Patch the arguments here before building 4316 the resolved CALL_EXPR. */ 4317 if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P 4318 && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P 4319 && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P) 4320 { 4321 tree t; 4322 t = args[2], args[2] = args[1], args[1] = t; 4323 t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t; 4324 4325 args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0], 4326 build_int_cst (NULL_TREE, 2)); 4327 } 4328 4329 switch (n) 4330 { 4331 case 0: 4332 call = build_call_expr (impl_fndecl, 0); 4333 break; 4334 case 1: 4335 call = build_call_expr (impl_fndecl, 1, 4336 fully_fold_convert (arg_type[0], args[0])); 4337 break; 4338 case 2: 4339 call = build_call_expr (impl_fndecl, 2, 4340 fully_fold_convert (arg_type[0], args[0]), 4341 fully_fold_convert (arg_type[1], args[1])); 4342 break; 4343 case 3: 4344 call = build_call_expr (impl_fndecl, 3, 4345 fully_fold_convert (arg_type[0], args[0]), 4346 fully_fold_convert (arg_type[1], args[1]), 4347 fully_fold_convert (arg_type[2], args[2])); 4348 break; 4349 default: 4350 gcc_unreachable (); 4351 } 4352 return fold_convert (ret_type, call); 4353} 4354 4355/* Implementation of the resolve_overloaded_builtin target hook, to 4356 support Altivec's overloaded builtins. */ 4357 4358tree 4359altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, 4360 void *passed_arglist) 4361{ 4362 vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist); 4363 unsigned int nargs = vec_safe_length (arglist); 4364 enum rs6000_builtins fcode 4365 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl); 4366 tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl)); 4367 tree types[3], args[3]; 4368 const struct altivec_builtin_types *desc; 4369 unsigned int n; 4370 4371 if (!rs6000_overloaded_builtin_p (fcode)) 4372 return NULL_TREE; 4373 4374 if (TARGET_DEBUG_BUILTIN) 4375 fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n", 4376 (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); 4377 4378 /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */ 4379 if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !VECTOR_ELT_ORDER_BIG) 4380 warning (OPT_Wdeprecated, "vec_lvsl is deprecated for little endian; use \ 4381assignment for unaligned loads and stores"); 4382 else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !VECTOR_ELT_ORDER_BIG) 4383 warning (OPT_Wdeprecated, "vec_lvsr is deprecated for little endian; use \ 4384assignment for unaligned loads and stores"); 4385 4386 /* For now treat vec_splats and vec_promote as the same. */ 4387 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS 4388 || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE) 4389 { 4390 tree type, arg; 4391 int size; 4392 int i; 4393 bool unsigned_p; 4394 vec<constructor_elt, va_gc> *vec; 4395 const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote"; 4396 4397 if (nargs == 0) 4398 { 4399 error ("%s only accepts %d arguments", name, (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE)+1 ); 4400 return error_mark_node; 4401 } 4402 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1) 4403 { 4404 error ("%s only accepts 1 argument", name); 4405 return error_mark_node; 4406 } 4407 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2) 4408 { 4409 error ("%s only accepts 2 arguments", name); 4410 return error_mark_node; 4411 } 4412 /* Ignore promote's element argument. */ 4413 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE 4414 && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1]))) 4415 goto bad; 4416 4417 arg = (*arglist)[0]; 4418 type = TREE_TYPE (arg); 4419 if (!SCALAR_FLOAT_TYPE_P (type) 4420 && !INTEGRAL_TYPE_P (type)) 4421 goto bad; 4422 unsigned_p = TYPE_UNSIGNED (type); 4423 switch (TYPE_MODE (type)) 4424 { 4425 case TImode: 4426 type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node); 4427 size = 1; 4428 break; 4429 case DImode: 4430 type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node); 4431 size = 2; 4432 break; 4433 case SImode: 4434 type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); 4435 size = 4; 4436 break; 4437 case HImode: 4438 type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); 4439 size = 8; 4440 break; 4441 case QImode: 4442 type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); 4443 size = 16; 4444 break; 4445 case SFmode: type = V4SF_type_node; size = 4; break; 4446 case DFmode: type = V2DF_type_node; size = 2; break; 4447 default: 4448 goto bad; 4449 } 4450 arg = save_expr (fold_convert (TREE_TYPE (type), arg)); 4451 vec_alloc (vec, size); 4452 for(i = 0; i < size; i++) 4453 { 4454 constructor_elt elt = {NULL_TREE, arg}; 4455 vec->quick_push (elt); 4456 } 4457 return build_constructor (type, vec); 4458 } 4459 4460 /* For now use pointer tricks to do the extraction, unless we are on VSX 4461 extracting a double from a constant offset. */ 4462 if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT) 4463 { 4464 tree arg1; 4465 tree arg1_type; 4466 tree arg2; 4467 tree arg1_inner_type; 4468 tree decl, stmt; 4469 tree innerptrtype; 4470 machine_mode mode; 4471 4472 /* No second argument. */ 4473 if (nargs != 2) 4474 { 4475 error ("vec_extract only accepts 2 arguments"); 4476 return error_mark_node; 4477 } 4478 4479 arg2 = (*arglist)[1]; 4480 arg1 = (*arglist)[0]; 4481 arg1_type = TREE_TYPE (arg1); 4482 4483 if (TREE_CODE (arg1_type) != VECTOR_TYPE) 4484 goto bad; 4485 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) 4486 goto bad; 4487 4488 /* If we are targeting little-endian, but -maltivec=be has been 4489 specified to override the element order, adjust the element 4490 number accordingly. */ 4491 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2) 4492 { 4493 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1; 4494 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2), 4495 build_int_cstu (TREE_TYPE (arg2), last_elem), 4496 arg2); 4497 } 4498 4499 /* If we can use the VSX xxpermdi instruction, use that for extract. */ 4500 mode = TYPE_MODE (arg1_type); 4501 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_MEM_VSX_P (mode) 4502 && TREE_CODE (arg2) == INTEGER_CST 4503 && wi::ltu_p (arg2, 2)) 4504 { 4505 tree call = NULL_TREE; 4506 4507 if (mode == V2DFmode) 4508 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF]; 4509 else if (mode == V2DImode) 4510 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI]; 4511 4512 if (call) 4513 return build_call_expr (call, 2, arg1, arg2); 4514 } 4515 else if (mode == V1TImode && VECTOR_MEM_VSX_P (mode) 4516 && TREE_CODE (arg2) == INTEGER_CST 4517 && wi::eq_p (arg2, 0)) 4518 { 4519 tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI]; 4520 return build_call_expr (call, 2, arg1, arg2); 4521 } 4522 4523 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */ 4524 arg1_inner_type = TREE_TYPE (arg1_type); 4525 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2, 4526 build_int_cst (TREE_TYPE (arg2), 4527 TYPE_VECTOR_SUBPARTS (arg1_type) 4528 - 1), 0); 4529 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type); 4530 DECL_EXTERNAL (decl) = 0; 4531 TREE_PUBLIC (decl) = 0; 4532 DECL_CONTEXT (decl) = current_function_decl; 4533 TREE_USED (decl) = 1; 4534 TREE_TYPE (decl) = arg1_type; 4535 TREE_READONLY (decl) = TYPE_READONLY (arg1_type); 4536 if (c_dialect_cxx ()) 4537 { 4538 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, 4539 NULL_TREE, NULL_TREE); 4540 SET_EXPR_LOCATION (stmt, loc); 4541 } 4542 else 4543 { 4544 DECL_INITIAL (decl) = arg1; 4545 stmt = build1 (DECL_EXPR, arg1_type, decl); 4546 TREE_ADDRESSABLE (decl) = 1; 4547 SET_EXPR_LOCATION (stmt, loc); 4548 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); 4549 } 4550 4551 innerptrtype = build_pointer_type (arg1_inner_type); 4552 4553 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); 4554 stmt = convert (innerptrtype, stmt); 4555 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); 4556 stmt = build_indirect_ref (loc, stmt, RO_NULL); 4557 4558 return stmt; 4559 } 4560 4561 /* For now use pointer tricks to do the insertion, unless we are on VSX 4562 inserting a double to a constant offset.. */ 4563 if (fcode == ALTIVEC_BUILTIN_VEC_INSERT) 4564 { 4565 tree arg0; 4566 tree arg1; 4567 tree arg2; 4568 tree arg1_type; 4569 tree arg1_inner_type; 4570 tree decl, stmt; 4571 tree innerptrtype; 4572 machine_mode mode; 4573 4574 /* No second or third arguments. */ 4575 if (nargs != 3) 4576 { 4577 error ("vec_insert only accepts 3 arguments"); 4578 return error_mark_node; 4579 } 4580 4581 arg0 = (*arglist)[0]; 4582 arg1 = (*arglist)[1]; 4583 arg1_type = TREE_TYPE (arg1); 4584 arg2 = (*arglist)[2]; 4585 4586 if (TREE_CODE (arg1_type) != VECTOR_TYPE) 4587 goto bad; 4588 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) 4589 goto bad; 4590 4591 /* If we are targeting little-endian, but -maltivec=be has been 4592 specified to override the element order, adjust the element 4593 number accordingly. */ 4594 if (!BYTES_BIG_ENDIAN && rs6000_altivec_element_order == 2) 4595 { 4596 unsigned int last_elem = TYPE_VECTOR_SUBPARTS (arg1_type) - 1; 4597 arg2 = fold_build2_loc (loc, MINUS_EXPR, TREE_TYPE (arg2), 4598 build_int_cstu (TREE_TYPE (arg2), last_elem), 4599 arg2); 4600 } 4601 4602 /* If we can use the VSX xxpermdi instruction, use that for insert. */ 4603 mode = TYPE_MODE (arg1_type); 4604 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode) 4605 && TREE_CODE (arg2) == INTEGER_CST 4606 && wi::ltu_p (arg2, 2)) 4607 { 4608 tree call = NULL_TREE; 4609 4610 if (mode == V2DFmode) 4611 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF]; 4612 else if (mode == V2DImode) 4613 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI]; 4614 4615 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types 4616 reversed. */ 4617 if (call) 4618 return build_call_expr (call, 3, arg1, arg0, arg2); 4619 } 4620 else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode) 4621 && TREE_CODE (arg2) == INTEGER_CST 4622 && wi::eq_p (arg2, 0)) 4623 { 4624 tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI]; 4625 4626 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types 4627 reversed. */ 4628 return build_call_expr (call, 3, arg1, arg0, arg2); 4629 } 4630 4631 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */ 4632 arg1_inner_type = TREE_TYPE (arg1_type); 4633 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2, 4634 build_int_cst (TREE_TYPE (arg2), 4635 TYPE_VECTOR_SUBPARTS (arg1_type) 4636 - 1), 0); 4637 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type); 4638 DECL_EXTERNAL (decl) = 0; 4639 TREE_PUBLIC (decl) = 0; 4640 DECL_CONTEXT (decl) = current_function_decl; 4641 TREE_USED (decl) = 1; 4642 TREE_TYPE (decl) = arg1_type; 4643 TREE_READONLY (decl) = TYPE_READONLY (arg1_type); 4644 if (c_dialect_cxx ()) 4645 { 4646 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, 4647 NULL_TREE, NULL_TREE); 4648 SET_EXPR_LOCATION (stmt, loc); 4649 } 4650 else 4651 { 4652 DECL_INITIAL (decl) = arg1; 4653 stmt = build1 (DECL_EXPR, arg1_type, decl); 4654 TREE_ADDRESSABLE (decl) = 1; 4655 SET_EXPR_LOCATION (stmt, loc); 4656 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); 4657 } 4658 4659 innerptrtype = build_pointer_type (arg1_inner_type); 4660 4661 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); 4662 stmt = convert (innerptrtype, stmt); 4663 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); 4664 stmt = build_indirect_ref (loc, stmt, RO_NULL); 4665 stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt, 4666 convert (TREE_TYPE (stmt), arg0)); 4667 stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); 4668 return stmt; 4669 } 4670 4671 for (n = 0; 4672 !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs; 4673 fnargs = TREE_CHAIN (fnargs), n++) 4674 { 4675 tree decl_type = TREE_VALUE (fnargs); 4676 tree arg = (*arglist)[n]; 4677 tree type; 4678 4679 if (arg == error_mark_node) 4680 return error_mark_node; 4681 4682 if (n >= 3) 4683 abort (); 4684 4685 arg = default_conversion (arg); 4686 4687 /* The C++ front-end converts float * to const void * using 4688 NOP_EXPR<const void *> (NOP_EXPR<void *> (x)). */ 4689 type = TREE_TYPE (arg); 4690 if (POINTER_TYPE_P (type) 4691 && TREE_CODE (arg) == NOP_EXPR 4692 && lang_hooks.types_compatible_p (TREE_TYPE (arg), 4693 const_ptr_type_node) 4694 && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)), 4695 ptr_type_node)) 4696 { 4697 arg = TREE_OPERAND (arg, 0); 4698 type = TREE_TYPE (arg); 4699 } 4700 4701 /* Remove the const from the pointers to simplify the overload 4702 matching further down. */ 4703 if (POINTER_TYPE_P (decl_type) 4704 && POINTER_TYPE_P (type) 4705 && TYPE_QUALS (TREE_TYPE (type)) != 0) 4706 { 4707 if (TYPE_READONLY (TREE_TYPE (type)) 4708 && !TYPE_READONLY (TREE_TYPE (decl_type))) 4709 warning (0, "passing arg %d of %qE discards qualifiers from" 4710 "pointer target type", n + 1, fndecl); 4711 type = build_pointer_type (build_qualified_type (TREE_TYPE (type), 4712 0)); 4713 arg = fold_convert (type, arg); 4714 } 4715 4716 args[n] = arg; 4717 types[n] = type; 4718 } 4719 4720 /* If the number of arguments did not match the prototype, return NULL 4721 and the generic code will issue the appropriate error message. */ 4722 if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs) 4723 return NULL; 4724 4725 if (n == 0) 4726 abort (); 4727 4728 if (fcode == ALTIVEC_BUILTIN_VEC_STEP) 4729 { 4730 if (TREE_CODE (types[0]) != VECTOR_TYPE) 4731 goto bad; 4732 4733 return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0])); 4734 } 4735 4736 for (desc = altivec_overloaded_builtins; 4737 desc->code && desc->code != fcode; desc++) 4738 continue; 4739 4740 /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in 4741 the opX fields. */ 4742 for (; desc->code == fcode; desc++) 4743 if ((desc->op1 == RS6000_BTI_NOT_OPAQUE 4744 || rs6000_builtin_type_compatible (types[0], desc->op1)) 4745 && (desc->op2 == RS6000_BTI_NOT_OPAQUE 4746 || rs6000_builtin_type_compatible (types[1], desc->op2)) 4747 && (desc->op3 == RS6000_BTI_NOT_OPAQUE 4748 || rs6000_builtin_type_compatible (types[2], desc->op3)) 4749 && rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) 4750 return altivec_build_resolved_builtin (args, n, desc); 4751 4752 bad: 4753 error ("invalid parameter combination for AltiVec intrinsic"); 4754 return error_mark_node; 4755} 4756