1;; Scheduling description for IBM POWER5 processor. 2;; Copyright (C) 2003-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Sources: IBM Red Book and White Paper on POWER5 21 22;; The POWER5 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). 23;; Instructions that update more than one register get broken into two 24;; (split) or more internal ops. The chip can issue up to 5 25;; internal ops per cycle. 26 27(define_automaton "power5iu,power5fpu,power5misc") 28 29(define_cpu_unit "iu1_power5,iu2_power5" "power5iu") 30(define_cpu_unit "lsu1_power5,lsu2_power5" "power5misc") 31(define_cpu_unit "fpu1_power5,fpu2_power5" "power5fpu") 32(define_cpu_unit "bpu_power5,cru_power5" "power5misc") 33(define_cpu_unit "du1_power5,du2_power5,du3_power5,du4_power5,du5_power5" 34 "power5misc") 35 36(define_reservation "lsq_power5" 37 "(du1_power5,lsu1_power5)\ 38 |(du2_power5,lsu2_power5)\ 39 |(du3_power5,lsu2_power5)\ 40 |(du4_power5,lsu1_power5)") 41 42(define_reservation "iq_power5" 43 "(du1_power5|du2_power5|du3_power5|du4_power5),\ 44 (iu1_power5|iu2_power5)") 45 46(define_reservation "fpq_power5" 47 "(du1_power5|du2_power5|du3_power5|du4_power5),\ 48 (fpu1_power5|fpu2_power5)") 49 50; Dispatch slots are allocated in order conforming to program order. 51(absence_set "du1_power5" "du2_power5,du3_power5,du4_power5,du5_power5") 52(absence_set "du2_power5" "du3_power5,du4_power5,du5_power5") 53(absence_set "du3_power5" "du4_power5,du5_power5") 54(absence_set "du4_power5" "du5_power5") 55 56 57; Load/store 58(define_insn_reservation "power5-load" 4 ; 3 59 (and (eq_attr "type" "load") 60 (eq_attr "sign_extend" "no") 61 (eq_attr "update" "no") 62 (eq_attr "cpu" "power5")) 63 "lsq_power5") 64 65(define_insn_reservation "power5-load-ext" 5 66 (and (eq_attr "type" "load") 67 (eq_attr "sign_extend" "yes") 68 (eq_attr "update" "no") 69 (eq_attr "cpu" "power5")) 70 "du1_power5+du2_power5,lsu1_power5,nothing,nothing,iu2_power5") 71 72(define_insn_reservation "power5-load-ext-update" 5 73 (and (eq_attr "type" "load") 74 (eq_attr "sign_extend" "yes") 75 (eq_attr "update" "yes") 76 (eq_attr "indexed" "no") 77 (eq_attr "cpu" "power5")) 78 "du1_power5+du2_power5+du3_power5+du4_power5,\ 79 lsu1_power5+iu2_power5,nothing,nothing,iu2_power5") 80 81(define_insn_reservation "power5-load-ext-update-indexed" 5 82 (and (eq_attr "type" "load") 83 (eq_attr "sign_extend" "yes") 84 (eq_attr "update" "yes") 85 (eq_attr "indexed" "yes") 86 (eq_attr "cpu" "power5")) 87 "du1_power5+du2_power5+du3_power5+du4_power5,\ 88 iu1_power5,lsu2_power5+iu1_power5,nothing,nothing,iu2_power5") 89 90(define_insn_reservation "power5-load-update-indexed" 3 91 (and (eq_attr "type" "load") 92 (eq_attr "sign_extend" "no") 93 (eq_attr "update" "yes") 94 (eq_attr "indexed" "yes") 95 (eq_attr "cpu" "power5")) 96 "du1_power5+du2_power5+du3_power5+du4_power5,\ 97 iu1_power5,lsu2_power5+iu2_power5") 98 99(define_insn_reservation "power5-load-update" 4 ; 3 100 (and (eq_attr "type" "load") 101 (eq_attr "sign_extend" "no") 102 (eq_attr "update" "yes") 103 (eq_attr "indexed" "no") 104 (eq_attr "cpu" "power5")) 105 "du1_power5+du2_power5,lsu1_power5+iu2_power5") 106 107(define_insn_reservation "power5-fpload" 6 ; 5 108 (and (eq_attr "type" "fpload") 109 (eq_attr "update" "no") 110 (eq_attr "cpu" "power5")) 111 "lsq_power5") 112 113(define_insn_reservation "power5-fpload-update" 6 ; 5 114 (and (eq_attr "type" "fpload") 115 (eq_attr "update" "yes") 116 (eq_attr "cpu" "power5")) 117 "du1_power5+du2_power5,lsu1_power5+iu2_power5") 118 119(define_insn_reservation "power5-store" 12 120 (and (eq_attr "type" "store") 121 (eq_attr "update" "no") 122 (eq_attr "cpu" "power5")) 123 "((du1_power5,lsu1_power5)\ 124 |(du2_power5,lsu2_power5)\ 125 |(du3_power5,lsu2_power5)\ 126 |(du4_power5,lsu1_power5)),\ 127 (iu1_power5|iu2_power5)") 128 129(define_insn_reservation "power5-store-update" 12 130 (and (eq_attr "type" "store") 131 (eq_attr "update" "yes") 132 (eq_attr "indexed" "no") 133 (eq_attr "cpu" "power5")) 134 "du1_power5+du2_power5,lsu1_power5+iu2_power5,iu1_power5") 135 136(define_insn_reservation "power5-store-update-indexed" 12 137 (and (eq_attr "type" "store") 138 (eq_attr "update" "yes") 139 (eq_attr "indexed" "yes") 140 (eq_attr "cpu" "power5")) 141 "du1_power5+du2_power5+du3_power5+du4_power5,\ 142 iu1_power5,lsu2_power5+iu2_power5,iu2_power5") 143 144(define_insn_reservation "power5-fpstore" 12 145 (and (eq_attr "type" "fpstore") 146 (eq_attr "update" "no") 147 (eq_attr "cpu" "power5")) 148 "((du1_power5,lsu1_power5)\ 149 |(du2_power5,lsu2_power5)\ 150 |(du3_power5,lsu2_power5)\ 151 |(du4_power5,lsu1_power5)),\ 152 (fpu1_power5|fpu2_power5)") 153 154(define_insn_reservation "power5-fpstore-update" 12 155 (and (eq_attr "type" "fpstore") 156 (eq_attr "update" "yes") 157 (eq_attr "cpu" "power5")) 158 "du1_power5+du2_power5,lsu1_power5+iu2_power5,fpu1_power5") 159 160(define_insn_reservation "power5-llsc" 11 161 (and (eq_attr "type" "load_l,store_c,sync") 162 (eq_attr "cpu" "power5")) 163 "du1_power5+du2_power5+du3_power5+du4_power5,\ 164 lsu1_power5") 165 166 167; Integer latency is 2 cycles 168(define_insn_reservation "power5-integer" 2 169 (and (ior (eq_attr "type" "integer,trap,cntlz,isel,popcnt") 170 (and (eq_attr "type" "add,logical,shift,exts") 171 (eq_attr "dot" "no")) 172 (and (eq_attr "type" "insert") 173 (eq_attr "size" "64"))) 174 (eq_attr "cpu" "power5")) 175 "iq_power5") 176 177(define_insn_reservation "power5-two" 2 178 (and (eq_attr "type" "two") 179 (eq_attr "cpu" "power5")) 180 "((du1_power5+du2_power5)\ 181 |(du2_power5+du3_power5)\ 182 |(du3_power5+du4_power5)\ 183 |(du4_power5+du1_power5)),\ 184 ((iu1_power5,nothing,iu2_power5)\ 185 |(iu2_power5,nothing,iu2_power5)\ 186 |(iu2_power5,nothing,iu1_power5)\ 187 |(iu1_power5,nothing,iu1_power5))") 188 189(define_insn_reservation "power5-three" 2 190 (and (eq_attr "type" "three") 191 (eq_attr "cpu" "power5")) 192 "(du1_power5+du2_power5+du3_power5|du2_power5+du3_power5+du4_power5\ 193 |du3_power5+du4_power5+du1_power5|du4_power5+du1_power5+du2_power5),\ 194 ((iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\ 195 |(iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\ 196 |(iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\ 197 |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))") 198 199(define_insn_reservation "power5-insert" 4 200 (and (eq_attr "type" "insert") 201 (eq_attr "size" "32") 202 (eq_attr "cpu" "power5")) 203 "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5") 204 205(define_insn_reservation "power5-cmp" 3 206 (and (ior (eq_attr "type" "cmp") 207 (and (eq_attr "type" "add,logical") 208 (eq_attr "dot" "yes"))) 209 (eq_attr "cpu" "power5")) 210 "iq_power5") 211 212(define_insn_reservation "power5-compare" 2 213 (and (eq_attr "type" "shift,exts") 214 (eq_attr "dot" "yes") 215 (eq_attr "cpu" "power5")) 216 "du1_power5+du2_power5,iu1_power5,iu2_power5") 217 218(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 219 220(define_insn_reservation "power5-lmul-cmp" 7 221 (and (eq_attr "type" "mul") 222 (eq_attr "dot" "yes") 223 (eq_attr "size" "64") 224 (eq_attr "cpu" "power5")) 225 "du1_power5+du2_power5,iu1_power5*6,iu2_power5") 226 227(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 228 229(define_insn_reservation "power5-imul-cmp" 5 230 (and (eq_attr "type" "mul") 231 (eq_attr "dot" "yes") 232 (eq_attr "size" "32") 233 (eq_attr "cpu" "power5")) 234 "du1_power5+du2_power5,iu1_power5*4,iu2_power5") 235 236(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf") 237 238(define_insn_reservation "power5-lmul" 7 239 (and (eq_attr "type" "mul") 240 (eq_attr "dot" "no") 241 (eq_attr "size" "64") 242 (eq_attr "cpu" "power5")) 243 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)") 244 245(define_insn_reservation "power5-imul" 5 246 (and (eq_attr "type" "mul") 247 (eq_attr "dot" "no") 248 (eq_attr "size" "32") 249 (eq_attr "cpu" "power5")) 250 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)") 251 252(define_insn_reservation "power5-imul3" 4 253 (and (eq_attr "type" "mul") 254 (eq_attr "size" "8,16") 255 (eq_attr "cpu" "power5")) 256 "(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)") 257 258 259; SPR move only executes in first IU. 260; Integer division only executes in second IU. 261(define_insn_reservation "power5-idiv" 36 262 (and (eq_attr "type" "div") 263 (eq_attr "size" "32") 264 (eq_attr "cpu" "power5")) 265 "du1_power5+du2_power5,iu2_power5*35") 266 267(define_insn_reservation "power5-ldiv" 68 268 (and (eq_attr "type" "div") 269 (eq_attr "size" "64") 270 (eq_attr "cpu" "power5")) 271 "du1_power5+du2_power5,iu2_power5*67") 272 273 274(define_insn_reservation "power5-mtjmpr" 3 275 (and (eq_attr "type" "mtjmpr,mfjmpr") 276 (eq_attr "cpu" "power5")) 277 "du1_power5,bpu_power5") 278 279 280; Branches take dispatch Slot 4. The presence_sets prevent other insn from 281; grabbing previous dispatch slots once this is assigned. 282(define_insn_reservation "power5-branch" 2 283 (and (eq_attr "type" "jmpreg,branch") 284 (eq_attr "cpu" "power5")) 285 "(du5_power5\ 286 |du4_power5+du5_power5\ 287 |du3_power5+du4_power5+du5_power5\ 288 |du2_power5+du3_power5+du4_power5+du5_power5\ 289 |du1_power5+du2_power5+du3_power5+du4_power5+du5_power5),bpu_power5") 290 291 292; Condition Register logical ops are split if non-destructive (RT != RB) 293(define_insn_reservation "power5-crlogical" 2 294 (and (eq_attr "type" "cr_logical") 295 (eq_attr "cr_logical_3op" "no") 296 (eq_attr "cpu" "power5")) 297 "du1_power5,cru_power5") 298 299(define_insn_reservation "power5-delayedcr" 4 300 (and (eq_attr "type" "cr_logical") 301 (eq_attr "cr_logical_3op" "yes") 302 (eq_attr "cpu" "power5")) 303 "du1_power5+du2_power5,cru_power5,cru_power5") 304 305; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu 306(define_insn_reservation "power5-mfcr" 6 307 (and (eq_attr "type" "mfcr") 308 (eq_attr "cpu" "power5")) 309 "du1_power5+du2_power5+du3_power5+du4_power5,\ 310 du1_power5+du2_power5+du3_power5+du4_power5+cru_power5,\ 311 cru_power5,cru_power5,cru_power5") 312 313; mfcrf (1 field) 314(define_insn_reservation "power5-mfcrf" 3 315 (and (eq_attr "type" "mfcrf") 316 (eq_attr "cpu" "power5")) 317 "du1_power5,cru_power5") 318 319; mtcrf (1 field) 320(define_insn_reservation "power5-mtcr" 4 321 (and (eq_attr "type" "mtcr") 322 (eq_attr "cpu" "power5")) 323 "du1_power5,iu1_power5") 324 325; Basic FP latency is 6 cycles 326(define_insn_reservation "power5-fp" 6 327 (and (eq_attr "type" "fp,fpsimple,dmul") 328 (eq_attr "cpu" "power5")) 329 "fpq_power5") 330 331(define_insn_reservation "power5-fpcompare" 5 332 (and (eq_attr "type" "fpcompare") 333 (eq_attr "cpu" "power5")) 334 "fpq_power5") 335 336(define_insn_reservation "power5-sdiv" 33 337 (and (eq_attr "type" "sdiv,ddiv") 338 (eq_attr "cpu" "power5")) 339 "(du1_power5|du2_power5|du3_power5|du4_power5),\ 340 (fpu1_power5*28|fpu2_power5*28)") 341 342(define_insn_reservation "power5-sqrt" 40 343 (and (eq_attr "type" "ssqrt,dsqrt") 344 (eq_attr "cpu" "power5")) 345 "(du1_power5|du2_power5|du3_power5|du4_power5),\ 346 (fpu1_power5*35|fpu2_power5*35)") 347 348(define_insn_reservation "power5-isync" 2 349 (and (eq_attr "type" "isync") 350 (eq_attr "cpu" "power5")) 351 "du1_power5+du2_power5+du3_power5+du4_power5,\ 352 lsu1_power5") 353 354