1;; Scheduling description for IBM Power4 and PowerPC 970 processors. 2;; Copyright (C) 2003-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Sources: IBM Red Book and White Paper on POWER4 21 22;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). 23;; Instructions that update more than one register get broken into two 24;; (split) or more internal ops. The chip can issue up to 5 25;; internal ops per cycle. 26 27(define_automaton "power4iu,power4fpu,power4vec,power4misc") 28 29(define_cpu_unit "iu1_power4,iu2_power4" "power4iu") 30(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc") 31(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu") 32(define_cpu_unit "bpu_power4,cru_power4" "power4misc") 33(define_cpu_unit "vec_power4,vecperm_power4" "power4vec") 34(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4" 35 "power4misc") 36 37(define_reservation "lsq_power4" 38 "(du1_power4,lsu1_power4)\ 39 |(du2_power4,lsu2_power4)\ 40 |(du3_power4,lsu2_power4)\ 41 |(du4_power4,lsu1_power4)") 42 43(define_reservation "lsuq_power4" 44 "((du1_power4+du2_power4,lsu1_power4)\ 45 |(du2_power4+du3_power4,lsu2_power4)\ 46 |(du3_power4+du4_power4,lsu2_power4))\ 47 +(nothing,iu2_power4|nothing,iu1_power4)") 48 49(define_reservation "iq_power4" 50 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 51 (iu1_power4|iu2_power4)") 52 53(define_reservation "fpq_power4" 54 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 55 (fpu1_power4|fpu2_power4)") 56 57(define_reservation "vq_power4" 58 "(du1_power4,vec_power4)\ 59 |(du2_power4,vec_power4)\ 60 |(du3_power4,vec_power4)\ 61 |(du4_power4,vec_power4)") 62 63(define_reservation "vpq_power4" 64 "(du1_power4,vecperm_power4)\ 65 |(du2_power4,vecperm_power4)\ 66 |(du3_power4,vecperm_power4)\ 67 |(du4_power4,vecperm_power4)") 68 69 70; Dispatch slots are allocated in order conforming to program order. 71(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4") 72(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4") 73(absence_set "du3_power4" "du4_power4,du5_power4") 74(absence_set "du4_power4" "du5_power4") 75 76 77; Load/store 78(define_insn_reservation "power4-load" 4 ; 3 79 (and (eq_attr "type" "load") 80 (eq_attr "sign_extend" "no") 81 (eq_attr "update" "no") 82 (eq_attr "cpu" "power4")) 83 "lsq_power4") 84 85(define_insn_reservation "power4-load-ext" 5 86 (and (eq_attr "type" "load") 87 (eq_attr "sign_extend" "yes") 88 (eq_attr "update" "no") 89 (eq_attr "cpu" "power4")) 90 "(du1_power4+du2_power4,lsu1_power4\ 91 |du2_power4+du3_power4,lsu2_power4\ 92 |du3_power4+du4_power4,lsu2_power4),\ 93 nothing,nothing,\ 94 (iu2_power4|iu1_power4)") 95 96(define_insn_reservation "power4-load-ext-update" 5 97 (and (eq_attr "type" "load") 98 (eq_attr "sign_extend" "yes") 99 (eq_attr "update" "yes") 100 (eq_attr "indexed" "no") 101 (eq_attr "cpu" "power4")) 102 "du1_power4+du2_power4+du3_power4+du4_power4,\ 103 lsu1_power4+iu2_power4,nothing,nothing,iu2_power4") 104 105(define_insn_reservation "power4-load-ext-update-indexed" 5 106 (and (eq_attr "type" "load") 107 (eq_attr "sign_extend" "yes") 108 (eq_attr "update" "yes") 109 (eq_attr "indexed" "yes") 110 (eq_attr "cpu" "power4")) 111 "du1_power4+du2_power4+du3_power4+du4_power4,\ 112 iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4") 113 114(define_insn_reservation "power4-load-update-indexed" 3 115 (and (eq_attr "type" "load") 116 (eq_attr "sign_extend" "no") 117 (eq_attr "update" "yes") 118 (eq_attr "indexed" "yes") 119 (eq_attr "cpu" "power4")) 120 "du1_power4+du2_power4+du3_power4+du4_power4,\ 121 iu1_power4,lsu2_power4+iu2_power4") 122 123(define_insn_reservation "power4-load-update" 4 ; 3 124 (and (eq_attr "type" "load") 125 (eq_attr "sign_extend" "no") 126 (eq_attr "update" "yes") 127 (eq_attr "indexed" "no") 128 (eq_attr "cpu" "power4")) 129 "lsuq_power4") 130 131(define_insn_reservation "power4-fpload" 6 ; 5 132 (and (eq_attr "type" "fpload") 133 (eq_attr "update" "no") 134 (eq_attr "cpu" "power4")) 135 "lsq_power4") 136 137(define_insn_reservation "power4-fpload-update" 6 ; 5 138 (and (eq_attr "type" "fpload") 139 (eq_attr "update" "yes") 140 (eq_attr "cpu" "power4")) 141 "lsuq_power4") 142 143(define_insn_reservation "power4-vecload" 6 ; 5 144 (and (eq_attr "type" "vecload") 145 (eq_attr "cpu" "power4")) 146 "lsq_power4") 147 148(define_insn_reservation "power4-store" 12 149 (and (eq_attr "type" "store") 150 (eq_attr "update" "no") 151 (eq_attr "cpu" "power4")) 152 "((du1_power4,lsu1_power4)\ 153 |(du2_power4,lsu2_power4)\ 154 |(du3_power4,lsu2_power4)\ 155 |(du4_power4,lsu1_power4)),\ 156 (iu1_power4|iu2_power4)") 157 158(define_insn_reservation "power4-store-update" 12 159 (and (eq_attr "type" "store") 160 (eq_attr "update" "yes") 161 (eq_attr "indexed" "no") 162 (eq_attr "cpu" "power4")) 163 "((du1_power4+du2_power4,lsu1_power4)\ 164 |(du2_power4+du3_power4,lsu2_power4)\ 165 |(du3_power4+du4_power4,lsu2_power4))+\ 166 ((nothing,iu1_power4,iu2_power4)\ 167 |(nothing,iu2_power4,iu2_power4)\ 168 |(nothing,iu2_power4,iu1_power4))") 169 170(define_insn_reservation "power4-store-update-indexed" 12 171 (and (eq_attr "type" "store") 172 (eq_attr "update" "yes") 173 (eq_attr "indexed" "yes") 174 (eq_attr "cpu" "power4")) 175 "du1_power4+du2_power4+du3_power4+du4_power4,\ 176 iu1_power4,lsu2_power4+iu2_power4,iu2_power4") 177 178(define_insn_reservation "power4-fpstore" 12 179 (and (eq_attr "type" "fpstore") 180 (eq_attr "update" "no") 181 (eq_attr "cpu" "power4")) 182 "((du1_power4,lsu1_power4)\ 183 |(du2_power4,lsu2_power4)\ 184 |(du3_power4,lsu2_power4)\ 185 |(du4_power4,lsu1_power4)),\ 186 (fpu1_power4|fpu2_power4)") 187 188(define_insn_reservation "power4-fpstore-update" 12 189 (and (eq_attr "type" "fpstore") 190 (eq_attr "update" "yes") 191 (eq_attr "cpu" "power4")) 192 "((du1_power4+du2_power4,lsu1_power4)\ 193 |(du2_power4+du3_power4,lsu2_power4)\ 194 |(du3_power4+du4_power4,lsu2_power4))\ 195 +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))") 196 197(define_insn_reservation "power4-vecstore" 12 198 (and (eq_attr "type" "vecstore") 199 (eq_attr "cpu" "power4")) 200 "(du1_power4,lsu1_power4,vec_power4)\ 201 |(du2_power4,lsu2_power4,vec_power4)\ 202 |(du3_power4,lsu2_power4,vec_power4)\ 203 |(du4_power4,lsu1_power4,vec_power4)") 204 205(define_insn_reservation "power4-llsc" 11 206 (and (eq_attr "type" "load_l,store_c,sync") 207 (eq_attr "cpu" "power4")) 208 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") 209 210 211; Integer latency is 2 cycles 212(define_insn_reservation "power4-integer" 2 213 (and (ior (eq_attr "type" "integer,trap,cntlz,isel") 214 (and (eq_attr "type" "add,logical,shift,exts") 215 (eq_attr "dot" "no")) 216 (and (eq_attr "type" "insert") 217 (eq_attr "size" "64"))) 218 (eq_attr "cpu" "power4")) 219 "iq_power4") 220 221(define_insn_reservation "power4-two" 2 222 (and (eq_attr "type" "two") 223 (eq_attr "cpu" "power4")) 224 "((du1_power4+du2_power4)\ 225 |(du2_power4+du3_power4)\ 226 |(du3_power4+du4_power4)\ 227 |(du4_power4+du1_power4)),\ 228 ((iu1_power4,nothing,iu2_power4)\ 229 |(iu2_power4,nothing,iu2_power4)\ 230 |(iu2_power4,nothing,iu1_power4)\ 231 |(iu1_power4,nothing,iu1_power4))") 232 233(define_insn_reservation "power4-three" 2 234 (and (eq_attr "type" "three") 235 (eq_attr "cpu" "power4")) 236 "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\ 237 |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\ 238 ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\ 239 |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\ 240 |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\ 241 |(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))") 242 243(define_insn_reservation "power4-insert" 4 244 (and (eq_attr "type" "insert") 245 (eq_attr "size" "32") 246 (eq_attr "cpu" "power4")) 247 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 248 ((iu1_power4,nothing,iu2_power4)\ 249 |(iu2_power4,nothing,iu2_power4)\ 250 |(iu2_power4,nothing,iu1_power4))") 251 252(define_insn_reservation "power4-cmp" 3 253 (and (ior (eq_attr "type" "cmp") 254 (and (eq_attr "type" "add,logical") 255 (eq_attr "dot" "yes"))) 256 (eq_attr "cpu" "power4")) 257 "iq_power4") 258 259(define_insn_reservation "power4-compare" 2 260 (and (eq_attr "type" "shift,exts") 261 (eq_attr "dot" "yes") 262 (eq_attr "cpu" "power4")) 263 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 264 ((iu1_power4,iu2_power4)\ 265 |(iu2_power4,iu2_power4)\ 266 |(iu2_power4,iu1_power4))") 267 268(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 269 270(define_insn_reservation "power4-lmul-cmp" 7 271 (and (eq_attr "type" "mul") 272 (eq_attr "dot" "yes") 273 (eq_attr "size" "64") 274 (eq_attr "cpu" "power4")) 275 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 276 ((iu1_power4*6,iu2_power4)\ 277 |(iu2_power4*6,iu2_power4)\ 278 |(iu2_power4*6,iu1_power4))") 279 280(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 281 282(define_insn_reservation "power4-imul-cmp" 5 283 (and (eq_attr "type" "mul") 284 (eq_attr "dot" "yes") 285 (eq_attr "size" "32") 286 (eq_attr "cpu" "power4")) 287 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 288 ((iu1_power4*4,iu2_power4)\ 289 |(iu2_power4*4,iu2_power4)\ 290 |(iu2_power4*4,iu1_power4))") 291 292(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 293 294(define_insn_reservation "power4-lmul" 7 295 (and (eq_attr "type" "mul") 296 (eq_attr "dot" "no") 297 (eq_attr "size" "64") 298 (eq_attr "cpu" "power4")) 299 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 300 (iu1_power4*6|iu2_power4*6)") 301 302(define_insn_reservation "power4-imul" 5 303 (and (eq_attr "type" "mul") 304 (eq_attr "dot" "no") 305 (eq_attr "size" "32") 306 (eq_attr "cpu" "power4")) 307 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 308 (iu1_power4*4|iu2_power4*4)") 309 310(define_insn_reservation "power4-imul3" 4 311 (and (eq_attr "type" "mul") 312 (eq_attr "size" "8,16") 313 (eq_attr "cpu" "power4")) 314 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 315 (iu1_power4*3|iu2_power4*3)") 316 317 318; SPR move only executes in first IU. 319; Integer division only executes in second IU. 320(define_insn_reservation "power4-idiv" 36 321 (and (eq_attr "type" "div") 322 (eq_attr "size" "32") 323 (eq_attr "cpu" "power4")) 324 "du1_power4+du2_power4,iu2_power4*35") 325 326(define_insn_reservation "power4-ldiv" 68 327 (and (eq_attr "type" "div") 328 (eq_attr "size" "64") 329 (eq_attr "cpu" "power4")) 330 "du1_power4+du2_power4,iu2_power4*67") 331 332 333(define_insn_reservation "power4-mtjmpr" 3 334 (and (eq_attr "type" "mtjmpr,mfjmpr") 335 (eq_attr "cpu" "power4")) 336 "du1_power4,bpu_power4") 337 338 339; Branches take dispatch Slot 4. The presence_sets prevent other insn from 340; grabbing previous dispatch slots once this is assigned. 341(define_insn_reservation "power4-branch" 2 342 (and (eq_attr "type" "jmpreg,branch") 343 (eq_attr "cpu" "power4")) 344 "(du5_power4\ 345 |du4_power4+du5_power4\ 346 |du3_power4+du4_power4+du5_power4\ 347 |du2_power4+du3_power4+du4_power4+du5_power4\ 348 |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4") 349 350 351; Condition Register logical ops are split if non-destructive (RT != RB) 352(define_insn_reservation "power4-crlogical" 2 353 (and (eq_attr "type" "cr_logical") 354 (eq_attr "cr_logical_3op" "no") 355 (eq_attr "cpu" "power4")) 356 "du1_power4,cru_power4") 357 358(define_insn_reservation "power4-delayedcr" 4 359 (and (eq_attr "type" "cr_logical") 360 (eq_attr "cr_logical_3op" "yes") 361 (eq_attr "cpu" "power4")) 362 "du1_power4+du2_power4,cru_power4,cru_power4") 363 364; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu 365(define_insn_reservation "power4-mfcr" 6 366 (and (eq_attr "type" "mfcr") 367 (eq_attr "cpu" "power4")) 368 "du1_power4+du2_power4+du3_power4+du4_power4,\ 369 du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\ 370 cru_power4,cru_power4,cru_power4") 371 372; mfcrf (1 field) 373(define_insn_reservation "power4-mfcrf" 3 374 (and (eq_attr "type" "mfcrf") 375 (eq_attr "cpu" "power4")) 376 "du1_power4,cru_power4") 377 378; mtcrf (1 field) 379(define_insn_reservation "power4-mtcr" 4 380 (and (eq_attr "type" "mtcr") 381 (eq_attr "cpu" "power4")) 382 "du1_power4,iu1_power4") 383 384; Basic FP latency is 6 cycles 385(define_insn_reservation "power4-fp" 6 386 (and (eq_attr "type" "fp,fpsimple,dmul") 387 (eq_attr "cpu" "power4")) 388 "fpq_power4") 389 390(define_insn_reservation "power4-fpcompare" 5 391 (and (eq_attr "type" "fpcompare") 392 (eq_attr "cpu" "power4")) 393 "fpq_power4") 394 395(define_insn_reservation "power4-sdiv" 33 396 (and (eq_attr "type" "sdiv,ddiv") 397 (eq_attr "cpu" "power4")) 398 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 399 (fpu1_power4*28|fpu2_power4*28)") 400 401(define_insn_reservation "power4-sqrt" 40 402 (and (eq_attr "type" "ssqrt,dsqrt") 403 (eq_attr "cpu" "power4")) 404 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 405 (fpu1_power4*35|fpu2_power4*35)") 406 407(define_insn_reservation "power4-isync" 2 408 (and (eq_attr "type" "isync") 409 (eq_attr "cpu" "power4")) 410 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") 411 412 413; VMX 414(define_insn_reservation "power4-vecsimple" 2 415 (and (eq_attr "type" "vecsimple,veclogical,vecmove") 416 (eq_attr "cpu" "power4")) 417 "vq_power4") 418 419(define_insn_reservation "power4-veccomplex" 5 420 (and (eq_attr "type" "veccomplex") 421 (eq_attr "cpu" "power4")) 422 "vq_power4") 423 424; vecfp compare 425(define_insn_reservation "power4-veccmp" 8 426 (and (eq_attr "type" "veccmp,veccmpfx") 427 (eq_attr "cpu" "power4")) 428 "vq_power4") 429 430(define_insn_reservation "power4-vecfloat" 8 431 (and (eq_attr "type" "vecfloat") 432 (eq_attr "cpu" "power4")) 433 "vq_power4") 434 435(define_insn_reservation "power4-vecperm" 2 436 (and (eq_attr "type" "vecperm") 437 (eq_attr "cpu" "power4")) 438 "vpq_power4") 439 440(define_bypass 4 "power4-vecload" "power4-vecperm") 441 442(define_bypass 3 "power4-vecsimple" "power4-vecperm") 443(define_bypass 6 "power4-veccomplex" "power4-vecperm") 444(define_bypass 3 "power4-vecperm" 445 "power4-vecsimple,power4-veccomplex,power4-vecfloat") 446(define_bypass 9 "power4-vecfloat" "power4-vecperm") 447 448(define_bypass 5 "power4-vecsimple,power4-veccomplex" 449 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 450 451(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore") 452(define_bypass 7 "power4-veccomplex" "power4-vecstore") 453(define_bypass 10 "power4-vecfloat" "power4-vecstore") 454