1;; Scheduling description for Motorola PowerPC processor cores. 2;; Copyright (C) 2003-2020 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_automaton "mpc,mpcfp") 21(define_cpu_unit "iu_mpc,mciu_mpc" "mpc") 22(define_cpu_unit "fpu_mpc" "mpcfp") 23(define_cpu_unit "lsu_mpc,bpu_mpc" "mpc") 24 25;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU 26;; 505/801/821/823 27 28(define_insn_reservation "mpccore-load" 2 29 (and (eq_attr "type" "load,load_l,store_c,sync") 30 (eq_attr "cpu" "mpccore")) 31 "lsu_mpc") 32 33(define_insn_reservation "mpccore-store" 2 34 (and (eq_attr "type" "store,fpstore") 35 (eq_attr "cpu" "mpccore")) 36 "lsu_mpc") 37 38(define_insn_reservation "mpccore-fpload" 2 39 (and (eq_attr "type" "fpload") 40 (eq_attr "cpu" "mpccore")) 41 "lsu_mpc") 42 43(define_insn_reservation "mpccore-integer" 1 44 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") 45 (and (eq_attr "type" "add,logical,shift,exts") 46 (eq_attr "dot" "no"))) 47 (eq_attr "cpu" "mpccore")) 48 "iu_mpc") 49 50(define_insn_reservation "mpccore-two" 1 51 (and (eq_attr "type" "two") 52 (eq_attr "cpu" "mpccore")) 53 "iu_mpc,iu_mpc") 54 55(define_insn_reservation "mpccore-three" 1 56 (and (eq_attr "type" "three") 57 (eq_attr "cpu" "mpccore")) 58 "iu_mpc,iu_mpc,iu_mpc") 59 60(define_insn_reservation "mpccore-imul" 2 61 (and (eq_attr "type" "mul") 62 (eq_attr "cpu" "mpccore")) 63 "mciu_mpc") 64 65; Divide latency varies greatly from 2-11, use 6 as average 66(define_insn_reservation "mpccore-idiv" 6 67 (and (eq_attr "type" "div") 68 (eq_attr "cpu" "mpccore")) 69 "mciu_mpc*6") 70 71(define_insn_reservation "mpccore-compare" 3 72 (and (ior (eq_attr "type" "cmp") 73 (and (eq_attr "type" "add,logical,shift,exts") 74 (eq_attr "dot" "yes"))) 75 (eq_attr "cpu" "mpccore")) 76 "iu_mpc,nothing,bpu_mpc") 77 78(define_insn_reservation "mpccore-fpcompare" 2 79 (and (eq_attr "type" "fpcompare") 80 (eq_attr "cpu" "mpccore")) 81 "fpu_mpc,bpu_mpc") 82 83(define_insn_reservation "mpccore-fp" 4 84 (and (eq_attr "type" "fp,fpsimple") 85 (eq_attr "cpu" "mpccore")) 86 "fpu_mpc*2") 87 88(define_insn_reservation "mpccore-dmul" 5 89 (and (eq_attr "type" "dmul") 90 (eq_attr "cpu" "mpccore")) 91 "fpu_mpc*5") 92 93(define_insn_reservation "mpccore-sdiv" 10 94 (and (eq_attr "type" "sdiv") 95 (eq_attr "cpu" "mpccore")) 96 "fpu_mpc*10") 97 98(define_insn_reservation "mpccore-ddiv" 17 99 (and (eq_attr "type" "ddiv") 100 (eq_attr "cpu" "mpccore")) 101 "fpu_mpc*17") 102 103(define_insn_reservation "mpccore-mtjmpr" 4 104 (and (eq_attr "type" "mtjmpr,mfjmpr") 105 (eq_attr "cpu" "mpccore")) 106 "bpu_mpc") 107 108(define_insn_reservation "mpccore-jmpreg" 1 109 (and (eq_attr "type" "jmpreg,branch,cr_logical,mfcr,mtcr,isync") 110 (eq_attr "cpu" "mpccore")) 111 "bpu_mpc") 112 113