1;; Scheduling description for PowerPC 604, PowerPC 604e, PowerPC 620, 2;; and PowerPC 630 processors. 3;; Copyright (C) 2003-2020 Free Software Foundation, Inc. 4;; 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_automaton "ppc6xx,ppc6xxfp,ppc6xxfp2") 22(define_cpu_unit "iu1_6xx,iu2_6xx,mciu_6xx" "ppc6xx") 23(define_cpu_unit "fpu_6xx" "ppc6xxfp") 24(define_cpu_unit "fpu1_6xx,fpu2_6xx" "ppc6xxfp2") 25(define_cpu_unit "lsu_6xx,bpu_6xx,cru_6xx" "ppc6xx") 26 27;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU 28;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU 29;; MCIU used for imul/idiv and moves from/to spr 30;; LSU 2 stage pipelined 31;; FPU 3 stage pipelined 32;; Max issue 4 insns/clock cycle 33 34;; PPC604e is PPC604 with larger caches and a CRU. In the 604 35;; the CR logical operations are handled in the BPU. 36;; In the 604e, the CRU shares bus with BPU so only one condition 37;; register or branch insn can be issued per clock. Not modelled. 38 39;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU 40;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU 41;; Max issue 4 insns/clock cycle 42;; Out-of-order execution, in-order completion 43 44;; No following instruction can dispatch in the same cycle as a branch 45;; instruction. Not modelled. This is no problem if RCSP is not 46;; enabled since the scheduler stops a schedule when it gets to a branch. 47 48;; Four insns can be dispatched per cycle. 49 50(define_insn_reservation "ppc604-load" 2 51 (and (eq_attr "type" "load") 52 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 53 "lsu_6xx") 54 55(define_insn_reservation "ppc604-fpload" 3 56 (and (eq_attr "type" "fpload") 57 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 58 "lsu_6xx") 59 60(define_insn_reservation "ppc604-store" 3 61 (and (eq_attr "type" "store,fpstore") 62 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 63 "lsu_6xx") 64 65(define_insn_reservation "ppc604-llsc" 3 66 (and (eq_attr "type" "load_l,store_c") 67 (eq_attr "cpu" "ppc604,ppc604e")) 68 "lsu_6xx") 69 70(define_insn_reservation "ppc630-llsc" 4 71 (and (eq_attr "type" "load_l,store_c") 72 (eq_attr "cpu" "ppc620,ppc630")) 73 "lsu_6xx") 74 75(define_insn_reservation "ppc604-integer" 1 76 (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") 77 (and (eq_attr "type" "add,logical,shift,exts") 78 (eq_attr "dot" "no"))) 79 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 80 "iu1_6xx|iu2_6xx") 81 82(define_insn_reservation "ppc604-two" 1 83 (and (eq_attr "type" "two") 84 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 85 "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx") 86 87(define_insn_reservation "ppc604-three" 1 88 (and (eq_attr "type" "three") 89 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 90 "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx") 91 92(define_insn_reservation "ppc604-imul" 4 93 (and (eq_attr "type" "mul") 94 (eq_attr "cpu" "ppc604")) 95 "mciu_6xx*2") 96 97(define_insn_reservation "ppc604e-imul" 2 98 (and (eq_attr "type" "mul") 99 (eq_attr "cpu" "ppc604e")) 100 "mciu_6xx") 101 102(define_insn_reservation "ppc620-imul" 5 103 (and (eq_attr "type" "mul") 104 (eq_attr "size" "32") 105 (eq_attr "cpu" "ppc620,ppc630")) 106 "mciu_6xx*3") 107 108(define_insn_reservation "ppc620-imul2" 4 109 (and (eq_attr "type" "mul") 110 (eq_attr "size" "16") 111 (eq_attr "cpu" "ppc620,ppc630")) 112 "mciu_6xx*3") 113 114(define_insn_reservation "ppc620-imul3" 3 115 (and (eq_attr "type" "mul") 116 (eq_attr "size" "8") 117 (eq_attr "cpu" "ppc620,ppc630")) 118 "mciu_6xx*3") 119 120(define_insn_reservation "ppc620-lmul" 7 121 (and (eq_attr "type" "mul") 122 (eq_attr "size" "64") 123 (eq_attr "cpu" "ppc620,ppc630")) 124 "mciu_6xx*5") 125 126(define_insn_reservation "ppc604-idiv" 20 127 (and (eq_attr "type" "div") 128 (eq_attr "cpu" "ppc604,ppc604e")) 129 "mciu_6xx*19") 130 131(define_insn_reservation "ppc620-idiv" 37 132 (and (eq_attr "type" "div") 133 (eq_attr "size" "32") 134 (eq_attr "cpu" "ppc620")) 135 "mciu_6xx*36") 136 137(define_insn_reservation "ppc630-idiv" 21 138 (and (eq_attr "type" "div") 139 (eq_attr "size" "32") 140 (eq_attr "cpu" "ppc630")) 141 "mciu_6xx*20") 142 143(define_insn_reservation "ppc620-ldiv" 37 144 (and (eq_attr "type" "div") 145 (eq_attr "size" "64") 146 (eq_attr "cpu" "ppc620,ppc630")) 147 "mciu_6xx*36") 148 149(define_insn_reservation "ppc604-compare" 3 150 (and (ior (eq_attr "type" "cmp") 151 (and (eq_attr "type" "add,logical,shift,exts") 152 (eq_attr "dot" "yes"))) 153 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 154 "(iu1_6xx|iu2_6xx)") 155 156; FPU PPC604{,e},PPC620 157(define_insn_reservation "ppc604-fpcompare" 5 158 (and (eq_attr "type" "fpcompare") 159 (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 160 "fpu_6xx") 161 162(define_insn_reservation "ppc604-fp" 3 163 (and (eq_attr "type" "fp,fpsimple") 164 (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 165 "fpu_6xx") 166 167(define_insn_reservation "ppc604-dmul" 3 168 (and (eq_attr "type" "dmul") 169 (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 170 "fpu_6xx") 171 172; Divides are not pipelined 173(define_insn_reservation "ppc604-sdiv" 18 174 (and (eq_attr "type" "sdiv") 175 (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 176 "fpu_6xx*18") 177 178(define_insn_reservation "ppc604-ddiv" 32 179 (and (eq_attr "type" "ddiv") 180 (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 181 "fpu_6xx*32") 182 183(define_insn_reservation "ppc620-ssqrt" 31 184 (and (eq_attr "type" "ssqrt") 185 (eq_attr "cpu" "ppc620")) 186 "fpu_6xx*31") 187 188(define_insn_reservation "ppc620-dsqrt" 31 189 (and (eq_attr "type" "dsqrt") 190 (eq_attr "cpu" "ppc620")) 191 "fpu_6xx*31") 192 193 194; 2xFPU PPC630 195(define_insn_reservation "ppc630-fpcompare" 5 196 (and (eq_attr "type" "fpcompare") 197 (eq_attr "cpu" "ppc630")) 198 "fpu1_6xx|fpu2_6xx") 199 200(define_insn_reservation "ppc630-fp" 3 201 (and (eq_attr "type" "fp,dmul") 202 (eq_attr "cpu" "ppc630")) 203 "fpu1_6xx|fpu2_6xx") 204 205(define_insn_reservation "ppc630-sdiv" 17 206 (and (eq_attr "type" "sdiv") 207 (eq_attr "cpu" "ppc630")) 208 "fpu1_6xx*17|fpu2_6xx*17") 209 210(define_insn_reservation "ppc630-ddiv" 21 211 (and (eq_attr "type" "ddiv") 212 (eq_attr "cpu" "ppc630")) 213 "fpu1_6xx*21|fpu2_6xx*21") 214 215(define_insn_reservation "ppc630-ssqrt" 18 216 (and (eq_attr "type" "ssqrt") 217 (eq_attr "cpu" "ppc630")) 218 "fpu1_6xx*18|fpu2_6xx*18") 219 220(define_insn_reservation "ppc630-dsqrt" 25 221 (and (eq_attr "type" "dsqrt") 222 (eq_attr "cpu" "ppc630")) 223 "fpu1_6xx*25|fpu2_6xx*25") 224 225(define_insn_reservation "ppc604-mfcr" 3 226 (and (eq_attr "type" "mfcr") 227 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 228 "mciu_6xx") 229 230(define_insn_reservation "ppc604-mtcr" 2 231 (and (eq_attr "type" "mtcr") 232 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 233 "iu1_6xx|iu2_6xx") 234 235(define_insn_reservation "ppc604-crlogical" 2 236 (and (eq_attr "type" "cr_logical") 237 (eq_attr "cpu" "ppc604")) 238 "bpu_6xx") 239 240(define_insn_reservation "ppc604e-crlogical" 2 241 (and (eq_attr "type" "cr_logical") 242 (eq_attr "cpu" "ppc604e,ppc620,ppc630")) 243 "cru_6xx") 244 245(define_insn_reservation "ppc604-mtjmpr" 2 246 (and (eq_attr "type" "mtjmpr") 247 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 248 "mciu_6xx") 249 250(define_insn_reservation "ppc604-mfjmpr" 3 251 (and (eq_attr "type" "mfjmpr") 252 (eq_attr "cpu" "ppc604,ppc604e,ppc620")) 253 "mciu_6xx") 254 255(define_insn_reservation "ppc630-mfjmpr" 2 256 (and (eq_attr "type" "mfjmpr") 257 (eq_attr "cpu" "ppc630")) 258 "mciu_6xx") 259 260(define_insn_reservation "ppc604-jmpreg" 1 261 (and (eq_attr "type" "jmpreg,branch") 262 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) 263 "bpu_6xx") 264 265(define_insn_reservation "ppc604-isync" 0 266 (and (eq_attr "type" "isync") 267 (eq_attr "cpu" "ppc604,ppc604e")) 268 "bpu_6xx") 269 270(define_insn_reservation "ppc630-isync" 6 271 (and (eq_attr "type" "isync") 272 (eq_attr "cpu" "ppc620,ppc630")) 273 "bpu_6xx") 274 275(define_insn_reservation "ppc604-sync" 35 276 (and (eq_attr "type" "sync") 277 (eq_attr "cpu" "ppc604,ppc604e")) 278 "lsu_6xx") 279 280(define_insn_reservation "ppc630-sync" 26 281 (and (eq_attr "type" "sync") 282 (eq_attr "cpu" "ppc620,ppc630")) 283 "lsu_6xx") 284 285